1 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm 68020 features n selection of processor speeds: 16.67, 20, 25 mhz n military temperature range: -55 c to +125 c n packaging ? 114 pin ceramic pga (p2) ? 132 lead ceramic quad flatpack, cqfp (q2) n object-code compatible with earlier 68000 microprocessors n addressing mode extensions for enhanced support of high- level languages n bit field data type accelerates bit-oriented applicationsC i.e., video graphics n fast on-chip instruction cache speeds instructions and improves bus bandwidth n coprocessor interface to companion 32-bit peripheralsCthe 68881 and 68882 floating-point coprocessors and the 68851 paged memory management unit n pipelined architecture with high degree of internal parallelism allowing multiple instructions to be executed concurrently december 1998 fig. 1 block diagram n high-performance asynchronous bus is nonmultiplexed and full 32-bits n dynamic bus sizing efficiently supports 8-/16-/32-bit memories and peripherals n full support of virtual memory and virtual machine n 16 32-bit general-purpose data and address registers n two 32-bit supervisor stack pointers and five special- purpose control registers n 18 addressing modes and 7 data types n 4 gigabyte direct addressing range description the wc32p020 is a 32-bit implementation of the 68000 family of microprocessors. using hcmos technology, the wc32p020 is implemented with 32-bit registers and data paths, 32-bit addresses, a powerful instruction set, and flexible addressing modes.
2 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 2 pin configuration for wc32p020-xxm, cqfp (q2) 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 nc bgac br a 0 a 1 a 31 a 30 a 29 a 28 a 27 a 26 a 25 a 24 a 23 a 22 a 21 a 20 a 19 a 18 a 17 v dd v dd gnd gnd a 16 a 15 a 14 a 13 a 12 a 11 a 10 nc nc nc nc nc a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 gnd osc ipend v dd v dd gnd gnd ipl 2 ipl 1 ipl 0 d 0 d 1 d 2 d 3 d 4 gnd gnd v dd v dd d 5 nc nc nc d 31 d 30 d 29 d 28 d 27 d 26 d 25 d 24 d 23 d 22 d 21 d 20 d 19 d 18 d 17 d 16 gnd gnd v dd v dd d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 nc nc nc nc gnd bg v dd gnd gnd clk reset v dd v dd rmc fc 0 fc 1 fc 2 siz 0 siz 1 dben ecs cdis avec dsack 0 dsack 1 berr gnd gnd halt as ds gnd gnd r/w nc 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 wc32p020-xxm fig. 3 pin configuration for wc32p020-xxm, pga (p2) top view d 31 ds as gnd cdis ecs siz 0 fc 0 v cc reset gnd bgack 1 2 3 4 5 6 7 8 9 10 11 12 13 d 28 d 29 r/w halt berr avec siz 1 fc 2 rmc v cc clk bg a 1 dsack 1 d 25 d 26 d 30 gnd gnd dsack 0 dben fc 1 v cc v cc gnd br a 31 d 22 d 24 d 27 a 0 a 30 a 28 d 20 d 21 d 23 a 29 a 27 a 26 d 17 d 18 d 19 a 25 a 24 a 23 gnd d 16 gnd a 21 a 20 a 22 v cc v cc d 15 a 17 a 18 a 19 d 14 d 13 d 11 a 16 gnd v cc d 12 d 10 d 7 a 12 d 15 gnd d 9 d 6 gnd a 9 d 13 a 14 d 8 d 5 d 3 d 1 ipl 0 ipl 2 gnd gnd a 2 a 4 a 7 a 10 a 11 v cc d 4 d 2 d 0 ipl 1 gnd v cc ipend ocs a 3 a 5 a 6 a 8 v cc n m l k j h g f e d c b a
3 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm addressing modes addressing syntax register direct data register direct dn address register direct an register indirect address register indirect (an) address register indirect with postincrement (an) + address register indirect with predecrement - (an) address register indirect with displacement (d 16 ,an) register indirect with index address register indirect with index (8-bit displacement) (d 8 ,an,xn) address register indirect with index (base displacement) (bd,an,xn) memory indirect memory indirect postindexed ([bd,an],xn,od) memory indirect preindexed ([bd,an,xn],od) program counter indirect with displacement (d 16 ,pc) program counter indirect with index pc indirect with index (8-bit displacement) (d 8 ,pc,xn) pc indirect with index (base displacement) (bd,pc,xn) program counter memory indirect pc memory indirect postindexed ([bd,pc],xn,od) pc memory indirect preindexed ([bd,pc,xn],od) absolute absolute short (xxx).w absolute long (xxx).l immediate #(data) notes: dn = data register, do-d7 an = address register, ao-a7 d 8 , d 16 = a twos-complement or sign-extended displacement; added as part of the effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero. xn = address or data register used as an index register; form is xn.size*scale, where size is.w or .l (indicates index register size) and scale is 1, 2, 4, or 8 (index register is multiplied by scale); use of size and/or scale is optional. bd = a twos-complement base displacement; when present, size can be 16 or 32 bits. od = 0uter displacement, added as part of effective address calculation after any memory indirection, use is optional with a size of 16 or 32 bits. pc = program counter (data) = immediate value of 8, 16, or 32 bits ( ) = effective address [ ] = use as indirect access to long-word address. mnemonic description bcc branch conditionally bchg test bit and change bclr test bit and clear bfchg test bit field and change bfclr test bit field and clear bfexts signed bit field extract bfextu unsigned bit field extract bfffo bit field find first one bfins bit field insert bfset test bit field and set bftst test bit field bkpt breakpoint bra branch bset test bit and set bsr branch to subroutine btst test bit callm call module cas compare and swap operands cas2 compare and swap dual operands chk check register against bound chk2 check register against upper and lower bounds clr clear cmp compare cmpa compare address cmpi compare immediate cmpm compare memory to memory cmp2 compare register against upper and lower bounds dbcc test condition, decrement and branch divs, divsl signed divide divu, divul unsigned divide eor logical exclusive or eori logical exclusive or immediate exg exchange registers ext, extb sign extend illegal take illegal instruction trap jmp jump jsr jump to subroutine lea load effective address link link and allocate lsl, lsr logical shift left and right move move movea move address move ccr move condition code register move sr move status register move usp move user stack pointer movec move control register movem move multiple registers movep move peripheral moveq move quick moves move alternate address space muls signed multiply mulu unsigned multiple mnemonic description abcd add decimal with extend add add adda add address addi add immediate addq add quick addx add with extend and logical and andi logical and immediate asl, asr arithmetic shift left and right instruction set
4 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm instruction set (cont.) mnemonic description nbcd negate decimal with extend neg negate negx negate with extend nop no operation not logical complement or logical inclusive or ori logical inclusive or immediate ori ccr logical inclusive or immediate to condition codes ori sr logical inclusive or immediate to status register pack pack bcd pea push effective address reset reset external devices rol, ror rotate left and right roxl, roxr rotate with extend left and right rtd return and deallocate rte return from exception rtm return from module rtr return and restore codes rts return from subroutine sbcd subtract decimal with extend scc set conditionally stop stop sub subtract suba subtract address subi subtract immediate subq subtract quick subx subtract with extend swap swap register words tas test operand and set trap trap trapcc trap conditionally trapv trap on overflow tst test operand unlk unlink unpk unpack bcd mnemonic description cpbcc branch conditionally cpdbcc test coprocessor condition, decrement and branch cpgen coprocessor general instruction coprocessor instructions mnemonic description cprestore restore internal state of coprocessor cpsave save internal state of coprocessor cpscc set conditionally cptrapcc trap conditionally fig. 4 functional signal groups fc0-fc2 a0-a31 d0-d31 siz0 siz1 reset halt berr clk vcc (10) gnd (13) interrupt priority cdis ipend avec br bg bgack ecs ocs rmc as ds r/w dben dsack0 dsack1 asynchronous bus control interrupt control ipl0-ipl2 bus arbitration control bus exception control transfer size cache control function codes address bus data bus signal description the vcc and gnd pins are separated into four groups to provide individual power supply connections for the address bus buffers, data bus buffers, and all other buffers and internal logic. see fig. 4. group vcc gnd address bus a 9 , d 3 a 10 , b 9 , c 3 , f 12 data bus m 8 , n 8 , n 13 l 7 , l 11 , n 7 , k 3 logic d 1 , d 2 , e 3 , g 11 , g 13 g 12 , h 13 , j 3 , k 1 clock b 1
5 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm signal index signal name mnemonic function function codes fc2-fc0 3-bit function code used to identify the address space of each bus cycle. address bus a0-a31 32-bit address bus. data bus d0-d31 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. size siz0/siz1 indicates the number of bytes remaining to be transferred for this cycle. these signals, together with a1 and a0, define the active sections of the data bus. external cycle start ecs provides an indication that a bus cycle is beginning. operand cycle start ocs identical operation to that of ecs except that ocs is asserted only during the first bus cycle of an oper and transfer. read,write r/w defines the bus transfer as a processor read or write. read-modify-write cycle rmc provides an indicator that the current bus cycle is part of an indivisible read-modify-write operatio n. address strobe as indicates that a valid address is on the bus. data strobe ds indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the wc32p020-xxm. data buffer enable dben provides an enable signal for external data buffers. data transfer and dsack0/dsack1 bus response signals that indicate the requested data transfer operation has completed. in additi on, these size acknowledge two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. interrupt priority level ipl0-ipl2 provides an encoded interrupt level to the processor. interrupt pending ipend indicates that an interrupt is pending. autovector avec requests an autovector during an interrupt acknowledge cycle. bus request br indicates that an external device requires bus mastership. bus grant bg indicates that an external device may assume bus mastership. bus grant acknowledge bgack indicates that an external device has assumed bus mastership. reset reset system reset. halt halt indicates that the processor should suspend bus activity. bus error berr indicates that an erroneous bus operation is being attempted. cache disable cdis dynamically disables the on-chip cache to assist emulator support clock clk clock input to the processor. power supply vcc power supply. ground gnd ground connection.
6 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm power considerations the average chip junction temperature, t j , in c can be obtained from: t j = t a + (p d ? q ja ) (1) where: t a = ambient temperature, c q ja = package thermal resistance, junction-to-ambient, c/w p d =p int +p i/o p int =i cc x v cc , watts-chip internal power p i/o = power dissipation on input and output pins-user determined for most applications, p i/o 7 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm dc electrical characteristics (v cc = 5.0 v dc 5%, gnd = 0 v dc , t a = -55 c to +125 c) notes: 1. capacitance is guaranteed by design but not tested. characteristics symbol min max unit input high voltage v ih 2.0 vcc v input low voltage v il gnd 0.8 v -0.5 input leakage current berr, br, bgack, clk, ipl 0 - 2 , avec, i in -4 4.0 m a gnd v in vcc cdis, dsack0, dsack1 halt, reset -20 20 high-z (off state) leakage current a 31-0 , as, dben, ds, d 31-0 , fc 2-0 i tsi -20 20 m a r/w, rmc, siz 1-0 output high voltage a 31-0 , as, bg, d 31-0 , dben, ds, ecs, r/w, ipend, v oh 2.4 - v ocs, rmc, siz 1-0 , fc 2-0 output low voltage v ol v i ol = 3.2 ma a 31-0 , fc 2-0 , siz 1-0 , bg, d 31-0 -0.5 i ol = 5.3 ma as, ds, r/w, rmc, dben, ipend - 0.5 i ol = 2.0 ma ecs, ocs - 0.5 i ol = 10.7 ma halt, reset - 0.5 maximum supply current i cc - 333 ma capacitance (1) c in -20pf v in = 0v, t a = 25 c, f = 1mhz load capacitance ecs, ocs c l -50pf all other 130 ac electrical specifications C clock input (see fig. 5) characteristic specification 16.67 mhz 20 mhz 25mhz unit min max min max min max frequency of operation 8 16.67 12.5 20 12.5 25 mhz cycle time 1 60 125 50 80 40 80 ns clock pulse width 2,3 24 95 20 54 19 61 ns rise and fall times 4,5 C5C5C4ns note: timing measurements are referenced to and from a low 0.8v and a high voltage of 2.0v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8v and 2.0v. 2 3 1 5 4 2.0 v 0.8 v fig.5 clock input timing diagram
8 white microelectronics ? phoenix, az ? (602) 437-1520 ac electrical specifications C read and write cycles (v cc = 5.0 v dc 5%, gnd = 0 v dc , t a = -55 c to +125 c) characteristic specification 16.67 mhz 20 mhz 25 mhz unit min max min max min max clock high to address, fc, size, rmc valid 6 0 30 0 25 0 25 ns clock high to ecs, ocs asserted 6a 0 20 0 15 0 12 ns clock high to address, data, fc, size, rmc, high impedance 7 0 60 0 50 0 40 ns clock high to address, fc, size, rmc invalid 8 0 - 0 - 0 - ns clock low to as, ds asserted 9 1 30 1 25 1 18 ns as to ds assertion (read) (skew) 9a (1) -15 15 -10 10 -10 10 ns as asserted to ds asserted (write) 9b (11) 37 - 32 - 27 - ns ecs width asserted 10 20 - 15 - 15 - ns ocs width asserted 10 20 - 15 - 15 - ns ecs, ocs width negated 10b (7) 15 - 10 - 5 - ns address, fc, size, rmc, valid to as (and ds asserted read) 11 15 - 10 - 6 - ns clock low to as, ds negated 12 0 30 0 25 0 15 ns clock low to ecs, ocs negated 12a 0 30 0 25 0 15 ns as, ds negated to address, fc, size, rmc invalid 13 15 - 10 - 10 - ns as (and ds read) width asserted 14 100 - 85 - 70 - ns ds width asserted write 14a 40 - 38 - 30 - ns as, ds width negated 15 40 - 38 - 30 - ns ds negated to as asserted 15a (8) 35 - 30 - 25 - ns clock high to as, ds, r/w invalid, high impedance 16 - 60 - 50 - 40 ns as, ds negated to r/w invalid 17 15 - 10 - 10 - ns clock high to r/w high 18 0 30 0 25 0 20 ns clock high to r/w low 20 0 30 0 25 0 20 ns r/w high to as asserted 21 15 - 10 - 5 - ns r/w low to ds asserted (write) 22 75 - 60 - 50 - ns clock high to data out valid 23 - 30 - 25 - 25 ns ds negated to data out invalid 25 15 - 10 - 5 - ns ds negated to dben negated (write) 25a (9) 15 - 10 - 5 - ns data out valid to ds asserted (write) 26 15 - 10 - 5 - ns data-in valid to clock low (data setup) 27 5 - 5 - 5 - ns late berr/halt asserted to clock low setup time 27a 20 - 15 - 10 - ns as, ds negated to dsackx, berr, halt, avec negated 28 0 80 0 65 0 50 ns ds negated to data-in invalid (data-in hold time) 29 0 - 0 - 0 - ns ds negated to data-in (high impedance) 29a - 60 - 50 - 40 ns dsackx asserted to data-in valid 31 (2) - 50 - 43 - 32 ns dsackx asserted to dsackx valid (dsack asserted skew) 31a (3) - 15 - 10 - 10 ns reset input transition time 32 - 1.5 - 1.5 - 1.5 clks clock low to bg asserted 33 0 30 0 25 0 20 ns clock low to bg negated 34 0 30 0 25 0 20 ns br asserted to bg asserted (rmc not asserted) 35 1.5 3.5 1.5 3.5 1.5 3.5 clks bgack asserted to bg negated 37 1.5 3.5 1.5 3.5 1.5 3.5 clks wc32p020-xxm
9 white microelectronics ? phoenix, az ? (602) 437-1520 notes: 1. this number can be reduced to 5ns if strobes have equal loads. 2. if the asynchronous setup time (#47a) requirements are satisfied, the dsackx low data setup time (#31) and dsackx low to berr low setup time (#48) can be ignored. the data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle, and berr must only satisfy the late berr low to clock low setup time (#27a) for the following clock cycle. 3. this parameter specifies the maximum allowable skew between dsack0 to dsack1 asserted or dsack1 to dsack0 asserted; specifica tion #47a must be met by dsack0 or dsack1. 4. this specification applies to the first (dsack0 or dsack1) dsackx signal asserted. in the absence of dsackx, berr is an async hronous input setup time (347a). 5. dben may stay asserted on consecutive write cycles. 6. the minimum values must be met to guarantee proper operation. if this maximum value is exceeded, bg may be reasserted. 7. this specification indicates the minimum high time for ecs and ocs in the event of an internal cache hit followed immediately by a cache miss or operand cycle. 8. this specification guarantees operation with the 68881/68882, which specifies a minimum time for ds negated to as asserted. w ithout this specification, incorrect interpretation of specifications #9a and #15 would indicate that the wc32p020-xxm does not meet the 68881/68882 requirements. 9. this specification allows a system designer to guarantee data hold times on the output side of data buffers that have output enable signals generated with dben. 10.these specifications allow system designers to guarantee that an alternate bus master has stopped driving the bus when the 6 8020 regains control of the bus after an arbitration sequence. 11.this specification allows system designers to qualify the cs signal of an 68881/68882 with as (allowing 7 ns for a gate dela y) and still meet the cs to ds setup time requirement. ac electrical specifications C read and write cycles (cont.) characteristic specification 16.67 mhz 20 mhz 25mhz unit min max min max min max bgack asserted to br negated 37a (6) 0 1.5 0 1.5 0 1.5 clks bg width negated 39 90 - 75 - 60 - ns bg width asserted 39a 90 - 75 - 60 - ns clock high to dben asserted (read) 40 0 30 0 25 0 20 ns clock high to dben negated (read) 41 0 30 0 25 0 20 ns clock high to dben asserted (write) 42 0 30 0 25 0 20 ns clock high to dben negated (write) 43 0 30 0 25 0 20 ns r/w low to dben asserted (write) 44 15 - 10 - 10 - ns dben width asserted read 45 (5) 60 - 50 - 40 - ns write 120 - 100 - 80 - r/w width valid (write or read) 46 150 - 125 - 100 - ns asynchronous input setup time 47a 5 - 5 - 5 - ns asynchronous input hold time 47b 15 - 15 - 10 - ns dsackx asserted to berr, halt asserted 48 (4) - 30 - 20 - 18 ns data out hold from clock high 53 0 - 0 - 0 - ns r/w valid to data bus impedance change 55 30 - 25 - 20 - ns reset pulse width (reset instruction) 56 512 - 512 - 512 - clks berr negated to halt negated (rerun) 57 0 - 0 - 0 - ns bgack negated to bus driven 58 (10) 1 - 1 - 1 - clks bg negated to bus driven 59 (10) 1 - 1 - 1 - clks wc32p020-xxm
10 white microelectronics ? phoenix, az ? (602) 437-1520 note: timing measurements are referenced to and from a low 0.8v and a high voltage of 2.0v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8v and 2.0v. fig. 6 read cycle timing diagram wc32p020-xxm
11 white microelectronics ? phoenix, az ? (602) 437-1520 note: timing measurements are referenced to and from a low 0.8v and a high voltage of 2.0v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8v and 2.0v. fig. 7 write cycle timing diagram wc32p020-xxm
12 white microelectronics ? phoenix, az ? (602) 437-1520 note: timing measurements are referenced to and from a low 0.8v and a high voltage of 2.0v, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8v and 2.0v. fig. 8 bus arbitration timing diagram wc32p020-xxm
13 white microelectronics ? phoenix, az ? (602) 437-1520 fig. 10 132 lead, ceramic quad flat pack, cqfp (q2) all linear dimensions are millimeters and parenthetically in inches pin 1 27.43 (1.080) sq 0.12 (0.005) 0.25 (0.010) 0.04 (0.002) 0.64 (0.025) 22.36 (0.880) 0.50 (0.020) sq 4.13 (0.162) 0.19 (0.007) 0.17 (0.006) 0.04 (0.001) 27.43 (1.080) 0.12 (0.005) 4.13 (0.162) 0.19 (0.007) 0.64 (0.025) min 0.64 (0.025) 0.13 (0.005) 0 - 8 detail a detail a 0.76 (0.030) 0.12 (0.005) 20.32 (0.800) ref wc32p020-xxm fig. 9 114 pin grid array, pga (p2) all linear dimensions are millimeters and parenthetically in inches 34.55 (1.360) 0.50 (0.020) sq. 2.54 (0.100) 3.18 (0.125) 0.64 (0.025) 4.64 (0.182) 0.32 (0.012) n m l k j h g f e d c b a 1 2 3 45 6 7 8 910 11 12 13 0.49 (0.019) 0.06 (0.002) 2.54 (0.100)
14 white microelectronics ? phoenix, az ? (602) 437-1520 wc32p020-xxm w c 32 p020 - x x m device grade: m = military temperature -55 c to +125 c package: q2 = 132 lead ceramic quad flatpack, cqfp p2 = 114 pin ceramic pga operating frequency in mhz 68020 32 bit wide microcontroller white microelectronics ordering information
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