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1 of 28 december 14, 2001 ? 20 01 integrated device techno logy, in c. dsc 5607 i dt and the i dt lo go are re giste re d tra dema rks o f i nte grate d de vice te chno log y, i nc. advanced 64-bit microprocessors product family features features features features high-performance 64-bit embedded microprocessor ? 250mhz operating frequency ? >33 0 dhrysto ne mip s pe rf orman ce ? 300mflops/s floating-point performance ? up to 125 million multiply accumulate per second (mac/s) ? mips-iv i nst ruction set archit ecture (isa), with integer dsp an d 3-o pe ran d in te ge r multip ly ex ten sion s ? limite d du al-issue microa rchite ctu re compatible with rc4640 and rc32364 dsp extensions ? dsp extensions, for consumer applications ? 2-cycle repeat rate, on atomic multiply-add ? multiply-subtract (msub) support, for complex number pro ces sin g ? count-leading-zero/one support, for string searches and no rmalizat ion high-performance on-chip cache subsystem ? 32kb, two-set ass ociative instruction cache (i-cache) ? 32kb, two-set associative data cache (d-cache) ? write -thro ug h an d write -ba ck d at a c ach e op era tion s ? high-performance cache-ops, bandwidth management i -cache and d-cache locki ng capability (per line), provides improved real-time support joint tlb on-chip, for virtual-to-physical address mapping big- or little-endian capability rc5000 compatible memory management ? on-chip 48-entry, 96-page tlb, for advanced operating system support ? compatible with major operating systems: windows ? ce, vxworks, and others bus compatible with idt 64-bit microprocessor families ? pip elin e ru ns at 2 to 8 t ime s t he b us f re q ue ncy ? bus speeds to 125mhz ? 32-bit bus option, for lower cos t systems ? enhanced timing protocol for syncdram systems (compatible with idt79rc64474/475) rc64574: ? 32-bit sysad bus, for low-cost systems ? pin compatible with rc4640 and rc64474 ? 12 8 -p in qfp pa cka ge rc64575: ? 64 -bit sysa d bu s in terfa ce ? pin compatible with rc4650 and rc64475 ? 20 8 -p in qfp pa cka ge industrial temperature range support jtag boundary scan interface 2.5v operation with 3.3v tolerant i/o block block block block di di di diagra agra agra agram m m m figure 1 rc64574/rc64575 block diagra m 64-bit integer ds p accelerator execution unit 666 mfiops floati ng-poi nt accelerator pll dual-issue instruction fetch unit primary cache controller rc5000 compatible system control coprocessor 48-entry 96-page tlb 32kb 2 set-associative instruction cache 32kb 2 set-associative data cache 64-bit/32-bit rc64474/475 compatible system interface cl ki n (lockable) (lockable) ieee 1284 79rc64574 ? 79rc64575 ?
2 of 28 december 14, 2001 79rc64574? 79rc64575? device overview device overview device overview device overview 1 1 1 1 idt?s 79rc64574/575 processors serve a wide range of perfor- mance-critical embedded applications that include high-end internet- working systems, digital set-top boxes, web browsers, color printers, an d gra ph ic s te rmin als. the rc64574/575 allow a socket compatible upgrade path for idt?s rc4640/50 and rc64474/475 processors. this unprecedented upgrad- ability allows a 2:1 range of frequencies; 4:1 range of cache size; 15:1 range of floating-point; and 4:1 range of dsp performance in a single soc ket. with special emphasis on system bandwidth, floating- point and dsp operations, the rc64574/575 have been optimized for high-perfor- mance applications through the integration of high-performance compu- ta tion al un its an d a hig h-p erfo rma nce me mory hie ra rchy. the res ult is a low-cost cpu that is capable of more than 330 dhrystone mips. thro ug h the rc6 45 74 /6 45 75 p ro ce ssors idt o ffe rs: hig h-p erfo rma nce u pg rad e pa th s to e xisting e mbe dd ed c ust omers in th e int erne two rk in g, o ffice au to matio n an d visualization markets. s ign ifican t floa ting -po int pe rforma nce impro veme nts ove r currently available, moderately priced mips cpus. p erfo rman ce imp rove men ts t hro ug h t he u se of th e mi ps-iv is a. high-performance dsp acceleration 1. detailed system operation information is provided in the rc64574/rc64575 us er ?s m an ua l . instruction issue mechanism instruction issue mechanism instruction issue mechanism instruction issue mechanism the rc64574 and rc64575 are limited dual-issue super-scalar machines that use a traditional 5-stage integer pipeline, as shown in the pipeline diagram on page 3. for multi-issue operations, these devices recognize the following two general classes of instructions: flo at ing -p oin t a lu a ll ot he rs such a broad separation of instruction classes insure that there are no data dependencies to restrict multi-issue performance. as they are bro ug ht on -chip , th es e in struct ion classe s a re p re-de co de d by t he rc64574/575, and the class information is then stored in the instruction cache. assuming there are no pending resource conflicts, the devices can issue one instruction per class per pipeline cloc k cycle. however, longer latency resources?in either the floating-point alu (f or e xamp le, division o r sq u are ro ot inst ru ctio ns) o r in te ge r un it (such a s multiply)?can restrict the issue of instructions. note that these proces- sors do not perform out-of-order or speculative execution; instead, the pipeline slips until the required resource becomes available. on dual-issue instruction pairs, there are no alignment restrictions, and the rc64574/575 fetch two instruc tions from the cache per cycle. thus, for optimal performance, compilers should attempt to align branch targets to allow dual-issue on the first target cycle, bec ause the instruc- tion cache only performs aligned fetches. riscore4000/riscore5000 family of socket compatible processors riscore4000/riscore5000 family of socket compatible processors riscore4000/riscore5000 family of socket compatible processors riscore4000/riscore5000 family of socket compatible processors 32-bit external bus processors 64-bit external bus processor s rc4640 rc64474 rc64574 rc4650 rc64475 rc64575 cpu 6 4-b it r iscor e40 00 w / d sp exten sio ns 6 4-b it r iscor e40 00 6 4-b it r isco re50 00 w / d sp exten sio ns 64-b it risco re4 000 w/ dsp exten sio ns 64-b it risco re4 000 64 -bi t risc ore5 00 0 w/ dsp e xte nsi ons performance >350mips >330mips >330mips >350mips >330mips >330mips fpa 89 mflops, single preci- sion only 125 mflops, single and double precision 666 mflops, single and d ou ble prec isio n 89 mflo ps, sing le p reci - sion only 125 m fl ops , sin gl e an d dou bl e pre cisio n 66 6 mflop s, si ng le an d do ub le pre cisi on caches 8kb/8kb, 2-way, lockable by set 16kb/16kb, 2-way, lockable by set 3 2kb/3 2kb, 2-wa y, locka bl e by li ne 8kb/8kb, 2-w ay, locka bl e by set 16kb /1 6kb, 2-w ay, locka bl e by set 32 kb/32kb , 2-w ay, lockable by line external bus 32-bit 32-bit, superset pin compatible w/rc4640 32-bit, superset pin co mpa tibl e w/rc 46 40 , rc64474 32- o r 6 4-b it 32-o r 64-b it, su pe rset pin compatible w/ rc4 65 0 32 -or 64 -bit, sup erse t pi n comp atib le w / rc 46 50, rc 64 475 voltage 3 .3 v 3 .3 v 2 .5v 3.3v 3.3v 2.5v frequencies 1 00 -267 mhz 1 80 -250 mhz 2 00 -25 0 mhz 100 -26 7 mhz 180 -25 0 mhz 25 0 mhz packages 128 pqfp 128 qfp 128 qfp 208 qfp 208 qfp 208 qfp mmu ba se-bo un ds 9 6 pa ge tlb 9 6 pa ge tlb base -boun ds 96 pa ge tl b 96 p ag e tlb k e y fe at ure s c ach e lo cking , o n-ch ip mac, 32-bit external bus c ache locking, jtag, syncdr am mode, 32-bit external bus c ache locking, jtag, sy ncdr am m ode , 32 -bit external bus cache locking, on-chip mac, 32-b it & 6 4 bi t bus o ption cache locking, jtag, syncd ram mode, 32- 64- b it b us op ti on cache locking, jtag, syncd ram mode, 32- 64- bit bus option table 1 riscore4000/ riscore 5000 proce ssor family
3 of 28 december 14, 2001 79rc64574? 79rc64575? instruction set architecture instruction set architecture instruction set architecture instruction set architecture the rc64 57 4/ 57 5 imple men t a su pe rset of t he mi ps -i v 64 -bit i sa, including cp1 and cp1x functional units and their instruction set. both 32- and 64-bit data operations are performed by utilizing thirty-two general purpose 64-bit registers (gpr) that are used for integer opera- tions and address calculation. the complete on-chip floating-point co- processor (cp1)?which includes a floating-point register file and execu- tion units?forms a ?seamless? interface, decoding and executing instructions in parallel with the integer unit. cp1?s floating-point execution units su pp ort b ot h sing le a nd double precision arithmetic?as specified in the ieee standard 754? and are separated into a multiply unit and a combined add/convert/ divid e/s qu are ro ot un it. o verlap of multip lie s a nd ad d/ sub trac t is supported, and the multiplier is partially pipelined, allowing the initiation of a new multiply ins truction every fourth pipeline cycle. the floating- point register file is made up of thirty-two 64-bit registers. the floating- point unit can take advantage of the 64-bit wide data cache and issue a co-processor load or store doubleword instruction in every c ycle. the system control coprocessor (cp0) registers are also incorpo- rated on-chip and provide the path through which the virtual memory system?s page mapping is ex amined and changed, exc eptions are ha nd led , an d an y op era ting mo de s elec tion s a re con tro lle d. a se cure use r p roce ssing en viro nme nt is provided through the user, supervisor, and kernel operating modes of virtual addressing to system s oftware. bits in a st atu s re giste r de te rmin e which of th ese mo de s is u se d. integer pipeline integer pipeline integer pipeline integer pipeline the integer instruction execution speed is tabulated?in number of pipeline clocks?as follows: table 2 int eger in stru ctio n exe cut ion speed to insure that the maximum frequency of operation is not limited by the speed of the multiplier unit, a ?fast multiply? disable reset mode bit (s ee ta ble 2 ) is fe at ured . wh en t his b it is asse rte d, ea ch multip ly o pe ra - tion shown in table 1 has its latency and repeat rate increased by one cycle. operation latency repeat load 2 1 store 2 1 mult/multu 4 3 dmult/dmu ltu 6 5 div/divu 36 36 ddiv/d divu 68 68 mad/madu 3 2 msub/msubu 4 3 othe r intege r alu 1 1 branch 2 2 jum p 2 2 load and branch latencies are minimized by the short pipeline of the rc64574/575, and the caches contain special logic that will allow any combination of loads and stores to execute in bac k-to-back cycles without requiring pipeline slips or stalls, assuming the operation does not miss in the cache. computational units computational units computational units computational units the rc64574/575 implement a full, single-cycle 64-bit arithmetic logic unit (alu), for integer alu functions other than multiply and divid e. byp ass in g is us ed to su pp ort b a ck-to-b ack al u op era tion s a t t he full pipeline rate, without requiring stalls for data dependencies. to allow the longer latency operations to run in parallel with other operations, the integer mul ti ply/divide unit of the rc64574/ 575 is separated from the primary alu. the pipeline stalls only if an attempt to access the hi or lo registers is made before an operation completes. the floating-point alu u n it is resp on sible f or all of th e cp 1/cp 1x alu operations?other than div/sqrt operations?and is pipelined to allow a single-cycle repeat rate for single-precision operations. the floating-point div/sqrt unit is s eparated from the floating- point alu, to ensure that these longer latency operations do not prevent the issue of other floating-point operations. separate logical units are also p ro vide d on th e rc6 45 7 4/5 75 to imple men t lo ad , st ore, an d bra nch op era tion s. in ten d ed to en ha nc e th e pe rf orman ce of dsp algo rithms s uch as fast fused multiply-adds, multiply-subtracts and three operand multiply oper- ations , new instructions have been added over and above the mips-iv isa. system interfaces system interfaces system interfaces system interfaces the rc6 45 75 supports a 64-bit system interface th at is pin a nd bus compatible with the rc4650 and rc64475 system interface. the system interface consists of a 64-bit address/data bus with eight parity- check bits and a 9-bit command bus. during 64-bit operation, rc64575 system address/data (sy sad) transfers are protected with an 8-bit parity check bus, sysadc. when initialized for 32-bit operation, the rc64575?s sysad can be viewed as a 32-bit multiplexed bus that is protected by four parity-check bits. the rc64574 supports a 32 -bit sy stem interfa ce th at is p in a nd bus compatible with the rc4640 and rc64474. during 32-bit operation, sysad transfers are performed on a 32-bit multiplexed bus (sysad 31:0) that is protected by 4 parity check bits (sysadc 6:0). writes to external memory?whether they are cache miss write- backs, stores to uncached or write-through addresses?use the on-chip write buffer . the write buffer holds a maximum of four 64-bit addresses and 64-bit data pairs. the entire buffer is used for a data cache write- ba ck an d a llo ws t he p roce sso r to proc ee d in pa rallel with me mo ry up da te s. included in the system interface are six handshake signals : rdrdy*, wrrdy* , extrqst*, release*, validout* , and validin*; six i nte r- rupt inputs, an d a simple ti ming specification that is capable of trans-
4 of 28 december 14, 2001 79rc64574? 79rc64575? ferring data between the processor and memory at a peak rate of 1000mb/sec. a boot-time selectable option to run the system interface as 32-bits wide?using basically the same protocols as the 64-bit system?is als o s upported. a boot-time mode control interface initializes fundamental processor modes and is a serial interface that operates at a very low freq ue n cy (s ysclock d ivide d b y 25 6). th is lo w-freq ue ncy o pe rat io n allows the initialization information to be kept in a low-cost eprom; alternatively, the twenty-or-so bits could be generated by the system interface asic or a simple pal. the boot-time serial stream is shown in tab le 3. serial bit description value & mode setting 0 reserved must be set to 0. 1:4 transmit-dat a- patte rn. bit 4 is msb 64-bit bus width: 0: d ddd 1: d dxddx 2: ddxxddxx 3: dxdxdxdx 4: ddxxxddxxx 5: ddxxxxddxxxx 6: dxxdxxdxxdxx 7: ddxxxxxxddxxxxxx 8: dxxxdxxxdxxxdxxx 9-15: reserved . must not be selecte d. 32-bit bus width: 0: wwwwwwww 1: wwxwwxwwxwwx 2: wwxxwwxxwwxxwwxx 3: wxwxwxwxwxwxwxwx 4: wwxxxwwxxxwwxxxwwxxx 5: wwxxxxwwxxxxwwxxxxwwxxxx 6: wx x wxx wx xwx x wxx wx xwx x wxx 7: wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx 8: wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx 9-15: reserved . must not be selecte d. 5:7 pclock-to- sysclk-ratio. bit 7 is msb 0: 2 1: 3 2: 4 3: 5 4: 6 5: 7 6: 8 7: rese rved 8 endianness 0: little endian 1: big endian 9:1 0 non-block write mod e. bit 10 is msb 00: r4400 compatible 01: reserved 10: pipelin ed-write-mode 11: writ e-re issue-mod e table 3 boot-time mode stream (pa ge 1 of 2) the clocking interface allows the cpu to be easily mated with ex ternal reference clocks. the cpu input clock is the bus reference clock and can be between 33 and 125mhz. an on-chip phase-locked- loop (pll) generates the pipeline clock (pclock) through multiplication of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at system reset. this allows the pipeline c lock to be implemented at a significantly higher frequency than the system interface clock. the rc64574/575 support both single data (one byte through full cpu bus width) and 8-word block transfers on the sysad bus. the rc64574/575 implement additional write protocols that double the effective write bandwidth . th e writ e re -iss ue h as a re pe at rate of 2 cycles per write. pipelined writes have the same 2-cycle per writ e rep ea t rat e, b ut ca n issu e a n a dd it ion al writ e af te r wrrd y* de - as serts. 11 timerinten timer inte rru pt se tting s: 0: enable timer interrupt on int(5) 1: disable timer interrupt on int(5) 12 system inte rface bus width. interface bus wid th co ntrol settin gs: 0: 64-bit system interface 1: 32-bit system interface 13:14 drv_out bit 14 is msb slew rate cont rol of the outp ut drivers: 10: 100% strengt h (fastest) 11: 83% strength 00: 67% strength 01: 50% strength (slowest) 15:17 write address to write d ata delay. from 0 to 7 sysclk cycles: 0: ad... 1: axd... 2: axxd... 3: axxxd... 4: axxxxd... 5: axxxxxd... 6: axxxxxxd... 7: axxxxxxxd... 18 reserved user m ust select ?0? 19 ext end mul tip li ca tion repea t rate. initial setting of the ?fast multiply? bit. 0: enable fast m ultiply 1: do n ot enable fast multiply note: for pipeline speeds >25 0mhz, this b it must be set to ?1?. 20:24 reserved user m ust select ?0? 25:26 system config uration id entif ier . software visible in processorconfig[21:20] 0: con fig[21 :20] = mo de bit [2 5:26] must be set to 0. 27:256 reserved user m ust select ?0? serial bit description value & mode setting table 3 boot-time m ode stream (page 2 of 2)
5 of 28 december 14, 2001 79rc64574? 79rc64575? choosing a 32- or 64-bit wide system interface dictates whether a cac he line block transaction requires 4 double word data cycles or 8 sing le wo rd cyc le s a s well a s wh eth er a sin gle da ta tran sfe r?large r th an 4 bytes?must be divided into two smaller transfers. as shown in table 3, the bus delay can be defined as 0 to 7 sysclock cycles and is activated and controlled through mode bit (1 7 :15 ) s ett in g s se lect ed du rin g th e res et init ia lizatio n se qu en ce . the ?000? setting provides the same write operations timing protocol as the rc4640, rc4650, and rc5000 processors. to facilitate discrete interface to syncdram , the rc64574/575 bus interface is enhanced during write cycles with a programmable delay th at is in se rt ed be twe en th e write ad dre ss an d the write d a ta (fo r bo th block and non-block writes). board-level testing during run-time mode is facilitated through the full jtag boundary scan facility. five pins?tdi , tdo, tms, tck, trst*? ha ve b ee n inc orpo rat ed t o su pp ort th e st an da rd jta g int er- face. the rc64 5 74 /57 5 de vices off er a direct migrat io n pa th fo r de sign s th at are b ase d on idt?s rc4 64 0 /rc46 50 a nd rc6 44 74 /rc6 44 75 pro cesso rs 2 , through full pin and socket compatibility. full 64-bit-family sof tware a nd b us pro toc ol co mpa tib ility en su re s t he rc6 45 74 /5 75 pro cesso rs acce ss to a n e xisting ma rket a nd de velo pme nt in frast ru c- ture, allowing quicker time to market. development tools development tools development tools development tools an array of hardware and software tools is available to assist system designers in the rapid development of rc64574/575 based systems. this access ibility allows a wide variety of cus tomers to take full advan- tage of the device?s high-performance features while addressing today?s ag gre ssive time-to -ma rket de man ds. cache memor y cache memor y cache memor y cache memor y to keep the high-performance pipeline of the rc64574/575 full and op era ting e fficie ntly, o n -ch ip instru ctio n an d da ta ca che s h av e be en incorporated. each cache has its own data path and can be accessed in the s ame single pipeline cloc k cycle. the 32k b two-way set associative instruction cache is virtually ind exe d, p hysica lly ta gg ed , an d wo rd pa rit y p ro te cte d. be cau se th is cac he is virtually indexed, the virtual-to-physical address translation occ urs in p aralle l with th e cach e acc ess, fu rthe r incre asin g pe rforma nce by allowing both operations to occur simultaneously. the instruction cache provides a peak instruction bandwidth of 2gb/sec at 250mhz. the 32kb two-way set assoc iative data cache is byte parity pro tec ted a nd ha s a fixe d 32 -b yte (eig ht words ) lin e s ize . i ts t ag is protected with a single parity bit. to allow simultaneous address transla- tion an d da ta c ach e ac cess, t he d-ca che is virtua lly in de xed an d ph ysi- cally tagged. the data cache can provide 8 bytes each clock cycle, for a pe ak ba nd widt h o f 2gb /s. 2. to ensure socket compatibility, refer to table 8 and table 9. to lock critical sections of code and/or data into the caches for quick access, a per line ?cache locking? feature has been implemented. once enabled, a cache is said to be locked when a particular piece of cod e or da ta is lo ad ed in to th e cach e a nd th at ca che lo cat ion will no t be selected later for refill by other data. power management power management power management power management executing the wait instruction enables the processor to enter standby mode. the internal c locks w ill shut down, thus freezing the pipeline. the pll, internal timer, and some of the input pins (int[5:0]*, nmi*, extreq*, reset*, and coldreset*) will continue to run. once in standby mode, any interrupt, including the internally generated timer interrupt, will cause the cpu to exit standby mode. thermal considerations thermal considerations thermal considerations thermal considerations the rc64574 is packaged in a 128-pin qfp footprint package and use s a 32 -bit e xte rn al bu s, o ffe rin g th e ide al co mb ina tio n of 6 4-b it processing power and 32-bit low-cost memory systems. the rc64575 is packaged in a 208-pin qfp footprint package and uses the full 64-bit external bus. the rc64575 is ideal for applications requiring 64-bit performance and 64-bit external bandwidth. both devices are guaranteed in a case temperature range of 0 to +85 c for commercial temperature devices and -40 to +85 c for industrial temperature devices. package type, speed (power) of the de vice, an d air flow c on ditio ns a ffe ct t he eq u iva len t a mbie nt temp era ture con d it io n s th at will me et th es e sp e cif icat io ns . using the thermal resistance from case to ambient ( ? ca ) o f t he given package, the equivalent allowable ambient temperature, t a , can be calculated. the following equation relates ambient and case temper- at ures : t a = t c - p * ? ca whe re p is th e ma ximum po wer co nsu mptio n a t h ot t emp erat ure, calcu lat ed by u sing th e ma ximu m i cc specification for the device. typical values for ? ca at various air flow are shown in table 4. note th at th e rc64 57 4/ 57 5 pro cesso r imple men ts ad van ce d po wer ma na ge - ment, which substantially reduces the typical power dissipation of the device. revision history revision history revision history revision history july 22, 1999: original data sheet. ? ca airflow (ft/min) 0 200 400 600 800 1000 1 28 qfp 16 10 9 7 6 5 2 08 qfp 20 13 10 9 8 7 table 4 thermal resis tance ( ? ca) at various ai rflows
6 of 28 december 14, 2001 79rc64574? 79rc64575? september 9, 1999: made s everal changes in jtag interface section of table 5. added information on pin 63 in table 5. october 14, 1999 : revise d d a ta in th e po wer co nsu mpt io n ta bles for rc64574 and rc64575. november 16, 1999 : a dd e d po wer cu rve gra ph s, re vise d da ta in system interface parameters table, added system clock jitter row to clock parameter table. december 20, 1999 : table 7 ?rc64574 128-pin package? on page 12, changed pin #75 function from vcc to n.c. marc h 7 , 20 00 : in table 1, added ?with dsp extensions? in the cpu row under rc64574 and rc64575 columns and changed ?by set? to ?by line? in the caches row for rc64574 and rc64575 columns. added rows in the data out put and data output hold rows in the syst em i nt er- fa ce pa rame ters ta ble . remo ved re fe re n ces to 30 0 mhz, an d ch an ge d ba nd widt h sp ee d t o 2 gb /sec on d in ca ch e me mo ry sect ion . re v ise d power curves. marc h 2 8, 20 00 : replaced existing figure in mode configuration interface reset sequence section with 3 reset figures. revised values for 250mhz in system interface parameters table. changed data sheet from preliminary to final. april 3, 2000 : deleted signal t dz from figure 6. april 25, 2001 : in the absolute maximum ratings table, changed upper voltage limit from 3.8 to 4.0v and removed ?vin should not exceed vcc +0.5 volts? from footnote #1. in dc electrical characteristics table, changed maximum value for vih from 3.3 to 3.8v for all speeds. may 1, 2001 : in the data output hold category of the system inter- face parameters table, changed values in the min column for all speeds from 1.0 to 0. in the electrical characteristics table, values were added to the system clock jitter row. added industrial temperature range of -4 0 c to +85 c. december 14, 2001 : in absolute maximum ratings table, changed the industrial low-end temperature for symbol tc to read -40 degrees instead of 0 degrees.
7 of 28 december 14, 2001 79rc64574? 79rc64575? pin description table pin description table pin description table pin description table the following is a list of system interface pins available on the rc64574/575. pin names ending with an asterisk (*) are active when low. pin name type description sys tem interface extrqst* i external re quest an e xternal agent asserts extrqst* to requ est use of th e system interface . the processor grant s the request b y asserting release*. rele ase* o release interface in response to the a ssert ion o f extrqst* or a cpu read request, the p rocessor asserts release* and signa ls to the req uesting de vice that the syste m int erface is a vailable . rdrdy* i read ready the external a gent asserts rdrd y* to indicate that it can accept a processor read req uest . wrrdy* i write ready an e xternal agent asserts wrrdy* when it can now accept a processor write request. validin* i vali d input signals that an extern al age nt is now d riving a valid ad dress or data o n the sysad bu s and a valid co mmand o r data identifier on the syscm d bus. validout* o valid output signals that the processor is now driving a valid addre ss or data on the sysad bus and a valid co mmand or d ata id entifier on the syscmd bus. sysad(63 :0) i/o sys tem address/data bus a 64 -bit address and d ata bus for comm unication between the processor and an external agent. in 64 bit interface mode, during address phases only, sysad(35:0 ) contains invalid address in formation. the remain- ing sysad(63: 36) pins are n ot used. the whole 64-bit sysad(63 :0) may be u sed d uring the dat a transfer p hase . for all dou ble-word accesse s (read or write), the low-order 3 bits (sysad[2:0]) will always be out put as zero during the address phase. in 32-bit interfa ce m ode and in the rc64574, sysad(63:32) is not used, regard less of endianness. a 3 2-bit a ddress and data commu nication between pro cessor an d ext ernal agent is perf ormed via sysad(31:0). sysadc(7:0) i/o sys tem address/data check bus an 8 -bit bus co ntain ing p arity check bits for the sysad bus during da ta bus cycles. in 32-bit mode and in the rc64574, sysadc(7:4) is not used. the sysadc(3:0) contain s check bits for sysad(31:0). syscmd(8:0) i/o sys tem command/ data identifier bus a 9-bit bus for comma nd and data identifier transmission betwee n the processor a nd an externa l age nt. syscmdp i/o sys tem command parity a single, even-parit y bit for the syscmd bus. this signal is always d riven low. clock/ control interface sysclock i systemclock the system clock input e stablish es the processo r and bu s op erating frequency. it is multiplied internally by 2 ,3,4,5,6,7, or 8 to gen erate th e pip eline clock (pclock). v cc pi qu iet vc c fo r pll quiet v cc for the internal p hase locked loop. v ss pi quiet v ss for pll quiet v ss for the inte rnal phase locked loop. table 5 pin descriptions (page 1 of 2)
8 of 28 december 14, 2001 79rc64574? 79rc64575? inte rrupt interface in t*(5:0) i inte rrupt six general processor int errupts, bit-wise ored with bits 5:0 of the interrupt registe r. nmi* i non-maskable interrupt non-m askable interrupt, ored with bit 6 of the interrupt register. initi aliza tion interfa ce v cc o ki v cc is ok whe n a ssert ed, this signal in dicates to the processor that the power sup ply has be en above the vcc m inimum fo r more than 10 0 milliseconds and will remain stable. the assertion o f v cco k initiates the initialization seque nce. coldreset* i cold reset this signal must be asse rted for a power on reset or a cold rese t. coldreset must be de -asserted synchro- n ously with sysclock. reset* i reset this signal m ust be asserte d for any reset sequence. it can be asserted synchronously or a synchrono usly for a cold reset , or synchronously to initiate a warm reset . reset must be de-asserted synchronously with sysclock. m odeclock o boot-mode clock serial bo ot-mode data clock output at the system clock frequency d ivided by two hun dred fifty-six. m odein i boot-mode data in serial bo ot-mode data input. j tag interface tdi i j tag da ta in on the rising edg e of tck, se rial input d ata are shifted into either the instruction re gister or data reg ister, d epending on the tap controller state. an external pull-up resistor is required. tdo o j tag da ta out on the falling edge of tck, the tdo is serial data shifted out from eith er the instruction or data register. when n o data is shifted out, the tdo is tri-stated (high impedance). tck i j tag clock input an input te st clock used to shift into o r out of th e boundary-scan register cells. tck is inde pendent of the sys- te m and proce ssor clock with n omin al 40 -60% duty cycle . tms i j tag command select the logic signal received at the tms inp ut is decoded by the tap controller to control test operation. tms is sampled on the rising edge of tck. an extern al pu ll-up resistor is required. trst* i j tag re set the trst* pin is an active-low signal used for asynchron ous reset of the de bug unit, independent o f the pro- cessor logic. during normal cpu op eration, the jtag controller will be held in the reset mode, asserting this a ctive low pin. whe n asserted low, this pin will also tristate the tdo pin. an e xternal pull-down resistor is req uired. jtag32* i j tag 32-bit scan this pin is use d to control length of the scan chain for sysad (32-bit or 64-bit) for the jtag m ode. when set to vss, 32-bit b us m ode is select ed. in this mode, only sysad(31:0) a re part of the scan chain. when set to vcc, 64-bit bus mode is selected. in this mo de, sysad(63:0) a re part of the scan chain. this pin has a b uilt-in p ull-do wn device to guaran tee 32-b it scan, if it is le ft un connected. jr_v cc i jtag vcc this pin has an internal pull-down to continuously reset the jtag contro ller (if left uncon nect ed) bypassing th e trst* pin. when supplied with vcc, t he trst* pin will be the primary control for the jtag reset. pin name type description table 5 pin descriptions (page 2 of 2)
9 of 28 december 14, 2001 79rc64574? 79rc64575? logic diagram ? rc64574/rc64575 logic diagram ? rc64574/rc64575 logic diagram ? rc64574/rc64575 logic diagram ? rc64574/rc64575 figure 1 illustrates the direction and functional groupings for the processor signals. figure 1 logic sy mbol for rc64574/rc64575 sysad(63:0) sysclock coldreset* reset* v cc p v ss p initialization int erface interrupt system interface clock/control interface rc64574/ logic symbol 64 6 interf ace sysadc(7:0) 8 nmi * int*(5:0) jtag interface tdi tms trst* tdo ha nd sh ake s ign als rc64575 tck rdrdy* wrrdy* ex trqst * release* validin* validout* syscmd(8:0) syscmdp 9 vccok modeclock modein jtag 32 * jr_vcc
10 of 28 december 14, 2001 79rc64574? 79rc64575? rc64575 208-pin qfp package pin-out rc64575 208-pin qfp package pin-out rc64575 208-pin qfp package pin-out rc64575 208-pin qfp package pin-out pin names followed by an asterisk (*) are active when low. for maximum flexibility and compatibility with future designs, n.c. pin s sh ou ld b e left floating. pin function pin function pin function pin function 1 n.c. 53 jtag32* 105 n.c. 157 n.c. 2 n.c. 54 n.c. 106 n.c. 158 n.c. 3 n.c. 55 n.c. 107 n.c. 159 sysad59 4 n.c. 56 n.c. 108 n.c. 160 coldreset* 5 n.c. 57 syscmd 2 109 n.c. 161 sysad28 6 n.c. 58 sysad36 110 n.c. 162 v cc 7 n.c. 59 sysad4 111 n.c. 163 v ss 8 n.c. 60 syscmd 1 112 n.c. 164 sysad60 9n.c. 61v ss 113 n.c. 165 reset* 10 sysad11 62 v cc 114 sysad52 166 sysad29 11 v ss 63 sysad35 115 extrqst* 167 sysad61 12 v cc 64 sysad3 116 v cc 168 sysad30 13 syscmd 8 65 syscmd 0 117 v ss 169 v cc 14 sysad42 66 sysad34 118 sysad21 170 v ss 15 sysad10 67 v ss 119 sysad53 171 sysad62 16 syscmd 7 68 v cc 120 rdrd y* 172 sysad31 17 v ss 69 sysad2 121 modein 173 sysad63 18 v cc 70 int5* 122 sysad22 174 v cc 19 sysad41 71 sysad33 123 sysad54 175 v ss 20 sysad9 72 sysad1 124 v cc 176 v cc ok 21 syscmd 6 73 v ss 125 v ss 177 sysadc3 22 sysad40 74 v cc 126 release* 178 sysadc7 23 v ss 75 int4* 127 sysad23 179 n.c. 24 v cc 76 sysad32 128 sysad55 180 tdi 25 sysad8 77 sysad0 129 nmi* 181 trst* 26 syscmd 5 78 int3* 130 v cc 182 tck 27 sysadc4 79 v ss 131 v ss 183 tms 28 sysadc0 80 v cc 132 sysadc2 184 tdo 29 v ss 81 int2* 133 sysadc6 185 v cc p 30 v cc 82 sysad16 134 sysad24 186 v ss p 31 syscmd 4 83 sysad48 135 v cc 187 sysclock 32 sysad39 84 int1* 136 v ss 188 v cc 33 sysad7 85 v ss 137 sysad56 189 v ss tabl e 6 rc64575 208-pin qfp package pin-out (page 1 of 2)
11 of 28 december 14, 2001 79rc64574? 79rc64575? 34 syscmd 3 86 v cc 138 sysad25 190 sysadc5 35 v ss 87 sysad17 139 sysad57 191 sysadc1 36 v cc 88 sysad49 140 v cc 192 v cc 37 sysad38 89 int0* 141 v ss 193 v ss 38 sysad6 90 sysad18 142 n.c 194 sysad47 39 modeclock 91 v ss 143 sysad26 195 sysad15 40 wrrd y* 92 v cc 144 sysad58 196 sysad46 41 sysad37 93 sysad50 145 n.c. 197 v cc 42 sysad5 94 validin* 146 v cc 198 v ss 43 v ss 95 sysad19 147 v ss 199 sysad14 44 v cc 96 sysad51 148 sysad27 200 sysad45 45 n.c. 97 v ss 149 n.c. 201 sysad13 46 n.c. 98 v cc 150 jr_ v cc 202 sysad44 47 n.c. 99 validout* 151 n.c. 203 v ss 48 n.c. 100 sysad20 152 n.c. 204 v cc 49 n.c. 101 n.c. 153 n.c. 205 sysad12 50 n.c. 102 n.c. 154 n.c. 206 syscmd p 51 n.c. 103 n.c. 155 n.c. 207 sysad43 52 n.c. 104 n.c. 156 n.c. 208 n.c. pin function pin function pin function pin function tabl e 6 rc64575 208-pin qfp package pin-out (page 2 of 2)
12 of 28 december 14, 2001 79rc64574? 79rc64575? rc64574 128-pin package pin-out rc64574 128-pin package pin-out rc64574 128-pin package pin-out rc64574 128-pin package pin-out n.c. pins should be left floating for maximum flexibility as well as for compatibility with future designs. an asterisk (*) ide ntifies a pin that is active when low. pin function pin function pin function pin function 1 jtag32* 33 v cc 65 v cc 97 v cc 2 syscmd2 34 v ss 66 sysad28 98 v ss 3v cc 35 sysad13 67 coldreset* 99 sysad19 4v ss 36 sysad14 68 sysad27 100 validin* 5 sysad5 37 v ss 69 v ss 101 v cc 6wrrdy* 38v cc 70 v cc 102 v ss 7 mo declock 39 sysad15 71 jr_v cc 103 sysad18 8 sysad6 40 v ss 72 sysad26 104 int0* 9v cc 41 v cc 73 n.c. 105 sysad17 10 v ss 42 sysadc1 74 v ss 106 v cc 11 syscmd3 43 v ss 75 n.c. 107 v ss 12 sysad7 44 v cc 76 sysad25 108 int1* 13 syscmd4 45 sysclock 77 v ss 109 sysad16 14 v cc 46 v ss p78v cc 110 int2* 15 v ss 47 v cc p 79 sysad24 111 v cc 16 sysadc0 48 tdo 80 sysadc2 112 v ss 17 syscmd5 49 tms 81 v ss 113 int3* 18 sysad8 50 tck 82 v cc 114 sysad0 19 v cc 51 trst* 83 nmi* 115 int4* 20 v ss 52 tdi 84 sysad23 116 v cc 21 syscmd6 53 v ss 85 release* 117 v ss 22 sysad9 54 sysadc3 86 v ss 118 sysad1 23 v cc 55 v cc ok 87 v cc 119 int5* 24 v ss 56 v ss 88 sysad22 120 sysad2 25 syscmd7 57 vcc 89 modein 121 v cc 26 sysad10 58 sysad31 90 rdrd y* 122 v ss 27 syscmd8 59 v ss 91 sysad21 123 syscm d0 28 v cc 60 v cc 92 v ss 124 sysad3 29 v ss 61 sysad30 93 v cc 125 v cc 30 sysad11 62 sysad29 94 extrqst* 126 v ss 31 syscmdp 63 rese t* 95 sysad20 127 syscm d1 32 sysad12 64 v ss 96 validout* 128 sysad4 table 7 rc6457 4 128-pin package
13 of 28 december 14, 2001 79rc64574? 79rc64575? rc64574 socket compatibility to rc64474 & rc4640 rc64574 socket compatibility to rc64474 & rc4640 rc64574 socket compatibility to rc64474 & rc4640 rc64574 socket compatibility to rc64474 & rc4640 the rc64574/575 is 100% pin compatible with the rc64474/475 with the supply voltage being the only difference. rc64474/475 requ ires a 3.3v sup p ly, wh ile rc6 45 74 /5 75 req u ire s a 2. 5v su pp ly. to ensure socket compatibility between the rc64574/rc64474 and the rc4640 devices, several pin changes are required, as shown i n the tables be low. note: the rc64574/575 are 2.5v parts and as such all vcc must be at the correct voltage for a given part. rc64575 socket compatibility to rc64475 & rc4650 rc64575 socket compatibility to rc64475 & rc4650 rc64575 socket compatibility to rc64475 & rc4650 rc64575 socket compatibility to rc64475 & rc4650 pin rc4640 rc64574/ rc64474 compatible to rv4640? comments 1 n.c jtag32 * yes pin h as an internal pull-down, t o enable 32-b it scan. can also be left a n. c. 48 v ss tdo yes can be driven with v ss , if jtag is not need ed. is tristated when tr st* is low . 49 v ss tms yes can be drive n with v ss if jtag is not needed . 50 v ss tck yes can be drive n with v ss if jtag is not needed . 51 v ss trst* yes can be drive n with v ss if jtag is not needed . 52 v ss tdi yes can be drive n with v ss if jtag is not needed . 71 n.c. jr _v cc yes can be left n.c. in rc64574, if jtag is not need. if jtag is needed, it must be d riven to v cc . table 8 rc645 74 socke t compati bility to rc6 4474 and r4 640 pin rv4650 32-bit rc64575 32-bit rc64475 32-bit rv4650 64-bit rc64575 64-bit rc64475 64-bit compatible to rv4650? comments 53 n.c. jtag32* no connect jtag32* yes in 32-bit, this pin can be left uncon- nected because of internal p ull-d own. in 64-bit, this assumes that jtag will not be used . if using jtag, th is pin must be at v cc . 150 n.c. jr_v cc no connect jr_v cc ye s in rc64475, can be left a n.c, if jtag is not need. if jtag is n eeded, it must be driven to v cc . 180 n.c. tdi no connect tdo yes if jtag is no t needed, can be left a n.c . 181 n.c. trst* no connect trst* yes if jtag is no t needed, can be left a n.c . 182 n.c. tck no connect tck yes if jtag is no t needed, can be left a n.c . 183 n.c. tms no connect tms yes if jtag is no t needed, can be left a n.c . 184 n.c. tdo no connect tdio yes if jtag is no t needed, can be left a n.c . tabl e 9 rc64575 soc ket compatibility to rc64475 & rc4650
14 of 28 december 14, 2001 79rc64574? 79rc64575? absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operation temperature and supply voltage recommended operation temperature and supply voltage recommended operation temperature and supply voltage recommended operation temperature and supply voltage dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics commercia l temp era ture ra ng e?rc6 45 74 /5 75 (t case = 0 c to +85 c commercial, t case = -40 c to +85 c industrial, v cc = 2. 5v 5%) symbol rating commercial (2.5v5%) industrial (2.5v5%) unit v term terminal voltage with respect to gnd ?0.5 1 to +4.0 1. v in minimum = ?2.0v for pulse width less than 15ns. for 3.3v tolerant input, v in ma xi mu m i s 3.8 v. ?0.5 1 t o +4.0 v t c op erating temperature (case) 0 to +85 -40 to +8 5 c t bias 2 2. case temperature when device is powered up but not operating. case te mperat ure under bias ?5 5 to +125 ?5 5 to +125 c t stg storage tempe rature ?5 5 to +125 ?5 5 to +125 c i in dc in put current 20 3 3. when v in < 0v or v in > v cc . 20 3 ma i out dc outpu t current 50 4 4. not more than one output should be shorted at a time. duration of the short should not exceed 30 seconds. 50 4 ma grade temperature gnd rc64574/575 vcc comm ercia l 0 c to +85 c (case) 0v 2.5v5% industrial -40 c to + 8 5 c (ca se) 0v 2.5v5% parameter rc64574/rc64575 200mhz rc64574/rc64575 250mhz conditions min max min max v ol ? 0.1v ? 0.1v |iout|= 20ua v oh v cc - 0.1 v ? v cc - 0.1v ? v ol ? 0.4v ? 0.4v |iout|= 4ma v oh 2.0v ? 2.0v ? v il ?0.5v 0.2v cc ?0.5v 0.2v cc ? v ih 0.7 v cc 3.8v 0.7 v cc 3.8v ? i in ? 10ua ? 10ua 0 vin vcc c in ? 10pf ? 10pf ?
15 of 28 december 14, 2001 79rc64574? 79rc64575? power consumption?rc64574 power consumption?rc64574 power consumption?rc64574 power consumption?rc64574 note: th e follo win g ta ble ass ume s as 4: 1 pipe line to b us clock ra tio . rc64574 power curves rc64574 power curves rc64574 power curves rc64574 power curves the following two graphs contain power curves that show power consumption at various bus frequencies. power consumption is base d on the valu es fo r r4 x0 0 comp atib le write mod e , sh own in th e t ab le a b ove . note: only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported. c io ? 10pf ? 10pf ? c cl k ? 10pf ? 10pf i/o leak ? 20ua ? 20ua input/output l eaka ge par ameter rc64574 200mhz rc64574 250mhz conditions typical 1 1. typic al i nteger i ns truc ti on m ix and cache m iss r ates. max typical 1 max i cc stand-by ? 60 ma 2 2. these are not tested. they are the results of engineering analysis and are provided for reference only. ? 60 ma 2 c l = 0pf 3 3. guaranteed by design. ?120 ma 2 ? 120 ma 2 c l = 50pf active 470 ma 2 55 0 ma 2 550 m a 2 680 m a 2 c l = 0pf no sysad activity 3 vcc = 2.63v 550ma 2 65 0 ma 2 650 m a 2 800 ma 2 c l = 50pf r4x00 compatible writes, t c = 25 o c vcc = 2.63v 600 ma 2 71 5 ma 4 4. these are the specifications idt tests to insure compliance. 715 m a 2 880 m a 4 c l = 50pf pipelined writes or write re-issue, t c = 25 o c 3 vcc = 2.63v parameter rc64574/rc64575 200mhz rc64574/rc64575 250mhz conditions min max min max
16 of 28 december 14, 2001 79rc64574? 79rc64575? figure 2 typica l power usage - rc64574 figure 3 maxi mum power usage - rc64574 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0 100 0 20 40 60 8 0 100 12 0 syste m bus spe e d (mhz) typical power (ma) 2x m ode 3x m ode 4x m ode 5x m ode 6x m ode 7x m ode 2x 3x 4x 7x 6x 5x 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0 100 0 110 0 20 40 60 8 0 100 12 0 syste m bus spe e d (mhz) maximum power (ma) 2x m ode 3x m ode 4x m ode 5x m ode 6x m ode 7x m ode 2x 3x 4x 5x 6x 7x
17 of 28 december 14, 2001 79rc64574? 79rc64575? p p p power consumption?rc64575 ower consumption?rc64575 ower consumption?rc64575 ower consumption?rc64575 note: th e follo win g ta ble ass ume s a 4: 1 p ipe line to b us clo ck ra tio. rc64575 power curves rc64575 power curves rc64575 power curves rc64575 power curves the following two graphs contain power curves that show power consumption at various bus frequencies. power consumption is base d on the valu es fo r r4 x0 0 comp atib le write mod e , sh own in th e t ab le a b ove . note: only pipeline frequencies that are integer multiples (2x, 3x, etc.) of bus frequencies are supported. figure 4 typica l power usage - rc64575 parameter rc64575 200mhz rc64575 250mhz conditions typical 1 1. typic al integer i nstruction m ix and cache m iss rates. max typical 1 max i cc sta nd-by ? 60 ma 2 2. these are not tested. they are the results of engineering analysis and are provided for reference only. ? 60 ma 2 c l = 0pf 3 3. guaranteed by design. ? 120 m 2 a ? 120 m 2 ac l = 50pf act ive, 64-bit bus option 4 4. in 32-bit bus option, use rc64574 power consumption values. 510 ma 2 680 ma 2 600 m a 2 810 m a 2 c l = 0pf no sysad activity 3 vcc = 2.63v 60 0 m a 2 800 ma 2 70 0 m a 2 950 m a 2 c l = 50pf r4 x00 compa tible writes, t c = 25 o c vcc = 2.63v 660 m a 2 880 ma 5 5. these are the specifications idt tests to insure compliance. 770 m a 2 1050 ma 5 c l = 50pf pipelined writes or write re -issue, t c = 25 o c 3 vcc = 2.63v 100 300 500 700 900 1100 20 4 0 60 80 100 1 20 system bus speed (mhz) typical power (ma) 2x mode 3x mode 4x mode 5x mode 6x mode 7x mode 6x 7x 5x 3x 2x 4x
18 of 28 december 14, 2001 79rc64574? 79rc64575? figure 5 maxi mum power usage - rc64575 200 400 600 800 1000 1200 1400 20 4 0 60 80 100 1 20 system bus speed (mhz) maximum power (ma) 2x mode 3x mode 4x mode 5x mode 6x mode 7x mode 2x 3 x 4x 5x 6 x 7x
19 of 28 december 14, 2001 79rc64574? 79rc64575? timing characteristics?rc64574/rc64575 timing characteristics?rc64574/rc64575 timing characteristics?rc64574/rc64575 timing characteristics?rc64574/rc64575 figure 6 system clocks da ta setup, output, and hold timing fig ure 7 st an dard jtag tim ing cycle 1 2 3 4 sysclock t sysclk t sysclklow t sysclkp sysad,syscmd driven d d d t do s ysad, syscmd recei ved d d d d t ds t dh t doh sysadc control signal cpu driven validout* release * t do control signal cpu received rdrdy* wrrdy* extrqst* validin* t ds t dh nmi* int*(5:0) t doh sysadc * = acti ve lo w si gnal tdi/ tms tdo tdo tdo trst* tck t3 t1 t2 t ds t dh t do t4 t tck notes to diagram: t1 = t tcklow t2 = t tckhigh t4 = t rs t (reset pulse width) t3 = t tckfall > = 25 ns t5 t5 = t tckrise
20 of 28 december 14, 2001 79rc64574? 79rc64575? system interface parameters system interface parameters system interface parameters system interface parameters boot-time interface parameters boot-time interface parameters boot-time interface parameters boot-time interface parameters parameter symbol test conditions rc64574/ rc64575 200mhz rc64574/ rc64575 250mhz units min max min max data output t do = max mode 14 ..13 = 10 (f aste st) ?5 ?4.3ns mode 14 ..13 = 11 (85%) ?6 ?4.5ns mode 14 ..13 = 00 (66%) ?7 ?5 ns mode 14 ..13 = 01 (slowest) ?8 ?5 ns data output hold t doh 1 1. 50 pf loading on external output signals mode 14 ..13 = 100?0?ns mode 14 ..13 = 110?0?ns mode 14 ..13 = 000?0?ns mode 14 ..13 = 010?0?ns data input t ds t rise = 3ns t fa ll = 3ns 2?2?ns t dh 1.0 ? 1.0 ? ns parameter symbol tes t conditions rc64574/ rc64575 200mhz rc64574/ rc6457 5 250mhz conditions min max min max mod e data setup t ds ? 4 ? 4 ? sys cl oc k cy cl e mod e data hold t dh ? 0 ? 0 ? sys cl oc k cy cl e
21 of 28 december 14, 2001 79rc64574? 79rc64575? mode configuration interface reset sequenc mode configuration interface reset sequenc mode configuration interface reset sequenc mode configuration interface reset sequence e e e figure 8 powe r-on rese t figure 9 cold reset figure 10 warm reset masterclock vccok modeclock modei n co l dres et * reset* tds vc c tmds tds > 1 00ms tds 256 mclk cycles 2. 3v tds bi t 0 tmdh > 64k mclk cycles > 64 mclk cycles bit tds bit 1 256 cycles mcl k (mclk) 255 2. 3v m aster vcc ok m odeclock modein coldreset* reset* vcc td s 256 cycles mcl k tds tmds tds 256 mclk cycles td s > 100ms bit tmdh > 64k m clk cycles > 64 mclk cycles bit bi t 256 cycles mcl k 255 tds tds (mclk) 01 clock master vccok m odeclock modein c oldr eset* re set * vc c tds tds 256 mclk cycles > 64 mclk cyc les (mclk) clock
22 of 28 december 14, 2001 79rc64574? 79rc64575? a a a ac electrical characteristics c electrical characteristics c electrical characteristics c electrical characteristics (t case = 0 c to +85 c commercial, t case = -40 c to +85 c industrial, v cc = 2. 5v 5% ) clock parameters?rc64574/575 clock parameters?rc64574/575 clock parameters?rc64574/575 clock parameters?rc64574/575 capacitive load deration?rc64574/575 capacitive load deration?rc64574/575 capacitive load deration?rc64574/575 capacitive load deration?rc64574/575 output loading for ac testing output loading for ac testing output loading for ac testing output loading for ac testing parameter symbol test conditions rc64574/rc64575 200mhz rc64574/rc64575 250mhz units min max min max pipe line clock frequency pclk ? 100 200 100 250 mhz system clock high t schigh transition 3ns3 ?3 ?ns system clock low t sclow transition 3ns3 ?3 ?ns system clock frequency ? ? 33 100 33 125 mhz system clock period t scp ? 10 30 8 30 ns system clock jitter t jitter ??+ 25 0 ? + 250 ps system clock rise time 1 1. rise and fall times are measured between 10% and 90% t scrise ? ?2?2ns system clock fall time 1 t scfall ? ?2?2ns modeclock period t mo deckp ? ? 256 t scp ? 256 t scp ns jtag clock inpu t period t tck ? ? 100 ? 100 ns jtag clock high t tckhigh ??40?40ns jtag clock low t tcklow ??40?40ns jtag clock rise time t tckrise ? ?5?5ns jtag clock fall time t tckfall ? ?5?5ns parameter symbol tes t conditions 200mhz 250mhz units min max min max load derate c ld ? ? 2 ? 2 ns/25pf signal cld all signals 50 pf ? + to d evice under test c ld v ref +1.5v
23 of 28 december 14, 2001 79rc64574? 79rc64575? rc64575 208-pin package diagram rc64575 208-pin package diagram rc64575 208-pin package diagram rc64575 208-pin package diagram the rc64575 is available in a 208-pin qfp package.
24 of 28 december 14, 2001 79rc64574? 79rc64575? rc64575 208-pin package diagram (page2) rc64575 208-pin package diagram (page2) rc64575 208-pin package diagram (page2) rc64575 208-pin package diagram (page2)
25 of 28 december 14, 2001 79rc64574? 79rc64575? rc64574 128-pin package diagram (page 1 of 3) rc64574 128-pin package diagram (page 1 of 3) rc64574 128-pin package diagram (page 1 of 3) rc64574 128-pin package diagram (page 1 of 3) the rc64574 is available in a 128-pin qfp package.
26 of 28 december 14, 2001 79rc64574? 79rc64575? rc64574 128-pin package diagram (page 2 of 3 rc64574 128-pin package diagram (page 2 of 3 rc64574 128-pin package diagram (page 2 of 3 rc64574 128-pin package diagram (page 2 of 3) ) ) )
27 of 28 december 14, 2001 79rc64574? 79rc64575? rc64574 128-pin package diagram (page 3 of 3) rc64574 128-pin package diagram (page 3 of 3) rc64574 128-pin package diagram (page 3 of 3) rc64574 128-pin package diagram (page 3 of 3)
28 of 28 december 14, 2001 79rc64574? 79rc64575? corporate headquarters 29 75 s te nd er way santa clara, ca 95054 for sale s: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for tech support: email: rischelp@idt.com phone: 408-492-8208 ordering infor mation ordering infor mation ordering infor mation ordering infor mation valid combinations valid combinations valid combinations valid combinations idt79rc6 4t574 - 200, 25 0, dz 128-p in qfp package, commercial tem peratu re idt79rc6 4t575 - 200 , 25 0, dp 208-p in qfp package, commercial tem peratu re idt79rc6 4t574 - 200, 25 0, dzi 128-p in qfp package, industrial temperature idt79rc6 4t575 - 200, 25 0, dpi 08-pin qfp p ackage, in dust rial temperature idt79rcxx yy xxxx 999 a a operating voltage device typ e speed package te mp ra ng e/ process t 20 0 25 0 blank commercial temperature ( 0c t o + 8 5 c ca se ) 128-pin qfp 200 mhz pipeline clk 250 mhz pipeline clk 2. 5v +/-5% embe dd e d p roce sso r product typ e 79rc64 64-bit embedded microprocessor 208-pin qfp dp dz 57 4 57 5 i in du strial te mpe ratu re (-40c to +85c case)

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