this document is a general product description and is subject to change without notice. hynix e lectronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 02 / jun.01 hynix semiconductor hy62v f08 4 01c series 25 6kx16bit full cmos sram document title 512k x 8bit 3.0 ~ 3.6v super low power fcmos slow sram revision history revision no history draft date remark 00 initial draft dec.18.2000 final 01 changed logo mar.23.2001 final 02 changed isb1 values jun.07.2001 final
hy62 v f08401c series rev. 02 / jun.01 2 description the hy62 v f 0 840 1c is a high speed, super low power and 4mbit full cmos sram organized as 51 2k words by 8 bits. the hy62vf 08 40 1c uses high performance full cmos process technology and is designed for high speed and low power circuit technology. it is particularly well - suited for the high density low power system application. this device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1. 2 v. features fully static operation and tri - state output ttl compatible inputs and outputs battery backup - . 1.2v( min) data retention standard pin configuration - . 32 - stsop - 8x13.4(standard) standby current(ua) product no. voltage (v) speed (ns) operation current /icc(ma) ll sl temperature ( c ) hy62vf 0 840 1 c - i 3.0~3.6 55/70 5 15 6 - 40~85 note 1. i : industrial 2. current value is max. pin connection block diagram pin description pin name pin function pin name pin function /cs chip select i/o1 ~ i/o8 data input/output /we write enable vcc power ( 3.0 v ~3.6v ) /oe output enable vss ground a0 ~ a18 address input memory array 512k x 8 row decoder sense amp write driver data i/o buffer column decoder block decoder pre decoder add input buffer a0 a18 /oe /we /cs i/o1 i/o8 / oe a10 / cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 a11 a9 a8 a13 /we a18 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 / oe a10 / cs i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 a11 a9 a8 a13 /we a18 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 - stsop forward
hy62 v f08401c series rev. 02 / jun.01 2 ordering information part no. speed power temp . package hy62vf 0 840 1c - ds(i) 55/ 70 ll - part i stsop hy62vf 0 840 1 c - ss( i) 55/ 70 sl - part i stsop note 1. i : ind ustrial absolute maximum ratings (1) symbol parameter rating unit remark v in, v out input/output voltage - 0. 3 to 4.0 v vcc power supply - 0. 3 to 4. 6 v t a operating temperature - 40 to 85 c hy62vf 0 840 1 c - i t stg storage temperature - 55 to 150 c p d power dissipation 1.0 w t solder ball soldering temperature & time 260 10 c sec note 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating onl y and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect reliability. truth table /cs /we /oe mode i/o operation supply current h x x deselected high - z standby h output disabled high - z active h l read dout l l x write din active note: 1. h=v ih , l=v il , x=don't care ( v il or v ih )
hy62 v f08401c series rev. 02 / jun.01 3 recommended dc operating condition symbol parameter min. typ max. unit vcc supply voltage 3.0 3.3 3. 6 v vss ground 0 0 0 v v ih input high voltage 2.2 - vcc+0. 3 v v il input low voltage - 0. 3 1. - 0. 6 v note : 1. undershoot : vil = - 1.5v for pulse widt h less than 30ns 2. undershoot is sampled, not 100% tested. dc electrical characteristics t a = - 40 c to 85 c sym parameter test condition min ty p 1. max unit i li input leakage current vss < v in < vcc - 1 - 1 ua i lo output leakage current vss < v out < vcc, /cs = v ih or / oe = v ih or /we = v il - 1 - 1 ua icc operating power supply curren t /cs = v il , v in = v ih or v il, i i/o = 0ma 5 ma /cs = v il, v in = v ih or v il, cycle time = min, 100% duty, i i/o = 0ma 45 ma i cc1 average operating current /cs < 0.2v , v in < 0.2v or v in > vcc - 0.2v , cycle time = 1us, 100% duty, i i/o = 0ma 5 ma i sb standby current (ttl input) /cs = v ih or v in = v ih or v il 0.5 ma sl 0.2 6 ua i sb1 standby current (cmos input) /cs > vcc - 0.2v or v in > vcc - 0.2v or v in < vss + 0.2v ll 0.2 15 ua v ol output low i ol = 2.1ma - - 0. 4 v v oh output high i oh = - 1.0ma 2. 4 - - v note 1. typical values are at vcc = 3.3v t a = 25 c 2. typical values are not 100% tested capacitance (temp = 25 c , f= 1 .0mhz) symbol parameter condition max. unit c in input capacitance (add, /cs, /we, /oe) v in = 0v 8 pf c out output capacitance (i/o) v i/o = 0v 10 pf note : these parameters are sampled and not 100% tested
hy62 v f08401c series rev. 02 / jun.01 4 ac characteristics t a = - 40 c to 85 c , un less otherwise specified 55 ns 70 ns # symbol parameter min. max. min. max. unit 1 trc read cycle time 55 - 70 - ns 2 taa address access time - 55 - 70 ns 3 tacs chip select access time - 55 - 70 ns 4 toe output enable to output valid - 3 0 - 35 ns 5 tclz chip select to output in low z 10 - 10 - ns 6 tolz output enable to output in low z 5 - 5 - ns 7 tchz chip deselection to output in high z 0 30 0 30 ns 8 tohz out disable to output in high z 0 30 0 30 ns 9 toh output hold from address chang e 10 - 10 - ns 10 twc write cycle time 55 - 70 - ns 11 tcw chip selection to end of write 50 - 60 - ns 12 taw address valid to end of write 50 - 60 - ns 13 tas address set - up time 0 - 0 - ns 14 twp write pulse width 45 - 50 - ns 15 twr write reco very time 0 - 0 - ns 16 twhz write to output in high z 0 20 0 20 ns 17 tdw data to write time overlap 25 - 30 - ns 18 tdh data hold from write time 0 - 0 - ns 19 tow output active from end of write 5 - 5 - ns ac test conditions t a = - 40 c to 85 c , unless otherwise specified p arameter value input pulse level 0.4v to 2.2v input rise and fall time 5ns input and output timing reference level 1.5v tclz, tolz, tchz, tohz, twhz, tow cl = 5 pf + 1ttl load output load others cl = 3 0pf + 1ttl load ac test loads d out 1728 ohm cl(1) 1029 ohm v tm =2.8v note 1. including jig and scope capacitance read cycle write cycle
hy62 v f08401c series rev. 02 / jun.01 5 timing diagram read cycle 1 (note 1 ,4 ) read cycle 2 (note 1,2, 4 ) trc taa data valid previous data toh toh addr data out read cycle 3(note 1, 2, 4) /cs tacs data valid tclz(3) tchz(3) data out notes: 1. a read occurs during the overlap of a low /oe, a high /we and a low / cs. 2. /oe = v il 3. transition is measured + 200mv from steady state voltage. this parameter is sampled and not 100% tested. 4. /cs in high for the standby, low for active addr trc / cs taa tacs toh data valid high - z data out / oe toe tclz (3) t olz (3) t chz (3) tohz (3)
hy62 v f08401c series rev. 02 / jun.01 6 write cycle 1 (1,4, 8 ) (/we controlled) write cycle 2 (note 1,4, 8) (/cs controlled) data valid addr data ou t / cs / we twc tcw twr (2) taw twp data in high - z tas twhz (3,8) tdw tdh tow ( 5 ) ( 6 ) data valid addr data out / cs / we twc tcw twr (2) taw twp data in tdw tdh high - z high - z tas
hy62 v f08401c series rev. 02 / jun.01 7 notes: 1. a write occurs during the overlap of a low /we and a low /cs. 2. twr is measured from the earlier of /cs or /we going high to the end of write cycle. 3. during this period, i/o pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. if the /cs low transition occur s simultaneously with the /we low transition or after the /we transition, outputs remain in a high impedance state. 5. q(data out) is the same phase with the write data of this write cycle. 6. q(data out) is the read data of the next address. 7. transition is measured + 200mv from steady state. this paramet er is sampled and not 100% tested. 8 . /cs in high for the standby, low for active data retention electric characteristic t a = - 40 c to 85 c symbol parameter test condition min typ 1. max unit v dr vcc for data retention /cs > vcc - 0.2v , v in > vcc - 0.2v or v in < vss + 0.2v 1. 2 - 3.6 v sl - 0.1 3 ua iccdr data retention current vcc= 1.5v , /cs > vcc - 0.2v or v in > vcc - 0.2v or v in < vss + 0.2v ll - 0. 1 10 ua tcdr chip deselect to data retention time 0 - - ns tr operating recovery time see data retention timin g diagram trc - - ns notes: 1. typical values are under the condition of t a = 25 c . 2. typical value are sampled and not 100% tested data retention timing diagram / cs vdr / cs > vcc-0.2v tcdr tr vss vcc 2.7v vih data retention mode
hy62 v f08401c series rev. 02 / jun.01 8 packag e information 32pin 8x13.4mm smaller thin small outline package standard(st) unit : inch(mm) 0.319(8.1) 0.311(7.9) 0.468(11.9) 0.460(11.7) 0.536(13.6) 0.520(13.2) 0.024(0.6) 0.016(0.4) 0.008(0.2) 0.004(0.1) 0.020(0.50) 0.007(0.17) 0.041(1.05) 0.037(0.95) 0.008(0.20) 0.002(0.05) #1 #32 #16 #17 0.011(0.27)
hy62 v f08401c series rev. 02 / jun.01 9 marking information package marking example index ? hy62uf08401c : part name ? c : power consumption - d : low low power - s : super low power ? s : package type - s : stsop ? ss : speed - 55 : 55ns - 70 : 70ns ? t : temperature - i : industrial ( - 40 ~ 85 c ) ? yy : year ( ex : 00 = year 2000, 01 = year 2001 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item h y 6 2 u f 0 8 4 0 1 c - c s s s t y y w w p k o r stsop package marking example index ? hy62uf08401c : part name ? c : power consumption - d : low low power - s : super low power ? s : package type - s : stsop ? ss : speed - 55 : 55ns - 70 : 70ns ? t : temperature - i : industrial ( - 40 ~ 85 c ) ? yy : year ( ex : 00 = year 2000, 01 = year 2001 ) ? ww : work week ( ex : 12 = ww12 ) ? p : process code ? kor : origin country note - capital letter : fixed item - small letter : non - fixed item h y 6 2 u f 0 8 4 0 1 c - c s s s t y y w w p k o r h y 6 2 u f 0 8 4 0 1 c - c s s s t y y w w p k o r stsop
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