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fifosoi hx6409 hx6218 hx6136 aerospace electronics features ? 1k x 36, 2k x 18, 4k x 9 organizations ? fabricated with ricmos ? iv silicon on insulator (soi) 0.8 m m process (l eff = 0.65 m m) radiation ? total dose hardness through 1x10 6 rad(sio 2 ) ? neutron hardness through 1x10 14 cm -2 ? dynamic and static transient upset hardness through 1x10 9 rad(si)/s ? dose rate survivability through 1x10 11 rad(si)/s ? soft error rate of <1x10 -10 upsets/bit-day ? no latchup other ? read/write cycle times <35 ns (-55 to 125 c) ? expandable in width ? supports free-running 50% duty cycle clock ? empty, full, half full, 1/4 full, 3/4 full, error flags ? parity generation/checking ? fully asynchronous with simultaneous read and write operation ? output enable (oe) ? cmos or ttl compatible i/o ? single 5 v 10% power supply ? various flat pack options the hx6409, hx6218, and hx6136 are high speed, low- power, first-in first-out memories with clocked read and write interfaces. the hx6409 is a 4096 word by 9 bit memory array, the hx6218 is a 2048 word by 18 bit memory array, and the hx6136 is a 1024 word by 36 bit memory array. the fifos support width expansion while depth expansion requires external logic control using state machine techniques. features include programmable par- ity control, an empty/full flag, a quarter/three quarter full flag, a half full flag and an error flag. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffer- ing. these fifos have separate input and output ports that are controlled by separate clock and enable sig- nals. the input port is controlled by a free running clock (ckw) and a write enable pin enw . when enw is asserted, data is written into the fifo on the rising edge of the ckw signal. while enw is held active, data is continually written into the fifo on each ckw cycle. the output port is controlled in a similar manner by a free- running read clock (ckr) and a read enable pin ( enr ). in addition, the three fifos have an output enable pin ( oe ) and a master reset pin ( mr ). the read (ckr) and write (ckw) clocks may be tied together for single-clock opera tion or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 30 mhz are achievable in the three configurations. honeywells enhanced soi ricmos? iv (radiation in- sensitive cmos) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques. the fifo is fabricated with honeywells radiation hardened technology, and is de- signed for use in systems operating in radiation environ- ments. the soi ricmos? iv process is a 5-volt, simox cmos technology with a 150 ? gate oxide and a minimum drawn feature size of 0.8 m m, (0.65 m m effective gate arrayl eff ). additional features include tungsten via plugs, honeywells proprietary sharp planarization process, and a lightly doped drain (ldd) structure for improved short channel reliability. general description solid state electronics center ? 12001 state highway 55, plymouth, mn 55441 ? (800) 323-8295 ? http://www.ssec.honeywell. com
hx6409/hx6218/hx6136 2 word count ef_fa u lt e/ f qf/tqf hf state 4k x 9 2k x 18 1k x 36 0 0 0 1 empty fault (enabled read when empty) 00 0 1 0 0 1 empty 0 0 0 1 1 0 1 less than or equal to 1/4 full 1 to 1024 1 to 512 1 to 256 1 1 1 1 less than or equal to 1/2 full 1025 to 2048 513 to 1024 257 to 512 1 1 1 0 greater that 1/2 full 2049 to 3071 1025 to1535 513 to 767 1 1 0 0 greater than or equal to 3/4 full 3072 to 4095 1536 to 2047 768 to 1023 1 0 0 0 full 4096 2048 1024 0 0 0 0 full fault (enabled write when full) 4096 2048 1024 flag decode table logic block diagram ckw enw write control mr parity program register parity write pointer reset logic read pointer read control ckr enr input register q: 0 - 8 q: 0 - 17 q: 0 - 35 tri-state output register memory array 4096 x 9 2048 x 18 1024 x 36 oe d: 0 - 8 d: 0 - 17 d: 0 - 35 flag logic hf e/f qf/tqf ef_fault
3 hx6409/hx6218/hx6136 signal name i/o description d: 0 - 35 i data inputs: data inputs are written into the fifo on the rising edge of ckw when enw is active and the fifo is not full. q: 0 - 35 o data outputs: data outputs are read out of the fifo memory and updated on the rising edge of ckr when enr is active and the fifo is not empty. the data outputs are in a high impedance state if oe is not active. enw i enable write: an active low signal that enables the write of the data inputs on the ckw rising edge (if fifo is not full). enr i enable read: an active low signal that enables the read and update of the data outputs on the ckr rising edge (if fifo is not empty). ckw i write clock: the rising edge clocks data into the fifo when enw is low (active). on the rising edge, this signal also updates the half full, 3/4 full, full, and full fault flags. ckr i read clock: the rising edge clocks data out of the fifo when enr is low (active). on the rising edge, this signal also updates the 1/4 full, empty, and empty fault flags. hf o half full flag: updated on the rising edge of ckw and indicating that the fifo is greater than half full. e/ f o empty or full flag: empty is updated on the rising edge of ckr, and full is updated on the rising edge of ckw. qf/tqf o 1/4 full or 3/4 full flag: 1/4 full is updated on the rising edge of ckr, and 3/4 full is updated on the rising edge of ckw. 1/4 full signifies 256 or less words in the 1k x 36 fifo and 3/4 full signifies 256 words or less until a full condition. ef_fault o empty or full fault flag: empty fault is updated on the rising edge of ckr, and full fault is updated on the rising edge of ckw. empty fault signifies a read to an already empty fifo, and full fault signifies a write to an already full fifo. once a fault condition is detected, the fault flag remains latched until the empty or full condition is removed. mr i master reset: active low signal which, when active, resets device to empty condition. oe i output enable: active low signal which, when active, enables low impedance data outputs, q: 0 - 35. signal definitions programmable parity options 2 d1 d0 ds n o i t i d n o c oxx d e l b a s i d y t i r a p ioo 5 3 q , 6 2 q , 7 1 q , 8 q , y t i r a p n e v e e t a r e n e g ioi , y t i r a p d d o e t a r e n e g5 3 q , 6 2 q , 7 1 q , 8 q iio l a n g i s w o l a s i r o r r e , 5 3 q , 6 2 q , 7 1 q , 8 q n o r o r r e , y t i r a p n e v e r o f k c e h c iii n o r o r r e , y t i r a p d d o r o f k c e h cl a n g i s w o l a s i r o r r e , 5 3 q , 6 2 q , 7 1 q , 8 q
hx6409/hx6218/hx6136 4 total dose 3 1x10 6 rad(sio 2 ) transient dose rate upset 3 1x10 9 rad(si)/s transient dose rate survivability 3 1x10 11 rad(si)/s soft error rate <1x10 -10 upsets/bit-day neutron fluence 3 1x10 14 n/cm 2 parameter limits (2) test conditions radiation-hardness ratings (1) units t a =25 c radiation characteristics total ionizing radiation dose all fifo configurations will meet all stated functional and electrical specifications over the entire operating tempera- ture range after the specified total ionizing radiation dose. all electrical and timing performance parameters will re- main within specifications after rebound at vdd = 5.5 v and t = 125 c extrapolated to ten years of operation. total dose hardness is assured by wafer level testing of process monitor transistors and product using 10 kev x-ray and radiation sources. transistor gate threshold shift correla- tions have been made between 10 kev x-rays applied at a dose rate of 1x10 5 rad(sio 2 )/min at t = 25 c and gamma rays (cobalt 60 source) to ensure that wafer level x-ray testing is consistent with standard military radiation test environments. transient pulse ionizing radiation each fifo configuration is capable of writing, reading and retaining stored data during and after exposure to a transient ionizing radiation pulse of <50 ns duration up to 1x10 9 rad(si)/s, when applied under recommended oper- ating conditions. to ensure validity of all specified perfor- mance parameters before, during, and after radiation (timing degradation during transient pulse radiation (tim- ing degradation during transient pulse radiation is 10%), it is suggested that stiffening capacitance be placed near the package vdd and vss, with a maximum inductance between the package (chip) and stiffening capacitor of 0.7 nh per part. if there are no operate-through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. (1) device will not latch up due to any of the specified radiation exposure conditions. (2) operating conditions (unless otherwise specified): vdd=4.5 v to 5.5 v, ta=-55 c to 125 c. 1 mev equivalent energy, unbiased, t a =25 c t a =125 c, adams 90% worst case environment pulse width 50 ns, x-ray, vdd=6.0 v, t a =25 c pulse width 50 ns each fifo will meet any functional or electrical specifica- tion after exposure to a radiation pulse of 50 ns duration up to 1x10 11 rad(si)/s, when applied under recommended operating conditions. note the current conducted during the pulse by the inputs, outputs and power supply may significantly exceed the normal operating levels. the appli- cation design must accommodate these effects. neutron radiation each fifo configuration will meet any functional or timing specification after a total neutron fluence of up to 1x10 14 cm - 2 applied under recommended operating or storage condi- tions. this assumes an equivalent neutron energy of 1 mev. soft error rate this fifo configuration has a soft error rate (ser) perfor- mance of <1x10 -10 upsets/bit-day, under recommended operating conditions. this hardness level is defined by the adams 90% worst case cosmic ray environment. latchup this fifo configuration will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. fabrication with the simox substrate with its oxide isolation ensure latchup immunity.
5 hx6409/hx6218/hx6136 vdd supply voltage range (2) -0.5 7.0 v vpin voltage on any pin (2) -0.5 vdd+0.5 v tstore storage temperature (zero bias) -65 150 c tsolder soldering temperature (5 seconds) 270 c pd maximum power dissipation (3) 2.5 w iout dc or average output current 25 ma vprot esd input protection voltage (4) 2000 v q jc thermal resistance (jct-to-case) 5 c/w tj junction temperature 175 c vdd supply voltage (referenced to vss) 4.5 5.0 5.5 v ta ambient temperature -55 25 125 c vpin voltage on any pin (referenced to vss) -0.3 vdd+0.3 v parameter parameter symbol capacitance (1) symbol test conditions min max units (1) this parameter is tested during initial design characterization only. recommended operating conditions symbol max typ parameter min units data retention characteristics parameter symbol min max units rating ci input capacitance 7 pf vi=vdd or vss, f=1 mhz co output capacitance 9 pf vio=vdd or vss, f=1 mhz units typical (1) worst case min max test conditions (1) typical operating conditions: ta= 25 c, pre-radiation. (2) worst case operating conditions: tc= -55 c to +125 c, post total dose at 25 c. vdr data retention voltage 2.5 v idr data retention current 500 m a ncs=vdr vi=vdr or vss ncs=vdd=vdr vi=vdr or vss worst case (2) typical (1) description (1) stresses in excess of those listed above may result in permanent damage. these are stress ratings only, and operation at th ese levels is not implied. frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) voltage referenced to vss. (3) fifo power dissipation (iddsb + iddop) plus fifo output driver power dissipation due to external loading must not exceed th is specification. (4) class 2 electrostatic discharge (esd) input protection. tested per mil-std-883, method 3015 by desc certified lab. absolute maximum ratings (1)
hx6409/hx6218/hx6136 6 symbol test parameters worst case (1) min max units conditions vih input high voltage cmos ttl 0.7xvdd 2.2 v vdd=5.5v vil input low voltage cmos ttl 0.3xvdd 0.8 v vdd=4.5v voh1 high output voltage 3.5 v vdd=4.5v ioh=-4.0ma voh2 high output voltage vdd-0.4 v vdd=4.5v ioh=-100a vol low output voltage 0.4 v vdd=4.5v iol=4.0ma i i input leakage current -1.0 +1.0 a vdd=5.5v vin=0v or vdd tc=-55c to +125c iozl iozh output off, high z current -10.0 +10.0 a oe > vih , vss 7 hx6409/hx6218/hx6136 ac timing characteristics (1) (1) test conditions: input switching levels vil/vih=0.5v/vdd-0.5v (cmos), vil/vih=0v/3v (ttl), input rise and fall times <1 ns/v , input and output timing reference levels shown in the tester ac timing characteristics table, capacitive output loading c l =50 pf. for c l >50 pf, derate access times by 0.02 ns/pf (typical). (2) worst case operating conditions: vdd=4.5v to 5.5v, tc= -55 c to +125 c, post total dose at 25 c. (3) for flag updates, tskew1 is the minimum time an opposite clock can occur after a clock and still not be included in the curr ent clock cycle. at less that tskew1, inclusion of the opposite clock is arbitrary. (4) for flag updates, tskew2 is the minimum time an opposite clock can occur before a clock and still be included in the current clock cycle. at less than tskew2, inclusion of the opposite clock is arbitrary. (5) timing parameters are defined in figures 1 through 6. worst cast (2) 55?c to 125c symbol test parameter min max units tckw write clock cycle 2 4 ns tckr read clock cycle 34 ns tckh clock high read 24 ns tckh clock high write 14 ns tckl clock low 10 ns ta data access time 3 0 ns toh previous output data hold after rd high 2 ns tfh previous flag hold after rd/wr high 2 ns tsd data set-up 9 ns thd data hold 4 ns tsen enable set-up 8 ns then enable hold 2 ns toe oe low to output data valid 10 ns tolz oe low to output data in low z 1 ns tohz oe high to output data in high z 10 ns tfd flag delay 1 7 ns tskew1 opposite clock after clock (3) 0 ns tskew2 opposite clock before clock (4) 25 ns tpmr master reset pulse width (low) 25 ns tscmr last valid clock low set-up to master reset low 0 ns tohmr data hold from master reset low 2 ns tmrr master reset recovery 8 ns tmrf master reset high to flags valid 17 ns tamr master reset high to data outputs low 17 ns tsmrp parity program modemr low set-up 34 ns thmrp parity program modemr low hold 24 ns tftp parity program modewrite high to read high 3 4 ns tap parity program modedata access time 30 ns tohp parity program modedata hold time from mr high 4 ns
hx6409/hx6218/hx6136 8 ac timing waveforms figure 1. write timing figure 2. read timing tckh tckl disabled wr enabled wr ts d t h d tsen then tsen then tfh tfd tfh ckw data flags tckw tfd enw tckh tckl disabled rd enabled rd to h ta tsen then tsen then tfh tfd tfh ckr data flags tckw tfd enr
9 hx6409/hx6218/hx6136 figure 3. master reset timing note: if enw is held high during master reset, the parity is disabled. figure 4. read flag update timing note: when an empty condition occors, the empty flag is set. the performance of another read requires at least one write, on read clock to reset the empty flag and then an enabled read clock. ckw ckr data other flags tscmr tscmr tphmr valid data tmrf tmrf ta m r all data outputs low tmrr first write tmrr mr enw enr hf tpmr high tfd enable write tskew2 tskew1 enable read flag update enable read latent cycle tfd tfd tskew2 ckr ckw flags enr enw hf
hx6409/hx6218/hx6136 10 figure 6. output enable timing ckw ckr flags tfd enable read tskew2 tskew1 enable write flag update enable write latent cycle tfd tfd tskew2 enw enr read m+1 low tohz valid data word m to l z to e valid data word m+1 ckr data enr oe figure 7. parity programming mode ckw ckr data out tscmr valid data tckh tmrr first write tohmr mr enw enr tsmrp data in tscmr parity word thmrp tsd thmrp tamr last word tap parity write tftp tnd parity read tohp tsmrp word tckh parity word figure 5. write flag update timing note: when a full condition occurs, the full flag is set. the performance of another write requires at least one read, one write clock to reset the full flag and then one enabled write clock.
11 hx6409/hx6218/hx6136 quality and radiation hardness assurance honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a com- plete total quality assurance system, a computer data base process performance tracking system and a radiation hardness assurance strategy. the radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. radiation hardness is assured on every wafer by irradiat- ing test structures as well as sram product, and then monitoring key parameters which are sensitive to ionizing radiation. conventional mil-std-883 tm 5005 group e testing, which includes total dose exposure with cobalt 60, may also be performed as required. this total quality approach ensures our customers of a reliable product by engineering in reliability, starting with process develop- ment and continuing through product qualification and screening. screening levels honeywell offers several levels of device screening to meet your system needs. engineering devices are avail- able with limited performance and screening for bread- boarding and/or evaluation testing. hi-rel level b and s devices undergo additional screening per the require- ments of mil-std-883. as a qml supplier, honeywell also offers qml class q and v devices per mil-prf-38535 and are available per the applicable standard microcir- cuits drawing (smd). qml devices offer ease of procure- ment by eliminating the need to create detailed specifica- tions and offer benefits of improved quality and cost savings through standardization. reliability honeywell understands the stringent reliability requirements for space and defense systems and has extensive experi- ence in reliability testing on programs of this nature. this experience is derived from comprehensive testing of vlsi processes. reliability attributes of the ricmos tm process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. these specific mechanisms included, but were not limited to, hot carriers, electromigra- tion and time dependent dielectric breakdown. this data was then used to make changes to the design models and process to ensure more reliable products. in addition, the reliability of the ricmos ? process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dy- namic life test conditions. packages are qualified for prod- uct use after undergoing group b & d testing as outlined in mil-std-883, tm 5005, class s. the product is quali- fied by following a screening and testing flow to meet the customers requirements. quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. high z = 2.9v aaaa aaaa aa aa aa aa aa aaaa 3 v 0 v 1.5 v aaa aaaa vdd-0.5 v 0.5 v vdd/2 aaaaa aaaaa aa aa aa aa 1.5 v vdd-0.4v 0.4 v high z 3.4 v 2.4 v high z vdd/2 0.4 v high z 3.4 v 2.4 v high z ttl i/o configuration input levels* output sense levels cmos i/o configuration high z = 2.9v * input rise and fall times <1 ns/v vdd-0.4v tester ac timing characteristics
hx6409/hx6218/hx6136 12 pin list for hx6218 pin list for hx6409 n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s 1s s v 75 q 3 1 f q t / t q 9 1r n e 5 26 d 1 30 d 20 q 86 q 4 1f h 0 2w k c 6 25 d 2 3d d v 31 q 97 q 5 1f e 1 2w n e 7 24 d 42 q 0 18 q 6 1s s v 2 2r m 8 23 d 53 q 1 1e o 7 1d d v 3 28 d 9 22 d 64 q 2 1t l u a f _ f e 8 1r k c 4 27 d 0 31 d n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s 1r k c 3 1 7 1 d 5 2s s v 7 31 q 9 41 1 q 1 6s s v 2r n e 4 16 1 d 6 28 d 8 32 q 0 52 1 q 2 6d d v 3w k c 5 15 1 d 7 27 d 9 33 q 1 53 1 q 3 6e o 4w n e 6 14 1 d 8 26 d 0 44 q 2 5d d v 4 6t l u a f _ f e 5r m 7 1d d v 9 25 d 1 45 q 3 5s s v 5 6f q t / f q 6d d v 8 1s s v 0 34 d 2 46 q 4 54 1 q 6 6f h 7s s v 9 13 1 d 1 33 d 3 47 q 5 55 1 q 7 6f ? e 8s s v 0 22 1 d 2 32 d 4 48 q 6 56 1 q 8 6d d v 9s s v 1 21 1 d 3 31 d 5 4s s v 7 57 1 q 0 1d d v 2 20 1 d 4 30 d 6 4d d v 8 5d d v 1 1d d v 3 29 d 5 3d d v 7 49 q 9 5d d v 2 1d d v 4 2d d v 6 30 q 8 40 1 q 0 6d d v
13 hx6409/hx6218/hx6136 pin list for hx6236 n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s n i pl a n g i s 1s s v 3 2w k c 5 4c n 7 6s s v 9 82 q 1 1 1 9 1 q 2c n 4 2c n 6 45 2 d 8 6c n 0 9c n 2 1 1 0 2 q 3c n 5 2w n e 7 4c n 9 68 d 1 93 q 3 1 1 c n 4c n 6 2c n 8 44 2 d 0 77 d 2 9c n 4 1 1 1 2 q 5e o 7 2r m 9 4s s v 1 76 d 3 94 q 5 1 1 d d v 6c n 8 2c n n 0 5d d v 2 7c n 4 95 q 6 1 1 s s v 7t l u a f _ f e 9 2c n 1 53 2 d 3 75 d 5 96 q 7 1 1 2 2 q 8f q t / f q 0 3c n 2 52 2 d 4 74 d 6 97 q 8 1 1 3 2 q 9f h 1 3c n 3 51 2 d 5 73 d 7 98 q 9 1 1 4 2 q 0 1c n 2 3c n 4 50 2 d 6 7c n 8 9c n 0 2 1 5 2 q 1 1f e 3 3s s v 5 59 1 d 7 72 d 9 9s s v 1 2 1 6 2 q 2 1c n 4 3d d v 6 58 1 d 8 7c n 0 0 1d d v 2 2 1 7 2 q 3 1c n 5 35 3 d 7 57 1 d 9 71 d 1 0 19 q 3 2 1 8 2 q 4 1c n 6 34 3 d 8 56 1 d 0 8c n 2 0 10 1 q 4 2 1 c n 5 1c n 7 33 3 d 9 55 1 d 1 80 d 3 0 11 1 q 5 2 1 9 2 q 6 1s s v 8 32 3 d 0 64 1 d 2 8s s v 4 0 12 1 q 6 2 1 0 3 q 7 1d d v 9 31 3 d 1 63 1 d 3 8d d v 5 0 13 1 q 7 2 1 1 3 q 8 1c n 0 40 3 d 2 62 1 d 4 8c n 6 0 14 1 q 8 2 1 2 3 q 9 1r k c 1 49 2 d 3 61 1 d 5 80 q 7 0 15 1 q 9 2 1 3 3 q 0 2c n 2 48 2 d 4 60 1 d 6 8c n 8 0 16 1 q 0 3 1 4 3 q 1 2r n e 3 47 2 d 5 69 d 7 81 q 9 0 17 1 q 1 3 1 5 3 q 2 2c n 4 46 2 d 6 6d d v 8 8c n 0 1 18 1 q 2 3 1 d d v
hx6409/hx6218/hx6136 14 package drawing for 6409 (22018533-001) the fifo is offered in a 32-lead, 68-lead and a 132-lead flat pack, depending on the configuration. these packages are constructed of multilayer ceramic (al 2 o 3 ) and features internal power and ground planes. the flat packs also packaging feature non-conductive ceramic tie bars. the tie bars allows electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. [1] bsc - basic lead spacing between centers [2] where lead is brazed to package [3] parts delivered with leads unformed [4] lid connected to vss a b c d e e e2 e3 f l q s u v w x y z 0.135 0.015 0.017 0.002 0.004 to 0.009 0.820 0.008 0.050 0.005 [1] 0.600 0.008 0.500 0.008 0.040 ref 0.750 0.005 [2] 0.295 min [3] 0.026 to 0.045 0.035 0.010 0.080 ref 0.380 ref 0.050 ref 0.075 ref 0.010 ref 0.135 ref all dimensions in inches 22018533-001 e 1 e b d (width) (pitch) f l top view e2 a lead alloy 42 ceramic body c e3 cutout area q kovar lid [4] v optional capacitors in cutout 1 vss vdd vdd s u z x w y bottom view a a a a aa aa a a a a a a aa aa a a
15 hx6409/hx6218/hx6136 package drawing for 6218 (22019075-001) package drawing for 6136 (22018696-001) all dimensions in inches a 0.092 0.010 a1 0.080 0.008 b 0.018 0.002 c 0.010 0.002 d/e 0.950 0.015 e 0.050 0.005 (1) f 0.800 0.008 (1) n 68 ref. terminal 1 id area f d/e (4 places) b e (n places) 61 9 10 26 27 43 44 60 c a 68 1 (1) bsc C basic lead spacing between centers a1 0.091 0.057 0.036 0.005 0.004 0.942 0.025 bsc .800 bsc dimensions in inches a a1 a2 b c d/e e e1 hd/he l n 0.109 0.063 0.047 0.009 0.008 0.958 2.505 ref. min max 2.485 0.575 132 index corner & terminal no. 1 id area e1 hd/he d/e 4 places b e l 4 places n places 100 132 1 33 34 66 67 99 non-conductive tie bar: 4 places a2 c a1 a
honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. h oneywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. source h=honeywell x h process x=soi c input buffer type c=cmos level t=ttl level h 900157, rev. d 2/99 total dose hardness r=1x10 5 rad(sio 2 ) f=3x10 5 rad(sio 2 ) h=1x10 6 rad(sio 2 ) n=no level guaranteed ordering information (1) s screen level s=level s b=level b e=engr device (2) d package designation d=68-lead cqfp f=132-lead cqfp t=32-lead cqfp part number 6409 = 4k x 9 6218 = 2k x 18 6136 = 1k x 36 6409 to learn more about honeywell solid state electronics center, visit our web site at http://www.ssec.honeywell.com (1) orders may be faxed to 612-954-2051. please contact our customer service department at 612-954-2888 for further information. (2) engineering device description: parameters are tested from -55 to 125 c, 24 hr burn-in, no radiation guaranteed. contact factory with other needs. hx6409/hx6218/hx6136

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