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ddc112 1 ddc112 international airport industrial park ? mailing address: po box 11400, tucson, az 85734 ? street address: 6730 s. tucson bl vd., tucson, az 85706 ? tel: (520) 746-1111 twx: 910-952-1111 ? internet: http://www.burr-brown.com/ ? cable: bbrcorp ? telex: 066-6491 ? fax: (520) 889-1510 ? i mmediate product info: (800) 548-6132 ddc112 dual current input 20-bit analog-to-digital converter features l monolithic charge measurement adc l digital filter noise reduction: 3.2ppm, rms l integral linearity: 0.005% reading 0.5ppm fsr l high precision, true integrating function l programmable full scale l single supply l cascadable output applications l direct photosensor digitization l ct scanner das l infrared pyrometer l precision process control l liquid/gas chromatography l blood analysis description the ddc112 is a dual input, wide dynamic range, charge-digitizing analog-to-digital converter (adc) with 20-bit resolution. low level current output devices, such as photosensors, can be directly connected to its inputs. charge integration is continuous as each input uses two integrators; while one is being digitized, the other is integrating. for each of its two inputs, the ddc112 combines current-to-voltage conversion, continuous integration, programmable full-scale range, a/d conversion, and digital filtering to achieve a precision, wide dynamic range digital result. in addition to the internal program- mable full-scale ranges, external integrating capacitors allow an additional user-settable full-scale range of up to 1000pc. to provide single-supply operation, the internal adc utilizes a differential input, with the positive input tied to v ref . when the integration capacitor is reset at the beginning of each integration cycle, the capacitor charges to v ref . this charge is removed in proportion to the input current. at the end of the integration cycle, the remaining voltage is compared to v ref . the high-speed serial shift register which holds the result of the last conversion can be configured to allow multiple ddc112 units to be cascaded, minimizing interconnections. the ddc112 is available in a so-28 package and is offered in two performance grades. protected by us patent #5841310 dual switched integrator dual switched integrator ds modulator digital filter control digital input/output dvalid dxmit dout din dclk range2 range1 range0 test conv clk cap1a cap1a cap1b cap1b cap2a cap2a cap2b cap2b in2 in1 v ref dgnd dv dd agnd av dd channel 1 channel 2 ? 1997 burr-brown corporation pds-1421d printed in u.s.a. january, 2000 for most current data sheet and other product information, visit www.burr-brown.com sbas085
2 ddc112 specifications at t a = +25 c, av dd = dv dd = +5v, ddc112u: t int = 500 m s, clk = 10mhz, ddc112uk: t int = 333.3 m s, clk = 15mhz, v ref = +4.096v, continuous mode operation, and internal integration capacitors, unless otherwise noted. notes: (1) input is less than 1% of full scale. (2) c sensor is the capacitance seen at the ddc112 inputs from wiring, photodiode, etc. (3) fsr is full-scale range. (4) a best-fit line is used in measuring linearity. (5) matching between side a and side b, not input 1 to input 2. (6) voltage produced by the ddc112 at its input which is applied to the sensor. (7) range drift does not include external reference drift. (8) input reference current decreases with increasing t int (see text). (9) data format is straight binary with a small offset (see text). (10) guaranteed but not tested. ddc112u ddc112uk parameter conditions min typ max min typ max units analog inputs external, positive full-scale range 0 c ext = 250pf 1000 [ pc internal, positive full-scale range 1 47.5 50 52.5 [[[ pc range 2 95 100 105 [[[ pc range 3 142.5 150 157.5 [[[ pc range 4 190 200 210 [[[ pc range 5 237.5 250 262.5 [[[ pc range 6 285 300 315 [[[ pc range 7 332.5 350 367.5 [[[ pc negative full-scale input C0.4% of positive fs [ pc dynamic characteristics conversion rate 2 3 khz integration time, t int continuous mode 500 1,000,000 333.3 [ m s integration time, t int non-continuous mode 50 [ m s system clock input (clk) 1 10 12 [[ 15 mhz data clock (dclk) 12 15 mhz accuracy noise, low level current input (1) c sensor (2) = 0pf, range 5 (250pc) 3.2 [ ppm of fsr (3) , rms c sensor = 25pf, range 5 (250pc) 3.8 [ ppm of fsr, rms c sensor = 50pf, range 5 (250pc) 4.2 6.0 [ 7 ppm of fsr, rms differential linearity error 0.005% reading 0.5ppm fsr, max [ integral linearity error (4) 0.005% reading 0.5ppm fsr, typ [ 0.025% reading 1.0ppm fsr, max [ no missing codes 20 [ bits input bias current t a = +25 c 0.1 10 [[ pa range error range 5 (250pc) 5 [ % of fsr range error match (5) all ranges 0.1 0.5 [[ % of fsr range sensitivity to v ref v ref = 4.096 0.1v 1:1 [ offset error range 5, (250pc) 200 [ 600 ppm of fsr offset error match (5) 100 [ ppm of fsr dc bias voltage (6) (input v os ) 0.05 2 [[ mv power supply rejection ratio 25 200 [[ ppm of fsr/v internal test signal 13 [ pc internal test accuracy 10 [ % performance over temperature offset drift 0.5 3 (10) ppm of fsr/ c offset drift stability 0.2 [ 0.7 (10) ppm of fsr/minute dc bias voltage drift applied to sensor input 3 1 m v/ c input bias current drift +25 c to +45 c 0.01 1 (10) [[ pa/ c input bias current t a = +75 c250 (10) [[ pa range drift (7) range 5 (250pc) 25 0 25 50 (10) ppm/ c range drift match (5) range 5 (250pc) 0.05 [ ppm/ c reference voltage 4.000 4.096 4.200 [[[ v input current (8) t int = 500 m s 150 225 275 m a digital input/output logic levels v ih 4.0 dv dd + 0.3 [[ v v il C0.3 +0.8 [[ v v oh i oh = C500 m a 4.5 [ v v ol i ol = 500 m a 0.4 [ v input current, i in C10 +10 [[ m a data format (9) straight binary [ power supply requirements power supply voltage av dd and dv dd 4.75 5.25 [[ v supply current analog current av dd = +5v 14.8 15.2 ma digital current dv dd = +5v 1.2 1.8 ma total power dissipation 80 100 85 130 mw temperature range specified performance C40 +85 0 +70 c storage C60 +100 [[ c
ddc112 3 pin descriptions pin label description 1 in1 input 1: analog input for integrators 1a and 1b. the integrator that is active is set by the conv input. 2 agnd analog ground. 3 cap1b external capacitor for integrator 1b. 4 cap1b external capacitor for integrator 1b. 5 cap1a external capacitor for integrator 1a. 6 cap1a external capacitor for integrator 1a. 7av dd analog supply, +5v nominal. 8 test test control input. when high, a test charge is applied to the a or b integrators on the next conv transition. 9 conv controls which side of the integrator is connected to input. in continuous mode; conv high ? side a is integrating, conv low ? side b is integrating. conv must be synchronized with clk (see text). 10 clk system clock input, 10mhz nominal. 11 dclk serial data clock input. this input operates the serial i/o shift register. 12 dxmit serial data transmit enable input. when low, this input enables the internal serial shift register. 13 din serial digital input. used to cascade multiple ddc112s. 14 dv dd digital supply, +5v nominal. 15 dgnd digital ground. 16 dout serial data output, hi-z when dxmit is high. 17 dvalid data valid output. a low value indicates valid data is available in the serial i/o register. 18 range0 range control input 0 (least significant bit). 19 range1 range control input 1. 20 range2 range control input 2 (most significant bit). 21 agnd analog ground. 22 v ref external reference input, +4.096v nominal. 23 cap2a external capacitor for integrator 2a. 24 cap2a external capacitor for integrator 2a. 25 cap2b external capacitor for integrator 2b. 26 cap2b external capacitor for integrator 2b. 27 agnd analog ground. 28 in2 input 2: analog input for integrators 2a and 2b. the integrator that is active is set by the conv input. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or omissions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr- brown product for use in life support devices and/or systems. av dd to dv dd ....................................................................... C0.3v to +6v av dd to agnd ..................................................................... C0.3v to +6v dv dd to dgnd ..................................................................... C0.3v to +6v agnd to dgnd ............................................................................... 0.3v v ref voltage to agnd ............................................ C0.3v to av dd +0.3v digital input voltage to dgnd ................................ C0.3v to dv dd +0.3v digital output voltage to dgnd ............................. C0.3v to dv dd +0.3v package power dissipation ............................................. (t jmax C t a )/ q ja maximum junction temperature (t jmax ) ...................................... +150 c thermal resistance, q ja ............................................................. 150 c/w lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maxi- mum conditions for extended periods may affect device reliability. absolute maximum ratings (1) pin configuration top view so 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 in2 agnd cap2b cap2b cap2a cap2a v ref agnd range2 (msb) range1 range0 (lsb) dvalid dout dgnd in1 agnd cap1b cap1b cap1a cap1a av dd test conv clk dclk dxmit din dv dd ddc112 package/ordering information maximum specification package integral temperature drawing ordering transport product linearity error range package number number (1) media ddc112u 0.025% reading 1.0ppm% fsr C40 c to +85 c so-28 217 ddc112u rails """"" ddc112u/1k tape and reel ddc112uk 0.025% reading 1.0ppm% fsr 0 c to +70 c so-28 217 ddc112uk rails """"" ddc112uk/1k tape and reel notes: (1) models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /1k indicates 1000 devices p er reel). ordering 1000 pieces of ddc112u/1k will get a single 1000-piece tape and reel. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. burr-brown recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
4 ddc112 noise vs t int 1 1000 0.1 100 10 t int (ms) noise (ppm of fsr, rms) 0 1 2 3 4 5 6 c sensor = 50pf c sensor = 0pf range 5 typical performance curves at t a = +25 c, characterization done with range 5 (250pc), t int = 500 m s, v ref = +4.096, av dd = dv dd = +5v, and clk = 10mhz, unless otherwise noted. noise vs c sensor 200 800 0 1000 600 400 c sensor (pf) noise (ppm of fsr, rms) 0 10 20 30 40 50 60 70 range 7 range 2 range 1 range 0 (c ext = 250pf) noise vs input level 30 40 20 90 10 100 70 80 10 50 60 input level (% of full-scale) noise (ppm of fsr, rms) 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 c sensor = 50pf c sensor = 0pf range 5 noise vs temperature 9 8 7 6 5 4 3 2 1 0 ?0 ?5 10 35 60 85 temperature ( c) noise (ppm of fsr, rms) range 1 range 2 range 7 range 3 c sensor = 0pf range drift vs temperature ?0 ?5 10 35 60 85 temperature ( c) range drift (ppm) ranges 1 - 7 (internal integration capacitor) 2000 1500 1000 500 0 ?00 ?000 ?500 i b vs temperature 25 35 45 55 65 75 85 temperature (?) i b (pa) all ranges 10 1 0.1 0.01
ddc112 5 typical performance curves (cont.) at t a = +25 c, characterization done with range 5 (250pc), t int = 500 m s, v ref = +4.096, av dd = dv dd = +5v, and clk = 10mhz, unless otherwise noted. 600 power supply rejection ratio vs frequency 0 100 25 75 50 frequency (khz) psrr (ppm of fsr/v) 0 100 200 300 400 500 input v os vs range 36 35 34 33 32 31 30 1234567 range v os (?) digital supply current vs temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?0 ?5 10 35 60 85 temperature (?) current (ma) analog supply current vs temperature 18 16 14 12 10 8 6 4 2 0 ?0 ?5 10 35 60 85 temperature (?) current (ma) offset drift vs temperature 25 35 45 55 65 75 85 temperature ( c) offset drift (ppm of fsr) 100 50 0 ?0 ?00 all ranges crosstalk vs frequency 0 ?0 ?0 ?0 ?0 ?00 ?20 ?40 0 100 200 300 400 500 frequency (hz) separation (db) separation measured between inputs 1 and 2
6 ddc112 theory of operation the basic operation of the ddc112 is illustrated in figure 1. the device contains two identical input channels where each performs the function of current-to-voltage integration fol- lowed by a multiplexed analog-to-digital (a/d) conversion. each input has two integrators so that the current-to-voltage integration can be continuous in time. the output of the four integrators are switched to one delta-sigma converter via a four input multiplexer. with the ddc112 in the continuous integration mode, the output of the integrators from one side of both of the inputs will be digitized while the other two integrators are in the integration mode as illustrated in the timing diagram in figure 2. this integration and a/d con- version process is controlled by the system clock, clk. with a 10mhz system clock, the integrator combined with the delta-sigma converter accomplishes a single 20-bit con- version in approximately 220 m s. the results from side a and side b of each signal input are stored in a serial output shift register. the dvalid output goes low when the shift register contains valid data. the digital interface of the ddc112 provides the digital results via a synchronous serial interface consisting of a data clock (dclk), a transmit enable pin (dxmit), a valid data pin (dvalid), a serial data output pin (dout), and a serial data input pin (din). the ddc112 contains only one a/d converter, so the conversion process is interleaved between the two inputs, as shown in figure 2. the integration and conversion process is fundamentally independent of the data retrieval process. consequently, the clk frequency and dclk frequencies need not be the same. din is only used when multiple converters are cascaded and should be tied to dgnd otherwise. depending on t int , clk, and dclk, it is possible to daisy chain over 100 converters. this greatly simplifies the interconnection and routing of the digital outputs in those cases where a large number of converters are needed. dual switched integrator dual switched integrator ds modulator digital filter control digital input/output dvalid dxmit dout din dclk range2 range1 range0 test conv clk cap1a cap1a cap1b cap1b cap2a cap2a cap2b cap2b in2 in1 v ref dgnd dv dd agnd av dd input 1 input 2 in1, integrator a in1, integrator b in2, integrator a in2, integrator b conversion in progress dvalid in1b in2b in1a integrate integrate integrate integrate integrate integrate integrate integrate in2a in1b in2b in1a in2a figure 2. basic integration and conversion timing for the ddc112 (continuous mode). figure 1. ddc112 block diagram.
ddc112 7 device operation basic integration cycle the fundamental topology of the front end of the ddc112 is a classical analog integrator as shown in figure 3. in this diagram, only input 1 is shown. this representation of the input stage consists of an operational amplifier, a selectable feedback capacitor network (c f ), and several switches that implement the integration cycle. the timing relationships of all of the switches shown in figure 3 are illustrated in figure 4. figure 4 is used to conceptualize the operation of the integrator input stage of the ddc112 and should not be used as an exact timing tool for design. block diagrams of the reset, integrate, converter and wait states of the integrator section of the ddc112 are shown in figure 5. this internal switching network is controlled externally with the convert command (conv), range selection pins (range0- range2), and the system clock (clk). for the best noise performance, conv must be synchronized with the rising edge of clk. it is recommended conv toggle within 10ns of the rising edge of clk. the non-inverting inputs of the integrators are internally referenced to ground. consequently, the ddc112 analog ground should be as clean as possible. the range switches, along with the internal and external capacitors (c f ) are shown in parallel between the inverting input and output of the operational amplifier. table i shows the value of the integration capacitor (c f ) for each range. at the beginning of a conversion, the switches s a/d , s inta , s intb , s ref1 , s ref2 , and s reset are set (see figure 4). at the completion of an a/d conversion, the charge on the integration capacitor (c f ) is reset with s ref1 and c f input range range2 range1 range0 (pf, typ) (pc, typ) 0 0 0 external up to 1000 12.5 to 250 0 0 1 12.5 C0.2 to 50 0 1 0 25 C0.4 to 100 0 1 1 37.5 C0.6 to 150 1 0 0 50 C0.8 to 200 1 0 1 62.5 C0.1 to 250 1 1 0 75 C1.2 to 300 1 1 1 87.5 C1.4 to 350 table i. range selection of the ddc112. figure 3. basic integrator configuration for input 1 shown with a 250pc (c f = 62.5pf) input range. s reset (see figures 4 and 5a). this is done during the reset time. in this manner, the selected capacitor is charged to the reference voltage, v ref . once the integration capacitor is charged, s ref1 , and s reset are switched so that v ref is no longer connected to the amplifier circuit while it waits to begin integrating (see figure 5b). with the rising edge on conv, s inta closes which begins the integration of chan- nel a. this puts the integrator stage into its integrate mode (see figure 5c). charge from the input signal is collected on the integration capacitor causing the voltage output of the amplifier to decrease. a falling edge conv stops the integration by switching the input signal from side a to side b (s inta and s intb ). prior to the falling edge of conv, the signal on side b was converted by the a/d converter and reset during the time that side a was integrating. with the falling edge of conv, side b starts integrating the input signal. now the output voltage of side as operational amplifier is presented to the input of the ds a/d converter (see figure 5d). 50pf cap1a cap1a 25pf 12.5pf v ref range2 range1 range0 to converter s reset s ref2 s a/d1a s inta s ref1 s intb in1 esd protection diode input current integrator a integrator b (same as a) photodiode
8 ddc112 figure 5. diagrams for the four configurations of the front end integrators of the ddc112. figure 4. basic integrator timing diagram as illustrated in figure 3. to converter s reset s ref2 s a/d v ref s ref1 s int in c f a) reset configuration to converter s reset s ref2 s a/d v ref s ref1 s int in c f c) integrate configuration to converter s reset s ref2 s a/d v ref s ref1 s int in c f d) convert configuration to converter s reset s ref2 s a/d v ref s ref1 s int in c f b) wait configuration s a/d1a v ref integrator a voltage output configuration of integrator a wait convert wait convert integrate s ref1 s ref2 s inta s intb s reset conv clk wait reset wait reset
ddc112 9 determining the integration capacitor (c f ) value the value of the integrators feedback capacitor, the integra- tion period, and the reference voltage determine the positive full-scale (+fs) value of the ddc112. the approximate positive full-scale value of the ddc112 is given by the following equations: the 0.96 factor allows the front end integraters to reach full scale without having to completely swing to ground. the negative full-scale (Cfs) range is approximately 0.4% of the positive full-scale range. for example, range 5 has a nominal +fs range of 250pc. the Cfs range is then ap- proximately C1pc. this relationship holds for external ca- pacitors as well and is independent of v ref (for v ref within the allowable range, see the specification table). integration capacitors there are seven different capacitors available on chip for each side of each channel in the ddc112. these internal capacitors are trimmed in production to achieve the speci- fied performance for range error of the ddc112. the range control pins (range0-range2) change the capacitor value for all four integrators. consequently, both inputs and both sides of each input will always have the same full scale range unless external capacitors are used. external integration capacitors may be used instead of the internal capacitors values by setting range2-range0 = 000. the external capacitor pin connections are sum- marized in table ii. usually, all four external capacitors are equal in value, however, it is possible to have differ- ing pairs of external capacitors between input 1 and input 2 of the ddc112. regardless of the selected value of the capacitor, it is strongly recommended that the capacitors for sides a and b be the same. integrator external capacitor pins on the ddc112 channel side 5 and 6 1 a 3 and 4 1 b 23 and 24 2 a 25 and 26 2 b table ii. external capacitor connections with range con- figuration of range2-range0 = 000. since the range accuracy depends on the characteristics of the integration capacitor, they must be carefully selected. an external integration capacitor should have low voltage coef- ficient, temperature coefficient, memory, and leakage cur- rent. the optimum selection depends on the requirements of the specific application. suitable types include cog ce- ramic, polycarbonate, polystyrene, and silver mica. voltage reference the external voltage reference is used to reset the integration capacitors before an integration cycle begins. it is also used by the ds converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. during this sampling, the external reference must supply charge needed by the ds converter. for an integra- tion time of 500 m s, this charge translates to an average v ref current of approximately 150 m a. the amount of charge needed by the ds converter is independent of the integration time, therefore, increasing the integration time lowers the average current. for example, an integration time of 1000 m s lowers to average v ref current to 75 m a. it is critical that v ref be stable during the different modes of operation shown in figure 5. the ds converter measures the voltage on the integrator with respect to v ref . since the integrators capacitors are initially reset to v ref , any droop in v ref from the time the capacitors are reset to the time when the converter measures the integrators output will introduce an offset. it is also important that v ref be stable over longer periods of time as changes in v ref correspond directly to changes in the full-scale range. finally, v ref should introduce as little additional noise as possible. for reasons mentioned above, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in figure 6. in this circuit, the voltage reference is generated by a 4.096v reference. figure 6. recommended external voltage reference circuit for best low noise operation with the ddc112. 0.10 f +5v +5v 4.99k w 10k w 10 f lm404-4.1 4 3 1 2 7 6 + 0.10 f 0.1 f 10 f + opa350 to v ref pin 22 of the ddc112 qit qvc i vc t or c it v in in int fs ref f fs ref f int f fs int ref = = () = () = . . (. ) 096 096 096
10 ddc112 clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t 1 setup time for test mode enable 100 100 ns t 2 setup time for test mode disable 100 100 ns t 3 hold time for test mode enable 100 100 ns t 4 from rising edge of test to the edge of conv 5.4 3.6 m s while test mode enabled t 5 rising edge to rising edge of test 5.4 3.6 m s a low-pass filter to reduce noise connects it to an opera- tional amplifier configured as a buffer. this amplifier should have a unity gain bandwidth greater than 4mhz, low noise, and input/output common-mode ranges that support v ref . following the buffer are capacitors placed close to the ddc112s v ref pin. even though the circuit in figure 6 might appear to be unstable due to the large output capacitors, it works well for most operational amplifiers. it is not recommended that series resistance be placed in the output lead to improve stability since this can cause droop in v ref which produces large offsets. figure 8. timing diagram of the test mode of the ddc112. table iii. timing for the ddc112 in the test mode. ddc112 frequency response the frequency response of the ddc112 is set by the front end integrators and is that of a traditional continuous time integra- tor, as shown in figure 7. by adjusting t int , the user can change the 3db bandwidth and the location of the notches in the response. the frequency response of the ds converter that follows the front end integrator is of no consequence because the converter samples a held signal from the integrators. that is, the input to the ds converter is always a dc signal. since the output of the front end integrators are sampled, aliasing can occur. whenever the frequency of the input signal exceeds one-half of the sampling rate, the signal will fold back down to lower frequencies. test mode when test is used, pins in1 and in2 are grounded and packets of approximately 13pc charge are transferred to the integration capacitors of both input 1 and input 2. this fixed charge can be transferred to the integration capacitors either once during an integration cycle or multiple times. in the case where multiple packets are transferred during one integration period, the 13pc charge is additive. this mode can be used in both the continuous and non-continuous mode timing. the timing diagrams for test mode are shown in figure 8. the top three lines in figure 8 define the timing when one packet of 13pc is sent to the integration capaci- tors. the bottom three lines define the timing when multiple packets are sent to the integration capacitors. figure 7. frequency response of the ddc112. 0 ?0 ?0 ?0 ?0 ?0 0.1 t int 100 t int 1 t int 10 t int frequency gain (db) t 1 t 1 t 3 t 4 t 4 t 5 t 2 integrate b action conv test action conv test integrate a test mode disabled 13pc into b 13pc into a 13pc into b 13pc into a test mode disabled test mode enabled integrate b integrate a integrate b integrate a test mode disabled 13pc into b 26pc into a 39pc into b 52pc into a test mode disabled test mode enabled integrate b integrate a t 2
ddc112 11 test and conv work together to implement this feature. the test mode is entered when test is high prior to a conv edge. at that point, a conv edge triggers the grounding of the analog inputs and the switching of 13pc packets of charge onto the integration capacitors. if test is kept high through at least two conversions (i.e., a rise and fall of conv), all four integrators will be charged with a 13pc packet. at the end of each conversion, the voltage at the output of the integrators is digitized as discussed in the continuous mode and non-continuous mode section of this data sheet. the test mode is exited when test is low and a conv edge occurs. once the test mode is entered as described above, test can cycle as many times as desired. when this is done, additional 13pc packets are added on the rising edge of test to the existing charge on the integrator capacitors. multiple charge packets can be added in this way as long as the test pin is not low when conv toggles. digital issues the digital interface of the ddc112 provides the digital results via a synchronous serial interface consisting of a data clock (dclk), a transmit enable pin (dxmit), a valid data pin (dvalid), a serial data output pin (dout), and a serial data input pin (din). the ddc112 contains only one a/d converter, so the conversion process is interleaved between the two inputs (see figure 2). the integration and conversion process is fundamentally independent of the data retrieval process. consequently, the clk frequency and dclk fre- quencies need not be the same. din is used when multiple converters are cascaded. cascading or daisy chaining greatly simplifies the interconnection and routing of the digital outputs in cases where a large number of converters are needed. refer to cascading multiple converters section of this data sheet for more detail. the conversion rate of the ddc112 is set by a combination of the integration time (determined by the user) and the speed of the a/d conversion process. the a/d conversion time is primarily a function of the system clock (clk) speed. one a/d conversion cycle encompasses the conversion of two signals (one from each input of the ddc112) and reset time for each of the integrators involved in the two conversions. in most situations, the a/d conversion time is shorter than the integration time. if this condition exists, the ddc112 will operate in the continuous mode. when the ddc112 is in the continuous mode, the sensor output is continuously integrated by one of the two sides of each input. in the event that the a/d conversion takes longer than the integration time, the ddc112 will switch into a non-con- tinuous mode. in non-continuous mode, the a/d converter is not able to keep pace with the speed of the integration process. consequently, the integration process is periodi- cally halted until the digitizing process catches up. these two basic modes of operation for the ddc112continuous and non-continuous modesare described below. continuous and non-continuous operational modes the state diagram of the ddc112 is shown in figure 9. in all, there are 8 states. table iv provides a brief explanation of each of the states. state mode description 1 ncont complete m/r/az of side a, then side b (if previous state is state 4). initial power-up state when conv is initially held high. 2 ncont prepare side a for integration. 3 cont integrate on side a. 4 cont integrate on side b; m/r/az on side a. 5 cont integrate on side a; m/r/az on side b. 6 cont integrate on side b. 7 ncont prepare side b for integration. 8 ncont complete m/r/az of side b, then side a (if previous state is state 5). initial power-up state when conv is initially held low. table iv. state descriptions. int a/meas b cont 5 conv ?mbsy conv ?mbsy conv ?mbsy conv ?mbsy conv ?mbsy conv ?mbsy conv conv int b/meas a cont 4 ncont 1 ncont 2 int a cont 3 ncont 8 ncont 7 int b cont 6 conv conv mbsy mbsy figure 9. state diagram. four signals are used to control progression around the state diagram: conv and mbsy and their complements. the state machine uses the level as opposed to the edges of conv to control the progression. mbsy is an internally generated signal not available to the user. it is active whenever a measurement/reset/auto-zero (m/r/az) cycle is in progress.
12 ddc112 table v. timing specifications generalized in clk periods. symbol description value (clk periods) t 6 cont mode m/r/az cycle 4794 t 7 cont mode data ready 4212 (t int > 4794) 4212 3(t int = 4794) t 8 1st ncont mode data ready 4212 3 t 9 2nd ncont mode data ready 4548 t 10 ncont mode m/r/az cycle 9108 t 11 prepare side for integration 3 240 4 3 2 154 integrate b integrate a integrate a integrate b m/r/az a m/r/az b m/r/az a conv state mbsy m/r/az status integration status dvalid t 6 t 7 t = 0 power-up side a data side b data side a data figure 10. continuous mode timing (conv high at power-up). symbol description value (clk = 10mhz) value (clk = 15mhz) t 6 cont mode m/r/az cycle 479.4 m s 316.4 m s t 7 cont mode data ready 421.2 m s(t int > 479.4 m s) 280.5 m s(t int > 316.4 m s) 421.2 0.3 m s(t int = 479.4 m s) 280.5 0.2 m s(t int = 316.4 m s) during the cont mode, mbsy is not active when conv toggles. the non-integrating side is always ready to begin integrating when the other side finishes its integration. consequently, keeping track of the current status of conv is all that is needed to know the current state. cont mode operation corresponds to states 3-6. two of the states, 3 and 6, only perform an integration (no m/r/az cycle). mbsy becomes important when operating in the ncont mode; states 1, 2, 7, and 8. whenever conv is toggled while mbsy is active, the ddc112 will enter or remain in either ncont state 1 (or 8). after mbsy goes inactive, state 2 (or 7) is entered. this state prepares the appropriate side for integra- tion. as mentioned above, in the ncont states, the inputs to the ddc112 are grounded. one interesting observation from the state diagram is that the integrations always alternate between sides a and b. this relationship holds for any conv pattern and is inde- pendent of the mode. states 2 and 7 insure this relationship during the ncont mode. when power is first applied to the ddc112, the beginning state is either 1 or 8, depending on the initial level of conv. for conv held high at power-up, the beginning state is 1. conversely, for conv held low at power-up, the begin- ning state is 8. in general, there is a symmetry in the state diagram between states 1-8, 2-7, 3-6 and 4-5. inverting conv results in the states progressing through their sym- metrical match. timing examples cont mode a few timing diagrams will now be discussed to help illustrate the operation of the state machine. these are shown in figures 10 through 19. table v gives generalized timing specifications in units of clk periods. values in m s for table v can be easily found for a given clk. for example, if clk = 10mhz, then a clk period = 0.1 m s. t 6 in table v would then be 479.4 m s. figure 10 shows a few integration cycles beginning with initial power-up for a cont mode example. the top signal is conv and is supplied by the user. the next line indicates the current state in the state diagram. the following two traces show when integrations and measurement cycles are underway. the internal signal mbsy is shown next. finally, dvalid is given. as described in the data sheet, dvalid goes active low when data is ready to be retrieved from the ddc112. it stays low until dxmit is taken low by the user. in figure 10 and the following timing diagrams, it is assumed that dxmit it taken low soon after dvalid goes low. the text below the dvalid pulse indicates the side of the data and arrows help match the data to the corresponding integration. the signals shown in figures 10 through 19 are drawn at approximately the same scale. in figure 10, the first state is ncont state 1. the ddc112 always powers up in the ncont mode. in this case, the first state is 1 because conv is initially high. after the first two states, cont mode operation is reached and the states begin toggling between 4 and 5. from now on, the input is being continuously integrated, either by side a or side b.
ddc112 13 the time needed for the m/r/az cycle, t 6 , is the same time that determines the boundary between the cont and ncont modes described earlier in the overview section. dvalid goes low after conv toggles in time t 1 , indicating that data is ready to be retrieved. as shown in figure 10, there are two values for t 7 , depending on t int . the reason for this will be discussed in the special considerations section. figure 11 shows the result of inverting the logic level of conv. the only difference is in the first three states. afterwards, the states toggle between 4 and 5 just as in the previous example. figure 12 shows the timing diagram of the internal operations occurring during continuous mode operation. figure 11. continuous mode timing (conv low at power-up). 5 6 7 845 integrate a integrate b integrate b integrate a m/r/az b m/r/az a m/r/az b conv state integration status m/r/az status mbsy dvalid t 6 t 7 t = 0 power-up side b data side a data side b data figure 12. timing diagram of the internal operation in continuous mode of the ddc112. t 12 t 12 t 14 t 13 t int t int end integration side a start integration side b side a side a data ready side b data ready side b side a side b side a end integration side b start integration side a end integration side a start integration side b conv dvalid a/d conversion input 1 (internal) a/d conversion input 2 (internal) clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t int integration period (continuous mode) 500 1,000,000 333 1,000,000 m s t 12 a/d conversion time (internally controlled) 202.2 134.66 m s t 13 a/d conversion reset time (internally controlled) 13.2 8.8 m s t 14 integrator and a/d conversion reset time 61.8 41.2 m s (internally controlled) table vi. timing for the internal operation in the continuous mode.
14 ddc112 figure 13. non-continuous mode timing. ncont mode figure 13 illustrates operation in the ncont mode. the integrations come in pairs (i.e., sides a/b or sides b/a) followed by a time during which no integrations occur. during that time, the previous integrations are being mea- sured, reset and auto-zeroed. before the ddc112 can ad- vance to states 3 or 6, both sides a and b must be finished with the m/r/az cycle which takes time t 10 . when the m/r/az cycles are completed, time t 11 is needed to prepare the next side for integration. this time is required for the ncont mode because the m/r/az cycle of the ncont mode is slightly different from that of the cont mode. after the first integra- tion ends, dvalid goes low in time t 8 . this is the same time as in the cont mode. the second data will be ready in time t 9 after the first data is ready. one result of the naming convention used in this application bulletin is that when the ddc112 is operating in the ncont mode, it passes through both ncont mode states and cont mode states. for example, in figure 13, the state pattern is 3, 4, 1, 2, 3, 4, 1, 2, 3, 4...where 3 and 4 are cont mode states. ncont mode by definition means that for some portion of the time, neither side a nor b is integrating. states that perform an integration are labeled cont mode states while those that do not are called ncont mode states. since integrations are performed in the ncont mode, just not continuously, some cont mode states must be used in a ncont mode state pattern. symbol description value (clk = 10mhz) value (clk = 15mhz) t 8 1st ncont mode data ready 421.2 0.3 m s 280.5 0.2 m s t 9 2nd ncont mode data ready 4548.0 m s 3028.9 m s t 10 ncont mode m/r/az cycle 910.8 m s 601.1 m s t 11 prepare side for integration 3 24.0 m s 3 24.0 m s 23 1 34 4 1 2 int b int a int b int a m/r/az b m/r/az a m/r/az a m/r/az b conv state mbsy m/r/az status integration status dvalid t 10 t 9 t 11 t 8 side a data side b data side a data side b data
ddc112 15 clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t int integration time (non-continuous mode) 50 1,000,000 50 1,000,000 m s t 12 a/d conversion time (internally controlled) 202.2 134.6 m s t 13 a/d conversion reset time (internally controlled) 13.2 8.8 m s t 15 integrator and a/d conversion reset time 37.8 25.2 m s (internally controlled) t 16 total a/d conversion and rest time 910.8 606.6 m s (internally controlled) t 17 release time 24 24 m s figure 14. conversion detail for the internal operation of the non-continuous mode with side a integrated first. t 12 t int t int t 16 t 12 t 13 t 15 t 17 release state end integration side a start integration side b end integration side b wait state side a data ready side b data ready start integration side a start integration side a conv a/d conversion input 1 a/d conversion input 2 dvalid t 12 t int t int t 16 t 12 t 13 t 15 t 17 conv a/d conversion input 1 a/d conversion input 2 dvalid release state end integration side b start integration side a end integration side a wait state side b data ready side a data ready start integration side b start integration side b figure 15. internal operation timing diagram of the non-continuous mode with side b integrated first. table vii. internal timing for the ddc112 in the non-continuous mode.
16 ddc112 figure 16. equivalent conv signals in non-continuous mode. figure 17. non-continuous mode timing with a 50% duty cycle conv signal. conv1 conv2 23 1 34 4 1 2 state mbsy conv dvalid 23 1 34 41 state integration status mbsy int b int a int b side a data side b data side a data int a looking at the state diagram, one can see that the conv pattern needed to generate a given state progression is not unique. upon entering states 1 or 8, the ddc112 remains in those states until mbsy goes low, independent of conv. as long as the m/r/az cycle is underway, the state machine ignores conv (see figure 9). the top two signals are different conv patterns that produce the same state. this feature can be a little confusing at first, but it does allow flexibility in generating ncont mode conv patterns. for example, the ddc112 evaluation fixture operates in the ncont mode by generating a square wave with pulse width < t 6 . figure 17 illustrates operation in the ncont mode using a 50% duty cycle conv signal with t int = 1620 clk periods. care must be exercised when using a square wave to generate conv. there are certain integration times that must be avoided since they produce very short intervals for state 2 (or state 7 if conv is inverted). as seen in the state diagram, the state progresses from 2 to 3 as soon as conv is high. the state machine does not insure that the duration of state 2 is long enough to properly prepare the next side for integration (t 11 ). this must be done by the user with proper timing of conv. for example, if conv is a square wave with t int = 3042 clk periods, state 2 will only be 18 clk periods long, therefore, t 11 will not be met.
ddc112 17 conv 4 2 1 4 non-continuous continuous 33 state mbsy m/r/az status integration status m/r/az a m/r/az b m/r/az a int b int a integrate a integrate b figure 18. changing from continuous mode to non-continuous mode. figure 19. changing from non-continuous mode to continuous mode. conv 87 45 continuous non-continuous 5 65 state integration status m/r/az status mbsy m/r/az b m/r/az a m/r/az b m/r/az a m/r/az b integrate a integrate b int a int a int b changing between modes changing from the cont to ncont mode occurs whenever t int < t 6 . figure 18 shows an example of this transition. in this figure, the cont mode is entered when the integration on side a is completed before the m/r/az cycle on side b is complete. the ddc112 completes the measurement on sides b and a during states 8 and 7 with the input signal shorted to ground. ncont integration begins with state 6. changing from the ncont to cont mode occurs when t int is increased so that t int is always 3 t 6 (see figure 14). with a longer t int , the m/r/az cycle has enough time to finish before the next integration begins and continuous integra- tion of the input signal is possible. for the special case of the very first integration when changing to the cont mode, t int can be < t 6 . this is allowed because there is no simultaneous m/r/az cycle on the side b during state 3 there is no need to wait for it to finish before ending the integration on side a.
18 ddc112 special considerations ncont mode integration time the ddc112 uses a relatively fast clock. for clk = 10mhz, this allows t int to be adjusted in steps of 100ns since conv should be synchronized to clk. however, for the internal measurement, reset and auto-zero operations, a slower clock is more efficient. the ddc112 divides clk by six and uses this slower clock with a period of 600ns to run the m/r/az cycle and data ready logic. because of the divider, it is possible for the integration time to be a non-integer number of slow clock periods. for example, if t int = 5000 clk periods (500 m s for clk = 10mhz), there will be 833 1/3 slow clocks in an integration period. this non-integer relationship between t int and the slow clock period causes the number of rising and falling slow clock edges within an integration period to change from integration to integration. the digital coupling of these edges to the integrators will in turn change from integration to integration which produces noise. the change in the clock edges is not random, but will repeat every 3 integrations. the coupling noise on the integrators appears as a tone with a frequency equal to the rate at which the coupling repeats. to avoid this problem in cont mode, the internal slow clock is shut down after the m/r/az cycle is complete when it is no longer needed. it starts up again just after the next integra- tion begins. since the slow clock is always off when conv toggles, the same number of slow clock edges fall within an integration period regardless of its length. therefore, t int 3 4794 clk periods will not produce the coupling problem described above. for the ncont mode however, the slow clock must always be left running. the m/r/az cycle is not completed before an integration ends. it is then possible to have digital coupling to the integrators. the digital coupling noise depends heavily on the layout of the printed circuit board used for the ddc112. for solid grounds and power supplies with good bypassing, it is possible to greatly reduce the coupling. however, for guaranteeing the best performance in the ncont mode, the integration time should be chosen to be an integer multiple of 1/(2f slowclock ). for clk = 10mhz, the inte- gration time should be an integer multiple of 300ns t int = 100 m s is not. a better choice would be t int = 99 m s. data ready the dvalid signal which indicates that data is ready is generated using the internal slow clock. the phase relation- ship between this clock and clk is set when power is first applied and is random. since conv is synchronized with clk, it will have a random phase relationship with respect to the slow clock. when t int > t 6 , the slow clock will temporarily shut down as described above. this shutdown process synchronizes the internal clock with conv so that the time between when conv toggles to when dvalid goes low (t 7 and t 8 ) is fixed. for t int t 6 , the internal slow clock, is not allowed to shut down and the synchronization never occurs. therefore, the time between conv toggling and dvalid indicating data is ready has uncertainty due to the random phase relation- ship between conv and the slow clock. this variation is 1/(2f slowclock ) or 3/f clk . the timing to the second dvalid in the ncont mode will not have a variation since it is triggered off the first data ready (t 9 ) and both are derived from the slow clock. polling dvalid to determine when data is ready eliminates any concern about the variation in timing since the readback is automatically adjusted as needed. if the data readback is triggered off the toggling of conv directly (instead of polling), then waiting the maximum value of t 7 or t 8 insures that data will always be ready before readback occurs. data retrieval in the continuous and non-continuous modes of operation, the data from the last conversion is available for retrieval with the falling edge of dvalid (see figure 22). the falling edge of dxmit in combination with the data clock (dclk) will initiate the serial transmission of the data from the ddc112. typically, data is retrieved from the ddc112 as soon as dvalid falls and completed before the next conv transition from high to low or low to high occurs. if this is not the case, care should be taken to stop activity on dclk and consequently dout by at least 10 m s around a conv transition. if this caution is ignored it is possible that the integration that is being initiated by conv will have additional noise introduced. the serial output data at dout is transmitted in straight binary code per table viii. an output offset has been built into the ddc112 to allow for the measurement of input signals near and below zero. board leakage up to ? C0.4% of the positive full scale can be tolerated before the digital output clips to all zeroes. cascading multiple converters multiple ddc112 units can be connected in serial or parallel configurations, as illustrated in figures 20 and 21. dout can be used with din to daisy chain several ddc112 devices together to minimize wiring. in this mode of operation, the serial data output is shifted through mul- tiple ddc112s, as illustrated in figure 20. r pullup prevents din from floating when dxmit is high. care should be taken to keep the capacitive load on dout as low as possible when running clk=15mhz. code input signal 1111 1111 1111 1111 1111 fs 1111 1111 1111 1111 1110 fs C 1lsb 0000 0001 0000 0000 0001 +1lsb 0000 0001 0000 0000 0000 zero 0000 0000 0000 0000 0000 C0.4% fs table viii. straight binary code table.
ddc112 19 figure 20. daisy-chained ddc112s. in1 in2 dclk dxmit din dvalid dout ddc112 ? ? sensor ? sensor ? in1 in2 dclk dxmit din dvalid dout ddc112 ? ? sensor ? sensor ? in1 in2 dclk dxmit din dvalid dout data retrieval outputs ddc112 ? ? sensor ? sensor ? r p r p r p data retrievel inputs 40 bits 40 bits 40 bits figure 21. ddc112 in parallel operation. symbol description min typ max units t 18 propagation delay from rising edge of clk to dvalid low 30 ns t 19 propagation delay from dxmit low to dvalid high 30 ns t 20 setup time from dclk low to dxmit low 20 ns t 21 propagation delay from dxmit low to valid dout 30 ns t 22 hold time that dout is valid after falling edge of dclk 5 ns t 23 propagation delay from dxmit high to dout disabled 30 ns t 22a (1) propagaton delay from falling edge of dclk to valid dout 25 ns t 22b (2) propagation delay from falling edge of dclk to valid dout 30 ns notes: (1) applies to ddc112uk only, with a maximum load of one ddc112uk din (4pf typical) with an additional load of (5pf 100k w). (2) applies to ddc112u only, with a maximum load of one ddc112u din (4pf typical) with an additional load of (5pf 100k w). figure 22. digital interface timing diagram for data retrieval from a single ddc112. table ix. timing for the ddc112 data retrieval. din din din dout dxmit ddc112 data output ddc112 ddc112 enable dout dxmit dout dxmit t 18 t 19 t 20 t 21 t 22 t 23 input 2 bit 1 input 2 bit 20 input 1 bit 1 input 1 bit 20 msb lsb msb output disabled output enabled output disabled lsb clk dvalid dxmit dclk (1) dout note: (1) disable dclk (preferably hold low) when dxmit is high.
20 ddc112 retrieval before conv toggles (continuous mode) this is the most straightforward method. data retrieval begins soon after dvalid goes lo and finishes before conv toggles, see figure 24. for best performance, data retrieval must stop t 28 before conv toggles. this method is the most appropriate for longer integration times. the maxi- mum time available for readback is t int C t 27 C t 28 . for dclk and clk = 10mhz, the maximum number of ddc112s that can be daisy-chained together is: where t dclk is the period of the data clock. for example, if tint = 100 m s and dclk = 10mhz, the maximum number of ddc112s is: retrieval after conv toggles (continuous mode) for shorter integration times, more time is available if data retrieval begins after conv toggles and ends before the new data is ready. data retrieval must wait t 29 after conv toggles before beginning. figure 25 shows an example of this. the maximum time available for retrieval is t 27 C t 29 C t 26 (421.2 m s C 10 m s C2 m s for clk = 10mhz), regardless of tint. the maximum number of ddc112s that can be daisy-chained together is: for dclk = 10mhz, the maximum number of ddc112s is 102. figure 23. timing diagram when using the din function of the ddc112. ts int dclk . 431 2 40 m t 1000 431 2 40 100 142 2 142 112 mm =? ss ns ddc s . ()( ) . 409 2 40 . m s dclk t t 18 t 14 t 20 t 21 t 22 t 23 t 24 t 25 output disabled output enabled output disabled clk dvalid dxmit dclk (1) din input a bit 1 input e bit 20 input f bit 1 input f bit 20 msb output disabled output enabled lsb lsb output disabled msb dout note: (1) disable dclk (preferably low) when dxmit is high. t 26 t 22a, t 22b table x. timing for the ddc112 data retrieval using din. clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t 24 set-up time from din to rising edge of dclk 10 5 ns t 25 hold time for din after rising edge of dclk 10 10 ns t 26 hold time for dxmit high before falling 2 1.33 m s edge of dvalid
ddc112 21 clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t 27 cont mode data ready 421.2 280.5 m s t 28 data retrieval shutdown before edge of conv 10 10 m s side b data side a data t int t int t 27 t 28 conv dvalid dxmit dclk dout figure 24. readback before conv toggles. t int t 27 t 29 t 26 t int t int side a data side b data side a data conv dvalid dxmit dclk dout figure 25. readback after conv toggles. clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t 26 hold time for dxmit high before falling edge 2 1.33 m s of dvalid t 27 cont mode data ready 421.2 280.5 m s t 29 data retrieval start-up before edge of conv 10 10 m s
22 ddc112 retrieval before and after conv toggles (continuous mode) for the absolute maximum time for data retrieval, data can be retrieved before and after conv toggles. nearly all of t int is available for data retrieval. figure 26 illustrates how this is done by combining the two previous methods. you must pause the retrieval during convs toggling to prevent digital noise, as discussed previously, and finish before the next data is ready. the maximum number of ddc112s that can be daisy-chained together is: for t int = 500 m s and dclk = 10mhz, the maximum number of ddc112s is 119. dclk dxmit dvalid conv dout side b data side a data t int t 29 t 28 t 26 t int t int figure 26. readback before and after conv toggles. tss int dclk 20 2 40 mm t clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t 26 hold time for dxmit high before falling 2 1.33 m s edge of dvalid t 28 data retrieval shutdown before edge of conv 10 10 m s t 29 data retrieval start-up after edge of conv 10 10 m s
ddc112 23 retrieval: noncontinuous mode retrieving in noncontinuous mode is slightly different as compared with the continuous mode. as shown in figure 27 and described in detail in application bulletin ab-131, dvalid goes low in time t 30 after the first integration completes. if t int is shorter than this time, all of t 31 is available to retrieve data before the other sides data is ready. for t int > t 30 , the first integrations data is ready before the second integration completes. data retrieval must be delayed until the second integration completes leaving less time available for retrieval. the time available is t 31 C (t int C t 30 ). the second integrations data must be retrieved before the next round of integrations begin. this time is highly dependent on the pattern used to generate conv. as with the continuous mode, data retrieval must halt before and after conv toggles (t 28 , t 29 ) and be com- pleted before new data is ready (t 26 ). power-up sequencing prior to power-up, all digital and analog input pins must be low. at the time of power-up, these signal inputs can be biased to a voltage other than 0v, however, they should never exceed av dd or dv dd . the level of conv at power- up is used to determine which side (a or b) will be integrated first. before integrations can begin though, conv must toggle, as shown in figure 28. t int t int t 30 t int t int t 31 side a data side b data conv dvalid dxmit dclk dout figure 27. readback in noncontinuous mode. figure 28. timing diagram at power-up of the ddc112. t 32 t 33 integrate side a integrate side b power-up initialization release state start integration conv (high at power-up) conv (low at power-up) power supplies symbol description min typ max units t 32 power-on initialization period 50 m s t 33 from release edge to integration start 50 m s table xi. timing for the ddc112 power-up sequence. clk = 10mhz clk = 15mhz symbol description min typ max min typ max units t 30 1st ncont mode data ready (see ab-131) 421.2 0.3 280.5 0.2 m s t 31 2nd ncont mode data ready (see ab-131) 454.8 302.9 m s
24 ddc112 figure 30. recommended shield for ddc112 layout design. figure 29. power supply connection options. ddc112 0.1 f < 10 w 10 f v s + one +5v supply av dd dv dd av dd dv dd ddc112 0.1 f 0.1 f 0.1 f 10 f v s + separate +5v supplies 10 f v dd + 7 14 7 14 layout power supplies and grounding both av dd and dv dd should be as quiet as possible. it is particularly important to eliminate noise from av dd that is non-synchronous with the ddc112 operation. figure 29 illustrates two acceptable ways to supply power to the ddc112. the first case shows two separate +5v supplies for av dd and dv dd . in this case, each +5v supply of the ddc112 should be bypassed with 10 m f solid tantalum capacitors and 0.1 m f ceramic capacitors. the second case shows the dv dd power supply derived from the av dd supply with a < 10 w isolation resistor. in both cases, the 0.1 m f capacitors should be placed as close to the ddc112 package as possible. shielding analog signal paths as with any precision circuit, careful printed circuit layout will ensure the best performance. it is essential to make short, direct interconnections and avoid stray wiring capaci- tanceparticularly at the analog input pins. digital signals should be kept as far from the analog input signals as possible on the pc board. input shielding practices should be taken into consideration when designing the circuit layout for the ddc112. the inputs to the ddc112 are high impedance and extremely sensitive to extraneous noise. leakage currents between the pcb traces can exceed the input bias current of the ddc112 if shielding is not implemented. figure 30 illustrates an acceptable approach to this problem. a pc ground plane is placed around the inputs of the ddc112 (pins 1 and 28). this shield helps minimize coupled noise into the input pins. additionally, the pins that are used for the external integra- tion capacitors (pins 3, 4, 5, 6, 23, 24, 25 and 26) should be guarded by a ground plane when the external capacitors are used. the approach above reduces leakage affects by surrounding these sensitive pins with a low impedance analog ground. leakage currents from other portions of the circuit will flow harmlessly to the low impedance analog ground rather than into the analog input stage of the ddc112. ddc112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 digital i/o and digital power digital i/o and digital power shield external caps when used analog ground analog power shield external caps when used analog ground analog ground in1 in2 analog ground
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