july 2003 the following document refers to spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this document as a result of offering the device as a spansion product. any changes that have been made are the result of normal documentation impr ovements and are noted in the document revision summary, where supported. future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use on ly the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. amd mirrorbit? white paper publication number 25260 revision c amendment 0 issue date september 18, 2002
white paper
amd mirrorbit ? white paper o verview amd continues to revolutionize the world of flash memory. in 1991 amd introduced negative gate erase, a revolutionary architecture that enabled highly reliable, single power flash memory. in 2001, amd announced the mirrorbit? architecture, which C for the first time C enables a flash memory product to hold twice as much data as standard flash, without compromising device endurance, performance or reliability . this new architecture offers customers a highly reliable and low-cost, flash memory solution. the mirrorbit cell doubles the storage capability of the basic flash memory cell and therefore enables low-cost, high-density flash memory products. unlike competing multi-level cell (mlc) technology, the mirrorbit architecture delivers this enhanced storage without compromising device performance or reliability. this revolutionary architecture is the result of years of research and development on the design, processing, testing and characterization of multi-bit cells that have culminated in amds patented mirrorbit architecture. the mirrorbit architectures ability to store two bits of data in one cell, without compromising data integrity, is achieved by storing each of the two units of charge individually, and in a different location, within a single memory cell. since each bit in the mirrorbit memory cell is in a physically different location, the bits are independent and this allows amd to offer the same performance and reliability as standard single-bit flash memory products. customers can benefit from this revolutionary architecture in several ways: ?l o w-cost flash memory devices ? high-density flash memory devices ?h igh levels of reliability ?p erformance comparable to todays standard nor flash memory ? amds award winning service and support publication # 25260 rev: c amendment/0 issue date: september 18, 2002
amd mirrorbit ? 2 distinctive features ?t wo bits of data stored in one memory cell. C this reduces costs and enables low-cost, high-density flash memory. ? simple and symmetric cell architecture. C this makes the device easy to manufacture. ?t wo distinct charge storage areas with- in one cell. C this increases reliability and data integrity. ? each unit of charge individually programmed and erased. C allows high performance and high r eliability. ? full charge stored at each end of the cell. C enables higher levels of reliability and performance. ?p r oducts designed to be completely pin-compatible with amds current 64mb lv flash. C provides a seamless migration path from amd's single bit flash devices. benefits the amd mirrorbit architecture breaks the traditional trade-off between cost and performance. for the first time in history, flash memory designers and users can expect high levels of performance and reliability as w ell as the industrys leading cost structure. customers therefore are no longer forced to sacrifice reliability or performance for the sake of cost. amds mirrorbit based products have the same performance, endurance and reliability as amds standard 3 volt products. products based on this new architecture are completely pin-compatible with amds standard 3 volt (lv product family) and offer a simple migration path for customers from the current lv family of products to higher densities such as 256 mb and eventually 1gb. since these products are offered in the same packages and with the same pinouts as amds current lv family of products, amds customers can easily migrate their existing designs to mirrorbit based flash. most importantly, mirrorbit flash devices are a vailable today ,s o designers can immediately enjoy mirrorbit technology's many benefits. in addition to offering low cost and high r eliability, products based on the mirrorbit architecture also offer two new performance- enhancing features, a read and write page buffer that increases data throughput. as device densities increase data input and output become a major bottleneck and this limits how fast data gets in and out of the device. since the mirrorbit architecture is well suited f or ultra-high density flash memory devices, products based on mirrorbit architecture offer these page buffers to further improve functionality and device performance. mirrorbit cell diagram
amd mirrorbit ? 3 av ailability and roadmap the mirrorbit architecture has been developed and tested by amd on a number of different products and densities. the architecture and process technology have met our internal qualification g oals. we are currently in the midst of rolling out an entire family of products based on this architecture. the first 64 mb, mirrorbit product was introduced in early 2002 and a 256 mb mirrorbit product is slated for introduction in q3, 2002. the mirrorbit architecture based product family includes flash devices from 16 to 256 megabits and beyond, and is available in a variety of packages such as tsop, fbga, and amd's new fortified bga package. mirrorbit technology the mirrorbit architecture doubles device density while simultaneously overcoming the fundamental limitations of competing mlc technologies - namely low levels of reliability and performance. a breakthrough design and a relentless commitment to quality and performance solve the classical paradox. the breakthrough itself is achieved by storing electrons in two physically distinct and independent locations within a single memory cell. the mirrorbit architecture uses a radical new design and process technology to double the density without any performance penalty. in the mirrorbit cell, the basic transistor itself is very different from conventional transistors. instead of the classical asymmetric transistor with a distinctly doped source and drain, the mirrorbit cell uses a symmetric transistor with similar source and drain. the charge storage element has been modified to allow electrons to be stored on either side of the cell. once electrons are placed into one side of the storage element, say on the left side of the cell, they remain trapped on that side. consequently, read, program and erase operations are performed at full speed and power regardless of whether one is using the left bit or right bit. as a result, the basic memory cell behaves as though it were two independent conventional memory cells. this architecture therefore offers twice the density of standard flash without sacrificing performance or reliability. the mirrorbit architecture therefore allows amd to offer the same performance and reliability as standard single-bit flash memory products. amds customers therefore have access to low-cost, high-density flash memory solutions without compromising either performance or reliability.
amd mirrorbit ? 4 mirrorbit ?2 bits per cell ?l o w-cost structure ? each bit is independent ? fast programming ? fast read ? easily scalable competing mlc ?2 levels per cell ?l o w-cost structure ?two bi ts are interdependent ?s low programming ?slow r ead ? difficult to scale conventional flash ?1 level per cell ? consumes more silicon ? fast programming ? fast read ? scales with lithography amd mirrorbit? cell competing multi level (mlc) flash memory cell basic flash memory cell
amd mirrorbit ? 5 device technology overview in order to fully understand how the mirrorbit architecture works, one needs to understand how basic flash memory cells work. the following section gives a detailed overview of how flash memory cells, multi-level cell technologies and the mirrorbit architecture works. conventional flash memory cells are based on mos (metal oxide semiconductor) transistors, which are probably the most important component of semiconductor devices. this transistor typically consists of a thin, high-quality gate oxide sandwiched between a conducting polysilicon gate and a crystalline silicon semiconductor substrate. the substrate under the gate is lightly doped and is a p-type (electron-deficient) substrate. the source and drain areas are more heavily doped and are n-type (electron-rich). the floating gate memory cell is very similar to the basic mos transistor. the difference is in the presence of an additional polysilicon gate. this so-called "floating gate" lies between the control gate and the silicon substrate. insulating materials such as silicon dioxide surround the floating gate. flash memory devices store data by holding charge within the floating gate. the basic transistor works as f ollows. in a neutral state, there is no conductive path between the source and drain r egions. when a positive v oltage is applied to both the gate and drain, a channel begins to form between the source and drain. when the gate voltage is sufficiently large the channel is completely formed and electrons flow from the source to the drain. read operation
amd mirrorbit ? 6 the voltage at which the channel forms is called the threshold voltage of the transistor, and is often re fe rr ed to as vt. increasing the control gate voltage beyond the threshold voltage results in an increase in the current flowing between the source and drain. the key to flash memory cell operation is that when charge is stored in the floating gate, the threshold voltage of the transistor increases. this change in threshold v oltage enables one to detect whether or not a cell is programmed. single-bit cells basically have two threshold states, a programmed state (threshold voltage v tp ) and an erased state (threshold voltage v te ). the read v oltage is selected to be between the programmed and erased threshold v oltages. if current flows at the read v oltage, then the cell is read as erased. competing multi-level cell technologies one common way of increasing the density of memory cells is to use competing multi-level cell (mlc) technology. competing multi-level cells basically store fractional levels of charge within a cell to offer increased data storage capability. since the threshold voltage of a transistor depends on the number of electrons in the floating gate, it is possible to store different units of data based on differences in the number of electrons stored in the cell. as a result, multi level cells store more than the basic 0 and 1, and instead they store 00, 01, 10 and 11. to store n bits per cell, the device needs to have 2 n different states. each of these states requires a different number of electrons to be stored in the floating gate, and consequently each state has its own threshold voltage. threshold voltage
amd mirrorbit ? 7 competing mlc performance: the read operation for competing multi level cell technologies is intrinsically slow since the cell needs to distinguish between these multiple possible threshold voltages. in order to program a competing multi level cell, electrons must be very precisely metered into the floating gate. if too many or too few electrons are allowed into the floating gate, the data stored in the memory cell is corrupted. consequently, the program operation is performed very carefully and is inherently slow. competing mlc reliability: the reliability of competing mlc technology is even more problematic than the reduced program, erase and read performance. since competing mlc technology depends on differences between small numbers of electrons in the floating gate, a loss of few electrons can cause data corruption and device failure. competing mlc devices use higher operating voltages to ensure that the basic cell has a sufficiently wide vt window. however, the associated electric fields cause oxide breakdown and other stresses and consequently limit the endurance of the device. mirrorbit cell technology the mirrorbit architecture doubles device density while simultaneously overcoming the fundamental limitations of competing mlc technologies - namely low levels of reliability and performance. this breakthrough is the result of fundamental changes in device architecture and process technology. these two advances allow the mirrorbit memory cell to store electrons in two distinct and independent locations within a single cell and thereby double device density without compromising performance or reliability. in the mirrorbit cell the basic unit of charge storage - the memory cell transistor, is different from the conventional floating gate memory transistor. unlike other flash memory cells, which use an asymmetric transistor with a distinctly doped source and drain, the mirrorbit cell uses a symmetric transistor with similar source and drain. the floating gate or charge storage element has been fundamentally changed to allow electrons to be stored on either side of the cell. once electrons are placed into one side of the storage element, say on the left side of the cell, they remain trapped on that side. consequently, read, program and erase operations are performed at full speed and power r egardless of whether one is using the left bit or right bit. each bit within the mirrorbit cell has full operating margin and as a result, the basic memory cell behaves as though it were two independent conventional memory cells. this architecture therefore offers twice the density of standard flash without sacrificing performance or reliability. mirrorbit performance and reliability the mirrorbit architecture enables one memory cell to hold two virtual transistors. each of these transistors can be read or programmed independent of the other, and at full power. the threshold vo ltage margins of the device are also large, and about the same as that of single bit flash. the performance and the reliability of the device is therefore comparable to the performance and r eliability of today's conventional single bit nor flash memory. as a result, users can continue to expect the high levels of performance and reliability that they are currently used to.
amd mirrorbit ? 8 conclusion amd's mirrorbit cell doubles the storage capability of the basic flash memory cell and therefore enables low-cost, high-density flash memory products. the mirrorbit architecture delivers this enhanced storage without any compromises. a breakthrough design and a radical new process technology, coupled with a relentless commitment to quality and performance have enabled amd to create the mirrorbit architecture, which is the result of years of research and development on the design, processing, testing and characterization of multi-bit cells. the breakthrough itself is achieved by storing electrons in two physically distinct and independent locations within a single memory cell. the mirrorbit architecture enables one memory cell to hold two virtual transistors. each of these transistors can be read or programmed independent of the other, and at full power. as a result, the mirrorbit architecture delivers the same performance and r eliability as conventional flash memory, but at half the cost. amds mirrorbit products based on this new architecture are completely pin-compatible with amds standard 3 volt (lv product family). these products are offered in the same packages and with the same pinouts as amds current lv family of products, and provide an easy migration path to high-density devices such as 256 mb and eventually 1gb. most importantly, mirrorbit flash devices are a vailable today , so designers can immediately enjoy mirrorbit technology's many benefits.
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