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? semiconductor components industries, llc, 2003 october, 2003 ? rev. 0 1 publication order number: ncp1378/d ncp1378 pwm current-mode controller for free-running quasi-resonant operation the ncp1378 combines a true current mode modulator and a demagnetization detector to ensure full borderline/critical conduction mode in any load/line conditions and minimum drain voltage switching (quasi?resonant operation). due to its inherent skip cycle capability, the controller enters burst mode as soon as the power demand falls below a predetermined level. as this happens at low peak current, no audible noise can be heard. an internal 8.0 s timer prevents the free?run frequency to exceed 100 khz (therefore below the 150 khz cispr?22 emi starting limit), while the skip adjustment capability lets the user select the frequency at which the burst foldback takes place. the transformer core reset detection is done through an auxiliary winding which, brought via a dedicated pin, also enables fast over voltage protection (ovp). once an ovp has been detected, the ic permanently latches?off. the ncp1378 also features an efficient protective circuitry that, in presence of an overcurrent condition, disables the output pulses and enters a safe burst mode, trying to restart. once the default has gone, the device auto?recovers. finally an internal 1.0 ms soft?start eliminates the traditional startup stress. the ncp1378 is tailored for low voltage applications having uvlo thresholds of 8.4 v (on) and 7.5 v (off). features ? free?running borderline/critical mode quasi?resonant operation ? latched over voltage protection ? auto?recovery short?circuit protection via uvlo crossover ? current?mode with adjustable skip?cycle capability ? internal 1.0 ms soft?start ? internal temperature shutdown ? internal leading edge blanking ? 500 ma peak current source/sink capability ? external latch triggering, e.g. via overtemperature signal ? direct optocoupler connection ? spice models available for transient analysis ? internal 8.0 s minimum t off typical applications ? battery?based operations so?8 d suffix case 751 pin connections device package shipping ordering information NCP1378Dr2 so?8 2500 tape & reel http://onsemi.com marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 8 1 8 pdip?7 p suffix case 626b 1 dmg 8 hv 2 fb 3 cs 4 gnd 6 v cc 5 drv (top view) ncp1378p pdip?7 50 units/tube 1378 alyw 1 8 1378p awl yyww 1
ncp1378 http://onsemi.com 2 figure 1. typical application schematic 1 8 2 3 4 6 5 7 ncp1378 ovp and demag + universal network r* + 12 v @ 1 a ground + y1 type *please refer to the application information section. pin function description pin symbol function description 1 demag core reset detection and ovp the auxiliary flyback signal ensures discontinuous operation and offers a fixed over voltage detection level of 5.2 v. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. by bringing this pin below the internal skip level, you shut off the device. 3 cs current sense input and skip cycle level selection this pin senses the primary current and routes it to the internal comparator via an l.e.b. by inserting a resistor in series with the pin, you control the level at which the skip operation takes place. 4 gnd the ic ground ? 5 drv driving pulses the driver's output to an external mosfet. 6 v cc supplies the ic this pin is connected to an external bulk capacitor of typically 47 f. 7 nc ? this unconnected pin ensures adequate creepage distance. 8 hv high?voltage pin connected to the high?voltage rail, this pin injects a constant current into the v cc bulk capacitor and ensures a clean lossless startup sequence.
ncp1378 http://onsemi.com 3 figure 2. internal circuit architecture hv v cc gnd demag 4 ma to internal supply + + 8.4 v 7.5 v 5.6 v (fault) fault mngt. pon 5.2 v + + 4.5 s delay demag 8 s blanking s s * r * r q q + + - overload? 5 s timeout timeout reset demag 340 ns leb 1 v /3 200 a when drv is off fb 4.2 v driver src = 20 sink = 10 drv v cc cs + 50 mv 10 v ovp soft?start = 1 ms resd *s and r are level triggered whereas s is edge triggered. r has priority over the other inputs.
ncp1378 http://onsemi.com 4 maximum ratings rating symbol value unit power supply voltage v cc , drv 16 v maximum voltage on all other pins except pin 8 (hv), pin 6 (v cc ) and pin 5 (drv) ? ?0.3 to 10 v maximum current into all pins except v cc (6), hv (8) and demag (1) when 10 v esd diodes are activated ? 5.0 ma maximum current in pin 1 idem +3.0/?2.0 ma thermal resistance junction?to?case r jc 57 c/w thermal resistance junction?to?air, soic v ersion r ja 178 c/w thermal resistance junction?to?air, dip8 v ersion r ja 100 c/w maximum junction t emperature tj max 150 c temperature shutdown ? 155 c hysteresis in shutdown ? 30 c storage temperature range ? ?60 to +150 c esd capability, hbm model (all pins except v cc and hv) ? 2.0 kv esd capability, machine model ? 200 v maximum voltage on pin 8 (hv), pin 6 (v cc ) decoupled to ground with 10 f v hv 500 v electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic pin symbol min typ max unit supply section v cc increasing level at which the current source turns?off 6 vcc on 7.8 8.4 9.0 v v cc decreasing level at which the current source turns?on 6 vcc min 7.0 7.5 8.2 v v cc excursion between vcc on and vcc min 6 vcc hyst 0.8 ? ? ? v cc decreasing level at which the latch?off phase ends 6 vcc latch ? 5.5 ? v internal ic consumption, no output load on pin 5, f sw = 60 khz 6 icc1 ? 1.0 1.3 (note 1) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 60 khz 6 icc2 ? 1.6 2.0 (note 1) ma internal ic consumption, latch?off phase, v cc = 6.0 v 6 icc3 ? 220 ? a internal start?up current source (t j 0 c) high?voltage current source, v cc = 7.8 v 8 ic1 2.4 4.0 6.0 ma high?voltage current source, v cc = 0 8 ic2 ? 4.5 ? ma drive output output voltage rise?time @ cl = 1.0 nf, 10?90% of output signal 5 t r ? 40 ? ns output voltage fall?time @ cl = 1.0 nf, 10?90% of output signal 5 t f ? 20 ? ns source resistance 5 r oh 10 20 36 sink resistance 5 r ol 4.0 10 20 current comparator (pin 5 not loaded) input bias current @ 1.0 v input level on pin 3 3 i ib ? 0.02 ? a maximum internal current setpoint 3 i limit 0.9 1.0 1.1 v propagation delay from current detection to gate off state 3 t del ? 110 160 ns leading edge blanking duration 3 t leb ? 340 ? ns internal current offset injected on the cs pin during off time 3 iskip ? 200 ? a 1. max value at t j = 0 c, please see characterization curves.
ncp1378 http://onsemi.com 5 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic pin symbol min typ max unit overvoltage section (v cc = 11 v) sampling delay after on time 1 t sample ? 4.5 ? s ovp internal reference level 1 v ref 4.6 5.2 6.3 v feedback section (v cc = 11 v, pin 5 loaded by 1.0 k ) internal pull?up resistor 2 rup ? 20 ? k pin 3 to current setpoint division ratio ? iratio ? 3.3 ? ? internal soft?start ? ts s ? 1.0 ? ms demagnetization detection block input threshold voltage (vpin 1 decreasing) 1 v th 30 50 90 mv hysteresis (vpin 1 decreasing) 1 v h ? 20 ? mv input clamp v oltage high state (ipin 1 = 3.0 ma) low state (ipin 1 = ?2.0 ma) 1 1 vc h vc l 8.0 ?0.9 10 ?0.7 12 ?0.5 v demag propagation delay 1 t dem ? 240 ? ns internal input capacitance at vpin 1 = 1.0 v 1 c par ? 10 ? pf internal blanking delay after t on 1 t blank ? 8.0 ? s
ncp1378 http://onsemi.com 6 typical characteristics ?25 0 25 50 75 100 125 temperature ( c) i limit , (v) ?25 0 25 50 75 100 125 temperature ( c) i c1 , ( ma ) ?25 0 25 50 75 100 125 temperature ( c) i cc2 , (ma) ?25 0 25 50 75 100 12 5 temperature ( c) v ccmin , (v) 7.8 8.0 8.2 8.4 8.6 8.8 ?25 0 25 50 75 100 125 temperature ( c) 7.0 7.2 7.4 7.6 7.8 8.0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 1 2 3 4 5 6 7 8 0.90 0.95 1.00 1.05 1.10 figure 3. v ccon threshold versus temperature figure 4. v ccmin threshold versus temperature figure 5. current consumption (no load) versus temperature figure 6. current consumption (1.0 nf load) versus temperature figure 7. hv current source at v cc = 10 v versus temperature figure 8. maximum current setpoint versus temperature v ccon , ( v ) ?25 0 25 50 75 100 125 temperature ( c) i cc1 , ( ma )
ncp1378 http://onsemi.com 7 typical characteristics ?25 0 25 50 75 100 125 temperature ( c) t out , ( s) 0 2 4 6 8 10 12 14 16 18 20 0 5 10 15 20 25 30 35 40 0 20 40 60 80 100 120 3.0 3.5 4.0 4.5 5.0 5.5 6.0 7.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 figure 9. drive source resistance versus temperature figure 10. drive sink resistance versus temperature figure 11. demagnetization detection threshold versus temperature figure 12. ovp threshold versus temperature figure 13. minimum t off versus temperature figure 14. demagnetization detection timeout versus temperature ?25 0 25 50 75 100 125 temperature ( c) r oh , ( ) ?25 0 25 50 75 100 125 temperature ( c) r ol , ( ) ?25 0 25 50 75 100 125 temperature ( c) v th , (mv) ?25 0 25 50 75 100 125 temperature ( c) v ref , (v) ?25 0 25 50 75 100 125 temperature ( c) t off , ( s) 6.5
ncp1378 http://onsemi.com 8 application information introduction the ncp1378 implements a standard current mode architecture where the switch?off time is dictated by the peak current setpoint, whereas the core reset detection triggers the turn?on event . this component represents the ideal candidate where low part?count is the key parameter in applications supplied by a battery. due to its high? performance high?voltage technology, the ncp1378 incorporates all the necessary components/features needed to build a rugged and reliable switch?mode power supply (smps): ? transformer core reset detection: borderline/critical operation is ensured whatever the operating conditions are. as a result, there are virtually no primary switch turn?on losses and no secondary diode recovery losses. the converter also stays a first?order system and accordingly eases the feedback loop design. ? quasi?resonant operation: by delaying the turn?on event, it is possible to restart the mosfet in the minimum of the drain?source wave, ensuring reduced emi/video noise perturbations. in nominal power conditions, the ncp1378 operates in borderline conduction mode (bcm) also called critical conduction mode. ? under voltage lockout (uvlo): when v cc falls below uvlo, all pulses are stopped and the ic consumption drops down to a few hundreds of a (icc3 data). when v cc reaches the latch?off level (5.5 v typical), the startup current source is activated and brings v cc back to vcc on where the ic attempts to startup. ? over voltage protection (ovp): by sampling the plateau voltage on the demagnetization winding, the ncp1378 goes into latched fault condition whenever an over?voltage condition is detected. the controller stays fully latched in this position until the v cc is cycled down to 4.0 v, e.g. when the user unplugs the power supply from the mains outlet and replugs it. ? external latchtrip point: by externally forcing a level on the ovp greater than the internal setpoint, it is possible to latch?off the ic, e.g. with a signal coming from a temperature sensor. ? adjustable skip cycle level: by offering the ability to tailor the level at which the skip cycle takes place, the designer can make sure that the skip operation only occurs at low peak current. this point guarantees a noise?free operation with cheap transformer. this option also offers the ability to fix the maximum switching frequency when entering light load conditions. ? over current protection (ocp): ncp1378 enters burst mode as soon as the power supply undergoes an overload, which is detected through the sense of the auxiliary voltage. as detailed above, as soon as v cc crosses the uvlo level (called vcc min in the electrical table), all pulses are stopped and the device enters a safe low power operation that prevents from any lethal thermal runaway. by monitoring the v cc level, the startup current source is activated on and off to create a kind of burst mode where the smps tries to re?start. if the fault has gone, the smps resumes operation. on the other hand, if the fault is still there, the burst sequence starts again. start?up sequence when the power supply is first powered from the mains outlet, the internal current source (typically 4.0 ma) is biased and charges up the v cc capacitor. when the voltage on this v cc capacitor reaches the vcc on level (typically 8.4 v), the current source turns off and no longer wastes any power. at this time, the v cc capacitor only supplies the controller and the auxiliary supply is supposed to take over before v cc collapses below v ccmin . figure 15 shows the internal arrangement of this structure. ? + vcc on /vcc min 8 hv ic1 or 0 6 4 svcc aux figure 15. the current source brings vcc above vcc on and then turns off
ncp1378 http://onsemi.com 9 once the power supply has started, the vcc shall be constrained below 16 v, which is the maximum rating on pin 6. figure 16 portrays a typical ncp1378 startup sequence with a vcc regulated at 8.0 v. figure 16. a typical startup sequence for the ncp1378 5.0 6.0 7.0 8.0 9.0 8.4 v regulation v cc 3.00m 8.00m 13.0m 18.0m 23.0m time in secs skipping cycle mode the ncp1378 automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 2 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a determined level, the ic prevents the current from decreasing further down and starts to blank the output pulses: the ic enters the so?called skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches (figure 17) and follows the following formula: 1 2 lpip 2 fswd burst with: lp = primary inductance fsw = switching frequency within the burst ip = peak current at which skip cycle occurs d burst = burst width/burst recurrence figure 17. the skip cycle takes place at low peak currents which guarantees noise?free operation 0 300 200 100 max peak current width recurrence skip cycle current limit current sense signal (mv) + - reset r sense r skip + driver = high ? i = 0 driver = low ? i = 200 a 2 3 figure 18. a patented method allows for skip level selection via a series resistor inserted in series with the current normal current mode operation the skip level selection is done through a simple resistor inserted between the current sense input and the sense element. every time the ncp1378 output driver goes low, a 200 a source forces a current to flow through the sense pin (figure 18): when the driver is high, the current source is off and the current sense information is normally processed. as soon as the driver goes low, the current source delivers 200 a and develops a ground?referenced voltage across rskip. if this voltage is below the feedback voltage, the current sense comparator stays in the low state and the internal latch can be triggered by the next clock cycle. now, if because of a low load mode the feedback voltage is below rskip level, then the current sense comparator permanently resets the latch and the next clock cycle (given by the demagnetization detection) is ignored: we are skipping cycles as shown by figure 17. as soon as the feedback voltage goes up again, there can be two situations: the recurrent period is small and a new demagnetization detection (next wave) signal triggers the ncp1378. to the opposite, in low output power conditions, no more ringing waves are present on the drain and the toggling of the current sense comparator alone initiates a new cycle start. figure 19 depicts these two different situations.
ncp1378 http://onsemi.com 10 figure 19. when the primary natural ringing becomes too low, the current sense initiates a new cycle when fb passes the skip level. demag re?start current sense and timeout re?start 5 s 5 s drain signal timeout signal drain signal timeout signal demagnetization detection the core reset detection is done by monitoring the voltage activity on the auxiliary winding. this voltage features a flyback polarity. the typical detection level is fixed at 50 mv as exemplified by figure 20. figure 20. core reset detection is done through a dedicated auxiliary winding monitoring figure 21. internal pad implementation possible re?starts 50 mv 7.0 5.0 3.0 1.0 ?1.0 0 v demag signal (v) to internal comparator au x r esd 2 k r dem esd esd 5 3 4 1 42 1 an internal timer prevents any restart within 8.0 s further to the driver going?low transition. this prevents the switching frequency to exceed (1.0/t on + 8.0 s) but also avoid false leakage inductance tripping at turn?off. in some cases, the leakage inductance kick is so energetic, that a slight filtering is necessary.
ncp1378 http://onsemi.com 11 the ncp1378 demagnetization detection pad features a specific component arrangement as detailed by figure 21. in this picture, the zener diodes network protect the ic against any potential esd discharge that could appear on the pins. the first esd diode connected to the pad, exhibits a parasitic capacitance. when this parasitic capacitance (10 pf typically) is combined with rdem, a restart delay is created and the possibility to switch right in the drain?source wave exists. this guarantees qr operation with all the associated benefits (low emi, no turn?on losses etc.). rdem should be calculated to limit the maximum current flowing through pin 1 to less than +3.0 ma/?2.0 ma: if during turn?on, the auxiliary winding delivers 30 v (at the highest line level), then the minimum rdem value is defined by: 30 + 0.7/3.0 ma = 10.2 k . this value will be further increased e.g. to introduce a restart delay and also a slight filtering in case of high leakage energy. figure 22 portrays a typical v ds shot at nominal output power. figure 22. the ncp1378 operates in borderline/critical operation 400 300 200 100 0 drain voltage (v) over voltage protection the over voltage protection works by sampling the plateau voltage 4.5 s after the turn?off sequence. this delay guarantees a clean plateau, providing that the leakage inductance ringing has been fully damped. if this would not be the case, the designer should install a small rc damper across the transformer primary inductance connections. figure 23 shows where the sampling occurs on the auxiliary winding. figure 23. a voltage sample is taken 4.5 s after the turn?off sequence 8.0 6.0 4.0 2.0 0 sampling here demag signal (v) 4.5 s when an ovp condition has been detected, the ncp1378 enters a latch?off phase and stops all switching operations. the controller stays fully latched in this position and the startup source being still active, it keeps the v cc going up and down between 8.4 v and 5.5 v. this state lasts until the v cc is cycled down to 4.0 v, e.g. when the user unplugs the power supply from the mains outlet. by default, the ovp comparator is biased to a 5.2 v reference level and pin1 is directly routed to the comparator. as a result, when vpin1 reaches 5.2 v, the ovp comparator is triggered. the threshold can thus be adjusted by either modifying the power winding to auxiliary winding turn ratios to match this 5.2 v level or insert a resistor from pin1 to ground to cope with your design requirement. latching off the ncp1378 in certain cases, it can be very convenient to externally shut down permanently the ncp1378 via a dedicated signal, e.g. coming from a temperature sensor (figure 24). the reset occurs when the user unplugs the power supply from the mains outlet. to trigger the latch?off by an external signal, a simple pnp transistor can do the work, as figure 25 shows.
ncp1378 http://onsemi.com 12 figure 24. a simple ctn triggers the latch?off as s oon as the temperature exceeds a given setpoint. 1 8 2 3 4 6 5 7 aux. 1 8 2 3 4 6 5 7 ncp1378 on /off vcccap aux. figure 25. a simple transistor arrangement allows to trigger the latch?off by an external signal. ctn ncp1378 shutting off the ncp1378 shutdown can easily be implemented through a simple npn bipolar transistor as depicted by figure 6. when off, q1 is transparent to the operation. when forward biased, the transistor pulls the fb pin to ground (vcesat 200 mv) and permanently disables the ic. a small time constant on the transistor base will avoid false triggering (figure 26). 1 8 2 3 4 6 5 7 ncp1378 on /off figure 26. a simple bipolar transistor totally disables the ic q1 10 nf 10 k 32 1 overload operation in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is interesting to implement a true short?circuit protection. a short?circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the auxiliary voltage also decreases because it also operates in flyback and thus duplicates the output voltage, providing the leakage inductance between windings is kept low. to account for this situation and properly protect the power supply, ncp1378 hosts a dedicated overload detection circuitry. once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty?cycle. the system auto?recovers when the fault condition disappears. during the start?up phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. the auxiliary voltage takes place after a few switching cycles and self?supplies the ic. in presence of a short circuit on the output, the auxiliary voltage will go down until it crosses the undervoltage lockout level of typically 7.5 v. when this happens, ncp1378 immediately stops the switching pulses and unbiases all unnecessary logical blocks. the overall consumption drops, while keeping the gate grounded, and the v cc slowly falls down. as soon as v cc reaches typically 5.5 v, the startup source turns?on again and a new startup sequence occurs, bringing v cc toward 8.4 v as an attempt to restart. if the default has gone, then the power supply normally restarts. if not, a new protective burst is initiated, shielding the smps from any runaway. figure 27 portrays the typical operating signals in short circuit.
ncp1378 http://onsemi.com 13 driving pulses vcc on vcc min vcc latch vcc figure 27. typical waveforms in short circuit conditions soft?start the ncp1378 features an internal 1.0 ms soft?start to soften the constraints occurring in the power supply during start?up. it is activated during the power on sequence. as soon as v cc reaches vcc on , the peak current is gradually increased from nearly zero up to the maximum clamping level (e.g. 1.0 v). the soft?start is also activated during the over current burst (ocp) sequence. every restart attempt is followed by a soft?start activation. generally speaking, the soft?start will be activated when v cc ramps up either from zero (fresh poweron sequence) or 5.5 v, the latchoff voltage occurring during ocp. calculating the vcc capacitor the v cc capacitor can be calculated knowing the ic consumption as soon as v cc reaches vcc on . suppose that a ncp1378 is used and drives a mosfet with a 30 nc total gate charge (qg). the total average current is thus made of icc1 (1.0 ma) plus the driver current, fsw x qg or 1.8 ma. the total current is therefore 2.8 ma. the v available to fully startup the circuit (e.g. never reach the 7.5 v uvlo during power on) is 8.47.5 = 0.9 v. we have a capacitor that then needs to supply the ncp1378 with 2.8 ma during a given time until the auxiliary supply takes over. suppose that this time was measured at around 10 ms. cv cc is calculated using the equation c ti v or c 31.1 f. select a 47 f/25 v and this will fit. during the latch?off phase, the current consumption drops to 220 a. we can now calculate how long this latch?off phase will last: (7.55.5) x 47 /220 u = 427 ms. protecting pin 8 against negative spikes as any cmos controller, ncp1378 is sensitive to negative voltages that could appear on its pins. to avoid any adverse latch?up of the ic, we strongly recommend to insert a resistor in series with pin8. this resistor prevents from adversely latching the controller in case of negative spikes appearing on the bulk capacitor during the power?off sequence. a typical value of 6.8 k /0.5 w is suitable. this resistor does not dissipate any power since it only sees current during the startup sequence and during overload. operating shots below are some oscilloscope shots captured at vin = 120 vdc with a transformer featuring a 800 h primary inductance.
ncp1378 http://onsemi.com 14 1 st upper plot: free run, valley switching operation, pout = 26 w. 2 nd middle plot: min toff clamps the switching frequency and selects the second valley. 3 rd lowest plot: the skip slices the second valley pattern and will further expand the burst as pout goes low. figure 28. this plot gathers waveforms captured at three different operating points: figure 29. this picture explains how the 200 a internal offset current creates the skip cycle level. vrsense (200 mv/div) vgate 200 a x rskip current sense pin (200 mv/pin)
ncp1378 http://onsemi.com 15 package dimensions so?8 d suffix case 751?07 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751-01 thru 751-06 are obsolete. new standard is 751-07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m
ncp1378 http://onsemi.com 16 package dimensions pdip?7 p suffix case 626b?01 issue a notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension l to center of lead when formed parallel. 4. package contour optional (round or square corners). 5. dimensions a and b are datums. 14 5 8 f note 2 ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max millimeters a 9.40 10.16 b 6.10 6.60 c 3.94 4.45 d 0.38 0.51 f 1.02 1.78 g 2.54 bsc h 0.76 1.27 j 0.20 0.30 k 2.92 3.43 l 7.62 bsc m ??? 10 n 0.76 1.01 a b on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp1378/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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