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1996 microchip technology inc. preliminary ds30559a-page 1 devices included in this data sheet: pic16c641 pic16c642 pic16c661 pic16c662 high performance risc cpu: only 35 instructions to learn all single-cycle instructions (200 ns), except for program branches which are two-cycle operating speed: - dc - 20 mhz clock input - dc - 200 ns instruction cycle interrupt capability 8-level deep hardware stack direct, indirect and relative addressing modes peripheral features: up to 33 i/o pins with individual direction control high current sink/source for direct led drive analog comparator module with: - two analog comparators - programmable on-chip voltage reference (v ref ) module - programmable input multiplexing from device inputs and internal voltage reference - comparator outputs can be output signals timer0: 8-bit timer/counter with 8-bit programmable prescaler special microcontroller features: power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) brown-out reset watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code protection power saving sleep mode selectable oscillator options serial in-circuit programming (via two pins) device program memory x14 data memory x8 pic16c641 2k 128 pic16c642 4k 176 pic16c661 2k 128 pic16c662 4k 176 pin diagrams pdip, soic, windowed cerdip rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rc7 rc6 rc5 rc4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c64x mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref ra3/an3 ra4/t0cki ra5 v ss osc1/clkin osc2/clkout rc0 rc1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rc2 rc3 pdip, windowed cerdip pic16c66x 10 11 2 3 4 5 6 1 8 7 9 12 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 37 38 39 23 24 25 26 27 28 22 21 40 mclr /v pp ra0/an0 ra1/an1 ra2/an2/v ref ra3/an3 ra4/t0cki ra5 re0/rd osc1/clkin osc2/clkout re1/wr re2/cs v dd v ss rd0/psp0 rd1/psp1 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd4/psp4 rc7 rc6 rc5 rc4 rd3/psp3 rd2/psp2 rd5/psp5 rc0 rc1 rc2 rc3 four user programmable id locations program memory parity error checking circuitry with parity error reset (per) cmos technology: low-power, high-speed cmos eprom technology fully static design wide operating voltage range: 3.0v to 6.0v commercial, industrial and automotive temperature ranges low power consumption - < 2.0 ma @ 5.0v, 4.0 mhz - 15 m a typical @ 3.0v, 32 khz - < 1.0 m a typical standby current @ 3.0v 8-bit eprom microcontrollers with analog comparators pic16c64x & pic16c66x this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 2 preliminary 1996 microchip technology inc. pin diagrams (cont.d) 10 11 12 13 14 15 16 17 18 19 20 21 2223 24 2526 44 8 7 654321 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 pic16c66x ra4/t0cki ra5 re0/rd osc1/clkin osc2/clkout rc0 nc re1/wr re2/cs v dd v ss rb3 rb2 rb1 rb0/int v dd v ss rd7/psp7 rd6/psp6 rd5/psp5 rd4/psp4 rc7 ra3/an3 ra2/an2/v ref ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc nc rc6 rc5 rc4 rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3 rc2 rc1 10 11 2 3 4 5 6 1 1819 20 21 22 12 1314 15 38 8 7 44 43 42 41 40 39 16 17 29 30 31 32 33 23 24 25 26 27 28 36 34 35 9 pic16c66x 37 ra3/an3 ra2/an2/v ref ra1/an1 ra0/an0 mclr /v pp nc rb7 rb6 rb5 rb4 nc rc6 rc5 rc4 rd3/psp3 rd2/psp2 rd1/psp1 rd0/psp0 rc3 rc2 rc1 nc nc rc0 osc2/clkout osc1/clkin v ss v dd re2/cs re1/wr re0/rd ra5 ra4/t0cki rc7 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 v ss v dd rb0/int rb1 rb2 rb3 tqfp plcc
1996 microchip technology inc. preliminary ds30559a-page 3 pic16c64x & pic16c66x table of contents 1.0 general description .......................................................................................................................................... 5 2.0 pic16c64x & pic16c66x device varieties .................................................................................................... 7 3.0 architectural overview...................................................................................................................................... 9 4.0 memory organization ..................................................................................................................................... 17 5.0 i/o ports.......................................................................................................................................................... 29 6.0 timer0 module................................................................................................................................................ 41 7.0 comparator module ........................................................................................................................................ 47 8.0 voltage reference module ............................................................................................................................. 53 9.0 special features of the cpu .......................................................................................................................... 55 10.0 instruction set summary ................................................................................................................................ 73 11.0 development support ..................................................................................................................................... 87 12.0 electrical specifications .................................................................................................................................. 91 13.0 device characterization information............................................................................................................. 103 14.0 packaging information .................................................................................................................................. 105 appendix a: enhancements...................................................................................................................................... 115 appendix b: compatibility ......................................................................................................................................... 115 appendix c: what? new .......................................................................................................................................... 116 appendix d: what? changed ................................................................................................................................... 116 appendix e: pic16/17 microcontrollers ..................................................................................................................... 117 pin compatibility ......................................................................................................................................................... 125 index ........................................................................................................................................................................... 127 list of examples.......................................................................................................................................................... 129 list of figures.............................................................................................................................................................. 129 list of tables............................................................................................................................................................... 130 on-line support.......................................................................................................................................................... 131 reader response ....................................................................................................................................................... 132 pic16c64x & pic16c66x product identification system .......................................................................................... 135 to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an exceptional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document.
pic16c64x & pic16c66x ds30559a-page 4 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 5 pic16c64x & pic16c66x 1.0 general description pic16c64x & pic16c66x devices are 28-pin and 40-pin eprom-based members of the versatile pic16cxxx family of low-cost, high-performance, cmos, fully-static, 8-bit microcontrollers. all pic16/17 microcontrollers employ an advanced risc architecture. the pic16cxxx family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. the separate instruction and data buses of the harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. the two-stage instruction pipeline allows all instructions to execute in a sin- gle-cycle, except for program branches (which require two cycles). a total of 35 instructions (reduced instruc- tion set) are available. additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. pic16cxxx microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in its class. the pic16c641 has 128 bytes of ram and the pic16c642 has 176 bytes of ram. both devices have 22 i/o pins, and an 8-bit timer/counter with an 8-bit pro- grammable prescaler. in addition, they have two analog comparators with a programmable on-chip voltage ref- erence module. program memory has internal parity error detection circuitry with a parity error reset. the comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.). the pic16c661 has 128 bytes of ram and the pic16c662 has 176 bytes of ram. both devices have 33 i/o pins, and an 8-bit timer/counter with an 8-bit pro- grammable prescaler. they also have an 8-bit parallel slave port. in addition, the devices have two analog comparators with a programmable on-chip voltage ref- erence module. program memory has internal parity error detection circuitry with a parity error reset. the comparator module is ideally suited for applications requiring a low-cost analog interface (e.g., battery chargers, threshold detectors, white goods controllers, etc.). pic16cxxx devices have special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. there are four oscillator options, of which the single pin rc oscillator provides a low-cost solution, the lp oscillator minimizes power consumption, xt is a standard crystal, and the hs is for high speed crystals. the sleep (power-down) mode offers power saving. the user can wake-up the chip from sleep through several external and internal interrupts and resets. a highly reliable watchdog timer (wdt) with its own on-chip rc oscillator provides protection against soft- ware lock-up. a uv-erasable cerdip-packaged version is ideal for code development while the cost-effective one-time programmable (otp) version is suitable for production in any volume. the pic16cxxx series ? perfectly in applications ranging from battery chargers to low-power remote sensors. the eprom technology makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. the small footprint packages make this microcontroller series perfect for all applications with space limitations. low-cost, low-power, high-performance, ease of use, and i/o ?xibility make the pic16c64x & pic16c66x very versatile. 1.1 f amil y and upwar d compatibility those users familiar with the pic16c5x family of microcontrollers will realize that this is an enhanced version of the pic16c5x architecture. please refer to appendix a for a detailed list of enhancements. code written for pic16c5x can be easily ported to the pic16c64x & pic16c66x (appendix b). 1.2 de velopment suppor t pic16c64x & pic16c66x devices are supported by the complete line of microchip development tools, including: mplab integrated development environment including mplab-simulator. mpasm universal assembler and mplab-c uni- versal c compiler. pro mate ii and picstart plus device pro- grammers. picmaster in-circuit emulator system fuzzy tech-mp fuzzy logic development tools driveway visual programming tool please refer to section 11.0 for more details about these and other microchip development tools. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 6 preliminary 1996 microchip technology inc. table 1-1: pic16c64x & pic16c66x device features pic16c641 20 2k 128 tmr0 2 yes - 4 22 3.0-6.0 yes 28-pin pdip, soic, windowed cdip pic16c642 20 4k 176 tmr0 2 yes - 4 22 3.0-6.0 yes 28-pin pdip, soic, windowed cdip pic16c661 20 2k 128 tmr0 2 yes yes 5 33 3.0-6.0 yes 40-pin pdip, windowed cdip; 44-pin plcc, tqfp pic16c662 20 4k 176 tmr0 2 yes yes 5 33 3.0-6.0 yes 40-pin pdip, windowed cdip; 44-pin plcc, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16cxxx family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) comparator(s) internal reference voltage interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features parallel slave port
1996 microchip technology inc. preliminary ds30559a-page 7 pic16c64x & pic16c66x 2.0 pic16c64x & pic16c66x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements the proper device option can be selected using the information in the product identi?ation sys- tem page at the end of this data sheet. when placing orders, please use that page of the data sheet to spec- ify the correct part number. 2.1 uv erasab le de vices the uv erasable version, offered in cerdip package is optimal for prototype development and pilot programs. this version can be erased and reprogrammed to any of the oscillator modes. microchip's picstart plus and pro mate ii programmers both support programming of the pic16c64x & pic16c66x. 2.2 one-time-pr ogrammab le (o tp) de vices the availability of otp devices is especially useful for customers who need ?xibility for frequent code updates and small volume applications. in addition to the program memory, the con?uration bits must also be programmed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code pat- terns have stabilized. the devices are identical to the otp devices but with all eprom locations and con?- uration options already programmed by the factory. certain code and prototype veri?ation procedures apply before production shipments are available. please contact your microchip technology sales of?e for more details. 2.4 serializ ed quic k-t urnar ound- pr oduction (sqtp sm ) de vices microchip offers a unique programming service where a few user-de?ed locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry-code, password or id number. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 8 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 9 pic16c64x & pic16c66x 3.0 architectural overview the high performance of the pic16c64x & pic16c66x devices can be attributed to a number of architectural features commonly found in risc micro- processors. to begin with, the pic16c64x & pic16c66x use a harvard architecture in which pro- gram and data are accessed from separate memories using separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched from the same memory. separat- ing program and data memory further allows instruc- tions to be sized differently than an 8-bit wide data word. instruction opcodes are 14-bits wide making it possible to have all single word instructions. a 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. a two-stage pipeline over- laps fetch and execution of instructions. consequently, all instructions (35) execute in a single cycle (200 ns @ 20 mhz) except for program branches, which require two cycles. the pic16c641 and pic16c661 both address 2k x 14 on-chip program memory while the pic16c642 and pic16c662 address 4k x 14. all program memory is internal. pic16c64x & pic16c66x devices can directly or indi- rectly address their register ?es or data memory. all special function registers including the program counter are mapped in the data memory. these devices have an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmet- rical nature and lack of ?pecial optimal situations make programming with the pic16c64x & pic16c66x simple yet ef?ient. in addition, the learning curve is reduced signi?antly. pic16c64x & pic16c66x devices contain an 8-bit alu and working register. the alu is a general pur- pose arithmetic unit. it performs arithmetic and bool- ean functions between data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, subtraction, shift, and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the working register (w register). the other operand is a ?e register or an immediate constant. in single operand instructions, the operand is either the w register or a ?e register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a bo rrow and di git bo rrow out bit, respectively, bit in subtraction. see the sublw and subwf instructions for examples. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 10 preliminary 1996 microchip technology inc. figure 3-1: pic16c641/642 block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram bank 9 addr mux indirect addr fsr reg status reg mux alu w reg power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout mclr v dd , v ss voltage brown-out reset 8 3 timer0 porta comparator ra3/an3 ra2/an2/v ref ra1/an1 ra0/an0 reference ra4/t0cki + - + - portb rb0/int select rb1 rb2 rb3 rb4 rb5 rb6 rb7 portc rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 ra5 parity error reset pic16c641 has 2k x 14 program memory and 128 x 8 ram pic16c642 has 4k x 14 program memory and 176 x 8 ram
1996 microchip technology inc. preliminary ds30559a-page 11 pic16c64x & pic16c66x figure 3-2: pic16c661/662 block diagram eprom program memory 13 data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) ram file registers direct addr 7 ram bank 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation osc1/clkin osc2/clkout voltage 8 3 timer0 porta comparator ra3/an3 ra2/an2/v ref ra1/an1 ra0/an0 reference ra4/t0cki + - + - portb rb0/int select rb1 rb2 rb3 rb4 rb5 rb6 rb7 portc rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 portd rd0/psp0 rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4 rd5/psp5 rd6/psp6 rd7/psp7 porte re0/rd re1/wr re2/cs parallel slave port ra5 power-up timer oscillator start-up timer power-on reset watchdog timer mclr v dd , v ss brown-out reset parity error reset pic16c661 has 2k x 14 program memory and 128 x 8 ram pic16c662 has 4k x 14 program memory and 176 x 8 ram
pic16c64x & pic16c66x ds30559a-page 12 preliminary 1996 microchip technology inc. table 3-1: pic16c641/642 pinout description name pin # i/o/p type buffer type description osc1/clkin 9 i st/cmos oscillator crystal input or external clock source input. osc2/clkout 10 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 i/o st analog comparator input. ra1/an1 3 i/o st analog comparator input. ra2/an2/v ref 4 i/o st analog comparator input or v ref output. ra3/an3 5 i/o st analog comparator input or comparator output. ra4/t0cki 6 i/o st can be selected to be the clock input to the timer0 timer/counter or a comparator output. output is open drain type. ra5 7 i/o st portb is a bi-directional i/o port. portb can be software pro- grammed for internal weak pull-ups on all inputs. rb0/int 21 i/o ttl/st (1) rb0 can also be selected as an external interrupt pin. rb1 22 i/o ttl rb2 23 i/o ttl rb3 24 i/o ttl rb4 25 i/o ttl interrupt on change pin. rb5 26 i/o ttl interrupt on change pin. rb6 27 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 28 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0 11 i/o st rc1 12 i/o st rc2 13 i/o st rc3 14 i/o st rc4 15 i/o st rc5 16 i/o st rc6 17 i/o st rc7 18 i/o st v ss 8,19 p ground reference for logic and i/o pins. v dd 20 p positive supply for logic and i/o pins. legend: o = output i/o = input/output p = power i = input ?= not used st = schmitt trigger input ttl = ttl input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode.
1996 microchip technology inc. preliminary ds30559a-page 13 pic16c64x & pic16c66x table 3-2: pic16c661/662 pinout description name dip pin # qfp pin # plcc pin # i/o/p type buffer type description osc1/clkin 13 30 14 i st/cmos oscillator crystal input or external clock source input. osc2/clkout 14 31 15 o oscillator crystal output. connects to crystal or reso- nator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. mclr /v pp 1 18 2 i/p st master clear (reset) input or programming voltage input. this pin is an active low reset to the device. porta is a bi-directional i/o port. ra0/an0 2 19 3 i/o st analog comparator input. ra1/an1 3 20 4 i/o st analog comparator input. ra2/an2/v ref 4 21 5 i/o st analog comparator input or v ref output. ra3/an3 5 22 6 i/o st analog comparator input or comparator output. ra4/t0cki 6 23 7 i/o st can be selected to be the clock input to the timer0 timer/counter or a comparator output. output is open drain type. ra5 7 24 8 i/o st portb is a bi-directional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int 33 8 36 i/o ttl/st (1) rb0 can also be selected as an external interrupt pin. rb1 34 9 37 i/o ttl rb2 35 10 38 i/o ttl rb3 36 11 39 i/o ttl rb4 37 14 41 i/o ttl interrupt on change pin. rb5 38 15 42 i/o ttl interrupt on change pin. rb6 39 16 43 i/o ttl/st (2) interrupt on change pin. serial programming clock. rb7 40 17 44 i/o ttl/st (2) interrupt on change pin. serial programming data. portc is a bi-directional i/o port. rc0 15 32 16 i/o st rc1 16 35 18 i/o st rc2 17 36 19 i/o st rc3 18 37 20 i/o st rc4 23 42 25 i/o st rc5 24 43 26 i/o st rc6 25 44 27 i/o st rc7 26 1 29 i/o st legend: o = output i/o = input/output p = power i = input ?= not used st = schmitt trigger input ttl = ttl input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured as a general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor port).
pic16c64x & pic16c66x ds30559a-page 14 preliminary 1996 microchip technology inc. portd can be a bi-directional i/o port or parallel slave port for interfacing to a microprocessor bus. rd0/psp0 19 38 21 i/o st/ttl (3) rd1/psp1 20 39 22 i/o st/ttl (3) rd2/psp2 21 40 23 i/o st/ttl (3) rd3/psp3 22 41 24 i/o st/ttl (3) rd4/psp4 27 2 30 i/o st/ttl (3) rd5/psp5 28 3 31 i/o st/ttl (3) rd6/psp6 29 4 32 i/o st/ttl (3) rd7/psp7 30 5 33 i/o st/ttl (3) porte is a bi-directional i/o port. re0/rd 8 25 9 i/o st/ttl (3) re0/rd read control for parallel slave port. re1/wr 9 26 10 i/o st/ttl (3) re1/wr write control for parallel slave port. re2/cs 10 27 11 i/o st/ttl (3) re2/cs select control for parallel slave port. v ss 12,31 6,29 13,34 p ground reference for logic and i/o pins. v dd 11,32 7,28 12,35 p positive supply for logic and i/o pins. nc 12,13, 33,34 1,17 28,40 not connected. name dip pin # qfp pin # plcc pin # i/o/p type buffer type description legend: o = output i/o = input/output p = power i = input ?= not used st = schmitt trigger input ttl = ttl input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. 3: this buffer is a schmitt trigger input when con?ured as a general purpose i/o and a ttl input when used in the parallel slave port mode (for interfacing to a microprocessor port).
1996 microchip technology inc. preliminary ds30559a-page 15 pic16c64x & pic16c66x 3.1 cloc king sc heme/instruction cyc le the clock input (from osc1) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3, and q4. internally, the program counter (pc) is incremented every q1, the instruction is fetched from the program memory and latched into the instruction register in q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w is shown in figure 3-3. 3.2 instruction flo w/pipelining an ?nstruction cycle?consists of four q cycles (q1, q2, q3, and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the ?nstruction register (ir)?in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-3: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed?from the pipeline while the new instruction is being fetched and then executed. tcy0 tcy1 tcy2 tcy3 tcy4 tcy5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush 5. instruction @ address sub_1 fetch sub_1 execute sub_1
pic16c64x & pic16c66x ds30559a-page 16 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 17 pic16c64x & pic16c66x 4.0 memory organization 4.1 pr ogram memor y or ganization the pic16c64x & pic16c66x have a 13-bit program counter capable of addressing an 8k x 14 program memory space. for the pic16c641 and pic16c661 only the ?st 2k x 14 (0000h - 07ffh) is physically implemented. for the pic16c642 and pic16c662 only the ?st 4k x 14 (0000h - 0ffh) is physically imple- mented. accessing a location above the 2k or 4k boundary will cause a wrap-around. the reset vector is at 0000h and the interrupt vector is at 0004h (figure 4- 1 and figure 4-2). see section 4.4 for program mem- ory paging. figure 4-1: pic16c641/661 program memory map and stack pc<12:0> 13 0000h 0004h 0005h 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 2000h 2007h 3fffh test con?uration word test user memory space figure 4-2: pic16c642/662 program memory map and stack pc<12:0> 13 0000h 0004h 0005h 0fffh 1000h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 2000h 2007h 3fffh test con?uration word test user memory space page0 on-chip program memory page1 07ffh 0800h this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 18 preliminary 1996 microchip technology inc. 4.2 d ata memor y or ganization the data memory (figure 4-4) is partitioned into two banks which contain the general purpose registers and the special function registers. bank 0 is selected when bit rp0 (status<5>) is cleared. bank 1 is selected when the rp0 bit is set. the special function regis- ters are located in the ?st 32 locations of each bank. register locations a0h-efh (bank 1) are general pur- pose registers implemented as static ram. some spe- cial function registers are mapped in bank 1. 4.2.1 general purpose register file the register ?e is organized as 176 x 8 for the pic16c642/662, and 128 x8 for the pic16c641/661. each is accessed either directly, or indirectly through the file select register fsr (section 4.5). figure 4-3: pic16c641/661 data memory map indf (1) tmr0 pcl status fsr porta portb portc pir1 cmcon indf (1) option pcl status fsr trisa trisb trisc pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register general purpose register 7fh ffh bank 0 bank 1 file address bfh c0h unimplemented data memory locations, read as '0'. note 1: not a physical register. 2: not implemented on the pic16c641. file address portd (2) trisd (2) trise (2) pclath intcon porte (2) pclath intcon mapped in page 0 efh f0h
1996 microchip technology inc. preliminary ds30559a-page 19 pic16c64x & pic16c66x figure 4-4: pic16c642/662 data memory map indf (1) tmr0 pcl status fsr porta portb pclath intcon pir1 cmcon indf (1) option pcl status fsr trisa trisb pclath intcon pie1 pcon vrcon 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1ah 1bh 1ch 1dh 1eh 1fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8ah 8bh 8ch 8dh 8eh 8fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9ah 9bh 9ch 9dh 9eh 9fh 20h a0h general purpose register 7fh ffh bank 0 bank 1 file address unimplemented data memory loca- tions, read as '0'. note 1: not a physical register. 2: not implemented on the pic16c642. file address portc trisc portd (2) trisd (2) porte (2) trise (2) general purpose register mapped in bank 0 efh f0h 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral modules for controlling the desired operation of the device (table 4-1). these registers are static ram. the special function registers can be classi?d into two sets (core and peripheral). the special function regis- ters associated with the ?ore?functions are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature.
pic16c64x & pic16c66x ds30559a-page 20 preliminary 1996 microchip technology inc. table 4-1: special function registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor, per value on all other resets (1) bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 02h pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 03h status irp (2) rp1 (2) rp0 t o pd zdcc 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h porta porta data latch when written: porta pins when read --xx 0000 --xu 0000 06h portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 06h portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 06h portd (3) portd data latch when written: portd pins when read xxxx xxxx uuuu uuuu 06h porte (3) re2 re1 re0 ---- -xxx ---- -uuu 0ah pclath write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (4) cmif 00-- ---- 00-- ---- 0dh-1eh unimplemented 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl program counter's (pc) least signi?ant byte 0000 0000 0000 0000 83h status irp (2) rp1 (2) rp0 t o pd zdcc 0001 1xxx 000q quuu 84h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h trisa porta data direction register --11 1111 --11 1111 86h trisb portb data direction register 1111 1111 1111 1111 86h trisc portc data direction register 1111 1111 1111 1111 86h trisd (3) portd data direction register 1111 1111 1111 1111 86h trise (3) ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 8ah pclath write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000x 8ch pie1 pspie (4) cmie 00-- ---- 00-- ---- 8dh unimplemented 8eh pcon mpeen per por bor u--- -qqq u--- -uuu 8fh-9eh unimplemented 9fh vrcon vren vroe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: - = unimplemented locations read as ?? u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: the irp and rp1 bits are reserved, always maintain these bits clear. 3: the portd, porte, trisd, and trise registers are not implemented on the pic16c641/642. 4: bits pspie and pspif are reserved on the pic16c641/642, always maintain these bits clear.
1996 microchip technology inc. preliminary ds30559a-page 21 pic16c64x & pic16c66x 4.2.2.1 status register the status register, shown in figure 4-5, contains the arithmetic status of the alu, the reset status, and the bank select bits for data memory. the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper-three bits and set the z bit. this leaves the status register as 000uu1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf, and movwf instructions are used to alter the status register because these instructions do not affect any status bit. for other instructions, not affecting any status bits, see the ?nstruction set summary.? note 1: the irp and rp1 bits (status<7:6>) are reserved on the pic16c64x & pic16c66x and should be maintained clear. use of these bits as general pur- pose r/w bits is not recommended, since this may affect upward compatibility with future products. note 2: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. figure 4-5: status register (address 03h, 83h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 t o pd z dc c r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: irp: register bank select bit (used for indirect addressing) 1 = bank 2, 3 (100h - 1ffh) 0 = bank 0, 1 (00h - ffh) bit irp is reserved on the pic16c64x & pic16c66x, always maintain this bit clear. bit 6-5: rp1:rp0 : register bank select bits (used for direct addressing) 11 = bank 3 (180h - 1ffh) 10 = bank 2 (100h - 17fh) 01 = bank 1 (80h - ffh) 00 = bank 0 (00h - 7fh) each bank is 128 bytes. bit rp1 is reserved on the pic16c64x & pic16c66x, always maintain this bit clear. bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit ( addwf , addlw,sublw,subwf instructions) (for b orrow the polarity is reversed) 1 = a carry-out from the 4th low order bit of the result occurred 0 = no carry-out from the 4th low order bit of the result bit 0: c : carry/borrow bit ( addwf , addlw,sublw,subwf instructions) 1 = a carry-out from the most signi?ant bit of the result occurred 0 = no carry-out from the most signi?ant bit of the result occurred note: for borrow the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low order bit of the source register.
pic16c64x & pic16c66x ds30559a-page 22 preliminary 1996 microchip technology inc. 4.2.2.2 option register the option register is a readable and writable register which contains various control bits to con?ure the tmr0/wdt prescaler, the external rb0/int interrupt, tmr0, and the weak pull-ups on portb. note: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt. figure 4-6: option register (address 81h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg t0cs t0se psa ps2 ps1 ps0 r= readable bit w= writable bit u= unimplemented bit, read as ? - n= value at por reset bit7 bit0 bit 7: rbpu : portb pull-up enable bit 1 = portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6: intedg : interrupt edge select bit 1 = interrupt on rising edge of rb0/int pin 0 = interrupt on falling edge of rb0/int pin bit 5: t0cs : tmr0 clock source select bit 1 = transition on ra4/t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : tmr0 source edge select bit 1 = increment on high-to-low transition on ra4/t0cki pin 0 = increment on low-to-high transition on ra4/t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate
1996 microchip technology inc. preliminary ds30559a-page 23 pic16c64x & pic16c66x 4.2.2.3 intcon register the intcon register is a readable and writable register which contains the various enable and ?g bits for all non-peripheral interrupt sources. note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). figure 4-7: intcon register (address 0bh, 8bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte rbie t0if intf rbif r= readable bit w= writable bit u= unimplemented bit, read as ? - n= value at por reset bit7 bit0 bit 7: gie: global interrupt enable bit 1 = enables all un-masked interrupts 0 = disables all interrupts bit 6: peie : peripheral interrupt enable bit 1 = enables all un-masked peripheral interrupts 0 = disables all peripheral interrupts bit 5: t0ie : tmr0 over?w interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4: inte : rb0/int external interrupt enable bit 1 = enables the rb0/int external interrupt 0 = disables the rb0/int external interrupt bit 3: rbie : rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2: t0if : tmr0 over?w interrupt flag bit 1 = tmr0 register over?wed (must be cleared in software) 0 = tmr0 register did not over?w bit 1: intf : rb0/int external interrupt flag bit 1 = the rb0/int external interrupt occurred (must be cleared in software) 0 = the rb0/int external interrupt did not occur bit 0: rbif : rb port change interrupt flag bit 1 = when at least one of the rb7:rb4 pins changed state (see section 5.2 to clear interrupt) 0 = none of the rb7:rb4 pins have changed state
pic16c64x & pic16c66x ds30559a-page 24 preliminary 1996 microchip technology inc. 4.2.2.4 pie1 register this register contains the individual enable bits for the comparator and parallel slave port interrupts. figure 4-8: pie1 register (address 8ch) r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 pspie (1) cmie r= readable bit w= writable bit u= unimplemented bit, read as ? - n= value at por reset bit7 bit0 bit 7: pspie (1) : parallel slave port read/write interrupt enable bit 1 = enables the psp read/write interrupt 0 = disables the psp read/write interrupt bit 6: cmie : comparator interrupt enable bit 1 = enables the comparator interrupt 0 = disables the comparator interrupt bit 5-0: unimplemented : read as '0' note 1: bit pspie is reserved on the pic16c641/642, always maintain this bit clear.
1996 microchip technology inc. preliminary ds30559a-page 25 pic16c64x & pic16c66x 4.2.2.5 pir1 register this register contains the individual ?g bits for the comparator and parallel slave port interrupts. note: interrupt ?g bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt ?g bits are clear prior to enabling an interrupt. figure 4-9: pir1 register (address 0ch) r/w-0 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 pspif (1) cmif r= readable bit w= writable bit u= unimplemented bit, read as ? - n= value at por reset bit7 bit0 bit 7: pspif (1) : parallel slave port interrupt flag bit 1 = a read or write operation has taken place (must be cleared in software) 0 = no read or write operation has taken place bit 6: cmif : comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5-0: unimplemented : read as '0' note 1: bit pspif is reserved on the pic16c641/642, always maintain this bit clear.
pic16c64x & pic16c66x ds30559a-page 26 preliminary 1996 microchip technology inc. 4.2.2.6 pcon register the pcon register contains ?g bits to differentiate between a power-on reset (por), an external mclr reset, wdt reset, brown-out reset (bor), and parity error reset (per). the pcon register also contains a status bit, mpeen, which re?cts the value of the mpeen bit in con?uration word. see table 9-4 for status of these bits on various resets. note: bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor is cleared, indicating a brown-out has occurred. the bor status bit is a ?on't care?and is not necessarily predictable if the brown-out circuit is disabled (by programming the boden bit in the con?uration word). figure 4-10: pcon register (address 8eh) r-u u-0 u-0 u-0 u-0 r/w-1 r/w-0 r/w-u mpeen ? er por bor r= readable bit w= writable bit u= unimplemented bit, read as ? - n= value at por reset bit7 bit0 bit 7: mpeen : memory parity error circuitry status bit re?cts the value of con?uration word bit, mpeen bit 6-3: unimplemented : read as '0' bit 2: per : memory parity error reset status bit 1 = no error occurred 0 = program memory fetch parity error occurred (must be set in software after a parity error reset occurs) bit 1: por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0: bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs)
1996 microchip technology inc. preliminary ds30559a-page 27 pic16c64x & pic16c66x 4.3 pcl and pcla th the program counter (pc) is 13-bits wide. the low byte comes from the pcl register, which is readable and writable. the high byte (pc<12:8>) is not directly read- able or writable and comes from pclath. on any reset, the pc is cleared. figure 4-11 shows the two situations for the loading of the pc. the upper example in the ?ure shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in the ?ure shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 4-11: loading of pc in different situations 4.3.1 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when doing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256 byte block). refer to the application note ?mplementing a table read (an556). pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination 4.3.2 stack pic16c64x & pic16c66x devices have an 8 level deep x 13-bit wide hardware stack (figure 4-2). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the ?st push. the tenth push overwrites the second push (and so on). 4.4 pr ogram memor y p a ging pic16c642 and pic16c662 devices have 4k of pro- gram memory, but the call and goto instructions only have an 11-bit address range. this 11-bit address range allows a branch within a 2k program memory page size. to allow call and goto instructions to address the entire 4k program memory address range, there must be another bit to specify the program mem- ory page. this paging bit comes from the pclath<3> bit (figure 4-11). when doing a call or goto instruc- tion, the user must ensure that this page select bit (pclath<3>) is programmed so that the desired pro- gram memory page is addressed. if a return from a call instruction (or interrupt) is executed, the entire 13-bit pc is pushed onto the stack. therefore, manipu- lation of the pclath<3> bit is not required for the return instructions (which pops the address from the stack). note 1: there are no status bits to indicate stack over?w or stack under?w conditions. note 2: there are no instructions mnemonics called push or pop. these are actions that occur from the execution of the call, return, retlw, and retfie instruc- tions, or the vectoring to an interrupt address. note: the pic16c64x & pic16c66x ignore the pclath<4> bit, which is used for program memory pages 2 and 3 (1000h - 1fffh). the use of pclath<4> as a general pur- pose read/write bit is not recommended since this may affect upward compatibility with future products.
pic16c64x & pic16c66x ds30559a-page 28 preliminary 1996 microchip technology inc. 4.5 indirect ad dressing, indf , and fsr register s the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf reg- ister. any instruction using the indf register actually accesses data pointed to by the ?e select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no- operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr register and the irp bit (status<7>), as shown in figure 4-12. however, bit irp is not used in the pic16c64x & pic16c66x. a simple program to clear ram location 20h-2fh using indirect addressing is shown in example 4-1. example 4-1: indirect addressing movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no goto next ;yes continue continue: figure 4-12: direct/indirect addressing for memory map detail see figure 4-3 and figure 4-4. note 1: bits rp1 and irp are reserved, always maintain these bits clear. data memory indirect addressing direct addressing bank select location select (1) rp1 rp0 6 0 from opcode irp (1) fsr register 7 0 bank select location select 00 01 10 11 00h 7fh 00h 7fh bank 0 bank 1 bank 2 bank 3 not used
1996 microchip technology inc. preliminary ds30559a-page 29 pic16c64x & pic16c66x 5.0 i/o ports the pic16c641 and pic16c642 have three ports, porta, portb, and portc. pic16c661 and pic16c662 devices have ?e ports, porta through porte. some pins for these i/o ports are multiplexed with alternate functions for the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. 5.1 por t a and trisa register s porta is a 6-bit wide latch. ra4 is a schmitt trigger input and an open drain output. pin ra4 is multiplexed with the t0cki clock input. all other ra port pins have schmitt trigger input levels and full cmos output driv- ers. all pins have data direction bits (tris registers) which can con?ure these pins as input or output. setting a bit in the trisa register puts the correspond- ing output driver in a hi-impedance mode. clearing a bit in the trisa register puts the contents of the output latch on the selected pin. reading the porta register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modi?d, and then written to the port data latch. the porta pins are multiplexed with comparator and voltage reference functions. the operation of these pins are selected by control bits in the cmcon (comparator control register) register and the vrcon (voltage reference control) register. when selected as comparator inputs, these pins will read as '0's. figure 5-1: block diagram of ra1:ra0 pins trisa controls the direction of the ra pins, even when they are being used as comparator inputs. the user must make sure to keep the pins con?ured as inputs when using them as comparator inputs. the ra2 pin will also function as the output for the voltage reference. when in this mode, the v ref pin is a very hi-impedance output. the user must set the trisa<2> bit and use hi-impedance loads. in one of the comparator modes de?ed by the cmcon register, pins ra3 and ra4 become outputs of the comparators. the trisa<4:3> bits must be cleared to enable outputs to use this function. example 5-1: initializing porta clrf porta ;initialize porta by ;clearing output latches movlw 0x07 ;turn comparators off, movwf cmcon ;enable pins for i/o bsf status, rp0 ;select bank1 movlw 0x1f ;value to initialize ;data direction movwf trisa ;set ra<4:0> as inputs ;trisa<7:5> are clear note: on reset, the trisa register is set to all inputs. the digital inputs are disabled and the comparator inputs are forced to ground to reduce excess current consumption. note: i/o pins have protection diodes to v dd and v ss . data bus q d q ck p n wr port wr tris data latch tris latch rd tris rd port analog v ss v dd i/o pin q d q ck input mode d q en to comparator schmitt trigger input buffer this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 30 preliminary 1996 microchip technology inc. figure 5-2: block diagram of ra2 pin note: i/o pin has protection diodes to v dd and v ss . data bus q d q ck p n wr port wr tris data latch tris latch rd tris rd port analog v ss v dd ra2 pin q d q ck input mode d q en to comparator schmitt trigger input buffer vroe v ref figure 5-3: block diagram of ra3 pin data bus q d q ck p n wr port wr tris data latch tris latch rd tris rd port analog v ss v dd ra3 pin q d q ck d q en to comparator schmitt trigger input buffer input mode comparator output comparator mode = 110
1996 microchip technology inc. preliminary ds30559a-page 31 pic16c64x & pic16c66x figure 5-4: block diagram of ra4 pin table 5-1: porta functions table 5-2: summary of registers associated with porta name bit # buffer type function ra0/an0 bit0 st input/output or comparator input. ra1/an1 bit1 st input/output or comparator input. ra2/an2/v ref bit2 st input/output or comparator input or v ref output. ra3/an3 bit3 st input/output or comparator input/output. ra4/t0cki bit4 st input/output or external clock input for tmr0 or comparator output. out- put is open drain type. ra5 bit5 st input/output. legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h porta ra5 ra4 ra3 ra2 ra1 ra0 --xx 0000 --uu 0000 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vroe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: x = unknown, u = unchanged, - = unimplemented locations read as ?? shaded cells are not used by porta. data bus q d q ck n wr port wr tris data latch tris latch rd tris rd port v ss ra4 pin q d q ck d q en tmr0 clock input schmitt trigger input buffer comparator output comparator mode = 110
pic16c64x & pic16c66x ds30559a-page 32 preliminary 1996 microchip technology inc. 5.2 por tb and trisb register s portb is an 8-bit wide bi-directional port. the corresponding data direction register is trisb. setting a bit in the trisb register puts the corresponding out- put driver in a hi-impedance mode. clearing a bit in the trisb register puts the contents of the output latch on the selected pin(s). reading portb register reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. there- fore, a write to a port implies that the port pins are read, this value is modi?d, and then written to the port data latch. each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is done by clearing the rbpu (option<7>) bit. the weak pull-up is automatically turned off when the port pin is con?ured as an output. the pull-ups are dis- abled on a power-on reset. four of portb? pins, rb7:rb4, have an interrupt on change feature. only pins con?ured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin con?ured as an output is excluded from the interrupt on change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?ismatch?outputs of rb7:rb4 are or?d together to generate the rbif interrupt (?g latched in (intcon<0>)). figure 5-5: block diagram of rb7:rb4 pins data latch from other rbpu (2) p v dd i/o q d ck q d ck qd en qd en data bus wr port wr tris set rbif tris latch rd tris rd port rb7:rb4 pins weak pull-up rd port latch ttl input buffer pin (1) note 1: i/o pins have diode protection to v dd and v ss . 2: trisb = '1' enables weak pull-up if rbpu = '0' (option<7>). st buffer rb7:rb6 in serial programming mode this interrupt can wake the device from sleep. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb. this will end the mismatch condition. b) clear ?g bit rbif. a mismatch condition will continue to set ?g bit rbif. reading portb will end the mismatch condition, and allow ?g bit rbif to be cleared. this interrupt on mismatch feature, together with software con?urable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. (see an552 in the microchip embedded control handbook .) the interrupt on change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt on change feature. polling of portb is not recommended while using the interrupt on change feature. figure 5-6: block diagram of rb3:rb0 pins data latch rbpu (2) p v dd q d ck q d ck qd en data bus wr port wr tris rd tris rd port weak pull-up rd port rb0/int i/o pin (1) ttl input buffer note 1: i/o pins have diode protection to v dd and v ss . 2: trisb = '1' enables weak pull-up if rbpu = '0' (option<7>). st buffer
1996 microchip technology inc. preliminary ds30559a-page 33 pic16c64x & pic16c66x example 5-2: initializing portb clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs table 5-3: portb functions table 5-4: summary of registers associated with portb name bit # buffer type function rb0/int bit0 ttl/st (1) input/output or external interrupt input. internal software programmable weak pull-up. rb1 bit1 ttl input/output pin. internal software programmable weak pull-up. rb2 bit2 ttl input/output pin. internal software programmable weak pull-up. rb3 bit3 ttl input/output pin. internal software programmable weak pull-up. rb4 bit4 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb5 bit5 ttl input/output pin (with interrupt on change). internal software programmable weak pull-up. rb6 bit6 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming clock pin. rb7 bit7 ttl/st (2) input/output pin (with interrupt on change). internal software programmable weak pull-up. serial programming data pin. legend: st = schmitt trigger input, ttl = ttl input note 1: this buffer is a schmitt trigger input when con?ured as the external interrupt. 2: this buffer is a schmitt trigger input when used in serial programming mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 86h trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 1111 1111 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, shaded cells are not used by portb.
pic16c64x & pic16c66x ds30559a-page 34 preliminary 1996 microchip technology inc. 5.3 por tc and trisc register s portc is an 8-bit bi-directional port. each pin is indi- vidually con?urable as an input or output through the trisc register. portc pins have schmitt trigger input buffers. example 5-3: initializing portc clrf portc ; initialize portc by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs figure 5-7: portc block diagram (in i/o port mode) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en table 5-5: portc functions table 5-6: summary of registers associated with portc name bit# buffer type function rc0 bit0 st input/output rc1 bit1 st input/output rc2 bit2 st input/output rc3 bit3 st input/output rc4 bit4 st input/output rc5 bit5 st input/output rc6 bit6 st input/output rc7 bit7 st input/output legend: st = schmitt trigger input address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 87h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged.
1996 microchip technology inc. preliminary ds30559a-page 35 pic16c64x & pic16c66x 5.4 por td and trisd register s ( pic16c661 and pic16c662 onl y) portd is an 8-bit port with schmitt trigger input buff- ers. each pin is individually con?urable as an input or output. portd can be con?ured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit pspmode (trise<4>). in this mode, the input buffers are ttl. figure 5-8: portd block diagram (in i/o port mode) data bus wr port wr tris rd port data latch tris latch rd tris schmitt trigger input buffer i/o pin (1) note 1: i/o pins have protection diodes to v dd and v ss . q d ck q d ck en qd en table 5-7: portd functions table 5-8: summary of registers associated with portd name bit# buffer type function rd0/psp0 bit0 st/ttl (1) input/output port pin or parallel slave port bit0 rd1/psp1 bit1 st/ttl (1) input/output port pin or parallel slave port bit1 rd2/psp2 bit2 st/ttl (1) input/output port pin or parallel slave port bit2 rd3/psp3 bit3 st/ttl (1) input/output port pin or parallel slave port bit3 rd4/psp4 bit4 st/ttl (1) input/output port pin or parallel slave port bit4 rd5/psp5 bit5 st/ttl (1) input/output port pin or parallel slave port bit5 rd6/psp6 bit6 st/ttl (1) input/output port pin or parallel slave port bit6 rd7/psp7 bit7 st/ttl (1) input/output port pin or parallel slave port bit7 legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 xxxx xxxx uuuu uuuu 88h trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 1111 1111 1111 1111 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by portd.
pic16c64x & pic16c66x ds30559a-page 36 preliminary 1996 microchip technology inc. 5.5 por te and trise register ( pic16c661 and pic16c662 onl y) porte has three pins re0/rd , re1/wr , and re2/ cs , which are individually con?urable as inputs or outputs. these pins have schmitt trigger input buffers. i/o porte becomes control inputs for the micropro- cessor port when bit pspmode (trise<4>) is set. in this mode, the user must make sure that the trise<2:0> bits are set (pins are con?ured as digital inputs). in this mode the input buffers are ttl. figure 5-9 shows the trise register, which also con- trols the parallel slave port operation. figure 5-9: trise register (address 89h) r-0 r-0 r/w-0 r/w-0 u-0 r/w-1 r/w-1 r/w-1 ibf obf ibov pspmode trise2 trise1 trise0 r = readable bit w = writable bit u = unimplemented bit, read as ? - n = value at por reset bit7 bit0 bit 7: ibf: input buffer full status bit 1 = a word has been received and waiting to be read by the cpu 0 = no word has been received bit 6: obf : output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5: ibov : input buffer over?w detect bit (in microprocessor mode) 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no over?w occurred bit 4: pspmode : parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3: unimplemented : read as '0' bit 2: trise2 : direction control bit for pin re2/cs 1 = input 0 = output bit 1: trise1 : direction control bit for pin re1/wr 1 = input 0 = output bit 0: trise0 : direction control bit for pin re0/rd 1 = input 0 = output
1996 microchip technology inc. preliminary ds30559a-page 37 pic16c64x & pic16c66x figure 5-10: porte block diagram (in i/o port mode) table 5-9: porte functions table 5-10: summary of registers associated with porte name bit# buffer type function re0/rd bit0 st/ttl (1) input/output port pin or read control input in parallel slave port mode: rd 1 = not a read operation 0 = read operation. reads portd register (if chip selected) re1/wr bit1 st/ttl (1) input/output port pin or write control input in parallel slave port mode: wr 1 = not a write operation 0 = write operation. writes portd register (if chip selected) re2/cs bit2 st/ttl (1) input/output port pin or chip select control input in parallel slave port mode: cs 1 = device is not selected 0 = device is selected legend: st = schmitt trigger input, ttl = ttl input note 1: input buffers are schmitt triggers when in i/o mode and ttl buffers when in parallel slave port mode. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 legend: x = unknown, u = unchanged, - = unimplemented read as '0'. shaded cells are not used by porte. data bus wr port wr tris rd port data latch tris latch schmitt trigger input buffer q d q ck q d q ck en qd en i/o pin rd tris note: i/o pins have protection diodes to v dd and v ss .
pic16c64x & pic16c66x ds30559a-page 38 preliminary 1996 microchip technology inc. 5.6 i/o pr ogramming considerations 5.6.1 bi-directional i/o ports any instruction which writes, operates internally as a read followed by a write operation. the bcf and bsf instructions, for example, read the register into the cpu, execute the bit operation and write the result back to the register. caution must be used when these instructions are applied to a port with both inputs and outputs de?ed. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu. then the bsf operation takes place on bit5 and portb is written to the output latches. if another bit of portb is used as a bi-directional i/o pin (e.g., bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. reading the port register reads the values of the port pins. writing to the port register writes the value to the port latch. when using read-modify-write instructions (e.g., bcf, bsf , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch. example 5-4 shows the effect of two sequential read-modify-write instructions on an i/o port. a pin actively outputting a low or high should not be driven from external devices at the same time in order to change the level on this pin (?ired-or? ?ired-and?. the resulting high output currents may damage the chip. example 5-4: read-modify-write instructions on an i/o port ;initial port settings: portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- --------- bcf portb, 7 ; 01pp pppp 11pp pppp bcf portb, 6 ; 10pp pppp 11pp pppp bcf status, rp1 ; bsf status, rp0 ; bcf trisb, 7 ; 10pp pppp 11pp pppp bcf trisb, 6 ; 10pp pppp 10pp pppp ; ;note that the user may have expected the ;pin values to be 00pp ppp. the 2nd bcf ;caused rb7 to be latched as the pin value ;(high). 5.6.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-11). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ?e to be read into the cpu is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with an nop or another instruction not accessing this i/o port. figure 5-11: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb write to portb nop port pin sampled here nop movf portb,w instruction executed movwf portb write to portb nop movf portb,w pc t pd note: this example shows a write to portb followed by a read from portb. note that: data setup time = (0.25t cy - t pd ) where t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic.
1996 microchip technology inc. preliminary ds30559a-page 39 pic16c64x & pic16c66x 5.7 p aral lel sla ve p or t ( pic16c66 1 and pic16c66 2 onl y) portd operates as an 8-bit wide parallel slave port, or as a microprocessor port when control bit pspmode (trise<4>) is set. in slave mode it is asynchronously readable and writable by the external world through r d control input pin (re0/rd ) and w r control input pin (re1/wr ). it can directly interface to an 8-bit microprocessor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting pspmode enables port pin re0/rd to be the rd input, re1/wr to be the wr input and re2/cs to be the c s (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be con?ured as inputs (set). there are actually two 8-bit latches, one for data-out (from the pic16/17) and one for data input. the user writes 8-bit data to portd data latch and reads data from the port pin latch (note that they have the same address). in this mode, the trisd register is ignored since the microprocessor is controlling the direction of data ?w. input buffer full status flag bit ibf (trise<7>) is set if a received word is waiting to be read by the cpu. once the portd input latch is read, bit ibf is cleared. ibf is a read only status bit. output buffer full status flag bit obf (trise<6>) is set if a word written to portd latch is waiting to be read by the external bus. once the portd output latch is read by the micropro- cessor, bit obf is cleared. input buffer over?w status ?g bit ibov (trise<5>) is set if a second write to the microprocessor port is attempted when the previous word has not been read by the cpu (the ?st word is retained in the buffer). when not in parallel slave port mode, bits ibf and obf are held clear. however, if ?g bit ibov was pre- viously set, it must be cleared in software. an interrupt is generated and latched into ?g bit pspif (pir1<7>) when a read or a write operation is completed. flag bit pspif must be cleared by user software. the interrupt can be disabled by clearing the interrupt enable bit pspie (pie1<7>). figure 5-12: portd and porte as a parallel slave port data bus wr port rd rdx q d ck en qd en port pin one bit of portd set interrupt ?g pspif (pir1<7>) read chip select write rd cs wr note: i/o pins have protection diodes to v dd and v ss . ttl ttl ttl ttl table 5-11: registers associated with parallel slave port address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 08h portd psp7 psp6 psp5 psp4 psp3 psp2 psp1 psp0 xxxx xxxx uuuu uuuu 09h porte re2 re1 re0 ---- -xxx ---- -uuu 89h trise ibf obf ibov pspmode trise2 trise1 trise0 0000 -111 0000 -111 0ch pir1 pspif (1) cmif 00-- ---- 00-- ---- 8ch pie1 pspie (1) cmie 00-- ---- 00-- ---- legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by the psp. note 1: these bits are reserved on the pic16c641/642, always maintain these bits clear.
pic16c64x & pic16c66x ds30559a-page 40 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 41 pic16c64x & pic16c66x 6.0 timer0 module the timer0 module has the following features: 8-bit timer/counter register, tmr0 - read and write capability - interrupt on over?w from ffh to 00h 8-bit software programmable prescaler internal or external clock select - edge select for external clock figure 6-1 is a simpli?d block diagram of the timer0 module. timer mode is selected by clearing bit t0cs (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two instruction cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting bit t0cs. in this mode, timer0 will increment either on every rising or falling edge of pin ra4/t0cki. the incrementing edge is determined by the source edge select bit t0se (option<4>). clearing bit t0se selects the rising edge. restrictions on the external clock input are dis- cussed in detail in section 6.2. the prescaler is mutually exclusively shared between the timer0 module and the watchdog timer. the pres- caler assignment is controlled in software by control bit psa (option<3>). clearing bit psa will assign the prescaler to the timer0 module. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, ? 1:256 are selectable. section 6.3 details the operation of the prescaler. 6.1 t imer0 i nterrupt the tmr0 interrupt is generated when the register (tmr0) over?ws from ffh to 00h. this over?w sets interrupt ?g bit t0if (intcon<2>). the interrupt can be masked by clearing enable bit t0ie (intcon<5>). flag bit t0if must be cleared in software by the timer0 interrupt service routine before re-enabling this inter- rupt. the tmr0 interrupt cannot wake the processor from sleep since the timer is shut off during sleep. figure 6-4 displays the timer0 interrupt timing. figure 6-1: timer0 block diagram figure 6-2: timer0 timing: internal clock/no prescaler note 1: bits, t0cs, t0se, psa, and ps2, ps1, ps0 are (option<5:0). 2: the prescaler is shared with watchdog timer (refer to figure 6-6 for detailed diagram). ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 set bit t0if on over?w psa ps2, ps1, ps0 3 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 42 preliminary 1996 microchip technology inc. figure 6-3: timer0 timing: internal clock/prescale 1:2 figure 6-4: timer0 interrupt timing pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch tmr0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 1 1 osc1 clkout (3) timer0 t0if bit (intcon<2>) feh gie bit (intcon<7>) instruction pc instruction fetched pc pc +1 pc +1 0004h 0005h instruction executed inst (pc) inst (pc-1) inst (pc+1) inst (pc) inst (0004h) inst (0005h) inst (0004h) dummy cycle dummy cycle ffh 00h 01h 02h note 1: interrupt ?g bit t0if is sampled here (every q1). 2: interrupt latency = 4tcy where tcy = instruction cycle time. 3: clkout is available only in rc oscillator mode. f low
1996 microchip technology inc. preliminary ds30559a-page 43 pic16c64x & pic16c66x 6.2 using timer0 with external cloc k when an external clock input is used for timer0, it must meet certain requirements. the requirements ensure the external clock can be synchronized with the internal phase clock (t osc ). also, there is a delay in the actual incrementing of timer0 after synchronization. 6.2.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki to be high for at least 2tosc (and a small rc delay of 20 ns) and low for at least 2tosc (and a small rc delay of 20 ns). refer to the electrical speci?ation of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. there- fore, it is necessary for t0cki to have a period of at least 4tosc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the mini- mum pulse width requirement of 10 ns. refer to param- eters 40, 41, and 42 in the electrical speci?ation of the desired device. 6.2.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. figure 6-5: timer0 timing with external clock q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 external clock input or prescaler output (2) external clock/prescaler output after sampling increment timer0 (q4) timer0 t0 t0 + 1 t0 + 2 note 1: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. 2: external clock if no prescaler selected, prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. (3) (1) small pulse misses sampling
pic16c64x & pic16c66x ds30559a-page 44 preliminary 1996 microchip technology inc. 6.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (figure 6-6). for simplicity, this counter is being referred to as ?rescaler?through- out this data sheet. note that the prescaler may be used by either the timer0 module or the watchdog timer, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the watchdog timer, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine the prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x ) will clear the prescaler count. when assigned to watchdog timer, a clrwdt instruction will clear the prescaler count along with the watchdog timer. the prescaler is not readable or writable. figure 6-6: block diagram of the timer0/wdt prescaler ra4/t0cki t0se pin m u x clkout (=fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m u x m u x watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are (option<5:0>). psa wdt enable bit m u x 0 1 0 1 data bus set ?g bit t0if on over?w 8 psa t0cs
1996 microchip technology inc. preliminary ds30559a-page 45 pic16c64x & pic16c66x 6.3.1 switching prescaler assignment the prescaler assignment is fully under software con- trol, i.e., it can be changed ?n the ??during program execution. example 6-1: changing prescaler (timer0 ? wdt) bcf status, rp0 ;bank 0 clrf tmr0 ;clear tmr0 & prescaler bsf status, rp0 ;bank 1 clrwdt ;clears wdt movlw b'xxxx1xxx' ;select new prescale movwf option_reg ;value & wdt bcf status, rp0 ;bank 0 note: to avoid an unintended device reset, the following instruction sequence (shown in example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. this precaution must be followed even if the wdt is disabled. to change prescaler from the wdt to the timer0 mod- ule, use the sequence shown in example 6-2. example 6-2: changing prescaler (wdt ? timer0) clrwdt ;clear wdt and ;prescaler bsf status, rp0 ;bank 1 movlw b'xxxx0xxx' ;select tmr0, new ;prescale value and movwf option_reg ;clock source bcf status, rp0 ;bank 0 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h tmr0 timer0 modules register xxxx xxxx uuuu uuuu 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. shaded cells are not used by timer0.
pic16c64x & pic16c66x ds30559a-page 46 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 47 pic16c64x & pic16c66x 7.0 comparator module the comparator module contains two analog comparators. the inputs to the comparators are multiplexed with pins ra0 through ra4. the on-chip voltage reference (section 8.0) can also be an input to the comparators. the cmcon register, shown in figure 7-1, controls the comparator input and output multiplexers. a block diagram of the comparator is shown in figure 7-2. figure 7-1: cmcon register (address 1fh) r-0 r-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c2out c1out cis cm2 cm1 cm0 r =readable bit w =writable bit u =unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: c2out : comparator 2 output 1 = c2 v in + > c2 v in 0 = c2 v in + < c2 v in bit 6: c1out : comparator 1 output 1 = c1 v in + > c1 v in 0 = c1 v in + < c1 v in bit 5-4: unimplemented: read as '0' bit 3: cis : comparator input switch when cm2:cm0: = 001 : then: 1 = c1 v in ?connects to ra3 0 = c1 v in ?connects to ra0 when cm2:cm0 = 010 : then: 1 = c1 v in ?connects to ra3 c2 v in ?connects to ra2 0 = c1 v in ?connects to ra0 c2 v in ?connects to ra1 bit 2-0: cm2:cm0 : comparator mode figure 7-2 shows the comparator modes and cm2:cm0 bit settings. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 48 preliminary 1996 microchip technology inc. 7.1 comparator con guration there are eight modes of operation for the comparators. the cmcon register is used to select the mode. figure 7-2 shows the eight possible modes. the trisa register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the speci?d mode change delay shown in table 12-2. note: comparator interrupts should be disabled during a comparator mode change other- wise a false interrupt may occur. figure 7-2: comparator i/o operating modes c1 ra0/an0 v in - v in + ra3/an3 off (read as '0') comparators reset (por default value) a a cm2:cm0 = 000 c2 ra1/an1 v in - v in + ra2/an2 off (read as '0') a a c1 ra0/an0 v in - v in + ra3/an3 c1out two independent comparators a a cm2:cm0 = 100 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators a d cm2:cm0 = 011 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as '0') one independent comparator d d cm2:cm0 = 101 c2 ra1/an1 v in - v in + ra2/an2 c2out a a c1 ra0/an0 v in - v in + ra3/an3 off (read as '0') comparators off d d cm2:cm0 = 111 c2 ra1/an1 v in - v in + ra2/an2 off (read as '0') d d c1 ra0/an0 v in - v in + ra3/an3 c1out four inputs multiplexed to two comparators a a cm2:cm0 = 010 c2 ra1/an1 v in - v in + ra2/an2 c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 ra0/an0 v in - v in + ra3/an3 c1out two common reference comparators with outputs a d cm2:cm0 = 110 c2 ra1/an1 v in - v in + ra2/an2 c2out a a ra4 open drain c1 ra0/an0 v in - v in + ra3/an3 c1out three inputs multiplexed to two comparators a a cm2:cm0 = 001 c2 ra1/an1 v in - v in + ra2/an2 c2out a a cis = 0 cis = 1 a = analog input, port reads zeros always. d = digital input. cis (cmcon<3>) is the comparator input switch.
1996 microchip technology inc. preliminary ds30559a-page 49 pic16c64x & pic16c66x the code example in example 7-1 depicts the steps required to con?ure the comparator module. ra3 and ra4 are con?ured as digital outputs. ra0 and ra1 are con?ured as the v- inputs and ra2 as the v+ input to both comparators. example 7-1: initializing the comparator module flag_reg equ 0x20 clrf flag_reg ;init flag register clrf porta ;init porta andlw 0xc0 ;mask comp bits iorwf flag_reg,f ;bits to flag_reg movlw 0x03 ;init comp mode movwf cmcon ;cm2:cm0 = 011 bsf status,rp0 ;select bank 1 movlw 0x07 ;init data direction movwf trisa ;ra<2:0> to inputs ;ra<4:3> to outputs ;trisa<7:5> read '0' bcf status,rp0 ;select bank 0 call delay_10 m s ;10 m s delay movf cmcon,f ;read cmcon to end ;change condition bcf pir1,cmif ;clear pending ints bsf status,rp0 ;select bank 1 bsf pie1,cmie ;enable comp ints bcf status,rp0 ;select bank 0 bsf intcon,peie ;enable periph ints bsf intcon,gie ;global int enable 7.2 comparator operation a single comparator is shown in figure 7-3 along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in ? the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in ? the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 7-3 represents the uncertainty due to input offsets and response time. 7.3 comparator ref erence an external or internal reference signal may be used depending on the comparator operating mode. the analog signal that is present at v in ?is compared to the signal at v in +, and the digital output of the comparator is adjusted accordingly (figure 7-3). figure 7-3: single comparator 7.3.1 external reference signal when external voltage references are used, the comparator module can be con?ured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd , and can be applied to either pin of the comparator(s). 7.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference for the comparators. section 8.0, contains a detailed descrip- tion of the voltage reference module that provides this signal. the internal reference signal is used when the comparators are in mode cm2:cm0 = 010 (figure 7-2). in this mode, the internal voltage refer- ence is applied to the v in + pin of both comparators. v in - v in + output v in - v in + output
pic16c64x & pic16c66x ds30559a-page 50 preliminary 1996 microchip technology inc. 7.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output is guaranteed to have a valid level. if the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (table 12-2 and table 12-3). 7.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read only. the comparator outputs may also be directly output to the ra3 and ra4 i/o pins. when cm2:cm0 = 110 , multiplexors in the output path of the ra3 and ra4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the speci?ations. figure 7-4 shows the comparator output block diagram. the trisa bits will still function as an output enable/ disable for the ra3 and ra4 pins while in this mode. note 1: when reading the porta register, all pins con?ured as analog inputs will read as a ?? pins con?ured as digital inputs will convert an analog input according to the schmitt trigger input speci?ation. note 2: analog levels on any pin that is de?ed as a digital input may cause the input buffer to consume more current than is speci- ?d. figure 7-4: comparator output block diagram d q en to ra3 or ra4 pin rd cmcon set cmif bit multiplex d q en cl port pins rd cmcon nreset from other comparator to data bus
1996 microchip technology inc. preliminary ds30559a-page 51 pic16c64x & pic16c66x 7.6 c omparat or interrupts the comparator interrupt ?g is set whenever there is a change in the output value of either comparator. user software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that has occurred. the cmif bit (pir1<6>), is the comparator interrupt ?g and must be cleared in user software. to enable the comparator interrupt the following bits must be set: cmie (pie1<6>) peie (intcon<6>) gie (intcon<7>) the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon. this will end the mismatch condition. b) clear ?g bit cmif. a mismatch condition will continue to set ?g bit cmif. reading cmcon will end the mismatch condition, and allow ?g bit cmif to be cleared. 7.7 c omparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional if enabled. this interrupt will wake up the device from sleep mode when enabled. while the comparator is powered up, higher sleep currents than shown in the power-down current speci?ation will occur. each comparator that is operational will consume additional current as shown in the comparator speci?ations. to minimize power consumption while in sleep mode, turn off the comparators, cm2:cm0 = 111 , before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 7.8 eff ects of a reset a device reset forces the cmcon register to its reset state. this forces the comparator module to be in the comparator reset mode, cm2:cm0 = 000 . this ensures that all potential inputs are analog inputs. device current is minimized when analog inputs are present at reset time. the comparators will be powered down during the reset interval. 7.9 analog input connection considerations a simpli?d circuit for an analog input is shown in figure 7-5. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k w is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 7-5: analog input model v a r s a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r c < 10k i leakage 500 na v ss legend c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage
pic16c64x & pic16c66x ds30559a-page 52 preliminary 1996 microchip technology inc. table 7-1: registers associated with the comparator module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 9fh vrcon vren vroe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 0bh/8bh intcon gie peie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u 0ch pir1 pspif (1) cmif 00-- ---- 00-- ---- 8ch pie1 pspie (1) cmie 00-- ---- 00-- ---- 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 note 1: these bits are reserved on the pic16c641/642, always maintain these bits clear.
1996 microchip technology inc. preliminary ds30559a-page 53 pic16c64x & pic16c66x 8.0 voltage reference module the voltage reference is a 16-tap resistor ladder network that provides a selectable voltage reference. the resistor ladder is segmented to provide two ranges of v ref values and has a power-down function to conserve power when the reference module is not being used. the vrcon register, shown in figure 8-1, controls the operation of the voltage reference module. the block diagram is given in figure 8-2. figure 8-1: vrcon register (address 9fh) figure 8-2: voltage reference block diagram r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 vren vroe vrr vr3 vr2 vr1 vr0 r =readable bit w =writable bit u =unimplemented bit, read as ? - n =value at por reset bit7 bit0 bit 7: vren: v ref enable 1 = v ref circuit powered up 0 = v ref circuit powered down, no i dd drain bit 6: vroe: v ref output enable 1 = v ref is output on ra2 pin 0 = v ref is disconnected from ra2 pin bit 5: vrr: v ref range selection 1 = low range 0 = high range bit 4: unimplemented: read as '0' bit 3-0: vr3:vr0 : v ref value selection 0 vr3:vr0 15 when: vrr = 1 then: v ref = (vr3:vr0/ 24) ?v dd when: vrr = 0 then: v ref = 1/4 ?v dd + (vr3:vr0/ 32) ?v dd note: r is de?ed in table 12-3. vrr 8r vr3 vr0 (from vrcon<3:0>) 16-1 analog mux 8r r r r r vren v ref 16 stages vr2 vr1 this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 54 preliminary 1996 microchip technology inc. 8.1 con guring the v olta g e ref erence the voltage reference module can output 16 distinct voltage levels for each range. the equations used to calculate the output of the voltage reference are as follows: if vrr = 1 then v ref = (vr3:vr0/24) ?v dd if vrr = 0 then v ref = (v dd ?1/4) + (vr3:vr0/32) ?v dd the settling time of the voltage reference must be considered when changing the v ref output (table 12-2). example 8-1 shows an example of how to con?ure the voltage reference for an output voltage of 1.25v with v dd = 5.0v. example 8-1: voltage reference configuration movlw 0x02 ; 4 inputs muxed movwf cmcon ; to 2 comparators bsf status,rp0 ; select bank 1 movlw 0x07 ; ra3:ra0 to outputs movwf trisa ; movlw 0xa6 ; enable vref low movwf vrcon ; range, vr3:vr0 = 6 bcf status,rp0 ; select bank 0 call delay_10 m s ; 10 m s delay 8.2 v olta g e ref erence accurac y/err or the full range of v ss to v dd cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 8-2) keep v ref from approaching v ss or v dd . the voltage reference is v dd derived and therefore, the v ref output changes with ?ctuations in v dd . the absolute accuracy of the voltage reference can be found in table 12-3. 8.3 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the vrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference module should be disabled. 8.4 eff ects of a reset a device reset disables the voltage reference by clear- ing bit vren (vrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit vroe (vrcon<6>) and selects the high voltage range by clearing bit vrr (vrcon<5>). the v ref value select bits, vrcon<3:0>, are also cleared. 8.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the ra2 pin if the trisa<2> bit is set and bit vroe is set. enabling the voltage reference output onto the ra2 pin with an input signal present will increase current consumption. connecting ra2 as a digital output with v ref enabled will also increase current consumption. the ra2 pin can be used as a simple d/a output with limited drive capability. due to the limited drive capability, a buffer must be used in conjunction with the voltage reference output for external connections to v ref . figure 8-3 shows an example buffering technique. figure 8-3: voltage reference output buffer example table 8-1: registers associated with voltage reference address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets 9fh vrcon vren vroe vrr vr3 vr2 vr1 vr0 000- 0000 000- 0000 1fh cmcon c2out c1out cis cm2 cm1 cm0 00-- 0000 00-- 0000 85h trisa trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 note 1: r is dependent upon the voltage reference con?uration vrcon<3:0> and vrcon<5>. v ref output voltage reference output impedance r (1) pin ra2 v ref module pic16c662
1996 microchip technology inc. preliminary ds30559a-page 55 pic16c64x & pic16c66x 9.0 special features of the cpu what sets apart a microcontroller from other processors are special circuits to deal with the needs of real-time applications. the pic16c64x & pic16c66x families have a host of such features intended to max- imize system reliability, minimize cost through elimina- tion of external components, provide power saving operating modes and offer code protection. these are: 1. oscillator selection 2. resets power-on reset (por) power-up timer (pwrt) oscillator start-up timer (ost) brown-out reset (bor) parity error reset (per) 3. interrupts 4. watchdog timer (wdt) 5. sleep 6. code protection 7. id locations 8. in-circuit serial programming the pic16c64x & pic16c66x has a watchdog timer which is enabled by a con?uration bit (wdte). it runs off its own rc oscillator for added reliability. there are two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is sta- ble. the other is the power-up timer (pwrt), which provides a ?ed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. circuitry has been provided for checking program memory parity with a reset when an error is indicated. there is also circuitry to reset the device if a brown-out occurs which provides at least a 72 ms reset. with these three functions on-chip, most applications need no external reset circuitry. sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through external reset, watchdog timer wake-up or through an interrupt. several oscillator options are also made available to allow the part to ? the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of con?uration bits are used to select various options. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 56 preliminary 1996 microchip technology inc. 9.1 c on guration bits the con?uration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device con?urations. these bits are mapped in program memory location 2007h. the user will note that address 2007h is beyond the user program memory space. in fact, it belongs to the special test/con?uration memory space (2000h?fffh), which can be accessed only during programming. figure 9-1: configuration word cp1 cp0 cp1 cp0 cp1 cp0 mpeen boden cp1 cp0 pwr te wdte fosc1 fosc0 config address register: 2007h bit13 bit0 bit 13-8 cp1:cp0: code protection bits (2) 5-4: 11 = code protection off 10 = upper half of program memory code protected 01 = upper 3/4th of program memory code protected 00 = all memory is code protected bit 7: mpeen : memory parity error enable 1 = memory parity checking is enabled 0 = memory parity checking is disabled bit 6: boden : brown-out reset enable bit (1) 1 = bor enabled 0 = bor disabled bit 3: pwr te : power-up timer enable bit (1) 1 = pwrt disabled 0 = pwrt enabled bit 2: wdte : watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0 : oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: enabling brown-out reset automatically enables the power-up timer (pwrt) regardless of the value of bit pwr te . ensure the power-up timer is enabled anytime brown-out reset is enabled. 2: all of the cp1:cp0 pairs have to be given the same value to enable the code protection scheme listed.
1996 microchip technology inc. preliminary ds30559a-page 57 pic16c64x & pic16c66x 9.2 oscillator con gurations 9.2.1 oscillator types the pic16cxxx can be operated in four different oscillator modes. the user can program two con?uration bits (fosc1 and fosc0) to select one of these four modes: lp low power crystal xt crystal/resonator hs high speed crystal/resonator rc resistor/capacitor 9.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes a crystal or ceramic resonator is connected to the osc1 and osc2 pins to establish oscillation (figure 9-2). the pic16cxxx oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?ations. when in xt, lp or hs modes, the device can have an external clock source to drive the osc1 pin (figure 9-3). figure 9-2: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) figure 9-3: external clock input operation (hs, xt or lp osc configuration) see table 9-1 or table 9-2 for recommended val- ues of c1 and c2. note: a series resistor may be required for at strip cut crystals. c1 c2 xtal osc2 rs osc1 rf sleep to internal logic pic16cxxx see note clock from ext. system pic16cxxx osc1 osc2 open table 9-1: capacitor selection for ceramic resonators (preliminary) table 9-2: capacitor selection for crystal oscillator (preliminary) ranges tested: mode freq osc1 xt 455 khz 2.0 mhz 4.0 mhz 22 - 100 pf 15 - 68 pf 15 - 68 pf hs 8.0 mhz 16.0 mhz 10 - 68 pf 10 - 22 pf note: recommended values of c1 and c2 are identical to the ranges tested table. higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. resonators used: 455 khz panasonic efo-a455k04b 0.3% 2.0 mhz murata erie csa2.00mg 0.5% 4.0 mhz murata erie csa4.00mg 0.5% 8.0 mhz murata erie csa8.00mt 0.5% 16.0 mhz murata erie csa16.00mx 0.5% all resonators used did not have built-in capacitors. mode freq osc1 osc2 lp 32 khz 200 khz 68 - 100 pf 15 - 30 pf 68 - 100 pf 15 - 30 pf xt 100 khz 2 mhz 4 mhz 68 - 150 pf 15 - 30 pf 15 - 30 pf 150 - 200 pf 15 - 30 pf 15 - 30 pf hs 8 mhz 10 mhz 20 mhz 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf 15 - 30 pf higher capacitance increases the stability of the oscillator but also increases the start-up time. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level spec- i?ation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. crystals used: 32.768 khz epson c-001r32.768k-a 20 ppm 100 khz epson c-2 100.00 kc-p 20 ppm 200 khz std xtl 200.000 khz 20 ppm 2.0 mhz ecs ecs-20-s-2 50 ppm 4.0 mhz ecs ecs-40-s-4 50 ppm 10.0 mhz ecs ecs-100-s-4 50 ppm 20.0 mhz ecs ecs-200-s-4 50 ppm
pic16c64x & pic16c66x ds30559a-page 58 preliminary 1996 microchip technology inc. 9.2.3 external crystal oscillator circuit either a prepackaged oscillator can be used or a simple oscillator circuit with ttl gates can be built. prepack- aged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. figure 9-4 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fun- damental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiome- ter biases the 74as04 in the linear region. this could be used for external oscillator designs. figure 9-4: external parallel resonant crystal oscillator circuit figure 9-5 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental fre- quency of the crystal. the inverter performs a 180-degree phase shift in a series resonant oscillator circuit. the 330 k w resistors provide the negative feed- back to bias the inverters in their linear region. figure 9-5: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 clkin to other devices pic16cxxx 330 k w 74as04 74as04 pic16cxxx clkin to other devices xtal 330 k w 74as04 0.1 m f 9.2.4 rc oscillator for timing insensitive applications the ?c?device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resis- tor (rext) and capacitor (cext) values, and the operat- ing temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal pro- cess parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c compo- nents used. figure 9-6 shows how the r/c combina- tion is connected to the pic16cxxx. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g. 1 m w ), the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend to keep rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or pack- age lead frame capacitance. see characterization data for desired device for rc fre- quency variation from part to part due to normal pro- cess variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). see characterization data for desired device for varia- tion of oscillator frequency due to v dd for given rext/ cext values as well as frequency variation due to oper- ating temperature for given r, c, and v dd values. the oscillator frequency, divided by 4, is available on the osc2/clkout pin, and can be used for test pur- poses or to synchronize other logic (see figure 3-3 for waveform). figure 9-6: rc oscillator mode osc2/clkout cext v dd rext v ss pic16cxxx osc1 fosc/4 internal clock
1996 microchip technology inc. preliminary ds30559a-page 59 pic16c64x & pic16c66x 9.3 reset the pic16cxxx differentiates between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during sleep d) wdt reset (normal operation) e) brown-out reset (bor) f) parity error reset (per) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?eset state?on power-on reset, m clr , wdt reset, brown-out reset, parity error reset, and on mclr reset during sleep. they are not affected by a wdt wake-up, since this is viewed as the resumption of nor- mal operation. t o and pd bits are set or cleared differ- ently in different reset situations as indicated in table 9-4. these bits are used in software to determine the nature of the reset. see table 9-6 for a full descrip- tion of reset states of all registers. a simpli?d block diagram of the on-chip reset circuit is shown in figure 9-7. the mclr reset path has a noise ?ter to detect and ignore small pulses. see table 12-6 for pulse width speci?ation. figure 9-7: simplified block diagram of on-chip reset circuit s r q external reset mclr / v dd osc1/ wdt module v dd rise detect ost/pwrt on-chip (1) rc osc wdt time-out power-on reset ost pwrt chip_reset 10-bit ripple-counter enable ost enable pwrt sleep see table 9-3 for time-out situations. note 1: this is a separate oscillator from the rc oscillator of the clkin pin. brown-out reset boden clkin pin v pp pin 10-bit ripple-counter program memory parity mpeen
pic16c64x & pic16c66x ds30559a-page 60 preliminary 1996 microchip technology inc. 9.4 p o wer -on reset (por), p o wer -up timer (pwr t), oscillator star t-up timer (ost) , b r o wn-out reset (bor) , and p arity err o r reset (per) 9.4.1 power-on reset (por) a power-on reset pulse is generated on-chip when v dd rise is detected (in the range of 1.6v to 1.8v). to take advantage of the por, just tie the mclr pin directly (or through a resistor) to v dd . this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is required. see electrical speci?ations for details. when the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. for additional information, refer to application note an607 power-up trouble shooting. 9.4.2 power-up timer (pwrt) the power-up timer provides a ?ed 72 ms (nominal) delay on power-up only, from por or bor. the power-up timer operates on an internal rc oscillator. the chip is kept in reset as long as pwrt is active. the pwrt delay allows v dd to rise to an acceptable level. a con?uration bit, pw r te can disable (if set) or enable (if cleared or programmed) the power-up timer. the power-up timer should always be enabled when brown-out reset is enabled. the power-up time delay will vary from chip to chip due to v dd , temperature, and process variations. see dc parameters for details. 9.4.3 oscillator start-up timer (ost) the oscillator start-up timer (ost) provides a 1024 oscillator cycle (from osc1 input) delay after the pwrt delay is over. this ensures that the crystal oscillator or resonator has started and stabilized. the ost time-out is invoked only for xt, lp, and hs modes and only on power-on reset or wake-up from sleep. 9.4.4 brown-out reset (bor) pic16c64x & pic16c66x devices have on-chip brown-out reset circuitry. a con?uration bit, boden, can disable (if clear/programmed) or enable (if set) the brown-out reset circuitry. if v dd falls below 4.0v (parameter d005 in es section) for greater than parameter 35 in table 12-6, the brown-out situation will reset the chip. a reset is not guaranteed to occur if v dd falls below 4.0v for less than parameter 35. the chip will remain in brown-out reset until v dd rises above bv dd . the power-up timer will now be invoked and will keep the chip in reset an additional 72 ms. if v dd drops below bv dd while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above bv dd , the power-up timer will execute a 72 ms time delay. the power-up timer should always be enabled when brown-out reset is enabled. figure 9-8 shows typical brown-out situations. figure 9-8: brown-out situations 72 ms bv dd max. bv dd min. v dd internal reset bv dd max. bv dd min. v dd internal reset 72 ms <72 ms 72 ms bv dd max. bv dd min. v dd internal reset
1996 microchip technology inc. preliminary ds30559a-page 61 pic16c64x & pic16c66x 9.4.5 parity error reset (per) pic16c64x & pic16c66x devices have on-chip parity bits that can be used to verify the contents of program memory. parity bits may be useful in applications in order to increase overall reliability of a system. there are two parity bits for each word of program memory. the parity bits are computed on alternating bits of the program word. one computation is per- formed using even parity, the other using odd parity. as a program executes, the parity is veri?d. the even parity bit is xor? with the even bits in the program memory word. the odd parity bit is negated and xor? with the odd bits in the program memory word. when an error is detected, a reset is generated and the per ?g bit in the pcon register is set. this indication can allow software to act on a failure. however, there is no indication of the program memory location of the failure of the program memory. this ?g can only be cleared in software or by a por. the parity array is user selectable during programming. bit7 of the con?uration word located at address 2007h can be programmed (read as '0') to disable parity checking. if left unprogrammed (read as '1'), parity checking is enabled. 9.4.6 time-out sequence on power-up, the time-out sequence is as follows: first pwrt time-out is invoked after por has expired. then the ost is activated. the total time-out will vary based on oscillator con?uration and p w r te bit status. for example, in rc mode with the pwr te bit set (pwrt disabled), there will be no time-out at all. figure 9-9, figure 9-10 and figure 9-11 depict time-out sequences. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then bringing mclr high will begin execution immediately (figure 9-10). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 9-5 shows the reset conditions for some special registers, while table 9-6 shows the reset conditions for all the registers. 9.4.7 power control/status register (pcon) the power control/status register, pcon (address 8eh) has four bits. see figure 4-10 for register. bit0 is bor (brown-out reset). bor is unknown on a power-on-reset. it must initially be set by the user and checked on subsequent resets to see if bor = '0' indicating that a brown-out reset has occurred. the bor status bit is a ?on? care?bit and is not necessar- ily predictable if the brown-out circuit is disabled (by clearing the boden bit in the con?uration word). bit1 is por (power-on reset). it is cleared on a power-on reset and is unaffected otherwise. the user set this bit following a power-on reset. on subsequent resets if por is ?? it will indicate that a power-on reset must have occurred. bit2 is per (parity error reset). it is cleared on a parity error reset and must be set by user software. it will also be set on a power-on reset. bit7 is mpeen (memory parity error enable). this bit re?cts the status of the mpeen bit in con?uration word. it is unaffected by any reset or interrupt. table 9-3: time-out in various situations oscillator con?uration power-up brown-out reset wake-up from sleep pwr te = 0 pwr te = 1 xt, hs, lp 72 ms + 1024 t osc 1024 t osc 72 ms + 1024 t osc 1024 t osc rc 72 ms 72 ms
pic16c64x & pic16c66x ds30559a-page 62 preliminary 1996 microchip technology inc. table 9-4: status bits and their significance table 9-5: initialization condition for special registers per por bor t o pd 10x11 power-on reset x0x0x illegal, t o is set on por x0xx0 illegal, pd is set on por 11011 brown-out reset 11101 wdt reset 11100 wdt wake-up 111uu mclr reset during normal operation 11110 mclr reset during sleep 01111 parity error reset 00xxx illegal, per is set on por 0x0xx illegal, per is set on bor condition program counter status register pcon register power-on reset 000h 0001 1xxx u--- -10x mclr reset during normal operation 000h 000u uuuu u--- -uuu mclr reset during sleep 000h 0001 0uuu u--- -uuu wdt reset 000h 0000 1uuu u--- -uuu wdt wake-up pc + 1 uuu0 0uuu u--- -uuu brown-out reset 000h 0001 1uuu u--- -uu0 parity error reset 000h 0001 1uuu 1--- -0uu interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu u--- -uuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?? note 1: when the wake-up is due to an interrupt and global enable bit, gie is set, the pc is loaded with the inter- rupt vector (0004h) after execution of pc+1.
1996 microchip technology inc. preliminary ds30559a-page 63 pic16c64x & pic16c66x table 9-6: initialization condition for registers register address power-on reset brown-out reset parity error reset mclr reset during: - normal operation - sleep or wdt reset wake up from sleep through: - interrupt - wdt time-out w- xxxx xxxx uuuu uuuu uuuu uuuu indf 00h -- - tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h 0000 0000 0000 0000 pc + 1 (2) status 03h 0001 1xxx 000q quuu (3) uuuq quuu (3) fsr 04h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h --xx 0000 --xu 0000 --uu uuuu portb 06h xxxx xxxx uuuu uuuu uuuu uuuu portc 07h xxxx xxxx uuuu uuuu uuuu uuuu portd (4) 08h xxxx xxxx uuuu uuuu uuuu uuuu porte (4) 09h ---- -xxx ---- -uuu ---- -uuu cmcon 1fh 00-- 0000 00-- 0000 uu-- uuuu pclath 0ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh 0000 000x 0000 000u uuuu uuuu (1) pir1 0ch 00-- ---- 00-- ---- uu-- ---- (1) option 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h --11 1111 --11 1111 --uu uuuu trisb 86h 1111 1111 1111 1111 uuuu uuuu trisc 87h 1111 1111 1111 1111 uuuu uuuu trisd (4) 88h 1111 1111 1111 1111 uuuu uuuu trise (4) 89h 0000 -111 0000 -111 uuuu -uuu pie1 8ch 00-- ---- 00-- ---- uu-- ---- pcon 8eh u--- -qqq u--- -uuu u--- -uuu vrcon 9fh 000- 0000 000- 0000 uuu- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ?? q = value depends on condition. note 1: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 2: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 3: see table 9-5 for reset value for speci? condition. 4: these registers are associated with the parallel slave port and are not implemented on the pic16c641/642.
pic16c64x & pic16c66x ds30559a-page 64 preliminary 1996 microchip technology inc. figure 9-9: time-out sequence on power-up (mclr not tied to v dd ): case 1 figure 9-10: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 9-11: time-out sequence on power-up (mclr tied to v dd ) t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset v dd mclr internal por pwr t time-out ost time-out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwr t time-out ost time-out internal reset
1996 microchip technology inc. preliminary ds30559a-page 65 pic16c64x & pic16c66x figure 9-12: external power-on reset circuit (for slow v dd power-up) figure 9-13: external brown-out protection circuit 1 note 1: external power-on reset circuit is required only if v dd power-up slope is too slow. the diode d helps discharge the capaci- tor quickly when v dd powers down. 2: r < 40 k w is recommended to make sure that voltage drop across r does not vio- late the devices electrical speci?ation. 3: r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capaci- tor c in the event of mclr/ v pp pin breakdown due to electrostatic dis- charge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic16cxxx v dd note 1: this circuit will activate reset when v dd goes below (vz + 0.7v) where vz = zener voltage. 2: internal brown-out reset circuitry should be disabled when using this cir- cuit. 3: resistors should be adjusted for the characteristics of the transistor. v dd 33k 10k 40k v dd mclr pic16cxxx figure 9-14: external brown-out protection circuit 2 note 1: this brown-out circuit is less expensive, albeit less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: internal brown-out reset circuitry should be disabled when using this cir- cuit. 3: resistors should be adjusted for the characteristics of the transistor. v dd r1 r1 + r2 = 0.7 v v dd r2 40k v dd mclr pic16cxxx r1 q1
pic16c64x & pic16c66x ds30559a-page 66 preliminary 1996 microchip technology inc. 9.5 inte rrupts the pic16c641 and pic16c642 have four sources of interrupt, while the pic16c661 and pic16c662 have five sources: external interrupt rb0/int tmr0 over?w interrupt portb change interrupts (pins rb7:rb4) comparator interrupt parallel slave port interrupt (pic16c661/662) the interrupt control register, (intcon), records individual core interrupt requests in ?g bits. it also has various individual enable bits and the global interrupt enable bit. the global interrupt enable bit, gie (intcon<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register. gie is cleared on reset. the ?eturn from interrupt?instruction, retfie , exits the interrupt routine as well as sets the gie bit, which allows any pending interrupt to execute. those interrupts associated with the ?ore?have their ?g and enable bits in the intcon register. the core interrupts are: rb0/int pin interrupt, the rb port change interrupt, and the tmr0 over?w interrupt. the intcon register also contains the peripheral interrupt enable bit, peie. bit peie will enable/mask the periph- eral interrupts (cm and psp) from vectoring when bit peie is set/cleared. flag bits pspif and cmif are contained in special function register pir1. the corresponding interrupt enable bits (pspie and cmie) are contained in special function register pie1. when an interrupt is responded to, the gie is cleared to disable any further interrupt, the return address is pushed into the stack and the pc is loaded with 0004h. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid recur- sive interrupts. for external interrupt events, such as the rb0/int or port rb change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends when the interrupt event occurs (figure 9-16). the latency is the same for one or two cycle instructions. once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ?g bits. the interrupt ?g bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. individual interrupt ?g bits are set regardless of the status of their corresponding mask bit or the gie bit. note 1: individual interrupt ?g bits are set regard- less of the status of their corresponding mask bit or the gie bit. note 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the cpu will execute a nop in the cycle immediately following the instruction which clears the gie bit. the interrupts which were ignored are still pending to be serviced when the gie bit is set again. figure 9-15: interrupt logic rbif rbie t0if t0ie intf inte gie cmie wake-up (if in sleep mode) interrupt cmif to cpu pspie (1) pspif (1) peie note 1: the parallel slave port is implemented on the pic16c661 and pic16c662 only.
1996 microchip technology inc. preliminary ds30559a-page 67 pic16c64x & pic16c66x 9.5.1 rb0/int interrupt the external interrupt on the rb0/int pin is edge trig- gered: either rising if bit intedg (option<6>) is set, or falling, if bit intedg is clear. when a valid edge appears on the rb0/int pin, ?g bit intf (intcon<1>) is set. this interrupt can be enabled/dis- abled by setting/clearing enable bit inte (intcon<4>). the intf bit must be cleared in soft- ware in the interrupt service routine before re-enabling this interrupt. the rb0/int interrupt can wake-up the processor from sleep, if bit inte was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up. see section 9.8 for details on sleep and figure 9-19 for timing of wake-up from sleep through rb0/int interrupt. 9.5.2 tmr0 interrupt an over?w (ffh ? 00h) in the tmr0 register will set the t0if (intcon<2>) bit. the interrupt can be enabled/disabled by setting/clearing t0ie (intcon<5>) bit. for operation of the timer0 module, see section 6.0. 9.5.3 portb interrupt an input change on any bit of portb<7:4> sets ?g bit rbif (intcon<0>). the interrupt can be enabled/dis- abled by setting/clearing enable bit rbie (intcon<4>). for operation of portb (section 5.2). 9.5.4 comparator interrupt see section 7.6 for complete description of the com- parator interrupt. figure 9-16: rb0/int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf ?g (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) 1 4 5 1 note 1: intf ?g is sampled here (every q1). 2: interrupt latency = 3-4 tcy where tcy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in rc oscillator mode. 4: for minimum width of int pulse, refer to ac specs. 5: intf is enabled to be set anytime during the q4-q1 cycles. 2 3
pic16c64x & pic16c66x ds30559a-page 68 preliminary 1996 microchip technology inc. 9.6 conte xt sa ving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key reg- isters during an interrupt e.g. w register and status register. this will have to be implemented in software. example 9-1 stores and restores the status and w registers. the user register, w_temp, must be de?ed in both banks and must be de?ed at the same offset from the bank base address (i.e., w_temp is de?ed at 0x70 - 0x7f in bank 0). the user register, status_temp, must be de?ed in bank 0. example 9-1: stores the w register regardless of current bank stores the status register in bank 0 executes the isr code restores the status (and bank select bit register) restores the w register example 9-1: saving the status and w registers in ram movwf w_temp ; copy w to a temporary register regardless of current bank swapf status,w ; swap status nibbles and place into w register bcf status,rp0 ; change to bank 0 regardless of current bank movwf status_temp ; save status to a temporary register in bank 0 : : (interrupt service routine) : swapf status_temp,w ; swap original status register value into w (restores original bank) movwf status ; restore status register from w register swapf w_temp,f ; swap w_temp nibbles and return value to w_temp swapf w_temp,w ; swap w_temp to w to restore original w value without affecting status
1996 microchip technology inc. preliminary ds30559a-page 69 pic16c64x & pic16c66x 9.7 w atc hdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external com- ponents. the block diagram is shown in figure 9-17. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. this means that the wdt will run, even if the clock on the osc1 and osc2 pins has been stopped, for example, by execution of a sleep instruction. during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation, this is known as a wdt wake-up. the wdt can be permanently disabled by clearing con?uration bit wdte (section 9.1). 9.7.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). the time-out period varies with temper- ature, v dd and process variations from part to part (see dc specs). if longer time-outs are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt, under software control, by writing to the option register. thus, time-out periods of up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the postscaler (if assigned to the wdt) and prevent it from timing out and generating a device reset. the t o bit in the status register will be cleared upon a watchdog timer time-out (wdt reset and wdt wake-up). 9.7.2 wdt programming considerations it should also be taken in account that under worst case conditions (v dd = min., temperature = max., max. wdt prescaler) it may take several seconds before a wdt time-out occurs. note: when the prescaler is assigned to the wdt, always execute a clrwdt instruction before changing the prescale value, other- wise a wdt reset may occur. figure 9-17: watchdog timer block diagram figure 9-18: summary of watchdog timer registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2007h con?. bits mpeen boden (1) cp1 cp0 pwr te (1) wdte fosc1 fosc0 81h option rbpu intedg t0cs t0se psa ps2 ps1 ps0 legend: shaded cells are not used by the watchdog timer. note 1: see figure 9-1 for details of the operation of these bits. from tmr0 clock source (figure 7-6) to tmr0 (figure 7-6) postscaler wdt timer wdt enable bit 0 1 m u x psa 8 - to - 1 mux ps2:ps0 0 1 mux psa wdt time-out note: psa and ps2:ps0 are bits in the option register. 8
pic16c64x & pic16c66x ds30559a-page 70 preliminary 1996 microchip technology inc. 9.8 p o wer -do wn mode (sleep) power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the pd bit in the status register is cleared, the t o bit is set, and the oscillator driver is turned off. the i/o ports maintain the status they had, before the sleep instruction was executed (driving high, low, or hi-impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd , or v ss , with no external circuitry drawing current from the i/o pin and the com- parators and v ref module should be disabled. i/o pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by ?ating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribu- tion from on chip pull-ups on portb should be consid- ered. the mclr pin must be at a logic high level (v ihmc ). 9.8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. any device reset 2. watchdog timer wake-up (if wdt was enabled) 3. interrupt from rb0/int pin, rb port change, or the comparator. the ?st event will reset the device upon wake-up. however the latter two events will wake the device and then resume program execution. the t o and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up is cleared when sleep is invoked. the t o bit is cleared if wdt wake-up occurred. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the correspond- ing interrupt enable bit must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction and then branches to the inter- rupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction. 9.8.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt ?g set, one of the following events will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will com- plete as an nop. therefore, the wdt and wdt postscaler will not be cleared, the t o bit will not be set and pd bit will not be cleared. if the interrupt occurs during or after the execution of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. there- fore, the wdt and wdt postscaler will be cleared, the t o bit will be set and the pd bit will be cleared. even if the ?g bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as an nop. to ensure that the wdt is clear, a clrwdt instruction should be executed before a sleep instruction. figure 9-19: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout(4) int pin intf ?g (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (note 2) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale) this delay will not be there for rc osc mode. 3: gie = '1' assumed. in this case after wake- up, the processor jumps to the interrupt routine. if gie = '0', execution will continue in-line. 4: clkout is not available in these osc modes, but shown here for timing reference.
1996 microchip technology inc. preliminary ds30559a-page 71 pic16c64x & pic16c66x 9.9 code pr otection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veri?ation purposes. 9.10 id locations four memory locations (2000h-2003h) are designated as id locations where the user can store checksum or other code-identi?ation numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. only the least signi?ant 4 bits of the id locations are used. note: microchip does not recommend code protecting windowed devices. 9.11 in-cir cuit serial pr ogramming the pic16cxx microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. this allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. this also allows the most recent ?mware or a custom ?mware to be programmed. the device is placed into a program/verify mode by holding the rb6 and rb7 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming speci?ation). rb6 becomes the programming clock and rb7 becomes the programming data. both rb6 and rb7 are schmitt trigger inputs in this mode. after reset, to place the device into programming/verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic16c6x/7x programming speci?ations (literature #ds30228). a typical in-circuit serial programming connection is shown in figure 9-20. figure 9-20: typical in-circuit serial programming connection external connector signals to normal connections to normal connections pic16cxx v dd v ss mclr /v pp rb6 rb7 +5v 0v v pp clk data i/o v dd
pic16c64x & pic16c66x ds30559a-page 72 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30559a-page 73 pic16c64x & pic16c66x 10.0 instruction set summary each pic16cxx instruction is a 14-bit word divided into an opcode which speci?s the instruction type and one or more operands which further specify the operation of the instruction. the pic16cxx instruction set summary in table 10-2 lists byte-oriented , bit-ori- ented , and literal and control operations. table 10-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e reg- ister designator and 'd' represents a destination desig- nator. the ?e register designator speci?s which ?e register is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is zero, the result is placed in the w register. if 'd' is one, the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an eight or eleven bit constant or literal value. table 10-1: opcode field descriptions the instruction set is highly orthogonal and is grouped into three basic categories: field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0: store result in w, d = 1: store result in ?e register f. default is d = 1 label label name tos top of stack pc program counter pclath program counter high latch gie global interrupt enable bit wdt watchdog timer/counter to time-out bit pd power-down bit dest destination either the w register or the speci?d register ?e location [ ] options ( ) contents ? assigned to < > register bit ?ld ? in the set of i talics user de?ed term (font is courier) byte-oriented operations bit-oriented operations literal and control operations all instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles with the second cycle executed as a nop. one instruc- tion cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 m s. table 10-2 lists the instructions recognized by the mpasm assembler. figure 10-1 shows the three general formats that the instructions can have. all examples use the following format to represent a hexadecimal number: 0xhh where h signi?s a hexadecimal digit. figure 10-1: general format for instructions note: to maintain upward compatibility with future pic16cxx products, do not use the option and tris instructions. byte-oriented ?e register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit ?e register address bit-oriented ?e register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit ?e register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 74 1996 microchip technology inc. 10.1 special functi on register s as sour ce/destination the pic16c64x & pic16c66xs orthogonal instruction set allows read and write of all ?e registers, including special function registers. there are some special situ- ations the user should be aware of: 10.1.1 status as destination if an instruction writes to status, the z, c, and dc bits may be set or cleared as a result of the instruction and overwrite the original data bits written. for example, executing clrf status will clear register status, and then set the z bit leaving 0000 0100b in the reg- ister. 10.1.2 pcl as source or destination read, write or read-modify-write on pcl may have the following results: read pc: pcl ? dest write pcl: pclath ? pch; 8-bit destination value ? pcl read-modify-write: pcl ? alu operand pclath ? pch; 8-bit result ? pcl where pch = program counter high byte (not an addressable register), pclath = program counter high holding latch, dest = destination, wreg or f. 10.1.3 bit manipulation all bit manipulation instructions are done by ?st read- ing the entire register, operating on the selected bit and writing the result back (read-modify-write). the user should keep this in mind when operating on special function registers, such as ports.
1996 microchip technology inc. ds30559a-page 75 pic16c64x & pic16c66x table 10-2: instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0000 dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff 0011 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z t o , pd z t o , pd c,dc,z z note 1: when an i/o register is modi?d as a function of itself ( e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modi?d or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop.
pic16c64x & pic16c66x ds30559a-page 76 1996 microchip technology inc. 10.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k ? (w) status affected: c, dc, z encoding: 11 111x kkkk kkkk description: the contents of the w register are added to the eight bit literal 'k' and the result is placed in the w register . words: 1 cycles: 1 example addlw 0x15 before instruction w = 0x10 after instruction w = 0x25 addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d ? [0,1] operation: (w) + (f) ? (dest) status affected: c, dc, z encoding: 00 0111 dfff ffff description: add the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) ? (w) status affected: z encoding: 11 1001 kkkk kkkk description: the contents of w register are and?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example andlw 0x5f before instruction w = 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .and. (f) ? (dest) status affected: z encoding: 00 0101 dfff ffff description: and the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02
1996 microchip technology inc. ds30559a-page 77 pic16c64x & pic16c66x bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 ? (f) status affected: none encoding: 01 00bb bfff ffff description: bit 'b' in register 'f' is cleared . words: 1 cycles: 1 example bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47 bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 ? (f) status affected: none encoding: 01 01bb bfff ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 01 10bb bfff ffff description: if bit 'b' in register 'f' is '0' then the next instruction is skipped. if bit 'b' is '0' then the next instruction fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2 cycle instruction . words: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address true if flag<1>=1, pc = address false
pic16c64x & pic16c66x ds30559a-page 78 1996 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 01 11bb bfff ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and a nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example here false true btfsc goto flag,1 process_code before instruction pc = address here after instruction if flag<1> = 0, pc = address false if flag<1> = 1, pc = address true call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none encoding: 10 0kkk kkkk kkkk description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two cycle instruction. words: 1 cycles: 2 example here call there before instruction pc = address here after instruction pc = address there tos = address here+1 clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h ? (f) 1 ? z status affected: z encoding: 00 0001 1fff ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z encoding: 00 0001 0000 0011 description: w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example clrw before instruction w = 0x5a after instruction w = 0x00 z=1
1996 microchip technology inc. ds30559a-page 79 pic16c64x & pic16c66x clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? t o 1 ? pd status affected: t o , pd encoding: 00 0000 0110 0100 description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits t o and pd are set. words: 1 cycles: 1 example clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescaler = 0 t o =1 pd =1 comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d ? [0,1] operation: (f ) ? (dest) status affected: z encoding: 00 1001 dfff ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in w. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (dest) status affected: z encoding: 00 0011 dfff ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f' . words: 1 cycles: 1 example decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) - 1 ? (dest); skip if result = 0 status affected: none encoding: 00 1011 dfff ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded. a nop is executed instead making it a two cycle instruction. words: 1 cycles: 1(2) example here decfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt - 1 if cnt = 0, pc = address continue if cnt 1 0, pc = address here+1
pic16c64x & pic16c66x ds30559a-page 80 1996 microchip technology inc. goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none encoding: 10 1kkk kkkk kkkk description: goto is an unconditional branch. the eleven bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two cycle instruction. words: 1 cycles: 2 example goto there after instruction pc = address there incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (dest) status affected: z encoding: 00 1010 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d ? [0,1] operation: (f) + 1 ? (dest), skip if result = 0 status affected: none encoding: 00 1111 dfff ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded. a nop is executed instead making it a two cycle instruction . words: 1 cycles: 1(2) example here incfsz cnt, 1 goto loop continue before instruction pc = address here after instruction cnt = cnt + 1 if cnt= 0, pc = address continue if cnt 1 0, pc = address here +1 iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k ? (w) status affected: z encoding: 11 1000 kkkk kkkk description: the contents of the w register is or?d with the eight bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example iorlw 0x35 before instruction w = 0x9a after instruction w = 0xbf z=1
1996 microchip technology inc. ds30559a-page 81 pic16c64x & pic16c66x iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .or. (f) ? (dest) status affected: z encoding: 00 0100 dfff ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=1 movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k ? (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal 'k' is loaded into w register . the don? cares will assemble as 0s. words: 1 cycles: 1 example movlw 0x5a after instruction w = 0x5a movf move f syntax: [ label ] movf f,d operands: 0 f 127 d ? [0,1] operation: (f) ? (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register f is moved to a destination dependant upon the sta- tus of d. if d = 0, destination is w reg- ister. if d = 1, the destination is ?e register f itself. d = 1 is useful to test a ?e register since status ?g z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z= 1 movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) ? (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register 'f' . words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f
pic16c64x & pic16c66x ds30559a-page 82 1996 microchip technology inc. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop option load option register syntax: [ label ] option operands: none operation: (w) ? option status affected: none encoding: 00 0000 0110 0010 description: the contents of the w register are loaded in the option register. this instruction is supported for code com- patibility with pic16c5x products. since option is a readable/writable register, the user can directly address it. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by set- ting global interrupt enable bit, gie (intcon<7>). this is a two cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k ? (w); tos ? pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example table call table ;w contains table ;offset value ? ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8
1996 microchip technology inc. ds30559a-page 83 pic16c64x & pic16c66x return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none encoding: 00 0000 0000 1000 description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two cycle instruction. words: 1 cycles: 2 example return after interrupt pc = tos rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 1100 1100 c =1 register f c rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d ? [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example rrf reg1,0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 sleep syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? t o , 0 ? pd status affected: t o , pd encoding: 00 0000 0110 0011 description: the power-down status bit, p d is cleared. time-out status bit, t o is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. see power-down mode (sleep) for more details. words: 1 cycles: 1 example: sleep register f c
pic16c64x & pic16c66x ds30559a-page 84 1996 microchip technology inc. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 k 255 operation: k - (w) ? ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2s com- plement method) from the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w= 1 c= ? after instruction w= 1 c = 1; result is positive example 2: before instruction w= 2 c= ? after instruction w= 0 c = 1; result is zero example 3: before instruction w= 3 c= ? after instruction w = 0xff c = 0; result is nega- tive subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d ? [0,1] operation: (f) - (w) ? ( dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2s complement method) w reg- ister from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1: subwf reg1,1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1; result is positive example 2: before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1; result is zero example 3: before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0; result is negative
1996 microchip technology inc. ds30559a-page 85 pic16c64x & pic16c66x swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d ? [0,1] operation: (f<3:0>) ? (dest<7:4>), (f<7:4>) ? (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of regis- ter 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 f 7 operation: (w) ? tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x prod- ucts. since tris registers are read- able and writable, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibility with future pic16cxx products, do not use this instruction. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 k 255 operation: (w) .xor. k ? ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?d with the eight bit literal 'k'. the result is placed in the w regis- ter. words: 1 cycles: 1 example: xorlw 0xaf before instruction w = 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d ? [0,1] operation: (w) .xor. (f) ? ( dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg 1 before instruction reg = 0xaf w = 0xb5 after instruction reg = 0x1a w = 0xb5
pic16c64x & pic16c66x ds30559a-page 86 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 87 pic16c64x & pic16c66x 11.0 development support 11.1 de velopme nt t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster/picmaster ce real-time in-circuit emulator icepic low-cost pic16c5x and pic16cxx in-circuit emulator pro mate ii universal programmer picstart a plus entry-level prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board picdem-3 low-cost demonstration board mpasm assembler mplab-sim software simulator mplab-c (c compiler) fuzzy logic development system (fuzzytech a - mp) 11.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic12c5xx, pic14000, pic16c5x, pic16cxx and pic17cxx families. picmaster is supplied with the mplab ? integrated development environment (ide), which allows editing, ?ake?and download, and source debugging from a single environment. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new microchip micro- controllers. the picmaster emulator system has been designed as a real-time emulation system with advanced fea- tures that are generally found on more expensive devel- opment tools. the pc compatible 386 (and higher) machine platform and microsoft windows a 3.x environ- ment were chosen to best make these features avail- able to you, the end user. a ce compliant version of picmaster is available for european union (eu) countries. 11.3 i cepic: lo w-cost pic16cxx in-cir cuit em ulator icepic is a low-cost in-circuit emulator solution for the microchip pic16c5x and pic16cxx families of 8-bit otp microcontrollers. icepic is designed to operate on pc-compatible machines ranging from 286-at a through pentium ? based machines under windows 3.x environment. icepic features real time, non-intrusive emulation. 11.4 pr o ma te ii: univer sal pr ogrammer the pro mate ii universal programmer is a full-fea- tured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate ii has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate ii can read, verify or pro- gram pic16c5x, pic16cxx, pic17cxx and pic14000 devices. it can also set con?uration and code-protect bits in this mode. 11.5 p icst ar t plus entr y le vel de velopment system the picstart programmer is an easy-to-use, low- cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. mplab integrated development environment software makes using the programmer simple and ef?ient. picstart plus is not recommended for production programming. picstart plus supports all pic12c5xx, pic14000, pic16c5x, pic16cxx and pic17cxx devices with up to 40 pins. larger pin count devices such as the pic16c923 and pic16c924 may be supported with an adapter socket. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 88 preliminary 1996 microchip technology inc. 11.6 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrol- lers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate ii or picstart-16b programmer, and easily test ?m- ware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional pro- totype area is available for the user to build some addi- tional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 11.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate ii pro- grammer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding addi- tional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 inter- face, push-button switches, a potentiometer for simu- lated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connec- tion to an lcd module and a keypad. 11.8 picdem-3 lo w-cost pic16cxx demonstration boar d the picdem-3 is a simple demonstration board that supports the pic16c923 and pic16c924 in the plcc package. it will also support future 44-pin plcc microcontrollers with a lcd module. all the neces- sary hardware and software is included to run the basic demonstration programs. the user can pro- gram the sample microcontrollers provided with the picdem-3 board, on a pro mate ii program- mer or picstart plus with an adapter socket, and easily test ?mware. the picmaster emulator may also be used with the picdem-3 board to test ?m- ware. additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). some of the features include an rs-232 interface, push-button switches, a potenti- ometer for simulated analog input, a thermistor and separate headers for connection to an external lcd module and a keypad. also provided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments, that is capable of displaying time, temperature and day of the week. the picdem-3 provides an addi- tional rs-232 interface and windows 3.1 software for showing the demultiplexed lcd signals on a pc. a simple serial interface allows the user to construct a hardware demultiplexer for the lcd signals. picdem- 3 will be available in the 3rd quarter of 1996. 11.9 mplab integrated de velopment en vir onment softwar e the mplab ide software brings an ease of software development previously unseen in the 8-bit microcon- troller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or ?? one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 11.10 assemb ler (mp asm) the mpasm universal macro assembler is a pc- hosted symbolic assembler. it supports all microcon- troller series including the pic12c5xx, pic14000, pic16c5x, pic16cxx, and pic17cxx families. mpasm offers full featured macro capabilities, condi- tional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers.
1996 microchip technology inc. preliminary ds30559a-page 89 pic16c64x & pic16c66x mpasm allows full symbolic debugging from the micro chip universal emulator system (picmaster). mpasm has the following features to assist in develop- ing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability. produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. 11.11 s oftware sim ulator (mplab-sim) the mplab-sim software simulator allows code development in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/ output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mplab-sim fully supports symbolic debugging using mplab-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code out- side of the laboratory environment making it an excel- lent multi-project software development tool. 11.12 c compiler ( mplab-c) the mplab-c code development system is a com- plete ? compiler and integrated development environ- ment for microchips pic16/17 family of microcontrollers. the compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler pro- vides symbol information that is compatible with the mplab ide memory display (picmaster emulator software versions 1.13 and later). 11.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic development tool is avail- able in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for imple- menting more complex systems. both versions include microchips fuzzy lab ? demon- stration board for hands-on experience with fuzzy logic systems implementation. 11.14 mp-drivew a y ? ?application code generator mp-driveway is an easy-to-use windows-based appli- cation code generator. with mp-driveway you can visually con?ure all the peripherals in a pic16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in c language. the output is fully compatible with micro- chips mplab-c c compiler. the code produced is highly modular and allows easy integration of your own code. mp-driveway is intelligent enough to maintain your code through subsequent code generation. 11.15 seev al a ev aluation and pr ogramming system the seeval seeprom designers kit supports all microchip 2-wire and 3-wire serial eeproms. the kit includes everything necessary to read, write, erase or program special features of any microchip seeprom product including smart serials ? and secure serials. the total endurance ? disk is included to aid in trade- off analysis and reliability calculations. the total kit can signi?antly reduce time-to-market and result in an optimized system. 11.16 t ruegaug e a intellig ent batter y mana g ement the truegauge development tool supports system development with the mta11200b truegauge intelli- gent battery management ic. system design veri?a- tion can be accomplished before hardware prototypes are built. user interface is graphically-oriented and measured data can be saved in a ?e for exporting to microsoft excel. 11.17 k ee l oq a ev aluation and pr ogramming t ools k ee l oq evaluation and programming tools support microchips hcs secure data products. the hcs eval- uation kit includes an lcd display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters.
pic16c64x & pic16c66x ds30559a-page 90 preliminary 1996 microchip technology inc. table 11-1: development tools from microchip product ** mplab ? integrated development environment mplab ? c compiler mp-driveway applications code generator fuzzytech a -mp explorer/edition fuzzy logic dev. tool *** picmaster a / picmaster-ce in-circuit emulator icepic low-cost in-circuit emulator ****pro mate ? ii universal microchip programmer picstart a lite ultra low-cost dev. kit picstart a plus low-cost universal dev. kit pic12c508, 509 sw007002 sw006005 em167015/ em167101 dv007003 dv003001 pic14000 sw007002 sw006005 em147001/ em147101 dv007003 dv003001 pic16c52, 54, 54a, 55, 56, 57, 58a sw007002 sw006005 sw006006 dv005001/ dv005002 em167015/ em167101 em167201 dv007003 dv162003 dv003001 pic16c554, 556, 558 sw007002 sw006005 dv005001/ dv005002 em167033/ em167113 ? dv007003 dv003001 pic16c61 sw007002 sw006005 sw006006 dv005001/ dv005002 em167021/ n/a em167205 dv007003 dv162003 dv003001 pic16c62, 62a, 64, 64a sw007002 sw006005 sw006006 dv005001/ dv005002 em167025/ em167103 em167203 dv007003 dv162002 dv003001 pic16c620, 621, 622 sw007002 sw006005 sw006006 dv005001/ dv005002 em167023/ em167109 em167202 dv007003 dv162003 dv003001 pic16c63, 65, 65a, 73, 73a, 74, 74a sw007002 sw006005 sw006006 dv005001/ dv005002 em167025/ em167103 em167204 dv007003 dv162002 dv003001 pic16c641, 642, 661, 662* sw007002 sw006005 em167035/ em167105 ? dv007003 dv162002 dv003001 pic16c71 sw007002 sw006005 sw006006 dv005001/ dv005002 em167027/ em167105 em167205 dv007003 dv162003 dv003001 pic16c710, 711 sw007002 sw006005 sw006006 dv005001/ dv005002 em167027/ em167105 dv007003 dv162003 dv003001 pic16c72 sw007002 sw006005 sw006006 em167025/ em167103 dv007003 dv162002 dv003001 pic16f83 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 dv007003 dv162003 dv003001 pic16c84 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 em167206 dv007003 dv162003 dv003001 pic16f84 sw007002 sw006005 sw006006 dv005001/ dv005002 em167029/ em167107 dv007003 dv162003 dv003001 pic16c923, 924* sw007002 sw006005 sw006006 dv005001/ dv005002 em167031/ em167111 dv007003 dv003001 pic17c42, 42a, 43, 44 sw007002 sw006005 sw006006 dv005001/ dv005002 em177007/ em177107 dv007003 dv003001 *contact microchip technology for availability date **mplab integrated development environment includes mplab-sim simulator and mpasm assembler ***all picmaster and picmaster-ce ordering part numbers above include pro mate ii programmer ****pro mate socket modules are ordered separately. see development systems ordering guide for speci? ordering part numbers product truegauge a development kit seeval a designers kit hopping code security programmer kit hopping code security eval/demo kit all 2 wire and 3 wire serial eeprom's n/a dv243001 n/a n/a mta11200b dv114001 n/a n/a n/a hcs200, 300, 301 * n/a n/a pg306001 dm303001
1996 microchip technology inc. preliminary ds30559a-page 91 pic16c64x & pic16c66x 12.0 electrical specifications absolute maximum ratings ? ambient temperature under bias ............................................................................................................. ?0 to +125 c storage temperature ............................................................................................................................... ?5 to +150 c voltage on any pin with respect to v ss (except v dd and mclr ) .....................................................?.3v to v dd + 0.3v voltage on v dd with respect to v ss ................................................................................................................ 0 to +7.5v voltage on mclr with respect to v ss (note 2) .................................................................................................0 to +14v total power dissipation (note 1) ...............................................................................................................................1.0w maximum current out of v ss pin ..........................................................................................................................300 ma maximum current into v dd pin .............................................................................................................................250 ma input clamp current, i ik (v i <0 or v i > v dd ) ....................................................................................................................... 20 ma output clamp current, i ok (vo <0 or vo>v dd ) ................................................................................................................ 20 ma maximum output current sunk by any i/o pin ........................................................................................................25 ma maximum output current sourced by any i/o pin...................................................................................................25 ma maximum current sunk by porta, portb, and porte (combined) (note 2) ...................................................200 ma maximum current sourced by porta, portb, and porte (combined) (note 2) ..............................................200 ma maximum current sunk by portc and portd (combined) (note 2)..................................................................200 ma maximum current sourced by portc and portd (combined) (note 2).............................................................200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ) note 2: portd and porte are not implemented on the pic16c641 and pic16c642. table 12-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ? notice : stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. osc pic16c641-04 pic16c642-04 pic16c661-04 pic16c662-04 pic16c641-10 pic16c642-10 pic16c661-10 pic16c662-10 pic16c641-20 pic16c642-20 pic16c661-20 pic16c662-20 pic16lc641-04 pic16lc642-04 pic16lc661-04 pic16lc662-04 jw devices rc v dd : 4.0v to 6.0v i dd : 5 ma max. @ 5.5v i pd : 21 m a max. @ 4.0v freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. @ 5.5v i pd : 1.5 m a typ. @ 4.0v freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. @ 5.5v i pd : 1.5 m a typ. @ 4.0v freq: 4.0 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. @ 3.0v i pd : 0.9 m a typ. @ 3.0v freq: 4.0 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. @ 5.5v i pd : 21 m a max. @ 4.0v freq: 4.0 mhz max. xt v dd : 4.0v to 6.0v i dd : 5 ma max. @ 5.5v i pd : 21 m a max. @ 4.0v freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. @ 5.5v i pd : 1.5 m a typ. @ 4.0v freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 2.7 ma typ. @ 5.5v i pd : 1.5 m a typ. @ 4.0v freq: 4.0 mhz max. v dd : 3.0v to 6.0v i dd : 2.0 ma typ. @ 3.0v i pd : 0.9 m a typ. @ 3.0v freq: 4.0 mhz max. v dd : 4.0v to 6.0v i dd : 5 ma max. @ 5.5v i pd : 21 m a max. @ 4.0v freq: 4.0 mhz max. hs v dd : 4.5v to 5.5v i dd : 13.5 ma typ. @ 5.5v i pd : 1.5 m a typ. @ 4.5v freq: 4.0 mhz max. v dd : 4.5v to 5.5v i dd : 30 ma max. @ 5.5v i pd : 1.5 m a typ. @ 4.5v freq: 10 mhz max. v dd : 4.5v to 5.5v i dd : 30 ma max. @ 5.5v i pd : 1.5 m a typ. @ 4.5v freq: 20 mhz max. do not use in hs mode v dd : 4.5v to 5.5v i dd : 30 ma max. @ 5.5v i pd : 1.5 m a typ. @ 4.5v freq: 10 mhz max. lp v dd : 4.0v to 6.0v i dd : 52.5 m a typ. @ 32 khz, 4.0v i pd : 0.9 m a typ. @ 4.0v freq: 200 khz max. do not use in lp mode do not use in lp mode v dd : 3.0v to 6.0v i dd : 48 m a max. @ 32 khz, 3.0v i pd : 5.0 m a max. @ 3.0v freq: 200 khz max. v dd : 3.0v to 6.0v i dd : 48 m a max. @ 32 khz, 3.0v i pd : 5.0 m a max. @ 3.0v freq: 200 khz max. the shaded sections indicate oscillator selections which are tested for functionality, but not for min/max speci?ations. it is recommended that the user select the device type that ensures the speci?ations required. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 92 preliminary 1996 microchip technology inc. 12.1 dc characteristics: pic16c641/642/661/662-04 (commercial, industrial, automotive) pic16c641/642/661/662-10 (commercial, industrial, automotive) pic16c641/642/661/662-20 (commercial, industrial, automotive) standard operating conditions (unless otherwise stated) operating temperature ?0 c t a +85 c for industrial, 0 c t a +70 c commercial, and ?0 c t a +125 c automotive param no. sym characteristic min typ? max units conditions d001 d001a v dd supply voltage 4.0 4.5 6.0 5.5 v v xt, rc and lp osc con?uration hs osc con?uration d002* v dr ram data retention voltage (1) 1.5 v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section on power-on reset for details d005 v bor brown-out reset voltage 3.7 3.7 4.0 4.0 4.3 4.4 v v boden con?uration bit is clear automotive d010 i dd supply current (2) 2.7 5 ma xt and rc osc con?uration f osc = 4 mhz, v dd = 5.5v, wdt disabled (4) d010a 35 70 m a lp osc con?uration, pic16c64x & pic16c66x-04 only f osc = 32 khz, v dd = 4.0v, wdt disabled d013 13.5 30 ma hs osc con?uration f osc = 20 mhz, v dd = 5.5v, wdt disabled module differential current (5) d015 d i bor brown-out reset current 350 425 m a boden bit is clear, v dd = 5.0v d016 d i comp comparator current for each comparator 100 m av dd = 4.0v d017 d i vref v ref current 300 m av dd = 4.0v d021 d i wdt wdt current 6.0 20 25 m a m a v dd = 4.0v automotive d021 i pd power-down current (3) 1.5 2.5 21 24 m a m a v dd = 4.0v, wdt disabled automotive * these parameters are characterized but not tested. ? data in ?yp?column is at 5.0v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated ? , pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in k w . 5: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
1996 microchip technology inc. preliminary ds30559a-page 93 pic16c64x & pic16c66x 12.2 dc characteristics: pic16lc641/642/661/662-04 (commercial, industrial) standard operating conditions (unless otherwise stated) operating temperature ?0 c t a +85 c for industrial and 0 c t a +70 c commercial param no. sym characteristic min typ? max units conditions d001 v dd supply voltage 3.0 6.0 v xt, rc, and lp osc con?uration d002* v dr ram data retention voltage (1) 1.5 v device in sleep mode d003 v por v dd start voltage to ensure internal power-on reset signal ? ss v see section on power-on reset for details d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 v/ms see section on power-on reset for details d005 v bor brown-out reset voltage 3.7 4.0 4.3 v boden con?uration bit is clear d010 d010a i dd supply current (2) 2.0 22.5 3.8 48 ma m a xt and rc osc con?uration f osc = 4.0 mhz, v dd = 3.0v, wdt disabled (4) lp osc con?uration f osc = 32 khz, v dd = 3.0v, wdt disabled module differential current (5) d015 d i bor brown-out reset current 350 425 m a boden bit is clear, v dd = 5.0v d016 d i comp comparator current for each comparator 100 m av dd = 3.0v d017 d i vref v ref current 300 m av dd = 3.0v d021 d i wdt wdt current 6.0 20 m av dd = 3.0v d021 i pd power-down current (3) 0.9 5 m av dd = 3.0v, wdt disabled * these parameters are characterized but not tested. ? data in ?yp?column is at 5.0v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1=external square wave, from rail to rail; all i/o pins tristated, pulled to v dd , mclr = v dd ; wdt enabled/disabled as speci?d. 3: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd or v ss . 4: for rc osc con?uration, current through rext is not included. the current through the resistor can be estimated by the formula ir = v dd /2rext (ma) with rext in k w . 5: the d current is the additional current consumed when this peripheral is enabled. this current should be added to the base i dd or i pd measurement.
pic16c64x & pic16c66x ds30559a-page 94 preliminary 1996 microchip technology inc. 12.3 dc characteristics: pic16c641/661 (commercial, industrial, automotive) pic16c642/662 (commercial, industrial, automotive) pic16lc641/661 (commercial, industrial) pic16lc642/662 (commercial, industrial) standard operating conditions (unless otherwise stated) operating temperature ?0 c t a +85 c for industrial, 0 c t a +70 c commercial, and ?0 c t a +125 c automotive operating voltage v dd range as described in dc spec section 12.1 and 12.2 param no. sym characteristic min typ ? max unit conditions v il input low voltage i/o ports d030 with ttl buffer v ss v ss - - 0.15v dd 0.8v v v for entire v dd range 4.5v v dd 5.5v d031 with schmitt trigger input v ss - 0.2v dd v d032 mclr , ra4/t0cki,osc1 (in rc mode) vss - 0.2v dd v (1) d033 osc1 (xt and hs modes) vss - 0.3v dd v osc1 (lp modes) vss - 0.6v dd -1.0 v v ih input high voltage i/o ports d040 with ttl buffer 2.0 - v dd v d041 with schmitt trigger input 0.25v dd to 0.8v -v dd v d042 mclr ra4/t0cki 0.8v dd -v dd v d043 d043a osc1 (xt, hs, lp modes) osc1 (rc mode) 0.7v dd 0.9v dd - - v dd - v v (1) d070 i purb portb weak pull-up current 50 200 400 m av dd = 5.0v, v pin = v ss i il input leakage current (2,3) i/o ports (except porta) -- 1.0 m av ss v pin v dd , pin at hi-impedance d060 porta - - 0.5 m a vss v pin v dd , pin at hi-impedance d061 ra4/t0cki - - 1.0 m a vss v pin v dd d063 osc1, mclr -- 5.0 m a vss v pin v dd , xt, hs and lp osc con?uration v ol output low voltage d080 i/o ports - - 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 to +85 c - - 0.6 v i ol = 7.0 m a, v dd = 4.5v, +125 c d083 osc2/clkout - - 0.6 v i ol = 1.6 ma, v dd = 4.5v, -40 to +85 c (rc only) - - 0.6 v i ol = 1.2 ma, v dd = 4.5v, +125 c * these parameters are characterized but not tested. ? data in ?yp?column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic16c64x & pic16c66x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the speci?d levels repre- sent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin.
1996 microchip technology inc. preliminary ds30559a-page 95 pic16c64x & pic16c66x v oh output high voltage (3) d090 i/o ports (except ra4) v dd -0.7 - - v i oh = -3.0 ma, v dd = 4.5v, -40 to +85 c v dd -0.7 - - v i oh = -2.5 ma, v dd = 4.5v, +125 c d092 osc2/clkout v dd -0.7 - - v i oh = -1.3 ma, v dd =4.5v, -40 to +85 c (rc only) v dd -0.7 - - v i oh = -1.0 ma, v dd = 4.5v, +125 c capacitive loading specs on output pins d100 c osc2 osc2 pin - - 15 pf in xt, hs and lp modes when external clock used to drive osc1. d101 c io all i/o pins/osc2 (in rc mode) - - 50 pf standard operating conditions (unless otherwise stated) operating temperature ?0 c t a +85 c for industrial, 0 c t a +70 c commercial, and ?0 c t a +125 c automotive operating voltage v dd range as described in dc spec section 12.1 and 12.2 param no. sym characteristic min typ ? max unit conditions * these parameters are characterized but not tested. ? data in ?yp?column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator con?uration, the osc1 pin is a schmitt trigger input. it is not recommended that the pic16c64x & pic16c66x be driven with external clock in rc mode. 2: the leakage current on the mclr pin is strongly dependent on applied voltage level. the speci?d levels repre- sent normal operating conditions. higher leakage current may be measured at different input voltages. 3: negative current is de?ed as coming out of the pin.
pic16c64x & pic16c66x ds30559a-page 96 preliminary 1996 microchip technology inc. table 12-2: comparator specifications operating conditions: 3.0v < v dd < 6.0v, -40?c < t a < +125?c, unless otherwise stated. current consumption is spec- i?d in table 12-1. table 12-3: voltage reference specifications operating conditions: 3.0v < v dd < 6.0v, -40 c < t a < +125 c, unless otherwise stated. current consumption is spec- i?d in table 12-1. characteristics sym min typ max units comments input offset voltage - 5.0 10 mv input common mode voltage* 0 - v dd - 1.5 v cmrr* 35 - - db response time (1)* - 150 400 600 ns ns pic16c64x/66x pic16lc64x/66x comparator mode change to output valid* -- 10 m s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd - 1.5)/2 while the other input transitions from v ss to v dd . characteristics sym min typ max units comments resolution v dd /24 - v dd /32 lsb absolute accuracy - - - - 1/4 1/2 lsb lsb low range (vrr = 1) high range (vrr = 0) unit resistor value (r)* - 2k - w figure 8-2 settling time (1) * - - 10 m s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from 0000 to 1111 .
1996 microchip technology inc. preliminary ds30559a-page 97 pic16c64x & pic16c66x 12.4 timing p arameter symbology the timing parameter symbols have been created with one of the following formats: figure 12-1: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp ck clkout osc osc1 io i/o port t0 t0cki mc mclr uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance v dd /2 c l r l pin pin v ss v ss c l r l = 464 w c l = 50 pf for all pins except osc2 15 pf for osc2 output load condition 1 load condition 2
pic16c64x & pic16c66x ds30559a-page 98 preliminary 1996 microchip technology inc. 12.5 timing dia grams and speci cations figure 12-2: external clock timing table 12-4: external clock timing requirements param no. sym characteristic min typ? max units conditions fosc external clkin frequency (1) dc 4 mhz xt and rc osc mode, v dd = 5.0v dc 20 mhz hs osc mode dc 200 khz lp osc mode oscillator frequency (1) dc 4 mhz rc osc mode, v dd = 5.0v 0.1 4 mhz xt osc mode 4 20 mhz hs osc mode 5 200 khz lp osc mode 1 tosc external clkin period (1) 250 ns xt and rc osc mode 50 ns hs osc mode 5 m s lp osc mode oscillator period (1) 250 ns rc osc mode 250 10,000 ns xt osc mode 50 250 ns hs osc mode 5 m s lp osc mode 2t cy instruction cycle time (1) 200 dc ns t cy = f osc /4 3* tosl, tosh external clock in (osc1) high or low time 100 ns xt osc mode 2.5 m s lp osc mode 15 ns hs osc mode 4* tosr, tosf external clock in (osc1) rise or fall time 25 ns xt osc mode 50 ns lp osc mode 15 ns hs osc mode * these parameters are characterized but not tested. ? data in ?yp?column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time-base period. all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?in.?values with an external clock applied to the osc1 pin. when an external clock input is used, the ?ax.?cycle time limit is ?c?(no clock) for all devices. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
1996 microchip technology inc. preliminary ds30559a-page 99 pic16c64x & pic16c66x figure 12-3: clkout and i/o timing table 12-5: clkout and i/o timing requirements parameter no. sym characteristic min typ? max units conditions 10* tosh2ckl osc1 - to clkout 75 200 ns note 1 11* tosh2ckh osc1 - to clkout - 75 200 ns note 1 12* tckr clkout rise time 35 100 ns note 1 13* tckf clkout fall time 35 100 ns note 1 14* tckl2iov clkout to port out valid 0.5t cy + 20 ns note 1 15* tiov2ckh port in valid before clkout - t osc + 200 ns note 1 16* tckh2ioi port in hold after clkout - 0 ns note 1 17* tosh2iov osc1 - (q1 cycle) to port out valid 50 150 ns 18* tosh2ioi osc1 - (q2 cycle) to port input invalid (i/o in hold time) pic16c64x/66x 100 ns pic16lc64x/66x 200 ns 19* tiov2osh port input valid to osc1 - (i/o in setup time) 0 ns 20* tior port output rise time pic16c64x/66x 10 40 ns pic16lc64x/66x 80 ns 21* tiof port output fall time pic16c64x/66x 10 40 ns pic16lc64x/66x 80 ns 22??* tinp int pin high or low time t cy ns 23??* trbp rb7:rb4 change int high or low time t cy ns * these parameters are characterized but not tested. ? data in ?yp?column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. ?? these parameters are asynchronous events not related to any internal clock edges. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . 22 23 note: see figure 12-1 for load conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value
pic16c64x & pic16c66x ds30559a-page 100 preliminary 1996 microchip technology inc. figure 12-4: reset, watchdog timer, oscillator start-up timer, and power-up timer timing figure 12-5: brown-out reset timing table 12-6: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements parameter no. sym characteristic min typ? max units conditions 30 tmcl mclr pulse width (low) 2 m sv dd = 5v, -40?c to +125?c 31* twdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40?c to +125?c 32 tost oscillation start-up timer period 1024t osc t osc = osc1 period 33* tpwrt power up timer period 28 72 132 ms v dd = 5v, -40?c to +125?c 34 t ioz i/o hi-impedance from mclr low or watchdog timer reset 2.1 m s 35 t bor brown-out reset pulse width 100 m sv dd b vdd (d005) 36 t per parity error reset tbd m s * these parameters are characterized but not tested. ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por pwr t timeout osc timeout internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 parity error reset 36 v dd bv dd 35
1996 microchip technology inc. preliminary ds30559a-page 101 pic16c64x & pic16c66x figure 12-6: timer0 clock timing table 12-7: timer0 clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ns with prescaler 10 ns 41* tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ns with prescaler 10 ns 42* tt0p t0cki period t cy + 40 n ns n = prescale value (1, 2, 4, ? 256) * these parameters are characterized but not tested. ? data in ?yp?column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. 41 42 40 ra4/t0cki tmr0
pic16c64x & pic16c66x ds30559a-page 102 preliminary 1996 microchip technology inc. figure 12-7: parallel slave port timing (pic16c661 and pic16c662) table 12-8: parallel slave port requirements (pic16c661 and pic16c662) parameter no. sym characteristic min typ? max units conditions 62 tdtv2wrh data in valid before wr - or cs - (setup time) 20 ns 63* twrh2dti wr - or cs - to data?n invalid (hold time) pic16c66x 20 ns pic16lc66x 35 ns 64 trdl2dtv rd and cs to data?ut valid 80 ns 65 trdh2dti rd - or cs to data?ut invalid 10 30 ns ? data in "typ" column is at 5v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 12-1 for load conditions re2/cs re0/rd re1/wr rd7:rd0 62 63 64 65
1996 microchip technology inc. preliminary ds30559a-page 103 pic16c64x & pic16c66x 13.0 device characterization information not available at this time. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 104 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 105 pic16c64x & pic16c66x 14.0 packaging information package type: 28-lead skinny plastic dual in-line (sp) - 300 mil package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 3.632 4.572 0.143 0.180 a1 0.381 0.015 a2 3.175 3.556 0.125 0.140 b 0.406 0.559 0.016 0.022 b1 1.016 1.651 typical 0.040 0.065 typical b2 0.762 1.016 4 places 0.030 0.040 4 places b3 0.203 0.508 4 places 0.008 0.020 4 places c 0.203 0.331 typical 0.008 0.013 typical d 34.163 35.179 1.385 1.395 d1 33.020 33.020 bsc 1.300 1.300 bsc e 7.874 8.382 0.310 0.330 e1 7.112 7.493 0.280 0.295 e1 2.540 2.540 typical 0.100 0.100 typical ea 7.874 7.874 bsc 0.310 0.310 bsc eb 8.128 9.906 0.320 0.390 l 3.175 3.683 0.125 0.145 s 0.584 1.220 0.023 0.048 pin no. 1 indicator area e1 e s d d1 base plane seating plane a1 a2 a l e1 c e a e b detail a detail a b2 b1 b b3 this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 106 preliminary 1996 microchip technology inc. package type: 28-lead plastic small outline (so) - wide, 300 mil body package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 17.703 18.085 0.697 0.712 e 7.416 7.595 0.292 0.299 e 1.270 1.270 bsc 0.050 0.050 bsc h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 cp 0.102 0.004 a h x 45 c l b e chamfer h x 45 e h cp seating plane base plane d a1 a pin no. 1 indicator area
1996 microchip technology inc. preliminary ds30559a-page 107 pic16c64x & pic16c66x package type: 28-lead ceramic side brazed dual in-line with window (jw) (300 mil) package group: ceramic side brazed dual in-line (cer) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.937 5.030 0.155 0.198 a1 1.016 1.524 0.040 0.060 a2 2.921 3.506 0.115 0.138 a3 1.930 2.388 0.076 0.094 b 0.406 0.508 0.016 0.020 b1 1.219 1.321 typical 0.048 0.052 c 0.228 0.305 typical 0.009 0.012 d 35.204 35.916 1.386 1.414 d1 32.893 33.147 bsc 1.295 1.305 e 7.620 8.128 0.300 0.320 e1 7.366 7.620 0.290 0.300 e1 2.413 2.667 typical 0.095 0.105 ea 7.366 7.874 bsc 0.290 0.310 eb 7.594 8.179 0.299 0.322 l 3.302 4.064 0.130 0.160 s 1.143 1.397 0.045 0.055 s1 0.533 0.737 0.021 0.029 e1 e s base plane seating plane b1 b s1 d l a1 a2 a3 a e1 pin no. 1 indicator area d1 a c e a e b
pic16c64x & pic16c66x ds30559a-page 108 preliminary 1996 microchip technology inc. package type: 40-lead ceramic dual in-line with window (jw) - (600 mil) package group: ceramic cerdip dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.318 5.715 0.170 0.225 a1 0.381 1.778 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.435 52.705 2.025 2.075 d1 48.260 48.260 bsc 1.900 1.900 bsc e 15.240 15.875 0.600 0.625 e1 12.954 15.240 0.510 0.600 e1 2.540 2.540 bsc 0.100 0.100 bsc ea 14.986 16.002 typical 0.590 0.630 typical eb 15.240 18.034 0.600 0.710 l 3.175 3.810 0.125 0.150 s 1.016 2.286 0.040 0.090 s1 0.381 1.778 0.015 0.070 a c e a e b pin no. 1 indicator area e1 e s d b1 b d1 s1 a1 a3 a a2 l e1 seating plane base plane
1996 microchip technology inc. preliminary ds30559a-page 109 pic16c64x & pic16c66x package type: 40-lead plastic dual in-line (p) - 600 mil package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 5.080 0.200 a1 0.381 0.015 a2 3.175 4.064 0.125 0.160 b 0.355 0.559 0.014 0.022 b1 1.270 1.778 typical 0.050 0.070 typical c 0.203 0.381 typical 0.008 0.015 typical d 51.181 52.197 2.015 2.055 d1 48.260 48.260 bsc 1.900 1.900 bsc e 15.240 15.875 0.600 0.625 e1 13.462 13.970 0.530 0.550 e1 2.489 2.591 typical 0.098 0.102 typical ea 15.240 15.240 bsc 0.600 0.600 bsc eb 15.748 17.272 0.620 0.680 l 2.921 3.683 0.115 0.145 s 1.270 0.050 s1 0.508 0.020 pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 c e a e b
pic16c64x & pic16c66x ds30559a-page 110 preliminary 1996 microchip technology inc. package type: 44-lead plastic leaded chip carrier (l) - square package group: plastic leaded chip carrier (plcc) symbol millimeters inches min max notes min max notes a 4.191 4.572 0.165 0.180 a1 2.413 2.921 0.095 0.115 d 17.399 17.653 0.685 0.695 d1 16.510 16.663 0.650 0.656 d2 15.494 16.002 0.610 0.630 d3 12.700 12.700 bsc 0.500 0.500 bsc e 17.399 17.653 0.685 0.695 e1 16.510 16.663 0.650 0.656 e2 15.494 16.002 0.610 0.630 e3 12.700 12.700 bsc 0.500 0.500 bsc cp 0.102 0.004 lt 0.203 0.381 0.008 0.015 s 0.177 .007 b d-e -a- 0.254 d 1 d 3 3 3 -c- -f- -d- 4 9 8 -b- -e- s 0.177 .007 a f-g s s e e 1 -h- -g- 6 2 3 .010 max 1.524 .060 10 2 11 0.508 .020 1.651 .065 r 1.14/0.64 .045/.025 r 1.14/0.64 .045/.025 1.651 .065 0.508 .020 -h- 11 0.254 .010 max 6 min 0.812/0.661 .032/.026 3 -c- 0.64 .025 min 5 0.533/0.331 .021/.013 0.177 .007 m a f-g s , d-e s 1.27 .050 2 sides a s 0.177 .007 b a s d 3 /e 3 d 2 0.101 .004 0.812/0.661 .032/.026 s 0.38 .015 f-g 4 s 0.38 .015 f-g e 2 d -h- a 1 seating plane 2 sides n pics d/2 e/2
1996 microchip technology inc. preliminary ds30559a-page 111 pic16c64x & pic16c66x package type: 44-lead thin plastic quad flatpack (pt/tq) - 10x10x1 mm body 1.0/0.10 mm lead form package group: plastic tqfp symbol millimeters inches min max notes min max notes a 0 7 0 7 a 1.200 0.047 a1 0.050 0.150 0.002 0.006 a2 0.950 1.050 0.037 0.041 b 0.300 0.450 0.012 0.018 b1 0.300 0.400 0.012 0.016 d 12.0 12.0 bsc 0.472 0.0472 bsc d1 10.0 10.0 bsc 0.394 0.394 bsc e 12.0 12.0 bsc 0.472 0.472 bsc e1 10.0 10.0 bsc 0.394 0.394 bsc e 0.8 0.8 bsc 0.031 0.031 bsc l 0.450 0.750 0.018 0.030 d d/2 e e/2 e 0.09/0.20 b1 b 0.09/0.16 base metal with lead finish a2 a1 0.08 r min. 0.20 min. 1.00 ref. l 0-7 datum plane gauge plane 0.25 0 min. det ail b e1 d1 pinno. 1 indicator area a detail b 8 places 11/13
pic16c64x & pic16c66x ds30559a-page 112 preliminary 1996 microchip technology inc. 14.1 p ac ka g e marking inf ormation legend: mm...mmicrochip part number information xx...x customer speci? information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note :in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxxxxxxx aabbcde 28-lead pdip (skinny dip) mmmmmmmmmmmm aabbcde example pic16c642-10/sp 28-lead soic xxxxxxxxxxxxxxxxxxxx aabbcde mmmmmmmmmmmmmmmm example 945/caa pic16c642-10/so example 28-lead side brazed skinny windowed xxxxxxxxxxx xxxxxxxxxxx aabbcde pic16c642/jw 9517cat
1996 microchip technology inc. preliminary ds30559a-page 113 pic16c64x & pic16c66x 14.2 p ac ka g e marking inf ormation legend: mm...mmicrochip part number information xx...x customer speci? information* aa year code (last 2 digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note :in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. xxxxxxxxxxxxxxxxxx aabbcde 40-lead pdip mmmmmmmmmmmmmm 9512caa example pic16c662-04/p 44-lead plcc mmmmmmmm aabbcde xxxxxxxxxx xxxxxxxxxx 44-lead tqfp xxxxxxxxxx aabbcde mmmmmmmm xxxxxxxxxx example pic16c662 aabbcde -20/l example -20/tq aabbcde pic16c662 mmmmmmmmm xxxxxxxxxxx aabbcde 40-lead cerdip windowed xxxxxxxxxxx pic16c662/jw aabbcde example
pic16c64x & pic16c66x ds30559a-page 114 preliminary 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 115 pic16c64x & pic16c66x appendix a: enhancements the following are the list of enhancements over the pic16c5x microcontroller family: 1. instruction word length is increased to 14 bits. this allows larger page sizes both in program memory (4k now as opposed to 512 before) and register ?e (up to 176 bytes now versus 32 bytes before). 2. a pc high latch register (pclath) is added to handle program memory paging. pa2, pa1, pa0 bits are removed from status register. 3. data memory paging is slightly rede?ed. status register is modi?d. 4. four new instructions have been added: return , retfie , addlw , and sublw . two instructions tris and option are being phased out although they are kept for compatibility with pic16c5x. 5. option and tris registers are made addressable. 6. interrupt capability is added. interrupt vector is at 0004h. 7. stack size is increased to 8 deep. 8. reset vector is changed to 0000h. 9. reset of all registers is revisited. six different reset (and wake-up) types are recognized. registers are reset differently. 10. wake up from sleep through interrupt is added. 11. two separate timers, oscillator start-up timer (ost) and power-up timer (pwrt) are included for more reliable power-up. these timers can be invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. portb has weak pull-ups and interrupt on change feature. 13. timer0 clock input, t0cki pin is also a port pin (ra4/t0cki) and has a tris bit. 14. fsr is made a full 8-bit register. 15. ?n-circuit programming?is made possible. the user can program pic16cxx devices using only ?e pins: v dd , v ss , v pp , rb6 (clock) and rb7 (data in/out). 16. pcon status register is added with a power-on reset status bit (por ), a brown-out reset sta- tus bit (bor ), a parity error reset (per ), and a memory parity enable (mpeen) bit. 17. code protection scheme is enhanced such that portions of the program memory can be protected, while the remainder is unprotected. 18. porta inputs are now schmitt trigger inputs. 19. brown-out reset circuitry has been added. appendix b: compatibility to convert code written for pic16c5x to pic16cxx, the user should take the following steps: 1. remove any program memory page select operations (pa2, pa1, pa0 bits) for call , goto . 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any data memory page switching. rede?e data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to 0000h. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 116 preliminary 1996 microchip technology inc. appendix c: whats new new data sheet appendix d: whats changed new data sheet
pic16c64x & pic16c66x 1996 microchip technology inc. ds30559a-page 117 appendix e: pic16/17 microcontrollers e.1 pic14000 de vices pic14000 20 4k 192 tmr0 adtmr i 2 c/ smbus 14 11 22 2.7-6.0 yes internal oscillator, bandgap reference, temperature sensor, calibration factors, low voltage detector, sleep, hibernate, comparators with programmable references (2) 28-pin dip, soic, ssop (.300 mil) maximum frequency of operation (mhz) data memory (bytes) timer module(s) serial port(s) (spi/i 2 c, usart) slope a/d converter interrupt sources i/o pins voltage range (volts) eprom program memory (x14 words) clock memory peripherals features in-circuit serial programming additional on-chip features packages (high-res) channels this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 118 1996 microchip technology inc. e.2 pic16c5x f amil y of de vices pic16c52 4 384 25 tmr0 12 2.5-6.25 33 18-pin dip, soic pic16c54 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16c55 20 512 24 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c56 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c57 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57b 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c58a 20 2k 73 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. packages number of instructions voltage range (volts) i/o pins timer module(s) ram data memory (bytes) (x12 words) program memory rom eprom maximum frequency of operation (mhz) features peripherals memory clock
pic16c64x & pic16c66x 1996 microchip technology inc. ds30559a-page 119 e.3 pic16cxxx f amil y of de vices pic16c554 20 512 80 tmr0 ? 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c556 20 1k 80 tmr0 3 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c558 20 2k 128 tmr0 3 13 2.5-6.0 18-pin dip, soic; 20-pin ssop pic16c620 20 512 80 tmr0 2 yes 4 13 2.5-6.0 yes 18-pin dip, soic; 20-pin ssop pic16c621 20 1k 80 tmr0 2 yes 4 13 2.5-6.0 yes 18-pin dip, soic; 20-pin ssop pic16c622 20 2k 128 tmr0 2 yes 4 13 2.5-6.0 yes 18-pin dip, soic; 20-pin ssop pic16c641 20 2k 128 tmr0 2 yes 4 22 3.0-6.0 yes 28-pin pdip, soic windowed cdip pic16c642 20 4k 176 tmr0 2 yes 4 22 3.0-6.0 yes 28-pin pdip, soic windowed cdip pic16c661 20 2k 128 tmr0 2 yes 5 33 3.0-6.0 yes 40-pin pdip, windowed cdip; 44-pin plcc, mqfp pic16c662 20 4k 176 tmr0 2 yes 5 33 3.0-6.0 yes 40-pin pdip, windowed cdip; 44-pin plcc, mqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c6xxx family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) comparator(s) internal reference voltage i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features (x14 words) interupt source
pic16c64x & pic16c66x ds30559a-page 120 1996 microchip technology inc. e.4 pic16c6x f amil y of de vices pic16c62 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes 28-pin sdip, soic, ssop pic16c62a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16cr62 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16c63 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 2.5-6.0 yes yes 28-pin sdip, soic pic16cr63 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 2.5-6.0 yes yes 28-pin sdip, soic pic16c64 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c64a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr64 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16c65 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c65a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr65 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16c6x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features rom in-circuit serial programming (x14 words)
pic16c64x & pic16c66x 1996 microchip technology inc. ds30559a-page 121 e.5 pic16c7x f amil y of de vices pic16c710 20 512 36 tmr0 4 4 13 2.5-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c71 20 1k 36 tmr0 4 4 13 2.5-6.0 yes 18-pin dip, soic pic16c711 20 1k 68 tmr0 4 4 13 2.5-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c72 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 5 8 22 2.5-6.0 yes yes 28-pin sdip, soic, ssop pic16c73 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 2.5-6.0 yes 28-pin sdip, soic pic16c73a 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 2.5-6.0 yes yes 28-pin sdip, soic pic16c74 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 2.5-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c74a 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 2.5-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16c7x family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom program memory (x14 words) data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages clock memory peripherals features in-circuit serial programming
pic16c64x & pic16c66x ds30559a-page 122 1996 microchip technology inc. e.6 pic16c8x f amil y of de vices pic16c84 10 1k 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16f84 (1) 10 1k 68 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16cr84 (1) 10 1k 68 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16f83 (1) 10 512 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic pic16cr83 (1) 10 512 36 64 tmr0 4 13 2.0-6.0 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16c8x family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eeprom data eeprom (bytes) data memory (bytes) timer module(s) interrupt sources i/o pins voltage range (volts) packages program memory clock memory peripherals features rom flash
pic16c64x & pic16c66x 1996 microchip technology inc. ds30559a-page 123 e.7 pic16c9xx f amil y of de vices pic16c923 8 4k 176 tmr0, tmr1, tmr2 1 spi/i 2 c 4 com 32 seg 8 25 27 3.0-6.0 yes 64-pin sdip (1) , tqfp, 68-pin plcc, die pic16c924 8 4k 176 tmr0, tmr1, tmr2 1 spi/i 2 c 5 4 com 32 seg 9 25 27 3.0-6.0 yes 64-pin sdip (1) , tqfp, 68-pin plcc, die all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local microchip representative for availability of this package. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming input pins lcd module
pic16c64x & pic16c66x ds30559a-page 124 1996 microchip technology inc. e.8 pic17cxx f amil y of de vices pic17c42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 4.5-5.5 55 40-pin dip; 44-pin plcc, mqfp pic17c42a 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17cr42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17c43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17cr43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp pic17c44 25 8k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes yes 11 33 2.5-6.0 58 40-pin dip; 44-pin plcc, tqfp, mqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. maximum frequency of operation (mhz) eprom ram data memory (bytes) timer module(s) captures serial port(s) (usart) external interrupts interrupt sources i/o pins voltage range (volts) number of instructions packages clock memory peripherals features pwms hardware multiply program memory (words) rom
1996 microchip technology inc. ds30559a-page 125 pic16c64x & pic16c66x pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table e-1: pin compatible devices pin compatible devices package pic12c508, pic12c509 8-pin pic16c54, pic16c54a, pic16cr54a, pic16c56, pic16c58a, pic16cr58a, pic16c61, pic16c554, pic16c556, pic16c558 pic16c620, pic16c621, pic16c622, pic16c710, pic16c71, pic16c711, pic16f83, pic16cr83, pic16c84, pic16f84a, pic16cr84 18-pin 20-pin pic16c55, pic16c57, pic16cr57b 28-pin pic16c62, pic16cr62, pic16c62a, pic16c63, pic16c72, pic16c73, pic16c73a 28-pin pic16c64, pic16cr64, pic16c64a, pic16c65, pic16c65a, pic16c74, pic16c74a 40-pin pic17c42, pic17cr42, pic17c42a, pic17c43, pic17cr43, pic17c44 40-pin pic16c923, pic16c924 64/68-pin
pic16c64x & pic16c66x ds30559a-page 126 1996 microchip technology inc. notes:
1996 microchip technology inc. preliminary ds30559a-page 127 pic16c64x & pic16c66x index a addlw instruction ......................................................... 76 addwf instruction ........................................................ 76 andlw instruction ......................................................... 76 andwf instruction ........................................................ 76 architectural overview ..................................................... 9 assembler ........................................................................ 88 b bcf instruction ............................................................... 77 bit manipulation .............................................................. 74 block diagrams ............................................................... 30 comparator analog input mode .......................... 51 comparator i/o operating modes ....................... 48 comparator output ................................................ 50 crystal operation ................................................... 57 external brown-out protection 1 .......................... 65 external brown-out protection 2 .......................... 65 external clock input operation ............................ 57 external parallel cystal oscillator ....................... 58 external power-on reset circuit ......................... 65 external series crystal oscillator ........................ 58 in-circuit serial programming ............................... 71 interrupt logic ......................................................... 66 on-chip reset circuit ............................................ 59 parallel slave port, portd-porte .................. 39 pic16c641 .............................................................. 10 pic16c642 .............................................................. 10 pic16c661 .............................................................. 11 pic16c662 .............................................................. 11 portc (in i/o port mode) ................................... 34 portd (in i/o port mode) ................................... 35 porte (in i/o port mode) ................................... 37 ra1:ra0 pins .......................................................... 29 ra3 pin ..................................................................... 30 ra4 pin ..................................................................... 31 rb3:rb0 pins .......................................................... 32 rb7:rb4 pins .......................................................... 32 rc oscillator ........................................................... 58 single comparator ................................................. 49 timer0 ...................................................................... 41 timer0/wdt prescaler .......................................... 44 voltage reference ................................................. 53 voltage reference output buffer ........................ 54 watchdog timer ..................................................... 69 brown-out reset (bor) ................................................ 60 bsf instruction ............................................................... 77 btfsc instruction .......................................................... 77 btfss instruction .......................................................... 78 c c compiler (mplab-c) ................................................. 89 call instruction ............................................................. 78 clocking scheme/instruction cycle ............................. 15 clrf instruction ............................................................. 78 clrw instruction ........................................................... 78 clrwdt instruction ...................................................... 79 cmcon register ............................................................ 47 code examples changing prescaler (t0 to wdt) ........................ 45 changing prescaler (wdt to t0) ........................ 45 indirect addressing ................................................ 28 initializing comparator module ............................ 49 initializing porta .................................................. 29 initializing portc .................................................. 34 read-modify-write instructions on an i/o port .38 saving the status and w registers in ram .68 voltage reference configuration ........................ 54 code protection .............................................................. 71 comf instruction ........................................................... 79 comparator configuration ............................................ 48 comparator interrupt ..................................................... 51 comparator module ....................................................... 47 comparator operation .................................................. 49 comparator reference .................................................. 49 configuration bits ........................................................... 56 configuring the voltage reference ............................. 54 d data memory organization .......................................... 18 decf instruction ............................................................ 79 decfsz instruction ....................................................... 79 development support .................................................... 87 development tools ........................................................ 87 device drawings 28-lead ceramic cerdip dual in-line with win- dow (300 mil)) ....................................... 107 28-lead ceramic dual in-line with window (jw) - (300 mil) ................................................. 107 28-lead plastic small outline (so) - wide, 300 mil body ....................................................... 106 28-lead skinny plastic dual in-line (sp) - 300 mil ................................................... 105 40-lead ceramic dual in-line with window (jw) - (600 mil) ..................................... 108 40-lead plastic dual in-line (p) - 600 mil ....... 109 44-lead plastic leaded chip carrier (l) - square ................................................... 110 44-lead plastic quad flatpack (pq) - 10x10x2 mm body 1.6/0.15 mm lead form ... 111 f family of devices pic14xxx ............................................................. 117 pic16c5x ............................................................. 118 pic16c64x ................................................................6 pic16c66x ................................................................6 pic16c6x ............................................................. 120 pic16c7x ............................................................. 121 pic16c8x ............................................................. 122 pic16c9xx ........................................................... 123 pic16cxxx .......................................................... 119 pic17cxx ............................................................. 124 fuzzy logic dev. system ( fuzzy tech -mp) .... 87, 89 g general purpose register file .................................... 18 goto instruction ........................................................... 80 this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 128 preliminary 1996 microchip technology inc. i i/o ports ........................................................................... 29 porta ..................................................................... 29 portb ..................................................................... 32 portc ..................................................................... 34 portd ..................................................................... 35 porte ..................................................................... 36 i/o programming considerations ................................ 38 icepic in-circuit emulator ........................................... 87 id locations ..................................................................... 71 incf instruction .............................................................. 80 incfsz instruction ......................................................... 80 in-circuit serial programming ...................................... 71 indirect addressing, indf and fsr registers ......... 28 instruction flow/pipelining ............................................ 15 instruction format ........................................................... 73 instruction set addlw .................................................................... 76 addwf .................................................................... 76 andlw .................................................................... 76 andwf .................................................................... 76 bcf ........................................................................... 77 bsf ........................................................................... 77 btfsc ...................................................................... 77 btfss ...................................................................... 78 call ......................................................................... 78 clrf ........................................................................ 78 clrw ....................................................................... 78 clrwdt .................................................................. 79 comf ....................................................................... 79 decf ........................................................................ 79 decfsz ................................................................... 79 goto ....................................................................... 80 incf .......................................................................... 80 incfsz .................................................................... 80 iorlw ...................................................................... 80 iorwf ...................................................................... 81 movf ....................................................................... 81 movlw .................................................................... 81 movwf .................................................................... 81 nop .......................................................................... 82 option .................................................................... 82 retfie ..................................................................... 82 retlw ..................................................................... 82 return .................................................................. 83 rlf ........................................................................... 83 rrf ........................................................................... 83 sleep ...................................................................... 83 sublw ..................................................................... 84 subwf .................................................................... 84 swapf ..................................................................... 85 tris .......................................................................... 85 xorlw .................................................................... 85 xorwf .................................................................... 85 section ...................................................................... 73 summary table ...................................................... 75 int interrupt .................................................................... 67 intcon register ........................................................... 23 interrupts .......................................................................... 66 comparator .............................................................. 51 portb change ..................................................... 32 psp read-write ..................................................... 39 rb0/int ................................................................... 66 section ..................................................................... 66 timer0 ...................................................................... 41 timer0, timing ........................................................ 42 iorlw instruction .......................................................... 80 iorwf instruction ......................................................... 81 m movf instruction ........................................................... 81 movlw instruction ........................................................ 81 movwf instruction ....................................................... 81 mpasm assembler .................................................. 87, 88 mplab-c c compiler ................................................... 89 mplab-sim software simulator ........................... 87, 89 n nop instruction .............................................................. 82 o one-time-programmable (otp) devices ................... 7 opcode ............................................................................. 73 option instruction ....................................................... 82 option register ........................................................... 22 oscillator configurations ............................................... 57 oscillator start-up timer (ost) ................................... 60 p package marking information ............................ 112, 113 packaging information ................................................. 105 parallel slave port ......................................................... 35 section ..................................................................... 39 parity error reset (per) ........................................ 60, 61 pcl ................................................................................... 74 pcl and pclath .......................................................... 27 pcon register ......................................................... 26, 61 picdem-1 low-cost pic16/17 demo board ..... 87, 88 picdem-2 low-cost pic16cxx demo board ... 87, 88 picdem-3 low-cost pic16c9xx demo board ...... 88 picdem-3 pic16c9xx low-cost demonstration board ................................................................ 87 picmaster high performance in-circuit emulator ......................................... 87 picstart plus entry level development system ............................................................. 87 picstart plus entrvel prototype programmer .................................................... 87 pie1 register .................................................................. 24 pin compatible devices .............................................. 125 pin functions rd7/psp7:rd0/psp0 .......................................... 14 re0/rd ....................................................... 14, 39 re1/wr ...................................................... 14, 39 re2/cs ....................................................... 14, 39 pir1 register .................................................................. 25 port rb interrupt ............................................................ 67 porta ............................................................................. 29 portb ............................................................................. 32 portc register ............................................................ 34 portd register ............................................................ 35
1996 microchip technology inc. preliminary ds30559a-page 129 pic16c64x & pic16c66x porte register ............................................................. 36 ports parallel slave port .................................................. 39 porta ..................................................................... 29 portb ..................................................................... 32 portc ..................................................................... 34 portd ..................................................................... 14 porte ..................................................................... 14 power control/status register (pcon) ..................... 61 power-down mode (sleep) ........................................ 70 power-on reset (por) ................................................. 60 power-up timer (pwrt) ............................................... 60 prescaler .......................................................................... 44 pro mate universal programmer .......................... 87 program memory organization .................................... 17 pspmode bit ........................................................... 35, 36 q quick-turnaround-production (qtp) devices ............ 7 r ra2 pin ............................................................................. 30 rc oscillator ................................................................... 58 reset ................................................................................ 59 retfie instruction ......................................................... 82 retlw instruction ......................................................... 82 return instruction ...................................................... 83 rlf instruction ................................................................ 83 rrf instruction ............................................................... 83 s serialized quick-turnaround-production (sqtp) devices .............................................................. 7 sfr ................................................................................... 74 sfr as source/destination .......................................... 74 sleep instruction .......................................................... 83 software simulator (mplab-sim) ............................... 89 special features of the cpu ........................................ 55 special function registers ..................................... 19, 74 stack ................................................................................. 27 status register ........................................................... 21 sublw instruction ......................................................... 84 subwf instruction ......................................................... 84 swapf instruction ......................................................... 85 switching prescalers ..................................................... 45 t timer modules timer0 block diagram ................................................. 41 counter mode ................................................. 41 external clock ................................................. 43 interrupt ............................................................ 41 prescaler .......................................................... 44 section ............................................................. 41 timer mode ..................................................... 41 timing diagram .............................................. 41 tmr0 register ................................................. 41 timing diagrams and specifications .......................... 98 tmr0 interrupt ................................................................ 67 tris instruction .............................................................. 85 trisa ............................................................................... 29 trisb ............................................................................... 32 trisc register .............................................................. 34 trisd register .............................................................. 35 trise register ............................................................... 36 v voltage reference module ........................................... 53 vrcon register ............................................................ 53 w watchdog timer (wdt) ................................................ 69 x xorlw instruction ........................................................ 85 xorwf instruction ........................................................ 85 list of examples example 3-1:instruction pipeline flow ............................... 15 example 4-1:indirect addressing........................................ 28 example 5-1:initializing porta ......................................... 29 example 5-2:initializing portc ......................................... 34 example 5-3:read-modify-write instructions on an i/o port .......................................................... 38 example 6-1:changing prescaler (timer0 ? wdt)............. 45 example 6-2:changing prescaler (wdt ? timer0)............. 45 example 7-1:initializing comparator module ...................... 49 example 8-1:voltage reference configuration .................. 54 example 9-1:saving the status and w registers in ram............................................................... 68 list of figures figure 3-1: pic16c641/642 block diagram..................... 10 figure 3-2: pic16c661/662 block diagram..................... 11 figure 3-3: clock/instruction cycle .................................. 15 figure 4-1: pic16c641/661 program memory map and stack.............................................................. 17 figure 4-2: pic16c642/662 program memory map and stack.............................................................. 17 figure 4-3: pic16c641/661 data memory map .............. 18 figure 4-4: pic16c642/662 data memory map .............. 19 figure 4-5: status register (address 03h, 83h) .......... 21 figure 4-6: option register (address 81h) ................... 22 figure 4-7: intcon register (address 0bh, 8bh) .......... 23 figure 4-8: pie1 register (address 8ch)......................... 24 figure 4-9: pir1 register (address 0ch) ........................ 25 figure 4-10: pcon register (address 8eh)...................... 26 figure 4-11: loading of pc in different situations............ 27 figure 4-12: direct/indirect addressing.............................. 28 figure 5-1: block diagram of ra1:ra0 pins ................... 29 figure 5-2: block diagram of ra2 pin ............................. 30 figure 5-3: block diagram of ra3 pin ............................. 30 figure 5-4: block diagram of ra4 pin ............................. 31 figure 5-5: block diagram of rb7:rb4 pins ................... 32 figure 5-6: block diagram of rb3:rb0 pins ................... 32 figure 5-7: portc block diagram (in i/o port mode) .... 34 figure 5-8: portd block diagram (in i/o port mode) .... 35 figure 5-9: trise register (address 89h) ...................... 36 figure 5-10: porte block diagram (in i/o port mode) .... 37 figure 5-11: successive i/o operation.............................. 38 figure 5-12: portd and porte as a parallel slave port 39 figure 6-1: timer0 block diagram ................................... 41 figure 6-2: timer0 timing: internal clock/no prescaler.. 41 figure 6-3: timer0 timing: internal clock/prescale 1:2... 42
pic16c64x & pic16c66x ds30559a-page 130 preliminary 1996 microchip technology inc. figure 6-4: timer0 interrupt timing.................................. 42 figure 6-5: timer0 timing with external clock................ 43 figure 6-6: block diagram of the timer0/wdt prescaler 44 figure 7-1: cmcon register (address 1fh) ................... 47 figure 7-2: comparator i/o operating modes.................. 48 figure 7-3: single comparator ......................................... 49 figure 7-4: comparator output block diagram ................ 50 figure 7-5: analog input model ........................................ 51 figure 8-1: vrcon register(address 9fh) ..................... 53 figure 8-2: voltage reference block diagram ................. 53 figure 8-3: voltage reference output buffer example .... 54 figure 9-1: configuration word ........................................ 56 figure 9-2: crystal operation (or ceramic resonator) (hs, xt or lp osc configuration).................. 57 figure 9-3: external clock input operation (hs, xt or lp osc configuration).................. 57 figure 9-4: external parallel resonant crystal oscillator circuit ............................................................. 58 figure 9-5: external series resonant crystal oscillator circuit ............................................................. 58 figure 9-6: rc oscillator mode ........................................ 58 figure 9-7: simplified block diagram of on-chip reset circuit ............................................................. 59 figure 9-8: brown-out situations ...................................... 60 figure 9-9: time-out sequence on power-up (mclr not tied to v dd ): case 1 ....................................... 64 figure 9-10: time-out sequence on power-up (mclr not tied to v dd ): case 2 ....................................... 64 figure 9-11: time-out sequence on power-up (mclr tied to v dd ) ............................................................... 64 figure 9-12: external power-on reset circuit (for slow v dd power-up) ...................................................... 65 figure 9-13: external brown-out protection circuit 1 ......... 65 figure 9-14: external brown-out protection circuit 2 ......... 65 figure 9-15: interrupt logic ................................................ 66 figure 9-16: rb0/int pin interrupt timing ......................... 67 figure 9-17: watchdog timer block diagram .................... 69 figure 9-18: summary of watchdog timer registers ........ 69 figure 9-19: wake-up from sleep through interrupt ......... 70 figure 9-20: typical in-circuit serial programming connection ..................................................... 71 figure 10-1: general format for instructions ..................... 73 figure 12-1: load conditions ............................................. 97 figure 12-2: external clock timing .................................... 98 figure 12-3: clkout and i/o timing ................................ 99 figure 12-4: reset, watchdog timer, oscillator start-up tim- er, and power-up timer timing ................... 100 figure 12-5: brown-out reset timing .............................. 100 figure 12-6: timer0 clock timing .................................... 101 figure 12-7: parallel slave port timing (pic16c661 and pic16c662) ................................................. 102 list of tables table 1-1: pic16c64x & pic16c66x device features ... 6 table 3-1: pic16c641/642 pinout description ............... 12 table 3-2: pic16c661/662 pinout description ............... 13 table 4-1: special function registers ............................ 20 table 5-1: porta functions .......................................... 31 table 5-2: summary of registers associated with porta........................................................... 31 table 5-3: portb functions .......................................... 33 table 5-4: summary of registers associated with portb........................................................... 33 table 5-5: portc functions .......................................... 34 table 5-6: summary of registers associated with portc .......................................................... 34 table 5-7: portd functions.......................................... 35 table 5-8: summary of registers associated with portd .......................................................... 35 table 5-9: porte functions.......................................... 37 table 5-10: summary of registers associated with porte .......................................................... 37 table 5-11: registers associated with parallel slave port39 table 6-1: registers associated with timer0 ................. 45 table 7-1: registers associated with comparator module ....................................... 52 table 8-1: registers associated with voltage reference54 table 9-1: capacitor selection for ceramic resonators (preliminary) .................................................. 57 table 9-2: capacitor selection for crystal oscillator (preliminary) .................................................. 57 table 9-3: time-out in various situations....................... 61 table 9-4: status bits and their significance ................. 62 table 9-5: initialization condition for special registers.. 62 table 9-6: initialization condition for registers .............. 63 table 10-1: opcode field descriptions............................. 73 table 10-2: instruction set................................................ 75 table 11-1: development tools from microchip .............. 90 table 12-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) ................................... 91 table 12-2: comparator specifications............................. 96 table 12-3: voltage reference specifications.................. 96 table 12-4: external clock timing requirements ............ 98 table 12-5: clkout and i/o timing requirements ........ 99 table 12-6: reset, watchdog timer, oscillator start-up tim- er, power-up timer, and brown-out reset re- quirements ................................................... 100 table 12-7: timer0 clock requirements ........................ 101 table 12-8: parallel slave port requirements (pic16c661 and pic16c662) .......................................... 102 table e-1: pin compatible devices............................... 125
1996 microchip technology inc. ds30559a-page 131 pic16c64x & pic16c66x on-line support microchip provides two methods of on-line support. these are the microchip bbs and the microchip world wide web (www) site. use microchip's bulletin board service (bbs) to get current information and help about microchip products. microchip provides the bbs communication channel for you to use in extending your technical staff with micro- controller and memory experts. to provide you with the most responsive service possible, the microchip systems team monitors the bbs, posts the latest component data and software tool updates, provides technical help and embedded systems insights, and discusses how microchip products pro- vide project solutions. the web site, like the bbs, is used by microchip as a means to make ?es and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape or microsoft explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available by using your favor ite internet browser to attach to: www.microchip.com the ?e transfer site is available by using an ftp ser- vice to connect to: ftp.mchip.com/biz/mchip the web site and ?e transfer site provide a variety of services. users may download ?es for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip speci? business information is also available, including listings of microchip sales of?es, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products connecting to the microchip bbs connect worldwide to the microchip bbs using either the internet or the compuserve communications net- work. internet: you can telnet or ftp to the microchip bbs at the address: mchipbbs.microchip.com compuser ve comm unications netw ork: when using the bbs via the compuserve network, in most cases, a local call is your only expense. the microchip bbs connection does not use compuserve membership services, therefore you do not need compuserve membership to join microchip's bbs. there is no charge for connecting to the microchip bbs. the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allow multiple users various baud rates depending on the local point of access. the following connect procedure applies in most loca- tions. 1. set your modem to 8-bit, no parity, and one stop (8n1). this is not the normal compuserve setting which is 7e1. 2. dial your local compuserve access number. 3. depress the key and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress the key and ?ost name: will appear. 5. type mchipbbs, depress the key and you will be connected to the microchip bbs. in the united states, to ?d the compuserve phone number closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with ?ost name:? type network, depress the key and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 723-1550 for your local compuserve number. microchip regularly uses the microchip bbs to distribute technical information, application notes, source code, errata sheets, bug reports, and interim patches for microchip systems software products. for each sig, a moderator monitors, scans, and approves or disap- proves ?es submitted to the sig. no executable ?es are accepted from the user community in general to limit the spread of computer viruses. systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive any currently available upgrade kits.the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-602-786-7302 for the rest of the world. trademarks: the microchip name, logo, pic, picstart, picmaster, and are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. flex rom, mplab, pro mate, and fuzzy lab, are trade- marks and sqtp is a service mark of microchip in the u.s.a. fuzzy tech is a registered trademark of inform software corporation. ibm, ibm pc-at are registered trademarks of international business machines corp. pentium is a trade- mark of intel corporation. windows is a trademark and ms-dos, microsoft windows are registered trademarks of microsoft corporation. compuserve is a registered trademark of compuserve incorporated. all other trademarks mentioned herein are the property of their respective companies. this document was created with framemake r404
pic16c64x & pic16c66x ds30559a-page 132 1996 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to : technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds30559a pic16c64x & pic16c66x
1996 microchip technology inc. ds30559a-page 133 pic16c64x & pic16c66x notes:
pic16c64x & pic16c66x ds30559a-page 134 1996 microchip technology inc. notes:
1996 microchip technology inc. ds30559a-page 135 pic16c64x & pic16c66x pic16c64x & pic16c66x product identification system please contact your local sales of?e for exact ordering procedures. jw devices are uv erasable and can be programmed to any device con?uration. jw devices meet the electrical requirements of each oscillator type (including lc devices). pattern: special requirements package: so = soic l = plcc p = pdip tq = tqfp sp = skinny dip jw = windowed dip temperature range: -=0 c to +70 c i = -40 c to +85 c e = -40 c to +125 c frequency range: 04 = 4 mhz 10 = 10mhz 20 = 20 mhz device part no. -xx x /xx xxx examples a) pic16c662-04/p commercial temp., pdip package, 4 mhz, normal v dd limits b) pic16c662-04i/so industrial temp., soic package, 4 mhz, normal v dd limits c) pic16c662-04e/p automotive temp., pdip package, 4 mhz, normal v dd limits sales and suppor t products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: your local microchip sales of?e (see below) the microchip corporate literature center u.s. fax: (602) 786-7277 the microchips bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. 1. 2. 3.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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