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general description the MAX9471/max9472 multipurpose clock generators are ideal for consumer and communication applica- tions. the MAX9471/max9472 feature two buffered phase-locked loop (pll) outputs that can be indepen- dently set from 4mhz to 200mhz. these devices also provide one (max9472) or two (MAX9471) buffered outputs of the reference clock. the MAX9471 outputs a set of mpeg/ac3 audio and video frequencies most commonly used in consumer applications. the max9472 outputs a set of common audio frequencies. these frequencies are selected through an i 2 c ? interface (MAX9471) or by setting the three-level fs pins. the MAX9471/max9472 feature a one-time-programmable (otp) rom, allowing one-time programming of the two pll outputs. the MAX9471/max9472 include two basic configura- tions. in one configuration, the otp rom sets pll1 out- put to any frequency between 4mhz to 200mhz, and the i 2 c interface (MAX9471) or programmable pins set the pll2 output frequency to a set of audio and video frequencies. in the other configuration, the otp rom sets both pll1 and pll2 frequencies to fixed values between 4mhz to 200mhz. in both cases, the reference output is available, but the otp rom can disable it. the otp rom on the MAX9471/max9472 is factory set based on the customer requirements. contact the factory for samples with preferred frequencies. the devices operate from a 3.3v supply and are specified over the -40 c to +85 c extended temperature range. the MAX9471 is available in a 20-pin tqfn package. the max9472 is available in a 14-pin tssop package. applications digital tvs communication systems data networking systems set-top boxes home entertainment centers multimedia pcs features ? 5mhz to 50mhz input clock reference ? crystal or input-clock-based reference ? two fractional-n feedback plls (4mhz to 200mhz) with buffered outputs ? two buffered outputs of reference clock ? otp for factory-preset pll frequencies available (contact factory) ? programmable through i 2 c interface or three- level logic pins for video or audio clocks ? low-rms jitter pll (14ps for 45mhz) ? integrated vcxo with ?00ppm tuning range ? available in 20-pin tqfn and 14-pin tssop packages ? +3.3v supply ? -40? to +85? temperature range MAX9471/max9472 multiple-output clock generators with dual plls and otp ________________________________________________________________ maxim integrated products 1 15 14 13 12 pd fs2 v dd v dd 11 gnd 8 7 6 9 10 clk3 clk4 i.c. gnd clk2 19 18 17 16 fso/scl x1 x2 v dd 20 + fs1/sda 1 2 3 4 tune v dda agnd gnd 5 clk1 MAX9471 top view tqfn (5mm x 5mm) pin configurations 19-0524; rev 1; 8/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code MAX9471 etp+** -40? to +85? 20 tqfn-ep* t2055-5 m a x9 4 7 2 e u d + ** -40? to +85? 14 tssop u14-2 ordering information * ep = exposed pad. ** marking is for samples only. contact factory for ordering information. + denotes lead-free package. pin configurations continued at end of data sheet. ? purchase of i 2 c components from maxim integrated pr oducts, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these com- ponents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
MAX9471/max9472 multiple-output clock generators with dual plls and otp 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v dd = v dda = +3.0v to +3.6v and t a = -40? to +85?. typical values at v dd = v dda = 3.3v, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +4.0v v dda to agnd ......................................................-0.3v to +4.0v agnd to gnd ......................................................-0.3v to +0.3v all other pins to gnd ..................................-0.3v to v dd + 0.3v short-circuit duration (all lvcmos outputs)..............................................continuous esd protection (human body model)..................................?kv continuous power dissipation (t a = +70?) 20-pin tqfn (derate 21.3mw/? above +70?) .......2758mw 14-pin tssop (derate 9.1mw/? above +70?) ......796.8mw storage temperature range .............................-65? to +150? maximum junction temperature .....................................+150? operating temperature range ...........................-40? to +85? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units lvcmos inputs ( pd , x1 as a reference input clk) input high level v ih1 2.0 v dd v input low level v il1 0 0.8 v input current high level i ih1 v in = v dd 20 ? input current low level i il1 v in = 0 -20 ? three-level inputs (fs0, fs1, fs2, as fs2 = open) input high level v ih2 2.5 v input low level v il2 0.8 v input open level v io2 1.27 2.10 v input current i il2 , i ih2 v il2 = 0 or v ih2 = v dd -10 +10 ? serial interface (scl, sda) (note 2) (MAX9471) input high level v ih 0.7 x v dd v input low level v il 0.3 x v dd v input-leakage current i ih , i il -1 +1 ? low-level output v ol i sink = 4ma 0.4 v input capacitance c i (note 3) 8.4 pf clock outputs (clk_) output high level v oh i oh = -4ma v dd - 0.6 v output low level v ol i ol = 4ma 0.4 v power supplies digital power-supply voltage v dd 3.0 3.6 v analog power-supply voltage v dda 3.0 3.6 v total current for digital and analog supplies i dc clk1 at 125mhz and clk2 at 74.1758mhz; all outputs not loaded 12 ma total power-down current i pd pd = low 60 ?
MAX9471/max9472 multiple-output clock generators with dual plls and otp _______________________________________________________________________________________ 3 ac electrical characteristics (v dd = v dda = +3.0v to +3.6v, t a = -40? to +25?. typical values are at v dd = v dda = 3.3v, t a = +25? with f xtl = 27mhz, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units output clocks (clk1, clk2) minimum frequency range f out f in = 5mhz to 50mhz 4 mhz maximum frequency range f out f in = 5mhz to 50mhz, c l < 5pf 133 200 mhz clock rise time t r 20% to 80% of v dd , c l = 10p f, f out = 74.1758mhz (figure 5) 1.4 ns clock fall time t f 80% to 20% of v dd , c l = 10p f, f out = 74.1758mhz (figure 5) 1.2 ns duty cycle f ou t = 74.1758m h z, c l = 10p f425 058 % 125mhz, c l = 5p f, f i n = 27m h z 26.3 output period jitter j p 74.1758mhz, c l = 10p f, f i n = 27m h z 33.6 rmsps soft power-on time t fst s d a fr om l ow to hi g h, f ou t = 71.1758m h z, f i n = 13m h z ( fi g ur e 6) 1ms hard power-on time t po1 (figure 6) 15 ms vcxo clocks (clk3, clk4) crystal frequency f xtl 27 mhz crystal accuracy ?0 ppm tuning voltage range v tune 0.0 3.0 v vcxo tuning range v tune = 0 to 3v, c 1 = c 2 = 4.0p f ?50 ?00 ppm tune input impedance z tune 95 k ? output clk accuracy v tune = 1.5v, c 1 = c 2 = 4.0p f ?0 ppm output duty cycle c l = 10pf load, clk3 40 50 60 % output period jitter c l = 10pf 36 rmsps output rise time t r 20% to 80% of v dd (figure 5), c l = 10p f 1.4 ns output fall time t f 80% to 20% of v dd (figure 5), c l = 10p f 1.4 ns
MAX9471/max9472 multiple-output clock generators with dual plls and otp 4 _______________________________________________________________________________________ serial-interface timing characteristics (MAX9471) (v dd = v dda = +3.3v, t a = -40? to +85?, unless otherwise noted.) (note 1, figure 2) parameter symbol conditions min typ max units serial clock f scl 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time, repeated start condition t hd , sta 0.6 ? repeated start condition setup time t su,sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 4) 15 900 ns data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of sda and scl, receiving t r (notes 3, 5) 20 + 0.1c b 300 ns fall time of sda and scl, receiving t f (notes 3, 5) 20 + 0.1c b 300 ns fall time of sda, transmitting t f,tx (notes 3, 6) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (notes 3, 7) 0 50 ns capacitive load for each bus line c b (note 3) 400 pf note 1: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: no high-output level is specified, only the output resistance to the bus. pullup resistors on the bus provide the high-level voltage. note 3: guaranteed by design. note 4: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 5: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3 x v dd and 0.7 x v dd . note 6: bus sink current is less than 6ma. c b is the total capacitance of one bus line in pf. t r and t f are measured between 0.3 x v dd and 0.7 x v dd . note 7: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
MAX9471/max9472 multiple-output clock generators with dual plls and otp _______________________________________________________________________________________ 5 0 12 8 4 16 20 -40 10 -15 35 60 85 supply current vs. temperature MAX9471/2 toc01 temperature ( c) supply current (ma) f clk1 = 125mhz f clk2 = 74.1758mhz 0.2 0.6 1.4 1.0 1.8 2.2 -40 10 -15 35 60 85 rise time vs. temperature MAX9471/2 toc02 temperature ( c) rise time (ns) c l = 10pf f xtal = 27mhz f clk1 = 66mhz 0.2 0.6 1.4 1.0 1.8 2.2 -40 10 -15 35 60 85 MAX9471/2 toc03 temperature ( c) fall time (ns) fall time vs. temperature c l = 10pf f xtal = 27mhz f clk1 = 66mhz 0 5 20 10 30 25 15 35 40 -40 10 -15 35 60 85 jitter vs. temperature MAX9471/2 toc04 temperature ( c) jitter (ps) f clk1 = 33mhz f clk1 = 66mhz c l = 10pf f xtal = 27mhz 33mhz output MAX9471/2 toc05 clk1 1v/div 10ns/div 66mhz output MAX9471/2 toc06 clk1 1v/div 10ns/div 125mhz clk output MAX9471/2 toc07 clk1 1v/div 4ns/div 45 47 51 49 53 55 -40 10 -15 35 60 85 duty cycle vs. temperature MAX9471/2 toc08 temperature ( c) duty cycle (%) c l = 10pf f xtal = 27mhz f clk1 = 33mhz f clk1 = 66mhz t ypical operating characteristics (v dd = v dda = +3.3v, t a = +25?, f xtl = 27mhz, unless otherwise noted.) vcxo tuning range vs. vcxo accuracy max9741/2 toc09 vcxo tuning range (v) vcxo accuracy (ppm) 2.5 2.0 1.5 1.0 0.5 -200 -100 0 100 200 300 -300 03.0 f in = 27mhz f out = 45mhz 4pf 5pf 6pf
MAX9471/max9472 multiple-output clock generators with dual plls and otp 6 _______________________________________________________________________________________ pin description t ypical operating circuit/block diagram +3.3v v dd v dda * v dd v dd * 0.1 f x 3 0.1 f MAX9471 max9472 +3.3v gnd agnd* *MAX9471 only. fs2* serial interface tune 27mhz c 1 c 2 clk1 pll1 vcxo fs1/sda fs0/scl x1 x2 otp clk2 pll2 clk3 clk4* pin MAX9471 max9472 name function 15 tune vcxo tune voltage input. if using a reference clock input, connect tune to v dd . 2v dda analog power supply. bypass to gnd with a 0.1? capacitor. 3 agnd analog ground 4, 10, 11 6, 10, 11 gnd ground 57 clk1 output clock 1. pll1 buffered output. 68 clk2 output clock 2. pll2 buffered output. 79 clk3 output clock 3. vcxo buffered output. 8 clk4 output clock 4. vcxo buffered output. 9 i.c. internally connected. leave unconnected. 12, 13, 16 4, 12 v dd power supply. bypass to gnd with a 0.1? capacitor. 14 fs2 function select 2 15 13 pd active-low, power-down input. pull high for normal operation, drive pd low to place MAX9471/max9472 in power-down mode. 17 14 x2 crystal connection 2. leave open if using a reference clock. 18 1 x1 crystal connection 1 or reference clock input 19 fs0/scl functi on s el ect 0/s er i al c l ock. s et fs 2 hi g h to p l ace the d evi ce i n i 2 c m od e ( see tab l e 1) . 20 fs1/sda functi on s el ect 1/s er i al d ata. s et fs 2 hi g h to p l ace the d evi ce i n i 2 c m od e ( see tab l e 1) . ? fs1 function select 1 ? fs0 function select 0 ep ep exposed pad (MAX9471 only). connect ep to gnd.
detailed description the MAX9471/max9472 have two programmable frac- tional-n feedback plls so that almost any frequencies between 4mhz to 200mhz can be generated. the MAX9471 provides four outputs: two for the plls and two for the reference clock. the max9472 provides three outputs: two for the plls and one for the refer- ence clock. the crystal frequency can be between 5mhz and 30mhz. the internal vcxo has a fine-tuning range of ?00ppm. power-down driving pd low places the MAX9471/max9472 in power-down mode. pd overrides all other functions, setting all outputs to high impedance and shutting down the two plls. every output has an 80k ? (typ) internal pulldown resistor. voltage-controlled crystal oscillator (vcxo) the MAX9471/max9472s?internal vcxo produces a ref- erence clock for the plls used to generate the output clocks. the oscillator uses a crystal clock as the base frequency reference and has a voltage-controlled tuning input for micro adjustment in a range of ?00ppm. the tuning voltage v tune can vary from 0v to 3v as shown in figure 1. the crystal should be at cut and oscillate on its fundamental mode with ?0ppm accuracy. the crys- tal shunt capacitor should be less than 10pf, including board parasitic capacitance. to achieve up to 200ppm pullability, the crystal-loading capacitance should be less than 14pf. the vcxo is a free-running oscillator. it starts oscillating with an internal por signal and can be disabled by pd . vcxo settles at approximately 5ms at power-on and 10? at a change of the v tune voltage. choosing different c 1 and c 2 capacitors allows flexibility for centering the various crystals. see the typical operating characteristics for an example. to use the MAX9471/max9472 as a synthesizer with an input reference clock, connect the input clock to x1 and tune to v dd , and leave x2 unconnected. this configu- ration is for applications where the micro tuning is not needed, and there is a system reference clock available. one-time programmable memory the MAX9471/max9472 feature a factory-configurable, otp memory for nonvolatile applications allowing for simple and permanent clock generation. contact the fac- tory for presetting the MAX9471/max9472 to requested frequencies. using otp, the MAX9471/max9472 can be configured to two different configurations. one configuration is to have pll1 set to any frequency between 4mhz to 200mhz and select the pll2? frequency by i 2 c (MAX9471) or programmable pins. the second config- uration is to preset the frequencies in pll1 and pll2 to fixed values between 4mhz to 200mhz. in both cases, the reference output is available, but it can be disabled by otp. at power-up, all the outputs are enabled. frequency selection of clk2 output the otp rom can set pll2? output to be selectable from a group of frequencies that are common for mpeg video and audio applications. the frequency selection can be done by the fs_ inputs or through the i 2 c inter- face (MAX9471). for the MAX9471, pull fs2 high (table 1) to select the pll2 frequency through the i 2 c interface. otherwise, the frequencies are selected according to table 2. for the MAX9471, table 3 shows the mappings for i 2 c programming. serial interface (MAX9471) the MAX9471 can be programmed through a 2-wire, i 2 c-compatible serial interface. the device is activated after power-up and fs2 = high. the device operates as a slave that sends and receives data through clock line scl and data line sda for bidirectional communication with the master. a master (typically a microcontroller) initiates all data transfers to and from the MAX9471 and MAX9471/max9472 multiple-output clock generators with dual plls and otp _______________________________________________________________________________________ 7 27.0054 26.9946 -200ppm 3v v tune 0 +200ppm 27.00 vcxo output frequency (mhz) figure 1. vcxo tuning range for a 27mhz crystal fs2 mode low or open pin programmable high i 2 c enabled table 1. mode selection by fs2 (MAX9471 only)
MAX9471/max9472 generates the scl clock that synchronizes the data transfer. the sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on sda. the scl line operates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire bus, or if the master in a single-master system has an open-drain scl output. figure 2 is the i 2 c timing diagram. multiple-output clock generators with dual plls and otp 8 _______________________________________________________________________________________ fs2 fs1 fs0 frequency (mhz) audio frequencies open open open 4.096 open open low 6.144 open open high 8.1920 open low high 11.2896 open low open 12.2880 open low low 16.3840 open high high 22.5792 open high open 24.5760 open high low 9.216 low open high 16.9344 low open open 18.4320 low open low 33.8688 low high high 36.864 video frequencies low low low 74.1758241 low low high 74.25 low low open 54.054 high x x disable three-level pins and enable i 2 c table 2. MAX9471/max9472 frequency selection at clk2 a4 a3 a2 a1 frequency (mhz) audio frequencies 00 00 4.096 00 01 6.144 00 10 8.1920 00 11 11.2896 01 00 12.2880 01 01 16.3840 01 10 22.5792 01 11 24.5760 10 00 9.216 10 01 16.9344 10 10 18.4320 10 11 33.8688 11 00 36.864 video frequencies 11 01 74.1758241 11 10 74.25 11 11 54.054 table 3. MAX9471 i 2 c frequency selection at clk2 (fs2 = high) sda scl t hd, sta t r t high t su, dat t low t f start condition stop condition repeated start condition start condition t hd, dat t su, sto t su, sta t hd, sta t buf figure 2. i 2 c timing diagram *max9472 can be programmed to fs2 = open settings only.
device address the default i 2 c address for the MAX9471 is factory set to 1100111. contact factory for different addresses. start and stop conditions both scl and sda remain high when the interface is not busy. the active master signals the beginning of a transmission with a start (s) condition by transitioning sda from high to low while scl is high. when the mas- ter has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 3). data transfer and ack following the start condition, each scl clock pulse transfers 1 bit. between a start and a stop, multiple bits are transferred on the 2-wire bus. the first 7 bits are for the device address. bit 8 indicates the writing (low) or reading (high) operation (r/ w ). bit 9 is the ack for the address and operation type. the next 8 bits (bit 10 to bit 17) form the content byte. the next bit, bit 18, is the ack for the content byte. the master always trans- fers the first 8 bits (address + r/ w ). the slave (MAX9471) may receive a content byte from the bus or transfer a content byte to the bus. the ack bits are transmitted by the address or content recipient. a low- ack bit indicates a successful transfer; otherwise, a high-ack bit indicates an unsuccessful transfer. more content bytes can be continuously transferred until the master sends a stop. for the MAX9471 data writing, after the 9 bits with the slave id, r/ w , and ack, 1 data byte is sent to the MAX9471 from the master. figure 4 shows the structure of the data transfer. figure 5 shows clk_ rise and fall times. MAX9471/max9472 multiple-output clock generators with dual plls and otp _______________________________________________________________________________________ 9 sda scl start condition stop condition s p figure 3. start and stop diagram a a p a a w s slave address master-write data structure master-read data structure data aa p a a r s slave address data master transfers to slave slave transfers to master a = ack; a = 0: successful, a = 1: unsuccessful s = start condition p = stop condition figure 4. serial-interface data structure
MAX9471/max9472 multiple-output clock generators with dual plls and otp 10 ______________________________________________________________________________________ t r 80% 80% 20% 20% t f clk_ rise and fall time measures between 20% and 80%. figure 5. clk_ rise and fall times 2.2v clk1 or clk2 clk3 or clk4 sda (MAX9471) v dd t fst t po1 t po2 t stop pulse after writing stop edge figure 6. vcxo and pll timing diagram
MAX9471/max9472 multiple-output clock generators with dual plls and otp ______________________________________________________________________________________ 11 applications information crystal selection when using a crystal with the MAX9471/max9472s internal oscillator, connect the crystal to x1 and x2. choose an at-cut crystal that oscillates on its funda- mental mode with ?0ppm and loading capacitance less than 14pf. to achieve a wide vcxo tuning range, select a crystal with motional capacitance greater than 7ff and connect 6pf or less shunt capacitors at x1 and x2 to ground. when the vcxo is used as an oscillator, select both shunt capacitors to be approximately 13pf. the optimal shunt capacitors for achieving minimum frequency offset can be determined experimentally. board layout considerations and bypassing the MAX9471/max9472s?oscillator frequencies make proper layout important to ensure stability. for best per- formance, place components as close as possible to the device. digital or ac transient signals on gnd can create noise at the clock output. return gnd to the highest quality ground available. bypass each v dd and v dda with a 0.1? capacitor, placed as close as possible to the device. careful pc board ground layout minimizes crosstalk between the outputs and digital inputs. chip information process: cmos 14 13 12 11 10 9 8 1 2 3 4 5 6 7 x2 v dd gnd v dd fs0 fs1 x1 top view gnd clk3 clk2 clk1 gnd tune max9472 tssop pd + pin configurations (continued)
MAX9471/max9472 multiple-output clock generators with dual plls and otp 12 ______________________________________________________________________________________ pa cka ge information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps
MAX9471/max9472 multiple-output clock generators with dual plls and otp maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) tssop4.40mm.eps package outline, tssop 4.40mm body 21-0066 1 1 g springer

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