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fractional synthesizer - smt 8 8 - 2 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e 8 ghz 16-bit fractional n synthesizer v02.0908 features functional diagram 8 ghz, 16 bit prescaler ? fractional or integer modes ? ultra low phase noise ? 6 ghz; 50 mhz ref. -103 / -108 dbc/hz @ 20 khz (frac / integer) figure of merit (fom) -221 / -227 dbc/hz (frac / integer) 24 bit step size resolution, 3 hz typ ? 225 mhz, 14bit reference path input ? vco phase step control, micro-degrees ? direct fsk modulation mode ? cycle slip prevention ? read / write serial port, chip id ? 24 lead 4x4mm smt package: 16mm2 ? typical applications base stations for mobile radio ? wimax ? test & measurement ? catv equipment ? phased array applications ? simple fsk links ? dds replacement ?
fractional synthesizer - smt 8 8 - 3 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com electrical specifcations, vddcp, vcccp = 5v 10%; rvdd, avdd, dvddm, vddpfd, dvdd, vddio, dvddq, vccps, avcc = 3v 10%; agnd = dgnd = 0v parameter conditions min typ max units rf input characteristics max rf input frequency (3.3v) 8 9 ghz min rf input frequency 100 200 mhz rf input sensitivity -15 -10 dbm rf input capacitance external match recommended 3 pf 16 bit divider (integer) n divide ratio, 2 16 + 31 32 65,567 16 bit divider (fractional) 2 16 -1 36 65,535 ref input characteristics max ref input frequency (3.3v) 200 225 mhz min ref input frequency 100 200 khz ref input sensitivity ac coupled 500 700 mvpp max ref input dc coupled 0 vdd v ref input capacitance 5 pf 14 bit ref divider range 1 16,383 phase detector max phase detector frequency (frac) 70 105 mhz max phase detector frequency (integ) 140 160 mhz min phase detector frequency 100 khz charge pump max output current 2 ma min output current 500 a charge pump noise input referred, 50 mhz ref -145 dbc/hz HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer general description the HMC700LP4(e) is a sige bicmos fractional n frequency synthesizer. the synthesizer includes a very low noise digital phase frequency detector (pfd), and a precision controlled charge pump. the fractional synthesizer features an advanced delta-sigma modulator design that allows both ultra-fne step sizes and very low spurious products. spurious outputs are low enough to eliminate the need for costly direct digital syn- thesis (dds) references in many applications. the HMC700LP4(e) phase-frequency detector (pfd) features cycle slip prevention (csp) technology that allows faster frequency hopping times. ultra low in-close phase noise and low spurious also permit architectures with wider loop bandwidths for faster frequency hopping and low micro-phonics. phase step mode enables ultra fne phase step capability for phase critical applications. fsk mode allows the synthesizer to be used as a simple low cost direct fm transmitter source.
fractional synthesizer - smt 8 8 - 4 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer absolute maximum ratings nominal 3v supplies to gnd -0.3v to +3.6v nominal 3v digital supply to 3v analog supply -0.3v to +0.3v nominal 5v supply to gnd -0.3v to +5.8v maximum junction temperature +150 c refow soldering peak temperature time at peak temperature 260 c 40 sec operating temperature -40 c to +85 c storage temperature range -65 c to +125 c esd sensitivity (hbm) class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical specifcations, vddcp, vcccp = 5v 10%; rvdd, avdd, dvddm, vddpfd, dvdd, vddio, dvddq, vccps, avcc = 3v 10%; agnd = dgnd = 0v parameter conditions min typ max units logic inputs vih input high voltage vddio-0.4 v vil input low voltage 0.4 v logic outputs voh input high voltage vddio-0.4 v vol input low voltage 0.4 v power supplies rvdd, avdd, vddpfd, avcc, vccps - analog supply avdd should equal dvdd 2.7 3 3.3 v dvdd, dvddm, dvddq - digital supply dvdd v vddio - digital i/o supply logic i/o 1.8 3 5.2 v vddcp, vcccp charge pump supplies vcccp and vddcp must be equal 2.7 5 5.5 v idd - total current consumption 6 ghz operation 95 ma power down current csp disabled 1 10 a csp enabled 450 a bias reference voltage measured with 10 g ohm meter 1.880 1.920 1.960 v phase noise 6 ghz vco, integer mode 20khz offset, 50 mhz fpfd -108 dbc/hz 6 ghz vco, fractional mode 20khz offset, 50 mhz fpfd -103 dbc/hz
fractional synthesizer - smt 8 8 - 5 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer pin number function description 1 sck serial port clock input 2 sdi serial port data input 3 dvdd power supply pin for internal digital circuitry. nominally 3v 4 vddio power supply for digital i/o driver 5 ld_sdo lock detect, main serial data output or vco serial port data out 6 d0 gpo output bit 0, vco serial port le when in vco serial port mode 7 d1 gpo output bit 1, vco serial port clock when in vco serial port mode 8 dvddm power supply for m-counter 9 vccps power supply for prescaler 10 rfip input to the rf prescaler. this small signal input is ac-coupled to the external vco. 11 rfin complementary input to the rf prescaler. this point must be decoupled to the ground plane with a ceramic bypass capacitor, typically 100 pf. 12 avcc power supply pin for the rf section. a decoupling capacitor to the ground plane should be placed as close as possible to this pin. 13 vddcp +5v power supply for charge pump digital section 14 vcccp +5v power supply for the charge pump analog section 15 cp charge pump output 16 vddpfd power supply for the phase frequency detector 17 bias [1] external bypass decoupling for precision bias circuits, 1.920v 20mv [1] 18 avdd power supply for analog ref paths 19 refn reference input (negative or decoupled) 20 refp reference input (positive) 21 rvdd ref path supply 22 dvddq digital supply for substrate 23 ce chip enable 24 sen serial port latch enable input [1] note: bias ref voltage cannot drive an external load. must be measured with 10gohm meter such as agilent 34410a, typical 10mohm dvm will read erroneously. pin descriptions
fractional synthesizer - smt 8 8 - 6 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer figure 1. typical phase noise plots figure 2. comparison of low pfd integer mode w/ high pfd fractional at 1 ghz figure 3. typical phase noise performance vs. charge pump output voltage figure 4. rf divider sensitivity vs. frequency, mode and temperature, +3.3v figure 5. example of cycle slip prevention for frequency hop from 5200 to 3950 mhz figure 6. typical reference sensitivity vs. frequency, 3.3v -170 -160 -150 -140 -130 -120 -110 -100 -90 10 3 10 4 10 5 10 6 10 7 10 8 all plots 50 mhz pfd frequency offset (hz) 5800 mhz integer 5801 mhz fractional 2901 mhz fractional 2900 mhz integer 725 mhz fractional phase noise (dbc/hz) -50 -40 -30 -20 -10 0 10 20 0 50 100 150 200 250 300 frequency (mhz) r = max, +25c r = 3, +85c r = max, +85c r = 3, +25c sensitivity (dbm) 3900 4100 4300 4500 4700 4900 5100 5300 -10 0 10 20 30 40 50 60 70 time (usec) csp on csp off frequency (mhz) -40 -30 -20 -10 0 10 20 0 2000 4000 6000 8000 10000 frequency (mhz) integer fractional +25c +85c fractional integer sensitivity (dbm) -110 -105 -100 -95 -90 -85 -80 0 1 2 3 4 5 6 3800 4200 4600 5000 5400 tuning voltage (v) frequency (mhz) phase noise tuning voltage phase noise (dbc/hz) -170 -150 -130 -110 -90 -70 10 2 10 3 10 4 10 5 10 6 10 7 10 8 frequency offset (hz) -99.5dbc, 1ghz, 200khz pfd = -226.4dbc fom fractional mode 25mhz pfd integer mode 200khz pfd -107dbc, 1ghz, 25mhz pfd = -213dbc fom phase noise (dbc/hz)
fractional synthesizer - smt 8 8 - 7 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer theory of operation the HMC700LP4(e) is targeted for ultra low phase noise applications. the synthesizer has been designed with very low noise reference path, phase detector and charge pump. external vco the HMC700LP4(e) is targeted for ultra low phase noise applications with an external vco. the synthesizer charge pump can operate with the charge pump supply as high as 5.5 volts. the charge pump output at the varactor tuning port, normally can maintain low noise performance to within 500mv of either ground or the upper supply voltage. in some modes of operation the synthesizer can work as close as 100mv to ground or the upper supply voltage, see application notes. figure 7. HMC700LP4(e) synthesizer with external vco high performance low spurious operation the HMC700LP4(e) has been designed for the best phase noise and low spurious content possible in an integrated synthesizer. spurious signals in a synthesizer can occur in any mode of operation and can come from a number of sources. in general spurious can be the result of interference that gets through the loop flter and modulates the input tuning port of the vco directly. it can also result from interference that modulates the vco indirectly through power supplies, ground, or output ports, or bypasses the loop flter due to poor isolation of the flter. it can also simply add to the output of the synthesizer. interference is always present at multiples of the pfd frequency, and the input reference frequency. depending upon the mode of operation of the synthesizer spurious may also occur at integer sub-multiples of the reference frequency. if the fractional mode of operation is used the difference between the vco frequency and the nearest harmonic of the reference, will also create what are referred to as integer boundary spurs. the synthesizer necessarily contains digital circuitry to control the prescaler. the circuitry mostly operates at the pfd frequency. there is more circuitry active in fractional mode, hence more full switching cmos is used and the potential for interference is greater. the HMC700LP4(e) has been designed and tested for ultra-low spurious performance in either integer or fractional mode of operation. reference spurious levels are typically well below -100 dbc, and in-band fractional boundary spurious are typically well below integrated phase noise. reference spurious levels of well below -100 dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the synthesizer and isolation of the vco load from the synthesizer. typical board layout, evaluation boards and application information are available for very low spurious operation. operation with lower levels of isolation in the application circuit board from those recommended by hittite may result in higher spurious levels.
fractional synthesizer - smt 8 8 - 8 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer reference input stage the reference input provides the path from the external reference source to the phase detector. the input stage of the reference path is shown in figure 8. HMC700LP4(e) is a dc coupled, common emitter differential npn buffer. input pins have 1.8v bias on them. expected input is full swing 3v cmos. slightly degraded phase noise performance may result with quasi sine or sine inputs. input reference should have a noise foor better than -155 dbc/hz to avoid degradation of the input reference path. the input reference path phase noise foor is approximately equivalent to -155 dbc/hz. figure 8. reference path input stage ref path r divider the reference path r divider is based on a 14 bit counter and can divide input signals of up to 220 mhz input by values from 1 to 16,383 and is controlled by rdiv ( table 9 ). rf input stage the rf input stage provides the path from the external vco to the phase detector via the fractional divider. the rf input path is rated to operate nominally from 100 mhz to 7 ghz. the HMC700LP4(e) rf input stage is a differential common emitter stage with dc coupling, and is protected by esd diodes as shown in figure 9. the rf input stage is internally matched from a single ended 50 ohm source above about 3.5 ghz, with the complimentary input grounded. if a better match is required at low frequency a simple shunt 50ohm resistor can be used external to the package. figure 9. rf input stage
fractional synthesizer - smt 8 8 - 9 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer rf path n divider the main rf path divider is capable of average divide ratios between 2 16 -1 (65,535) and 36 in fractional mode, and 2 16 + 31 (65,567) to 32 in integer mode. charge pump and phase frequency detector the phase frequency detector or pfd has two inputs, one from the reference path divider and one from the rf path divider. when in lock these two inputs are at the same average frequency and are fxed at a constant average phase offset with respect to each other. we refer to the frequency of operation of the pfd as ? pfd . most formula related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the pfd, ? pfd . the pfd compares the phase of the rf path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full 2 radians input phase difference. pfd test functions phase detector registers are mainly used in test. pfd_phase_sel in table 1 8 allows swapping of the inputs to the phase detector, to allow investigation of any minor effects in feed through. pfd_up_en in table 1 8 allows masking of the pfd up output, which effectively prevents the charge pump from pumping up. pfd_dn_en in table 1 8 allows masking of the pfd down output, which effectively prevents the charge pump from pumping down. de-asserting both pfd_up_en and pfd_dn_en effectively tri-states the charge pump while leaving all other functions operating internally. pfd jitter and lock detect background in normal phase locked operation the divided vco signal arrives at the phase detector in phase with the divided crystal signal, known as the pfd reference signal. despite the fact that the device is in lock, the phase of the vco signal and the pfd reference signal vary in time due to the phase noise of the reference and vco oscillators, the loop bandwidth used and the presence of fractional modulation or not. the total integrated noise from the vco normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. if we wish to detect if the vco is in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. first, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. the standard deviation of the arrival time of the vco signal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked vco has a constant phase noise, 2 (? 0 ), at offsets less than the loop 3 db bandwidth and a 20 db per decade rolloff at greater offsets. the simple locked vco phase noise approximation is shown in figure 10. figure 10. synthesizer phase noise & jitter 2 (? 0 ) 2 (? 0 ) r 2 /hz ? 0 b
fractional synthesizer - smt 8 8 - 10 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com pfd jitter and lock detect background (continued) with this simplifcation the total integrated vco phase noise, f 2 , in rads 2 at the phase detector is given by where f ssb 2 (? 0 ) is the single sideband phase noise in rads 2 /hz inside the loop bandwidth, and b is the 3 db corner frequency of the closed loop pll n is the division ratio of the prescaler the ssb phase jitter of the vco in radians, f ssb , is the square root of the phase noise integral. the rms phase jitter of the vco in radians is f , is two times the ssb phase noise integral, 2 f ssb , since the sidebands are correlated. since the simple integral of (eq 1) is just a product of constants, we can easily do the integral in the log domain. for example if the vco phase noise inside the loop is -100 dbc/hz at 10 khz offset and the loop bandwidth is 100 khz, and the division ratio is 100, then the integrated phase noise at the phase detector, in db, is given by: f 2 db = 10log ( f 2 (? 0 ) b/n 2 ) = -100 +50 +5 -40 = 85dbrads 2 or equivalently, f = 10 -85/20 = 94.4 urads = 5.4 milli-degrees rms. while the phase noise reduces by a factor of 20logn after division to the reference, due to the increased period of the pfd reference signal, the jitter is constant. the rms jitter from the phase noise is then given by t jpn = t pfd f /2 in this example if the pfd reference was 50mhz, t pfd = 20nsec, and hence t jpn = 0.30 psec. a normal 3 sigma variation in the arrival time therefore would be 3t jpn = 0.9 psec. if the synthesizer was in fractional mode, the fractional modulation of the vco divider will dominate the jitter. the exact standard deviation of the divided vco signal will vary based upon the modulator type chosen, however a typical modulator will vary by about 3 division ratios, 4 division ratios, worst case. if, for example a nominal vco at 5 ghz is divided by 100 to equal the pfd reference at 50 mhz, then the worst case division ratios will vary by 100 4. hence the peak variation in the arrival times caused by ? modulation of the fractional synthesizer at the reference will be if we note that the distribution of the delta sigma modulation is approximately gaussian, we could approximate t j?pk as a 3 sigma jitter, and hence we could estimate the rms jitter of the ? modulator as about 1/3 of t j?pk or about 266 psec in this example. hence the total rms jitter t j , expected from the delta sigma modulation plus the phase noise of the vco would be given by the rms sum, where in this example the jitter contribution of the phase noise calculated previously would add only 0.18psec more jitter at the reference, hence we see that the jitter at the phase detector is totally dominated by the fractional modulation. hence, we have to expect about 800psec of normal variation in the phase detector arrival times when in fractional mode. in addition, lower vco frequencies with high pfd reference frequencies will have much larger variations. for example a 1ghz vco operating at near the minimum nominal divider ratio of 36, would according to (eq 2) exhibit about 4nsec of peak variation at the phase detector, under normal operation. HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer (eq 1) (eq 2) (eq 3)
fractional synthesizer - smt 8 8 - 11 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com pfd jitter and lock detect background (continued) in summary, the lock detect circuit must not interpret fractional modulation or normal phase noise related jitter as being out of lock, while at the same time declaring loss of lock when truly out of lock. pfd lock detect lkd_enable in table 1 4 enables the lock detect functions of the HMC700LP4(e). the lock detect circuit in the HMC700LP4(e) places a one shot window around the reference. the one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator. clearing ringosc_oneshot_sel ( table 1 4 ) will result in a fxed analog based nominal 10 nsec window, as shown in figure 11. setting ringosc_oneshot_sel will result in a variable length widow based upon a high frequency internal ring oscillator. the ring oscillator frequency is controlled by ringosc_cfg . the resulting lock detect window period is then generated by the number of ring oscillator periods defned in oneshot_duration , both in ( table 1 4 ). wincnt_max in table 1 4 defnes the number of consecutive counts of the divided vco that must land inside the lock detect window to declare lock. if for example we set wincnt_max = 1000 , then the vco arrival would have to occur inside the 10 nsec widow 1000 times in a row to be declared locked, which results in a lock detect flag high. a single occurrence outside of the window will result in an out of lock, i.e. lock detect flag low. once low, the lock detect flag will stay low until the wincnt_max =1000 condition is met again. the lock detect flag is output to ld_sdo pin according to pfd_ld_open or to the internal spi read only register if locked = 1 ( table 2 1 ). setting pfd_ld_open will display the lock detect flag on ld_sdo except when a serial port read is requested, in which case the pin reverts temporarily to the serial data out pin, and returns to the lock detect flag after the read is completed. timing of the lock detect and serial data out functions are shown in figure 11. figure 11. normal lock detect window when operating in fractional mode the linearity of the charge pump and phase detector are more critical than in in- teger mode. the phase detector linearity is worse when operated with zero phase offset. hence in fractional mode it is necessary to offset the phase of the pfd reference and the vco at the phase detector. in such a case, for example with an offset delay, as shown in figure 1 2 , the vco arrival will always occur after the reference. the lock detect circuit can accommodate a fxed offset delay by setting lkd_win_asym_enable and win_asym_up_sel in table 1 4 . similarly the offset can be in advance of the reference by clearing lkd_win_asym_up_sel while leaving lkd_win_asym_enable set both in table 1 4 . there are certain conditions, such as operating near the supply limits of the charge pump which make it advantageous to use advanced or delayed phase offset, hence both are available. HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 12 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com pfd lock detect (continued) figure 12. delayed lock detect window cycle slip prevention (csp) when the vco is not yet locked to the reference, the instantaneous frequencies of the two paths are different, and the phase difference of the two paths at the pfd varies rapidly over a range much greater than 2 radians. since the gain of the pfd varies linearly with phase up to 2, the gain of a conventional pfd will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. the charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. this can make the vco frequency actually reverse temporarily during locking. this phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in figure 13, and increases the time to lock to a value far greater than that predicted by normal small signal laplace analysis. the HMC700LP4(e) pfd features an ability to virtually eliminate cycle slipping during acquisition. when enabled, the cycle slip prevention (csp) feature essentially holds the pfd gain at maximum until such time as the frequency difference is near zero. cycle slip reduction, allows faster lock times as shown in figure 13. the use of the cycle slip feature is enabled with csp_enable (see table 1 4 ) . the cycle slip reduction feature may be optimized for a given set of pll dynamics by adjusting the pfd sensitivity to cycle slipping. this is achieved by adjusting csp_corr_magn in table 1 3 . figure 13. cycle slip prevention (csp) HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 13 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com charge pump gain a simplifed diagram of the charge pump is shown in figure 14. charge pump up and down gains are set by cp_upcurrent_sel and cpdncurrent_sel respectively ( table 1 6 ). each of the up and dn charge pumps consist of two 500ua current sources and one 1000ua current source. the current gain of the pump in radians/amp is equal to the gain setting of this register divided by 2. for example if both cp_upcurrent_sel and cpdncurrent_sel are set to 010 the output current of each pump will be 1ma and the phase detector gain kp = 1ma/2 radians, or 159ua/rad. charge pump gain trim each of the up and dn pumps may be trimmed to more precise values to improve current source matching or to allow fner control of pump gain. the pump trim controls are 4bits, binary weighted for up and dn, in cp_uptrim_sel and cp_dntrim_sel respectively ( table 1 6 ). lsb weight is 7a, maximum trim is 105a. charge pump phase offset ideally the phase detector operates with zero offset, that is, the divided reference signal and the divided vco signal arrive at the phase detector inputs at exactly the same time. in some modes of operation, such as fractional mode, charge pump linearity and ultimately, phase noise, is better if the vco and reference inputs are operated with a phase offset. normally integer mode of operation is best with no phase offset. a phase offset is implemented by adding a constant dc leakage to one of the charge pumps. dc leakage may be added to the up or dn pumps using chp_ upoffset_sel or chp_dnoffset_sel . these are 3 bit registers with 55a lsb. maximum offset is 385ua. charge pump operation near the rail it should be noted that the charge pump is a non-ideal device. phase locked operation with the tuning voltage very near the positive charge pump supply voltage or very near ground will degrade the phase noise performance of the synthesizer. exactly how close to the supply limits that one should operate is a question of margin needed for the application in question and user judgement. figure 3 . gives some idea of the typical performance near the supply limits. it should be noted that if operation is necessary very near the supply limits, for example less than 500mv from the supply limit, then it is recommended to operate with a dc leakage that leaks in the direction of the supply. for example, if the charge pump supply is 5.5v and locked operation is required with a vco tune voltage of 5.2v, then operating with up leakage on the charge pump will improve operation in this region. similarly if phase locked operation is needed, with a vco tune voltage of say 300mv, then operating with dn leakage is recommended. as an example, if the main pump gain was set at 1ma, an offset of 385ua would represent a phase offset of about (385/1000)*360 = 138degrees. normally it is sufficient to offset the pump by just slightly larger than the delta sigma excursions. figure 14. charge pump gain & offset control HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 14 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com fractional mode fractional frequency tuning the HMC700LP4(e) synthesizer in fractional mode can achieve frequencies at fractional multiples of the reference. the output frequency of the synthesizer is given by where n int is the integer division ratio, an integer number between 36 and 65,567 (see intg table 10) n frac is the fractional part, a number from 1 to 224 see frac table 11 r is the reference path division ratio, see rdiv table 9 ? xtal is the frequency of the reference oscillator input ? pfd is the pfd operating frequency ? xtal / r as an example ? xtal = 50 mhz r = 1 ? pfd = 50 mhz n int = 45 n frac = 1 in this example the output frequency of 2,300,000,002.98 hz is achieved by programming the 10 bit binary value of 46d =2eh = 0000 0000 0010 1110 into intg in table 13. similarly the 24 bit binary value of the fractional word is written into frac in table 1 1 , 16,777,215d = fff fffh = 1111 1111 1111 1111 1111 1111 1d = 000 001h = 0000 0000 0000 0000 0000 0001 example 2: set the output to 4.600 025 ghz using a 100 mhz reference, r=2. find the nearest integer value, n int , n int = 92, f int = 4.600 000 ghz this leaves the fractional part to be ? frac =25 khz here we program the 16 bit n int = 62d = 3e = 000 0000 0110 1110 and since n frac must be an integer number, the actual fractional frequency will be 4,600,025,001.17hz, an error of 1.17hz or 0.00025ppm. here we program the 16 bit nint = 92d = 5ch = 0000 0000 0101 1100 and the 24 bit nfrac = 8389d = 20c5h = 0000 0010 0000 1100 0101 in addition to the above frequency programming words, the fractional mode must be enabled by setting frac_rstb and buffrstb table 1 3 . other dsm confguration registers should be set to the recommended values in the product application note. HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer (eq 4) (eq 5) (eq 6)
fractional synthesizer - smt 8 8 - 15 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com phase step control the synthesizer has the ability to adjust the absolute phase of the vco relative to its current phase with a precision of 180 o /2 23 or about 21.4 micro-degrees. absolute phase control of the vco is based upon fractional control of the vco and hence is independent of the vco frequency. unlike charge pump offset control ( table 1 6 ), this type of phase control does not affect the phase of the divided vco signal at the phase detector. phase control of the vco is enabled by setting phase_adjust_mode table 1 3 . once enabled, phase steps are accomplished by writing a twos complement (signed) value seed register in table 1 2 . the output phase advance of the vco, ? ?, in degrees, is given by for example, to advance the phase of the vco by +2 o , write +93,207 decimal or 016c17hex to seed . if instead we wish to retard the vco by -2 o , we take the twos complement of 016c17h, i.e. fc93e9h. (recall twos complement of a binary number is complement +1. the complement of a hex number, n, is f-n. hence the twos complement of the hex number takes the complement of each hex digit and adds 1.) fsk modulation the HMC700LP4(e) is capable of a simple binary frequency shift keying (fsk) modulation. the internal modulation is unshaped fsk. the loop bandwidth of the synthesizer must be fxed by the user to achieve symbol shaping as required. when the fsk mode of operation is enabled, via fsk_enable ( table 1 3 ), and sen is held high, the synthesizer will output binary fsk frequency hops in response to data input on the sdi pin. when sen is reset, the fsk modulation will stop and return to f 0 . sck must not be toggle when transmitting data in fsk mode. fsk modulation is normally defned by a deviation, ? , and a modulation rate, ? m . the deviation is defned as the difference between the frequency transmitted when input data is 0, ? 0 , and the frequency transmitted when the input data is 1, ? 1 . ? o is the frequency programmed in the frequency registers as was defned in (eq 4), that is: ? 1 is the fractional frequency achieved by adding the value in the seed register to the value in the frac register, that is: where n int is the integer division ratio, an integer number between 36 and 65,567 (see integer register) n frac is the fractional part, a number from 1 to 2 24 n seed is the seed part, a number from 1 to 2 24 r is the reference path division ratio ? ref is the frequency of the external reference input in this case the deviation f is given simply by HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer (eq 7) (eq 8) (eq 9) (eq 10)
fractional synthesizer - smt 8 8 - 16 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com fsk modulation (continued) fsk data bits on sdi will be latched into the synthesizer on the falling edge of the divided reference rate, ? pfd . if for example r=1, and ? ref = 50 mhz, the input fsk data would be oversampled every 20nsec on the falling edge of the input reference. the ? m rate of the fsk data is simply the inverse of twice the period of the data bits. for example, if the data bit period is 1msec the fm rate is 500 hz. if an unshaped binary fsk is desired, the closed loop bandwidth of the synthesizer should be larger than the ? m rate by a sufficient margin. for practical fsk transmissions the ? m rate is limited by the radio link budget, channel spectral emission restrictions and practical closed loop bandwidths of the fractional synthesizer. integer mode the HMC700LP4(e) synthesizer is capable of operating in integer mode. in integer mode the synthesizer step size is fxed to that of the pfd frequency, f pfd . integer mode typically has the lower phase noise for a given pfd operating frequency, than fractional mode. the advantage is usually of the order of 1 to 3 db. integer mode, how- ever, often requires a lower pfd frequency to meet step size requirements. the fractional mode advantage is that higher pfd frequencies can be used, hence lower phase noise can often be realized in fractional mode. traditionally some applications have been forced to use integer mode due to the high fractional spurious content of available fractional synthesizers. the advantage of the HMC700LP4(e) is that it has ultra low spurious content in fractional mode. integer frequency tuning in integer mode the digital ? modulator is shut off and the division ratio of the prescaler is set at a fxed value. to run in integer mode clear frac_rstb and buffrstb table 1 3 . then program the integer portion of the frequency as explained by (eq 4), ignoring the fractional part. soft reset and power on reset the HMC700LP4(e) features a hardware power on reset (por). all chip registers will be reset to default states approximately 250us after power up. the spi registers may also be soft reset by an spi write to strobe register rst_swrst ( table 7 ) power down mode chip power down is normally done by asserting the chip enable, ce, pin 23. asserting ce with no spi overrides, will result in all analog functions and internal clocks disabled. current consumption will typically drop below 1ua in power down state. the serial port will still respond to normal communication in power down mode. it is possible to control power down mode from the serial port register rst_chipen_from_spi by clearing rst_chipen_ pin_select ( table 8 ). note: due to an anomally in the power down circuitry, the cycle slip prevention (csp), reg07<20>, must be disabled to achieve full power down current of typical 1ua. if csp is enabled prior to power down, then power down state leakage current will be about 500ua. diasabling csp after power down will result in the desired 1ua leakage current. toggling csp from on to off and back again, after power down will also result in full 1ua power down state. it is also possible to leave various blocks on when in power down (see table 8 ), including: a. digital clocks b. internal bias reference sources c. pfd block d. charge pump block e. reference path buffer f. vco path buffer g. digital i/o test pads HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 17 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com chip identifcation the version of the synthesizer is described in table 6 . version information may be read from the synthesizer by reading the content of chip_id in reg 00h. serial port typical serial port operation can be run with sck at speeds up to 50mhz. serial port write operation avdd = dvdd = 3v 10%, agnd = dgnd = 0v table 4. timing characteristics parameter conditions min typ max units t 1 sen to sck setup time 8 nsec t 2 sdi to sck setup time 10 nsec t 3 sdi to sck setup time 10 nsec t 4 sck high duration 8 nsec t 5 sck low duration 8 nsec t 6 sen high duration 640 nsec t 7 sen low duration 20 nsec a typical write cycle is shown in figure 15. a. the master (host) both asserts sen (serial port enable) and clears sdi to indicate a write cycle, followed by a rising edge of sck. b. the slave (synthesizer) reads sdi on the 1st rising edge of sck after sen. sdi low initiates the write cycle (/wr). c. host places the six address bits on the next six falling edges of sck, msb frst. d. slave registers the address bits in the next six rising edges of sck (2-7). e. host places the 24 data bits on the next 24 falling edges of sck, msb frst . f. slave registers the data bits on the next 24 rising edges of sck (8-31). g. sen is de-asserted on the 32nd falling edge of sck. h. the 32 nd falling edge of sck completes the cycle. figure 15. serial port timing diagram - write serial port write operation HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 18 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com serial port read operation a typical read cycle is shown in figure 16. a. the master (host) asserts both sen (serial port enable) and sdi to indicate a read cycle, followed by a rising edge sck. note: the lock detect function is multiplexed onto the ld_sdo pin. it is suggested that lock detect (ld) only be considered valid when sen is low. in fact ld will not toggle until the frst active data bit toggles on ld_sdo, and will be restored immediately after the trailing edge of the lsb of serial data out as shown in figure 15. b. the slave (synthesizer) reads sdi on the 1st rising edge of sck after sen. sdi high initiates the read cycle (rd). c. host places the six address bits on the next six falling edges of sck, msb frst. d. slave registers the address bits on the next six rising edges of sck (2-7). e. slave switches from lock detect and places the requested 24 data bits on sd_ldo on the next 24 rising edges of sck (8-31), msb frst . f. host registers the data bits on the next 24 falling edges of sck (8-31). g. slave restores lock detect on the 32nd rising edge of sck. h. sen is de-asserted on the 32nd falling edge of sck. i. the 32nd falling edge of sck completes the read cycle. figure 16. serial port timing diagram - read serial port operation vco serial port the hittite family of synthesizers support switched band vcos using an auxiliary vco serial port. certain hittite synthesizers will also support automatic calibration of switched band vcos. the HMC700LP4(e) supports the vco serial port but does not offer automatic calibration. the vco serial port is a 3 wire serial port that may be used to control external switched band vcos that support serial port control. when confgured, the 3 wire vco serial port uses the following multi-function pins, as shown in figure 16: pin d1 : vco serial port clock (vsck) pin d0: vco serial port latch enable (vsle) pin ld_sdo: vco serial port data out (vsdo) HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 19 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com vco serial port (continued) if the automatic vco serial port function is enabled by setting to_gpo_sdo ( table 2 0 ), and the ld_sdo pad is enabled, via sdo_pad_en ( table 1 5 ) then the vco serial port will automatically transfer the contents of the 10 bit register vcospi_vco_data ( table 1 9 ) when it is written. the vco should be designed to only register the data upon receipt of the latch signal, vsle, on in d0. it should be noted that the vco serial data out (vsdo) shares the multi-function output pin ld_sdo. if a vco serial port transfer is executed, the lock detect (ld) output is temporarily suspended as shown in figure 1 4 . vco serial port write operation dvdd = 3v 10%, dgnd = 0v table 5. timing characteristics parameter conditions min typ max units t 1 vsle to vsdo setup time 8 nsec t 2 vsdo to vsck setup time 10 nsec t 3 vsdo to vsck hold time 10 nsec t 4 vsck high duration 8 nsec t 5 vsck low duration 8 nsec t 6 vsle high duration 8 nsec a typical vco write cycle is shown in figure 17. a. the synthesizer (master) both clears vsle (vco serial port latch) and places data bit d9 (msb) on vsdo. b. the synthesizer places a rising edge on vsck to shift d9 into the vco. c. synthesizer places the next nine data bits on the next six falling edges of vsck, lsb last. d. the synthesizer clocks each data bit on the next nine rising edges of vsck. e. the synthesizer asserts vsle after the falling edge of the 10th vsck, which latches the data into the vco f. the synthesizer clears vsle to complete the cycle. figure 17. serial port timing diagram - write only HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 20 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com general purpose output (gpo) pins the HMC700LP4(e) also supports a simple two pin gpo bus implemented on pins d1 and d0. gpo operation requires that gpo output pads be enabled via gpio_pads_en ( table 1 5 ). two bit arbitrary data may be written to the gpo outputs via register gpo_test , when gpo_select is frst set to 10d ( table 2 0 ). other test waveforms, described in table 20, may be output to the gpo pins according to the value written to gpo_select . if the gpo outputs are not used, and it is desirable that they are as quiet as possible then the gpo pads should be disabled via gpio_pads_en ( table 1 5 ) and gpo_select set to a value that has a static source, such as 10d. register map note: for read operations from register 00h, it is read only containing the chip id. current hittite synthesizer chip ids are shown in table 6. table 6. reg00h id (read only) register bit name width default description [23:0] chip_id 24 375003h part number, description HMC700LP4, 16-bit 5.5v for write operations to register 00h, it is a write only strobe register as defned in table 7. table 7. reg00h rst strobe register bit name width default description [0] rst_swrst 1 1 strobe (write only) generates soft reset. resets all digital and registers to default states. table 8. reg 01h rst register bit name width default description [0] rst_chipen_pin_select 1 1 1 = chip enable via ce pin, ce high puts chip in power down mode, see power down mode description and csp_enable reg07 0 = chip enable via spi (rst_chipen_from_spi), ce pin is ignored [1] rst_chipen_from_spi 1 0 1= chip enable when rst_chipen_pin_select = 0 0= power down when rst_chipen_pin_select = 0 see power down mode description and csp_enable reg07 if rst_chipen_pin_select =1 this register is ignored [2] rst_chipen_digclks_keep_on 1 0 keeps digital clocks on when chip is power down from any source [3] rst_chipen_bias_keep_on 1 0 keeps chip internal bias generators on when chip is power down from any source [4] rst_chipen_pfd_keep_on 1 0 keeps internal pfd block on when chip is power down from any source [5] rst_chipen_chp_keep_on 1 0 keeps internal charge pump block on when chip is power down from any source [6] rst_chipen_refbuf_keep_on 1 0 keeps reference path buffer on when chip is power down from any source [7] rst_chipen_vcobuf_keep_on 1 0 keeps vco path rf buffer on when chip is power down from any source [8] rst_chipen_dig_io_keep_on 1 0 keeps digital io pins on when chip is power down from any source [9] rst_chipen_rdiv_fe_sync 1 0 tri-states the pfd on the next falling edge of the ref clock and also puts the chip to sleep table 9. reg 02h refdiv register bit name width default description [13:0] rdiv 14 1 reference divider r value (eq 4) (refdiven and seldivref must both = 1 to use divider) min 0d max 16383d HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 21 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com table 10. reg 03h frequency register - integer part bit name width default description [15:0] intg 16 1 vco divider integer part, used in all modes, see (eq 4) fractional mode min 36d max 2?16 -1 = 65,535d integer mode min 32d max 2?16+31 = 65,567d table 11. reg 04h frequency - fractional part register bit name width default description [23:0] frac 24 0 vco divider fractional part (24 bit unsigned) see section fractional frequency tuning used in fractional mode only min 0d max 2^24-1 table 12. reg 05h sd seed register bit name width default description [23:0] seed 24 0 fractional mode : seeds fractional modulator phase step mode : sets phase step when phase_adjust_mode=1 (see section phase step control) +180o = 7f ffffh +90o = 40 0000h +45o = 20 0000h ... +21e-6o = 00 0001h (+lsb step) +0o = 00 0000h -21e-6o = ff ffffh (-lsb step) ... -45o = e0 0000h -90o = c0 0000h -180o = 80 0000h fsk mode : sets f1 in fsk mode when fsk_enable=1 (see section fsk modulation) HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 22 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com table 13. reg 06h sd cfg register bit name width default description [7:0] reserved [9:8] order 2 0 select the modulator type 0 - not used 1 - not used 2 - type 1 3 - type 2 [10] frac_rstb 1 0 0 holds the frac core in reset reset is used for integer mode or integer mode with csp [11] buff_rstb 1 0 0 holds the frac core buffers in reset reset is used with frac_rstb=0 for integer mode, no csp [12] bypass_mode 1 0 fractional modulator output is ignored, but fractional modulator continues to be clocked, used to test the isolation of the digital fractional modulator from the vco output in integer mode [13] autoseed_mode 1 1 loads the seed whenever the frac register is written [14] phase_adjust_mode 1 0 phase adjust enable, when enabled, writes to seed register cause vco phase step as per (eq 7) [15] fsk_enable 1 0 enables the fsk mode of operation and fsk input on sdi pin, (see section fsk modulation) [16] reserved 1 0 [17] clkrq_refdiv_sel 1 0 selects the sd clock source 1 = reference divider clock 0 = vco divider clock [18] clkrq_invert_clk 1 0 inverts the selected sd clock [19] sd_spare_out 1 0 spare [23:20] csp_corr_magn 4 8h csp magnitude correction (see section cycle slip prevention (csp)) 0000 low magnitude 1111 high magnitude sign of the correction is determined automatically by the csp state machine see section pfd lock detect for more information about this register. HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 23 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com table 14. reg 07h lkd/csp register bit name width default description [9:0] wincnt_max 10 250h lock detect window sets the number of consecutive counts of divided vco that must land inside the lock detect window to declare lock [10] lkd_enable 1 0 enables internal lock detect function, note output to lock detect flag on ld_ sdo as per figure 13 controlled by pfd_ld_open , reg 0bh pfd register [11] lkd_winasym_enable 1 0 asymmetrical window enables lock detect window to only lag or only lead the divided reference signal at the pfd, see figure 9 [12] lkd_win_asym_up_sel 1 0 1 selects lead window when lkd_winasym_enable=1 0 selects lag window when lkd_winasym_enable=1 [13] ringosc_oneshot_sel 1 0 1 ring osc based one shot for lock detection mode 0 nominal 20nsec analog one shot for lock detection mode [16:14] oneshot_duration 3 0 duration of the ringosc based oneshot pulse in lock detection mode [18:17] ringosc_cfg 2 0 lock detect ringosc frequency trim 00 fastest 11 slowest [18] ringosc_mode 1 0 force ringosc on [20] csp_enable 1 0 cycle slip prevention (csp) enable note: this register must be disabled or toggled off and on after power down via ce or reg01<1> to achieve lowest power down leakage current. see section pfd lock detect for more information about this register. table 15. reg 08h analog en register bit name width default description [0] bias_en 10 1 enables main chip bias reference [1] cp_en 1 1 charge pump enable [2] pfd_en 1 1 pfd enable [3] refbuf_en 1 reference path buffer enable [4] vcobuf_en 1 1 vco path rf buffer enable [5] gpio_pads_en 1 1 gpio pads enable, pins d0 and d1 required for use of gpo port or vco serial port [6] sdo_pad_en 1 1 ld_sdo pad driver enable (pin 5) required for use of lock detect, serial port read operation or vco serial port operation [7] vcodiv_digclk_en 1 1 vco divider output clk to digital enable [8] vcodiv_en 1 0 enable vco divider [9] reserved [10] vcodiv_dutycyc_mode 1 0 vcodiv duty cycle mode stretches the vco divider output when n>32 [11] reserved [12] rdiv_ref_to_dig_en 1 1 reference input applied to digital [13] rdiv_refdiv_to_dig_en 1 1 reference divider applied to digital HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 24 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com charge pump control register. see figure 11 table 16. reg 09h cp register bit name width default description [2:0] cp_upoffset_sel 3 0 charge pump up offset control 55ua/step 000 = 0ua 001 = 55ua 010 = 110ua ... 111 = 385ua [4:3] reserved [7:5] cp_dnoffset_sel 3 0 charge pump dn offset control 55ua/step 000 = 0ua 001 = 55ua 010 = 110ua ... 111 = 385ua [9:8] reserved [13:10] cfg cp_uptrim_sel 4 0 charge pump up current trim 7ua/step 0000 = 0ua 0001 = 7ua 0010 = 14ua 0100 = 28ua 1000 = 56ua 1111 = 105ua [17:14] cp_dntrim_sel 4 0 charge pump dn current trim 7ua/step 0000 = 0ua 0001 = 7ua 0010 = 14ua 0100 = 28ua 1000 = 56ua 1111 = 105ua [20:18] cp_upcurrent_sel 3 0 charge pump up main current control 500ua step 000 tristate if pfd also disabled 001 500ua 010 1000ua 011 1500ua 100 2000ua 101 2000ua 110 2000ua 111 2000ua [23:21] cp_dncurrent_sel 3 0 charge pump up main current control 500ua step 000 tristate if pfd also disabled 001 500ua 010 1000ua 011 1500ua 100 2000ua 101 2000ua 110 2000ua 111 2000ua HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 25 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com table 17. reg 0ah cp op amp register bit name width default description [1:0] cp_opamp_bias_sel 2 0 charge pump op-amp bias select 11 - 540ua 10 - 689 01 - 943ua 11 - 1503ua opamp is expected to improve linearity with increased bias enabled with chg pump enable table 18. reg 0bh pfd register bit name width default description [2:0] pfd_del_sel 3 0 sets pfd reset path delay [3] pfd_phase_sel 1 0 swaps the pfd inputs 1 positive vco tuning slope, kvco 0 negative vco tuning slope, kvco [4] pfd_up_en 1 1 enables the pfd up output according to state of pfd_mute_when_locked_enable, see reg0b<9> [5] pfd_dn_en 1 1 enables the pfd dn output according to state of pfd_mute_when_locked_enable, see reg0b<9> [6] pfd_ld_open 1 1 pfd lock detect output enable, enables lock detect fag output to ld_sdo pin [7] pfd_pullup_ctrl 1 0 forces pfd up output on [8] pfd_puldn_ctrl 1 0 forces pfd dn output on [9] pfd_mute_when_locked_ enable 1 0 1: if set: when locked disables up if pfd_up_en=1 when locked disables dn if pfd_dn_en=1 when not locked, allows both up and dn to be active and ignores pdf_up_en and pfd_dn_en 0: if clear, pfd_dn_en and pfd_up_en enable up and dn outputs at all times [10] spare0 1 0 reserved [11] spare1 1 0 reserved table 19. reg 0ch vco spi register bit name width default description [9:0] vcospi_vco_data 10 0 data register contents, when written automatically outputs this data via vco spi when to_gpo_sdo=1 reg09<7> HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 26 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com table 20. reg 0dh gpo_spi_rdiv register bit name width default description [3:0] gpo_select 4 0 test signals selected here are output to gpo pins when gpo_pads_en=1 ( table 15 ) d0 & d1 0: clk_vcodiv & clk_refdiv 1: pfd_up & pfd_dn 2: refoutdg & refdivoutdg 3: seed_stb_sypulse_test & frac_stb_sypulse_test 4: intg_inbuff_enable_test & clk_sd 5: oneshot_trigg_test & oneshot_pulse_test 6: 0 & ringosc_test 7: csp_corr_add & csp_corr_sub 8: pfd_sat_refdiv & pfd_sat_vcodiv 9: (csp_corr_add or csp_corr_sub) & pfd_sat_rstb 10: gpo_test , see reg0d<5:4> 11: not used 12: not used 13: not used 14: not used 15: not used [5:4] gpo_test 2 0 data written to this register is output to d0 and d1 pins when gpo_select = 10d [6] refclkdiv4 1 0 1: sel ref divby4 for clocking the vco_spi 0: sel ref divby1 for clocking the vco_spi [7] to_gpo_sdo 1 0 enable the automatic output of vcospi_vco_data to ld_sdo output vco_spi clock to d1 (see reg0d<6> ) output vco_spi en to d0 table 21. reg 0fh ld state register (read only) bit name width default description [0] locked 3 0 read only lock detect fag, 1 when locked HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer
fractional synthesizer - smt 8 8 - 27 for price, delivery, and to place orders, please contact hittite microwave corporation: 20 alpha road, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com HMC700LP4 / 700lp4e v02.0908 8 ghz 16-bit fractional n synthesizer outline drawing part number package body material lead finish msl rating package marking [3] HMC700LP4 low stress injection molded plastic sn/pb solder msl1 [1] h700 xxxx HMC700LP4(e) rohs-compliant low stress injection molded plastic 100% matte sn msl1 [2] h700 xxxx [1] max peak refow temperature of 235 c [2] max peak refow temperature of 260 c [3] 4-digit lot number xxxx package information notes: 1. leadframe material: copper alloy 2. dimensions are in inches [millimeters]. 3. lead spacing tolerance is non-cumulative 4. pad burr length shall be 0.15mm maximum. pad burr height shall be 0.05mm maximum. 5. package warp shall not exceed 0.05mm. 6. all ground leads and ground paddle must be soldered to pcb rf ground. 7. refer to hittite application note for suggested pcb land pattern. evaluation pcb please reference HMC700LP4 product note for information on evaluation pcb kit and list of materials.

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