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integrated circuit systems, inc. ics91857 0494c?08/15/05 block diagram value sstl_2 clock driver (60mhz - 220mhz) pin configuration 48-pin tssop recommended application: zero delay board fan-out memory modules product description/features: meets pc3200 specification for ddri-400 support low skew, low jitter pll clock driver 1 to 10 differential clock distribution (sstl_2) feedback pins for input to output synchronization pd# for power management spread spectrum tolerant inputs auto pd when input signal removed switching characteristics: cycle - cycle jitter (>100mhz):<75ps output - output skew: <100ps s t u p n is t u p t u o e t a t s l l p d d v a# d pt n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f d n gh l h lh l h f f o / d e s s a p y b d n gh h l hl h l f f o / d e s s a p y b v 5 . 2 ) m o n ( ll hzzz z f f o v 5 . 2 ) m o n ( lh lzzz z f f o v 5 . 2 ) m o n ( hl hlhl h n o v 5 . 2 ) m o n ( hh l hlh l n o v 5 . 2 ) m o n ( x) z h m 0 2 < ) 1 ( zz z z f f o functionality pll fb_int fb_inc clk_inc clk_int pd# control logic fb_outt fb_outc clkt0 clkt1 clkt2 clkt3 clkt4 clkt5 clkt6 clkt7 clkt8 clkt9 clkc0 clkc1 clkc2 clkc3 clkc4 clkc5 clkc6 clkc7 clkc8 clkc9 6.10 mm. body, 0.50 mm. pitch tssop gnd clkc0 clkt0 vdd clkt1 clkc1 gnd gnd clkc2 clkt2 vdd vdd clk_int clk_inc vdd avdd agnd gnd clkc3 clkt3 vdd clkt4 clkc4 gnd gnd clkc5 clkt5 vdd clkt6 clkc6 gnd gnd clkc7 clkt7 vdd pd# fb_int fb_inc vdd fb_outc fb_outt gnd clkc8 clkt8 vdd clkt 9 clkc 9 gnd ics91 8 57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 48 47 46 45 44 43 42 41 40 3 9 38 37 36 35 34 33 32 31 30 2 9 28 27 26 25
2 ics91857 0494c?08/15/05 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 1 2 , 5 1 , 2 1 , 1 1 , 4 , 5 4 , 8 3 , 4 3 , 8 2 d d vr w p . 3 3 3 r d d o t p u v 5 . 2 y l p p u s r e w o p . z h m 0 0 4 t a i - r d d r o f v 6 . 2 y l p p u s r e w o p , 5 2 , 4 2 , 8 1 , 8 , 7 , 1 8 4 , 2 4 , 1 4 , 1 3 d n gr w pd n u o r g 6 1d d v ar w p . 3 3 3 r d d o t p u v 5 . 2 , y l p p u s r e w o p g o l a n a . z h m 0 0 4 t a i - r d d r o f v 6 . 2 y l p p u s r e w o p 7 1d n g ar w p. d n u o r g g o l a n a , 6 4 , 4 4 , 9 3 , 9 2 , 7 2 3 , 5 , 0 1 , 0 2 , 2 2 ) 0 : 9 ( t k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " , 7 4 , 3 4 , 0 4 , 0 3 , 6 2 2 , 6 , 9 , 9 1 , 3 2 ) 0 : 9 ( c k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " 4 1c n i _ k l cn it u p n i k c o l c e c n e r e f e r " y r a t n e m e l p m o c " 3 1t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " 3 3c t u o _ b ft u o t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " y r a t n e m e l p m o c " d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a s e h c t i w s . c n i _ b f o t 2 3t t u o _ b ft u o t a s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " e u r t " . t n i _ b f o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t 6 3t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " . r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s 5 3c n i _ b fn i l l p l a n r e t n i e h t o t l a n g i s s e d i v o r p , t u p n i k c a b d e e f " y r a t n e m e l p m o c " . r o r r e e s a h p e t a n i m i l e o t c n i _ k l c h t i w n o i t a z i n o r h c n y s r o f 7 3# d pn it u p n i s o m c v l . n w o d r e w o p this pll clock buffer is designed for a v dd of 2.5v, an av dd of 2.5v and differential data input and output levels. ics91857 is a zero delay buffer that distributes a differential clock input pair (clk_inc, clk_int) to ten differential pair of clock outputs (clkt[0:9], clkc[0:9]) and one differential pair feedback clock output (fb_out, fb_outc). the clock outputs are controlled by the input clocks (clk_inc, clk_int), the feedback clocks (fb_int, fb_inc) the 2.5- v lvcmos input (pd#) and the analog power input (av dd ). when input (pd#) is low while power is applied, the receivers are disabled, the pll is turned off and the differential clock outputs are tri-stated. when av dd is grounded, the pll is turned off and bypassed for test purposes. when the input frequency is less than the operating frequency of the pll, appproximately 20mhz, the device will enter a low power mode. an input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (pd#) input is low. when the input frequency increases to greater than approximately 20 mhz, the pll will be turned back on, the inputs and outputs will be enabled and pll will obtain phase lock between the feedback clock pair (fb_int, fb_inc) and the input clock pair (clk_inc, clk_int). the pll in the ics91857 clock driver uses the input clocks (clk_inc, clk_int) and the feedback clocks (fb_int, fb_inc) provide high-performance, low-skew, lo w-jitter output differential clocks (clkt [0:9], clkc [0:9]). the ics91857 is also able to track spread spectrum clock (ssc) for reduced emi. ics91857 is characterized for operation from 0c to 70c and will meet jedec standard 82-1 and 82-1a for registered ddr clock driver.
3 ics91857 0494c?08/15/05 absolute maximum ratings supply voltage (vdd & avdd) . . . . . . . . . . -0.5v to 4.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics for ddr200/266/333 - input/supply/common output parameters t a = 0 - 70c; supply voltage a vdd , v dd = 2.5v 0.2v (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2. 5 c l = 0pf @ 200mhz 260 ma i ddpd c l = 0pf 100 ma output high current i oh v dd = 2.3v, v out = 1v -18 -32 ma output low current i ol v dd = 2.3v, v out = 1.2v 26 35 ma high impedance out p ut current i oz v dd =2.7v, vout=v dd or gnd 10 ma input clamp voltage v ik v ddq = 2.3v iin = -18ma -1.2 v v dd = min to max, i oh = -1 ma v ddq - 0.1 v v ddq = 2.3v, i oh = -12 ma 1.7 v v dd = min to max i ol =1 ma 0.1 v v ddq = 2.3v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 3pf output capacitance 1 c out v out = gnd or v dd 3pf 1 guaranteed by design at 170mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
4 ics91857 0494c?08/15/05 electrical characteristics for ddri-400 - input/supply/common output parameters t a = 0 - 70c; supply voltage a vdd , v dd = 2.6v 0.1v parameter symbol conditions min typ max units input high current i ih v i = v dd or gnd 5 a input low current i il v i = v dd or gnd 5 a i dd2.5 c l = 0pf @ 200mhz 260 ma i ddpd c l = 0pf 100 ma output high current i oh v dd = 2.3v, v out = 1v -18 -32 ma output low current i ol v dd = 2.3v, v out = 1.2v 26 35 ma high impedance out p ut current i oz v dd =2.7v, vout=v dd or gnd 10 ma input clamp voltage v ik v ddq = 2.3v iin = -18ma -1.2 v v dd = min to max, i oh = -1 ma v ddq - 0.1 v v ddq = 2.3v, i oh = -12 ma 1.7 v v dd = min to max i ol =1 ma 0.1 v v ddq = 2.3v i oh =12 ma 0.6 v input capacitance 1 c in v i = gnd or v dd 3pf output capacitance 1 c out v out = gnd or v dd 3pf 1 guaranteed by design at 220mhz, not 100% tested in production. operating supply current high-level output voltage v oh low-level output voltage v ol
5 ics91857 0494c?08/15/05 recommended o p eratin g condition for ddr200/266/333 ( see note1 ) t a = 0 - 85c; supply voltage avdd, vdd = 2.5v 0.2v (unless otherwise stated) parameter symbol conditions min typ max units supply voltage v ddq , a vdd 2.3 2.7 v clkt, clkc, fb_inc v ddq /2 - 0.18 v pd# -0.3 0.7 v clkt, clkc, fb_inc v ddq /2 + 0.18 v pd# 1.7 v ddq + 0.6 v dc input signal voltage ( note 2 ) -0.3 v ddq v dc - clkt, fb_int 0.36 v ddq + 0.6 v ac - clkt, fb_int 0.7 v ddq + 0.6 v output differential cross - volta g e ( note 4 ) v ox v ddq /2 - 0.15 v ddq /2 + 0.15 v input differential cross- voltage (note 4) v ix v ddq /2 - 0.2 v ddq /2 + 0.2 v high level output current i oh 0.12 ma low level output current i ol 12 ma input slew rate s r 14v/ns operating free-air temperature t a 070c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v cc and is the voltage at which the differential signal must be crossing.
6 ics91857 0494c?08/15/05 recommended o p eratin g condition for ddri-400 ( see note1 ) t a = 0 - 70c; supply voltage avdd, vdd = 2.6v 0.1v parameter symbol conditions min typ max units supply voltage v ddq , a vdd 2.5 2.6 2.7 v clkt, clkc, fb_inc v ddq /2 - 0.18 v pd# -0.3 0.7 v clkt, clkc, fb_inc v ddq /2 + 0.18 v pd# 1.7 v ddq + 0.3 v dc input signal voltage ( note 2 ) -0.3 v ddq v dc - clkt, fb_int 0.36 v ddq + 0.6 v ac - clkt, fb_int 0.7 v ddq + 0.6 v output differential cross - volta g e ( note 4 ) v ox v ddq /2 - 0.15 v ddq /2 + 0.15 v input differential cross- voltage (note 4) v ix v ddq /2 - 0.2 v ddq /2 + 0.2 v high level output current i oh 12 ma low level output current i ol -12 ma input slew rate s r 14v/ns operating free-air temperature t a 070c differential input signal voltage (note 3) v id low level input voltage v il high level input voltage v ih notes: 1. unused inputs must be held high or low to prevent them from floating. 2. dc input signal voltage specifies the allowable dc execution of differential input. 3. differential inputs signal voltages specifies the differential voltage [vtr-vcp] required for switching, where vt is the true input level and vcp is the complementary input level. 4. differential cross-point voltage is expected to track variations of v cc and is the voltage at which the differential signal must be crossing.
7 ics91857 0494c?08/15/05 notes: 1. refers to transition on noninverting output in pll bypass mode. 2. switching characteristics guaranteed for application frequency range. 3. static phase offset shifted by design. timin g re q uirements for ddri-400 t a = 0 - 70c; supply voltage a vdd , v dd = 2.6v 0.1v parameter symbol conditions min max units max clock frequency freq op 2.6v 0.1v 60 230 mhz application frequency range freq app 2.6v 0.1v 95 220 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 100 s switching characteristics for ddr200/266/333 parameter symbol condition min typ max units low-to high level propagation delay time t plh 1 clk_in to any output 3.5 ns high-to low level propagation dela y time t pll 1 clk_in to any output 3.5 ns output enable time t en pd# to any output 3 ns output disable time t dis pd# to any output 3 ns period jitter t jit (per) 100 - 200 mhz -75 75 ps half-period jitter t (j it_h p er ) 100 - 200 mhz -75 75 input clock slew rate t ( sir_i ) 14v/ns output clock slew rate t (sl_o) 12v/ns cycle to cycle jitter 1 t c y c -t c y c 100 - 200 mhz -75 75 ps static phase offset t ( s p o ) 3 -50 0 50 ps output to output skew t skew 100 ps pulse skew t skewp 100 ps timing requirements for ddr200/266/333 t a = 0 - 70c; supply voltage a vdd , v dd = 2.5v 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v 0.2v @ 25c 60 170 mhz application frequency range freq app 2.5v 0.2v @ 25c 95 170 mhz input clock duty cycle d tin 40 60 % clk stabilization t stab 100 s
8 ics91857 0494c?08/15/05 switching characteristics for ddri-400 parameter symbol condition min typ max units low-to high level propagation delay time t plh 1 clk_in to any output 3.5 ns high-to low level propagation dela y time t pll 1 clk_in to any output 3.5 ns output enable time t en pd# to any output 3 ns output disable time t dis pd# to any output 3 ns period jitter t jit (per) 100 - 200 mhz -50 50 ps half-period jitter t (j it_h p er ) 100 - 200 mhz -75 75 input clock slew rate t ( sir_i ) 14v/ns output clock slew rate t (sl_o) 12v/ns cycle to cycle jitter 1 t c y c -t c y c 100 - 200 mhz -75 75 ps static phase offset t ( s p o ) 3 -50 0 50 ps output to output skew t skew 75 ps pulse skew t skewp 100 ps notes: 1. refers to transition on noninverting output in pll bypass mode. 2. switching characteristics guaranteed for application frequency range. 3. static phase offset shifted by design.
9 ics91857 0494c?08/15/05 gnd ics 9 1857 v dd v dd /2 v (clkc) v (clkc) scope c=14p f -vdd/2 -vdd/2 -vdd/2 vdd/2 z=60 ? z=60 ? z=50 ? z=50 ? r=10 ? r=10 ? r=50 ? r=60 ? r=60 ? r=50 ? v (tt) v (tt) c=14pf note: v (tt) = gnd t c(n) t c(n+1) t jit(cc) =t c(n) t c(n+1) figure 1. ibis model output load figure 2. output load test circuit y , fboutc x y , fboutt x parameter measurement information ics 9 1857 figure 3. cycle-to-cycle jitter
10 ics91857 0494c?08/15/05 (n is a large number of samples) t ( ) n+1 t ()n t () = 1 n=n t ()n n clk_inc clk_int fb_inc fb_int t (sk_o) y # x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y , fb_outc x y , fb_outt x y x parameter measurement information figure 4. static phase offset figure 5. output skew 1 f o t = t - (jit_per) c(n) 1 f o figure 6. period jitter
11 ics91857 0494c?08/15/05 clock inputs and outputs 80% 20% 80% 20% t slrr(i) t slrf(i) slrf(o) v id ,v od figure 8. input and output slew rates parameter measurement information t (hper_n) t (hper_n+1) 1 f o y , fb_outc x y , fb_outt x figure 7. half-period jitter t =- (jit_hper) t (jit_hper_n) 1 2xf o
12 ics91857 0494c?08/15/05 ordering information ics91857 y glft designation for tape and reel packaging rohs compliant (optional) pattern number package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y g - ppp - lf - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10 - 0 0 3 9 symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, m o-153
13 ics91857 0494c?08/15/05 designation for tape and reel packaging rohs compliant (optional) pattern number package type l = tssop (tvsop) revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxx y l - ppp - lf -t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c ordering information ics91857 yllft min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.13 0.23 .005 .009 c 0.09 0.20 .0035 .008 d e e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n a0 8 0 8 aaa -- 0.08 -- .003 variations min max min max 48 9.60 9.80 .378 .386 10 - 0 0 3 7 n d mm. d ( inch ) reference do c.: jedec p ublicatio n 95, m o-153 0.40 basic 0.016 basic see variations see variations see variations see variations 6.40 basic 0.252 basic symbol in millimeters in inches common dimensions common dimensions 4.40 mm. body, 0.40 mm. pitch tssop (tvsop) (173 mil) (16 mil)
14 ics91857 0494c?08/15/05 revision history rev. issue date description page # c 8/15/2005 added lf ordering information. 12-13

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