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rev: 1.03 10/2001 1/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp 128k x 8 1 mb asynchronous sram 8 ns 3.3 v v dd center v dd and v ss tsop commercial temp industrial temp features ? fast access time: 8 ns ? cmos low power operation: 150 ma at minimum cycle time ? single 3.3 v 0.3 v power supply ? all inputs and outputs are ttl-compatible ? fully static operation ? industrial temperature option: ? 40 to 85c ? package line up tp: 400 mil, 32 -pin tsop type ii package description the gs 7 1 2 08 is a high speed cmos static ram organized as 131,072 words by 8 bits. static design eliminates the need for external clocks or timing strobes. the gs operates on a single 3.3 v power supply and all inputs and outputs are ttl-com- patible. the gs 7 1 2 08 is available in a 400 mil tsop type-ii package. pin descriptions tsop-ii 128k x 8-pin configuration symbol description a 0 ? a 16 address input dq 1 ? dq 8 data input/output ce chip enable input we write enable input oe output enable input v dd +3.3 v power supply v ss ground nc no connect 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 3 a 2 a 1 a 0 ce dq 1 dq 2 v dd v ss dq 3 dq 4 we a 16 a 15 a 14 a 13 a 4 a 5 a 6 a 7 oe dq 8 dq 7 v ss v dd dq 6 dq 5 a 8 a 9 a 10 a 11 a 12 32-pin 400 mil tsop ii
rev: 1.03 10/2001 2/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp note: x: ?h? or ?l? truth table ce oe we dq 1 to dq 8 v dd current h x x not selected isb 1 , isb 2 l l h read i dd l x l write l h h high z memory array row decoder column decoder address input buffer control i/o buffer a 0 ce we oe dq 1 a 16 block diagram dq 8 rev: 1.03 10/2001 3/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation shall be restricted to rec- ommended operating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. note: 1. input overshoot voltage should be less than v dd +2 v and not exceed 20 ns. 2. input undershoot voltage should be greater than ? 2 v and not exceed 20 ns. notes: 1. tested at t a = 25c, f = 1 mhz 2. these parameters are sampled and are not 100% tested. absolute maximum ratings parameter symbol rating unit supply voltage v dd ? 0.5 to +4.6 v input voltage v in ? 0.5 to v dd +0.5 ( 4.6 v max.) v output voltage v out ? 0.5 to v dd +0.5 ( 4.6 v max.) v allowable power dissipation pd 0.7 w storage temperature t stg ? 55 to 150 o c recommended operating conditions parameter symbol min typ max unit supply voltage for - 8 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 ? v dd +0.3 v input low voltage v il ? 0.3 ? 0.8 v ambient temperature, commercial range t ac 0 ? 70 o c ambient temperature, industrial range t a i ? 40 ? 85 o c capacitance parameter symbol test condition max unit input capacitance c in v in = 0 v 5 pf output capacitance c out v out = 0 v 7 pf rev: 1.03 10/2001 4/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd ? 1 ua 1 ua output leakage current i lo output high z v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh i oh = ? 4ma 2.4 ? output low voltage v ol i lo = +4ma ? 0.4 v power supply currents parameter symbol test conditions 0 to 70c ? 40 to 85c 8 ns 8 ns operating supply current i dd (max) ce v il all other inputs 3 v ih or v il min. cycle time i out = 0 ma 150 ma 160 ma standby current i sb1 (max) ce 3 v ih all other inputs 3 v ih or v il min. cycle time 55 ma 65 ma standby current i sb2 (max) ce 3 v dd ? 0.2 v all other inputs 3 v dd ? 0.2 v or 0.2 v 15 ma 25 ma rev: 1.03 10/2001 5/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp ac test conditions ac characteristics * these parameters are sampled and are not 100% tested read cycle parameter symbol -8 unit min max read cycle time t rc 8 ? ns address access time t aa ? 8 ns chip enable access time ( ce ) t ac ? 8 ns output enable to output valid ( oe ) t oe ? 3.5 ns output hold from address change t oh 3 ? ns chip enable to output in low z ( ce ) t lz * 3 ? ns output enable to output in low z ( oe ) t olz * 0 ? ns chip disable to output in high z ( ce ) t hz * ? 4 ns output disable to output in high z ( oe ) t ohz * ? 3.5 ns dq vt = 1.4 v 50 w 30pf 1 dq 3.3 v output load 1 output load 2 589 w 434 w 5pf 1 note: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. output load 2 for t lz , t hz , t olz and t ohz parameter conditions input high level v ih = 2.4 v input low level v il = 0.4 v input rise time tr = 1 v/ns input fall time tf = 1 v/ns input reference level 1.4 v output reference level 1.4 v output load fig. 1& 2 rev: 1.03 10/2001 6/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp read cycle 1: ce = oe = v il , we = v ih read cycle 2: we = v ih t aa t oh t rc address data out previous data data valid t aa t rc address t ac t lz t oe t olz ce oe data out t hz t ohz d a t a v a l i d high impedance rev: 1.03 10/2001 7/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp * these parameters are sampled and are not 100% tested write cycle parameter symbol -8 unit min max write cycle time twc 8 ? ns address valid to end of write taw 5.5 ? ns chip enable to end of write tcw 5.5 ? ns data set up time tdw 4 ? ns data hold time tdh 0 ? ns write pulse width twp 5.5 ? ns address set up time tas 0 ? ns write recovery time ( we ) twr 0 ? ns write recovery time ( ce ) twr1 0 ? ns output low z from end of write twlz * 3 ? ns write to output in high z twhz * ? 3.5 ns rev: 1.03 10/2001 8/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp write cycle 1: we control write cycle 2: ce control t wc address ce we data in oe data out t aw t cw t as t wp t wr t dw t dh t wlz t whz d a t a v a l i d h i g h i m p e d a n c e t wc address ce we data in oe data out t aw t wp t as t cw t wr1 t dw t dh d a t a v a l i d h i g h i m p e d a n c e rev: 1.03 10/2001 9/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp 32-pin tsop-ii, 400mil d 1 32 e b q a a 1 a 2 y c detail a e 1 e l a zd l 1 note: 1.dimension d includes mold flash, protrusions or gate burrs. 2. dimension e does not include interlead flash. 3. controlling dimension: mm symbol dimension in inch dimension in mm min nom max min nom max a 0.039 ? 0.05 ? ? 1.27 a1 0.002 ? 0.006 0.01 ? 0.15 a2 0.037 0.040 0.045 0.90 1.02 1.14 b 0.012 0.016 0.018 0.30 0.40 0.45 c 0.0047 0.0051 0.0062 0.12 0.13 0.16 d 0.820 0.825 0.830 20.82 20.95 21.08 zd ? 0.037 ? ? 0.95 ? e 0.455 0.463 0.471 11.56 11.76 11.96 e1 0.395 0.400 0.405 10.03 10.16 10.29 e ? 0.05 ? ? 1.27 ? l 0.017 0.020 0.023 0.40 0.50 0.60 l1 0.024 0.031 0.039 0.60 0.80 1.00 y 0.00 ? 0.003 0.00 ? 0.76 q 0 o ? 5 o 0 o ? 5 o rev: 1.03 10/2001 10/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp * customers requiring delivery in tape and reel should add the character ?t? to the end of the part number. for example: gs 7 1 2 08 tp-8t ordering information part number * package access time temp. range status GS71208TP-8 400 mil tsop-ii 8 ns commercial rev: 1.03 10/2001 11/11 ? 1999, giga semiconductor, inc. specifications cited are subject to change without notice. for latest documentation see http://www.gsitechnology.com. gs7 1 2 08 tp revision history rev. code: old; new types of changes format or content page #/revisions/reason 1.0 0 12/1999 / 1.0 1 12/1999 content 1. added tp package to 71208 gs 7 1 2 08 rev 1.0 1 12/1999 krev 1 .0 1 2/2000l format/content ? gsi logo added dimension d to 32 pin 400 ml tsop ii package. 71208_r1_01; 71208_r1_02 format/content ? updated format to comply with technical publications standard ? specifically noted that numbers in power supply currents table are worst case scenario 71208_r1_02; 71208_r1_03 content ? removed all references to other parts except 71208tp-8 |
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