1 features ? pci 2.1 compliant supports 33/66 mhz operation master and slave support 32-bit address and data transfers supports variable burst size transfers performs zero wait state transfers master capable of performing i/o, memory and configuration types of transfers master supports byte mode operation master capable of performing memory write invalidate and memory read line operations performs back-to-back transfers fully synchronous design approximately 12k gates slave supports up to six address ranges verilog-hdl based design includes comprehensive test environment (complete results listed in this document) system overview overview the ATPCI-SSP8000-32 is a fully synthesizable core that can be implemented in any atmel asic library (gate array or standard cell). the core is supported by a compre- hensive pci test environment that can be used to verify the entire design, including the application. the pci core can be used in any application that requires a 32-bit master or slave core at either 33 or 66 mhz. the interface to the application consists of a master interface, a slave interface and a configuration interface. pci bus pci peripheral application 32-bit pci core 32-bit pci asic core atpci- ssp8000-32 summary rev. 1665as ? 07/01 note: this is a summary document. a complete document is avail- able under nda. for more information, please contact your local atmel sales office.
ATPCI-SSP8000-32 2 core block diagram pci interface this block communicates with the slave, configuration and master data paths and address paths to generate appropri- ate transfers on the pci bus. pad control, data multiplexing and parity generation and detection logic are performed in this block. master engine this block handles master cycles, retries, command gener- ation and data transfers. it also handles memory write invalidate (mwi) and memory read line (mrl) transfers. it generates handshake signals to communicate with the application. slave engine this block handles address decode, command decode and generation of slave pci cycles. it is capable of performing burst transfers. up to six address ranges can be configured. configuration this block has the configuration logic of the pci core. it is programmable to accommodate multiple base address reg- isters. it can be addressed from both application and slave interfaces. configuration logic pci interface master engine slave engine
ATPCI-SSP8000-32 3 pin diagram application signals pci signals atpci-ssp8000 ad[31:0] cbe_n[3:0] clk rst_n frame_n irdy_n trdy_n stop _n idsel devsel_n pa r perr_n serr_n req_n gnt_n lock_n a2m_xfr_req a2m_pci_addr[31:0] a2m_req_len[7:0] a2m_req_type[3:0] a2m_full_dw m2a_req_ack m2a_xfr_start m2a_active a2m_wrok a2m_rdok m2a_xfrdn m2a_xfr_sts m2a_wrnext m2a_wrdt[31:0] m2a_wrbe[3:0] a2m_wrdt[31:0] a2m_wrbe[3:0] m2a_rdnext s2a_cycle s2a_mem_cycle s2a_write s2a_wrdt[31:0] s2a_wrbe[3:0] s2a_next s2a_addr s2a_range a2s_rdok a2s_wrok a2s_endxfr a2s_rddt[31:0] a2c_init_done a2c_cfg_addr[3:0] a2c_wrdt[31:0] a2c_wrbe[3:0] pci bus interface master engine slave engine config. logic
ATPCI-SSP8000-32 4 pci ? bus signals table 1. pci interface pin name direction description ad [31:0] i/o pci address and data are multiplexed on the same pins. a bus transaction consists of an address phase followed by one or more data phases. during data phase, ad[7:0] contains the least significant byte, and ad[31:28] contains the most significant byte. these are tristate signals. cbe_n[3:0] i/o command and byte enables are multiplexed on the same pins. commands during the address phase of the pci transfer and byte enables during the data phase of the transfer are provided on this bus. these are bidirectional, tristate signals. clk input this is the pci clk. this determines the clock frequency of the pci system. a 30 ns period is used for 33 mhz frequency. all other pci signals except rst_n, inta_n, intb_n, intc_n and intd_n are sampled on the rising edge of clk. rst_n input this is an active-low signal to indicate a reset condition on the pci system. all pci-specific registers, sequencers and signals are reset. frame_n i/o this is an active-low signal indicating the start of a master transfer. frame continues to be asserted during the duration of the master cycle. when frame is deasserted, the transaction is in the final data phase or has completed. irdy_n i/o initiatorready indicates the initiating agent ? s (bus master ? s) ability to complete the current data phase of the transaction. a data phase is completed on any clock when both irdy_n and trdy_n are asserted. trdy_n i/o targetready indicates the target device ? s ability to complete the current data phase of the transaction. a data phase is completed on any clock when both irdy_n and trdy_n are asserted. stop_n i/o this signal is an active-low signal driven by the current target. it indicates to the requesting master to terminate the current transaction. idsel input initializationdeviceselect is used as chip select during configuration read and write transactions. devsel_n i/o this active-low signal is asserted when the target has decoded the current address on the bus and has found a match for that address. as input, devsel_n indicates whether any device on the bus has been selected. par i/o this active-high signal is driven by the device that has driven the address bus in the previous cycle. it indicates the even parity of address and command bits for an address phase or even parity of data and byte enables for a data phase. parity is always valid for the transfer that occurred the previous clock cycle. perr_n i/o parityerror is for reporting of data parity errors during all pci transactions except a special cycle. this is a sustained tristate signal. serr_n i/o this is an active-low signal for reporting address parity errors and data parity errors on the special cycle command or any other system error where the result will be catastrophic. req_n output this is an active-low output from the pci core to indicate request for ownership for the pci bus. gnt_n input this is an active-low input signal to the pci core to indicate grant of ownership of the pci bus after the completion of the current transfer on the bus. lock_n i/o lock is an active-low signal indicating an atomic operation that may require multiple transactions to complete. when lock_n is asserted, non-exclusive transactions may proceed to an address that is not currently locked. the pci core does not support the lock feature.
ATPCI-SSP8000-32 5 table 2. application/master interface signals signal name direction description a2m_xfr_req input an active-high signal asserted by the master to indicate a new transfer requested by the application. this is an input to the pci core. a2m_pci_addr[31:0] input the pci address of the next request is provided on the bus. this is valid before the a2m_xfr_req to indicate the pci address to which the data transfer needs to be performed. this is an input to the pci core. a2m_req_len[7:0] input this is valid along with a2m_xfr_req indicating the number of double words to be transferred for the request. this is an input to the pci core. a2m_req_type[3:0] input it indicates the type of transfer that needs to be performed on the bus for the request. it indicates whether it is a configuration, i/o or memory transfer. it also indicates whether it is a read or write transfer. a2m_full_dw input this is asserted by the application to indicate whether all the bytes in the current request are valid. this signal enables the pci core to determine whether it can perform a mwi transfer. the pci core does not rely on the byte enables once it has initiated a mwi. it is necessary that a master drive all its byte enables to ? 0 ? once it has initiated a mwi. this is an input to the pci core. m2a_req_ack output it indicates that the current request from the application has been accepted. upon receipt of acknowledge, the application may choose to post another request to the pci core. m2a_xfr_start output it indicates the start of a new transfer by the master for the previous application request. m2a_active output it indicates that the pci core is the current master on the bus. it is deasserted once the master transfer is completed. a2m_wrok input it indicates that the application is ready to accept data into its fifo. deassertion of this signal indicates that the pci core needs to insert a wait state on the bus for the next data transfer. a2m_rdok input it indicates that the application has data in its fifo. deassertion of this signal indicates that the pci core needs to insert a wait state on the bus for the next data transfer. m2a_xfrdn output this signal is asserted by the pci core upon completion of the transfer on the bus. m2a_xfr_sts output this signal is asserted by the pci core along with m2a_xfrdn indicating the status of the last master transfer. m2a_wrnext output when the pci core is in the master mode, the data from the current pci master read transaction is written into the application. this is asserted by the pci core to indicate that the application should advance its data pointer to the next location. m2a_wrdt[31:0] output the data from the pci bus is written into the application through the bus in the master mode. m2a_wrbe[3:0] output this indicates the byte enables for the current transfer. a2m_wrdt[31:0] input this is the data provided by the application. this data is latched into the pci core staging register with every m2a_rdnext assertion. during pci master write transactions, this data is transmitted on the bus. a2m_wrbe[3:0] input the byte enables to a pci write transaction in the master mode are provided by the application through this bus. this byte enable is provided by the application for every data transfer. m2a_rdnext output this indicates that the pci core has latched the data from the application for the current pci master write transaction and the application needs to increment its data pointer to point to the next data.
ATPCI-SSP8000-32 6 table 3. application/slave interface signals signal name direction description s2a_cycle output this indicates that the pci core has detected a valid slave cycle. s2a_mem_cycle output this signal indicates that the current cycle is a memory cycle when ? 1 ? and i/o cycle when ? 0 ? . this signal is valid when s2a_cycle is asserted . s2a_write output this signal indicates that the current cycle is a write cycle when ? 1 ? and read cycle when ? 0 ? . this signal is valid when s2a_cycle is asserted. s2a_wrdt [31:0] output this is the data that is transferred on the pci bus during the current pci slave write cycle. the pci core asserts trdy_n for further pci slave write transfers based on s2a_wrok. if s2a_wrok is deasserted, then it inserts wait states on the bus. if the s2a_wrok is deasserted for more than eight clocks, the pci core automatically performs a disconnect on the bus. s2a_wrbe [3:0] output the byte enables that were transferred on the pci bus for the current pci slave write cycle to the pci core are provided on this bus. s2a_next output the pci core in the slave mode will assert this signal to the application to advance to the next location in the case of a read or write transaction. s2a_addr output this indicates the current address from which data is needed in the case of a slave read cycle and the location to which data is written in the case of a slave write cycle. this address is incremented by the pci core every time a data transfer occurs on the bus. the signal s2a_range indicates the valid bits for that range of decoded addresses. s2a_range[2:0] output this indicates the range of addresses that were decoded for the current slave cycle. this is an output from the pci core. the pci core may have up to six address ranges as a slave. this indicates to which of the decoded addresses the current slave cycle belongs. a2s_rdok input this is an input to the pci core. this signal indicates whether the application data to slave is valid. if this signal is deasserted, the pci core inserts wait states on the trdy_n signal during a pci slave read cycle. a2s_wrok input this is an input to the pci core. this signal indicates that the application is ready to accept data from slave. deassertion of a2s_wrok forces the pci core to insert wait states on the pci bus for a pci slave write cycle. a2s_endxfr input this is an input to the pci core. this signal indicates that the application intends to end the current slave transaction and results in a disconnect. a2s_rddt[31:0] input the data to be read by the pci core in the slave read mode is provided on this bus. the signal s2a_addr addresses the location in the application to read the data. table 4. application/configuration interface signals signal name direction description a2c_init_done input this must be deasserted upon reset. it is asserted by the application after initializing the configuration space. this is an input to the pci core. in devices where there is no initialization required, it should be tied high. during initialization, the application can write to the configuration registers. the address is provided on the a2c_cfg_addr bus and the configuration data is provided on the a2c_wrdt bus. the byte enables for the data are on the a2c_wrbe bus. a2c_cfg_addr[3:0] input the application addresses the configuration space through this bus. a2c_wrdt[31:0] input the configuration data from the application is written through this bus. the a2c_cfg_addr bus addresses the configuration registers. a2c_wrbe[3:0] input the byte enables for the configuration data from the application are provided on this bus.
? atmel corporation 2001. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty which is detailed in atmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel (408) 441-0311 fax (408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 atmel colorado springs 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 tel (719) 576-3300 fax (719) 540-1759 atmel rousset zone industrielle 13106 rousset cedex france tel (33) 4-4253-6000 fax (33) 4-4253-6001 atmel smart card ics scottish enterprise technology park east kilbride, scotland g75 0qr tel (44) 1355-357-000 fax (44) 1355-242-743 atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex france tel (33) 4-7658-3000 fax (33) 4-7658-3480 fax-on-demand north america: 1-(800) 292-8635 international: 1-(408) 441-0732 e-mail literature@atmel.com web site http://www.atmel.com bbs 1-(408) 436-4309 printed on recycled paper. 1665as ? 07/01 marks bearing ? and/or ? are registered trademarks and trademarks of atmel corporation. terms and product names in this document may be trademarks of others.
|
