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SM5950BM seiko npc corporation ? asynchronous sample rate converter overview the SM5950BM is a digital audio signal asynchronous sample rate converter lsi. it supports 16/20/24-bit word-length input/output interface data. it also features a built-in digital deemphasis ?ter and direct mute functions. features functions l/r 2-channel (stereo) processing input sample rate range: 20khz to 100khz output sample rate range: 30khz to 50khz operating sample rate conversion ratio (fso/fsi) *1 : 0.45 to 2.205 selectable *1 : fsi = input sample rate fso = output sample rate asynchronous input and output clock timing system clock input input system clock: 1fsi (lrci) output system clock: 512fso (scko input) deemphasis ?ter function iir-type ?ter fsi = 44.1khz, 48khz, 32khz compatible direct mute function through mode operation direct connection from input to output output data clocks (lrco, bcko) slave mode: external inputs master mode: derived from the output system clock (scko) computation round-off processing normal round-off 5v tolerant input pins for direct connection to 5v operation devices 3.3v single supply package: 24-pin ssop ordering information pinout (top view) package dimensions (unit: mm) weight: 0.23g note: dimensions without tolerance are reference values. device package SM5950BM 24-pin ssop lrci 1 bcki 2 di 3 tmod0 4 rstn 5 vdd 6 iisi 7 imod0 8 imod1 9 deem 10 fs0 11 fs1 12 24 23 22 21 20 19 18 17 16 15 14 13 lrco bcko dout slave scko vss iiso omod0 omod1 tmod1 throu dmute 10.20 ?0.30 10.05 ?0.20 5.40 ?0.20 7.80 ?0.30 0.36 ?0.10 0.8 0.12 m 0.10 0.10 ?0.10 1.80 1.90 ? 0.10 + 0.20 0.50 ?0.20 0 to 10 0.15 ? 0.05 + 0.10
SM5950BM seiko npc corporation ? features interfaces input data format 2s-complement, msb-?st, l/r alternating serial data iis/non-iis formats l = low input level, h = high input level output data format 2s-complement, msb-?st, l/r alternating serial data bit clock continuous (64fso) l = low input level, h = high input level structure silicon-gate cmos process applications digital audio equipment-interface sample rate con- version (av ampli?r, cd-r/rw, dat, md, dvc) recording/editing equipment sample rate conver- sion converter performance internal data word length: 20 bits deemphasis ?ter characteristics (iir ?ter) 0.03db gain deviation from ideal ?ter char- acteristic anti-aliasing lpf characteristics (6 types of fir ?ter) output/input sample rate conversion ratio auto- matic ?ter select (6 fir ?ters) 1.up converter lpf 1.0 to 2.205 times 2.down converter lpf i about 0.92 times: 48.0khz to 44.1khz 3.down converter lpf ii about 0.73 times: 44.1khz to 32.0khz 4.down converter lpf iii about 0.67 times: 48.0khz to 32.0khz 5.down converter lpf iv about 0.50 times: 96.0khz to 48.0khz 6.down converter lpf v about 0.45 times: 96.0khz to 44.1khz - passband ripple: ?0.0001db - stopband attenuation: > 98db converter insertion quantization noise level internal calculation (quantization) noise : ?96db output round-off noise: - 16-bit output mode : ?98db - 20-bit output mode : ?122db - 24-bit output mode : ?146db output s/n ratio (theoretical values) format imod0 imod1 iisi 16-bit msb-?st right-justi?d l l l 20-bit msb-?st right-justi?d h l l 24-bit msb-?st right-justi?d l h l msb-?st left-justi?d (leading 16 bits valid data) hhl iis (leading 16 bits valid data) h or l h or l h format omod0 omod1 iiso 16-bit msb-?st right-justi?d l l l 20-bit msb-?st right-justi?d h l l 24-bit msb-?st right-justi?d l h l msb-?st left-justi?d (16-bit output) h h l iis (16-bit output) h or l h or l h output signal word length s/n ratio 16-bit input 20-bit input 24-bit input 16 bits ?92.5db ?94.0db ?94.0db 20 bits ?93.9db ?96.2db ?96.2db 24 bits ?93.9db ?96.2db ?96.2db
SM5950BM seiko npc corporation ? block diagram arithmetic operation block interpolation filter operation output operation lrco bcko dout scko lrci bcki deemphasis filter operation sequencer block interpolation operation output data operation rstn input data interface di conversion rate detector filter type selector output timing operation imod0 imod1 iisi deem fs0 fs1 output data interface though, mute, and slave mode control iiso omod0 omod1 throu slave dmute
SM5950BM seiko npc corporation ? pin description number name i/o description high low 1 lrci i sample rate clock input (fsi) 2 bcki i bit clock input (32fsi to 64fsi) 3 di i data input 4 tmod0 i ic test mode select pin (must be low for normal operation) test normal 5 rstn i reset pin reset 6 vdd vdd supply (3.3v) 7 iisi i iis input select pin 8 imod0 i input format select pin 0 9 imod1 i input format select pin 1 10 deem i deemphasis select pin on off 11 fs0 i deemphasis frequency select pin 0 12 fs1 i deemphasis frequency select pin 1 13 dmute i direct mute select pin on off 14 throu i through mode select pin through src 15 tmod1 i ic test mode select pin (must be low for normal operation) test normal 16 omod1 i output format select pin 1 17 omod0 i output format select pin 0 18 iiso i iis output select pin 19 vss gnd connection (0v) 20 scko i output system clock input (512fso) 21 slave i slave select pin slave master 22 dout o data output 23 bcko i/o bit clock input/output (64fso) 24 lrco i/o sample rate clock input/output (fso)
SM5950BM seiko npc corporation ? specifications absolute maximum ratings v ss = 0v, vdd pin voltage = v dd note: ratings also apply at supply switch on and off. recommended operating conditions v ss = 0v, vdd pin voltage = v dd dc electrical characteristics v ss = 0v, v dd = 3.0 to 3.6v, ta = ? 40 to 85 c (*a) all output pins with no load, system clock frequency: f scko = 24.576mhz, input word clock frequency: f lrci = 48khz, supply voltage: v dd = 3.3v pin type note. the input and input/output pins are all 5v tolerant. the maximum input voltage that can be applied to these pins are 5.5v . if supply voltage is within over the recommended operating voltage. if the input voltage is between 5.5v and vdd which is smaller than recommended operatin g voltage, the device doesn? breakdown itself, but it maybe generate reverse current from the input pins to the supply voltage (vdd). note th at input/output pins in input mode have a maximum input voltage of 5.5v, but the maximum voltage when in output mode is vdd level. in output mode, the output voltage must not be set, using external pull-up or other means, to voltages greater than vdd level. it is forbidden to add more voltage than vdd to output mode bidirectional pins. parameter symbol rating unit supply voltage range v dd ? 0.3 to 4.6 v input voltage range v i ? 0.3 to 5.5 v output voltage range v o ?0.3 to v dd + 0.3 v storage temperature range t stg ? 55 to 125 c power dissipation p w 400 mw parameter symbol rating unit min typ max supply voltage v dd 3.0 3.3 3.6 v operating temperature t opr ?40 25 85 c parameter pin symbol condition rating unit min typ max current consumption vdd i dd (*a) 22.0 30.0 ma high-level input voltage (*1) (*3) v ih 2.0 5.5 v low-level input voltage v il 0 0.7 v high-level output voltage (*2) (*3) v oh i oh = ? 2.0ma 2.4 v dd v low-level output voltage v ol i ol = 2.0ma 0 0.4 v input leakage current (*1) (*3) i lh v in = v dd ?1.0 1.0 ? i ll v in = 0v ?1.0 1.0 ? note type names (*1) inputs lrci, bcki, di, tmod0, rstn, iisi, imod0, imod1, deem, fs0, fs1, dmute, throu, tmod1, omod1, omod0, iiso, scko, slave (*2) output dout (*3) inputs/outputs bcko, lrco
SM5950BM seiko npc corporation ? ac electrical characteristics output system clock (scko input) reset input (rstn) parameter symbol condition rating unit min typ max clock pulse cycle time t cy 39.0 65.1 ns clock pulsewidth (high level) t cwh 15.6 39.1 ns clock pulsewidth (low level) t cwl 15.6 39.1 ns clock pulse duty 40 60 % parameter symbol condition rating unit min typ max rstn pulsewidth t rst 39 ns 0.5v dd scko t cwh t cwl t cy v il v ih 0.5v dd rstn v il v ih t rst
SM5950BM seiko npc corporation ? serial inputs (lrci, bcki, di) parameter symbol condition rating unit min typ max lrci cycle time t licy 10?0 s bcki pulse cycle time t bicy 156.25 1562.5 ns bcki pulsewidth (high level) t bicwh 60 ns bcki pulsewidth (low level) t bicwl 60 ns di setup time t dis 30 ns di hold time t dih 30 ns last bcki rising edge to lrci edge t bli 30 ns lrci edge to ?st bcki rising edge t lbi 30 ns 0.5v dd 0.5v dd di bcki lrci 0.5v dd t bli t lbi t bicwh t bicwl t bicy t dis t dih v il v ih v il v ih v il v ih
SM5950BM seiko npc corporation ? serial outputs (slave = high, lrco, bcko inputs, dout output) parameter symbol condition rating unit min typ max lrco cycle time t locy 20 33.34 s bcko pulse cycle time t bocy 312.5 520.8 ns bcko pulsewidth (high level) t bocwh 125 ns bcko pulsewidth (low level) t bocwl 125 ns last bcko rising edge to lrco edge t blo 30 ns lrco edge to ?st bcko rising edge t lbo 30 ns dout output delay t dodl c l = 15pf 30 ns 0.5v dd 0.5v dd dout bcko lrco 0.5v dd v il v ih v il v ih t blo t lbo t bocwh t bocwl t bocy t dodl v oh v ol
SM5950BM seiko npc corporation ? serial outputs (slave = low, lrco, bcko, dout outputs) t cy = output system clock (scko input) cycle time parameter symbol condition rating unit min typ max lrco cycle time t locy 512 t cy lrco pulsewidth (high level) t locwh 256 t cy lrco pulsewidth (low level) t locwl 256 t cy bcko pulse cycle time t bocy ?t cy bcko pulsewidth (high level) t bocwh ?t cy bcko pulsewidth (low level) t bocwl ?t cy bcko output delay t bodl c l = 15pf 30 ns lrco output delay t lodl c l = 15pf 30 ns dout output delay t dodl c l = 15pf 30 ns 0.5v dd 0.5v dd dout bcko lrco 0.5v dd t bocwh t bocwl t bocy t dodl v oh v ol scko t lodl 0.5v dd v il v ih v oh v ol v oh v ol t bodl t bodl
SM5950BM seiko npc corporation ?0 functional description input interface settings (imod0, imod1, iisi) input data format 2s-complement, msb-?st, l/r alternating serial data note: l = low input level, h = high input level input timing the input timing for each input format is shown in ?ures 4 to 8. output system clock (scko) a clock with frequency 512 times the output sampling frequency (fso) must be input on scko. in master mode, the lrco and bcko output clocks are derived from the input clock on scko. it also functions as the internal computation circuit system clock. output interface settings (omod0, omod1, iiso, throu, slave) output data format 2s-complement, msb-?st, l/r alternating serial note: l = low input level, h = high input level output mode select output timing the timing for each output format is shown in ?ures 9 to 13. in slave mode, the input timing of lrco and bcko for each output format is shown in ?ures 9 to 13. in through mode, the lrci, bcki, and di inputs are fed through to the outputs regardless of the output data format settings. imod0 imod1 iisi format l l l 16-bit msb-?st right-justi?d h l l 20-bit msb-?st right-justi?d l h l 24-bit msb-?st right-justi?d h h l msb-?st left-justi?d (leading 16 bits valid data) h or l h or l h iis (leading 16 bits valid data) omod0 omod1 iiso format l l l 16-bit msb-?st right-justi?d h l l 20-bit msb-?st right-justi?d l h l 24-bit msb-?st right-justi?d h h l msb-?st left-justi?d (16-bit output) h or l h or l h iis (16-bit output) pin setting function throu slave mode description lrco, bcko l l master lrco and bcko are derived form scko. function as outputs h slave lrco and bcko are supplied externally. function as inputs h h or l through lrco, bcko, and dout are connected directly to lrci, bcki, and di inputs. note: dmute is valid. function as outputs
SM5950BM seiko npc corporation ?1 system reset (rstn) the SM5950BM must be reset if any of the following conditions occur during normal operation. a reset pulse is a low-level pulse applied to rstn, although the reset operation actually occurs on the rising edge of the low-level pulse. when the power supply is applied a reset (rstn = low to high) is required when the power supply voltage is applied and after the lrci, bcki, scko (and lrco, bcko if in slave mode) clocks have stabilized. when the lrci and bcki clocks are interrupted this occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage, when the lrci, bcki clocks are dynamically switched, or when otherwise the clocks are not continuous. a reset (rstn = low to high) is required after the lrci, bcki clocks have stabilized. when the scko (and lrco, bcko if in slave mode) clocks are interrupted this occurs when the sampling frequency is switched, when clocks stop due to a condition in a previous stage, when the scko, lrco, bcko clocks are dynamically switched, or when otherwise the clocks are not contin- uous. a reset (rstn = low to high) is required after the scko, lrco, bcko clocks have stabilized. a reset pulse is required under these conditions because the conversion ratio calculated based on such non-con- tinuous clocks will result in an incorrect conversion ratio, and hence the output data will have incorrect values. output state during reset interval dout is tied low during the reset interval (refer to section "direct mute" for operation after the reset is released). in master mode, the lrco and bcko clocks are also tied low. direct mute (dmute) direct mute on/off other mute operations direct mute also occurs at system reset. dmute function l audio data output starts from the next output word. h 0 data is output from the next output word. rstn function l 0 data is output from the next output word. h computed data output starts after 8 output word cycles.
SM5950BM seiko npc corporation ?2 sample rate conversion the input/output sample rate conversion ratio is variable over a range 0.45 to 2.205 times frequency. the input sample rate (fsi) range is 20khz to 100khz, while the output sample rate (fso) range is 30khz to 50khz. note that the sample rate conversion ratio lower limit means that conversion from fsi = 96khz to fso = 32khz is not possible. anti-aliasing ?ter selection the following 6 ?ters are provided to function as anti-aliasing ?ters during sample rate conversion, where the optimum anti-aliasing ?ter is automatically selected in response to the automatic measurement of the sample conversion ratio between the input sampling frequency (on lrci) and the output sampling frequency (calcu- lated using scko as reference). if the selected anti-aliasing ?ter fs conversion ratio and the actual sample rate conversion ratio do not match, the following phenomena occur. if the fs conversion ratio is not ?ed, the conversion will slowly follow the change in ratio, but in the process the possibility exists that noise may occur in the audio data output. filter mode fs conversion ratio (fso/fsi) selects range conversion frequency (example) 1 1.0 to 2.205 times 0.969697 times up conversion 2 0.91875 times 0.864865 to 0.969697 times 48.0 44.1 3 0.72562 times 0.711111 to 0.864865 times 44.1 32.0 4 0.66667 times 0.627451 to 0.711111 times 48.0 32.0 5 0.50000 times 0.492308 to 0.627451 times 96.0 48.0 6 0.459375 times 0.492308 times 96.0 44.1 conversion condition response generated actual sample rate conversion ratio is lower than the selected ?ter conversion ratio. high-frequency aliasing noise occurs in the audio band. actual sample rate conversion ratio is higher than the selected ?ter conversion ratio. primarily cuts high-frequency components in the audio band.
SM5950BM seiko npc corporation ?3 conversion performance internal data word length: 20 bits gain deviation from deemphasis ?ter ideal characteristic: 0.03db anti-aliasing ?ter characteristic passband ripple: 0.0001db stopband attenuation: > 98db conversion insertion quantization noise level internal computation noise: ?96db output round-off noise: 16-bit output: ?98db 20-bit output: ?122db 24-bit output: ?146db overall theoretical output s/n ratio anti-aliasing ?ter characteristics output signal word length s/n ratio 16-bit input 20-bit input 24-bit input 16 bits ?92.5db ?94.0db ?94.0db 20 bits ?93.9db ?96.2db ?96.2db 24 bits ?93.9db ?96.2db ?96.2db figure 1. anti-aliasing ?ter characteristics -120 -100 -80 -60 -40 -20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 frequency [ fsi] attenuation [db] 48 to 44.1khz 48 to 32khz 48 to 22.05khz up conversion 44.1 to 32khz 48 to 24khz
SM5950BM seiko npc corporation ?4 deemphasis (deem) basic deemphasis ?ters are realized using analog circuit con?urations. here, an iir digital deemphasis ?ter con?uration faithfully reproduces the gain and phase characteristics of an analog deemphasis ?ter. the ?ter coef?ients are set by pins fs0 and fs1 for 3 input sampling frequencies (fsi) of 44.1khz, 48.0khz, and 32.0khz. deemphasis on/off deemphasis ?ter coef?ient selection the deemphasis ?ter is selected by pins fs0 and fs1. deemphasis ?ter characteristics deem deemphasis l off hon fs0 fs1 fsi l l 44.1khz h l 44.1khz l h 48.0khz h h 32.0khz figure 2. deemphasis ?ter frequency characteristics figure 3. deemphasis ?ter phase characteristics -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 10 100 1000 10000 100000 frequency [hz] attenuation [db] 44.1khz 48khz 32khz -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 frequency [hz] phase characteristics [degree] 44.1khz 48khz 32khz
SM5950BM seiko npc corporation ?5 group delay time if t input and t output are de?ed as: t input : serial input data (fsi rate) read end timing (lrci clock rising edge) t output : serial output data (fso rate) output start timing (lrco clock rising edge) the group delay is given by: t output ?t input = (48.41 8.41)/fsi response time the conversion rate detector stage requires a certain amount of time to calculate the sample rate conversion ratio with accuracy. the minimum response time, after the SM5950BM input sampling frequency (fsi: lrci input) and output sampling frequency (fso: derived from scko) have stabilized suf?iently, is the time required to determine the sample rate conversion ratio to 16-bit accuracy after reset is cleared, and is given by: response time = 16384/fso (371ms at fso = 44.1khz) t output (48.41 8.41)/fsi serial data input 1/fs t input 1/fso serial data output t output input ?t t output t input data waveform image
SM5950BM seiko npc corporation ?6 timing diagrams input timing (lrci, bcki, di) figure 4. 16-bit msb-?st right-justi?d (imod0 = l, imod1 = l, iisi = l), bcki = 32fsi to 64fsi figure 5. 20-bit msb-?st right-justi?d (imod0 = h, imod1 = l, iisi = l), bcki = 40fsi to 64fsi figure 6. 24-bit msb-?st right-justi?d (imod0 = l, imod1 = h, iisi = l), bcki = 48fsi to 64fsi figure 7. msb-?st left-justi?d, leading 16 data bits only are valid (imod0 = h, imod1 = h, iisi = l), bcki = 32fsi to 64fsi figure 8. iis, leading 16 data bits only are valid (imod0 = h, imod1 = h, iisi = h), bcki = 64fsi only lrci (fsi) bcki (64fsi) di lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lrci (fsi) bcki (64fsi) di 20 19 18 17 lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lrci (fsi) bcki (64fsi) di 24 23 22 21 lch rch 16 15 14 13 12 11 10 9 8 7 6 5 24 23 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 120 19 18 17 4 3 2 120 19 18 17 lrci (fsi) bcki (64fsi) di lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lrci (fsi) bcki (64fsi) di lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
SM5950BM seiko npc corporation ?7 output timing (lrco, bcko, dout) figure 9. 16-bit msb-?st right-justi?d (omod0 = l, omod1 = l, iiso = l), bcko = 64fso only figure 10. 20-bit msb-?st right-justi?d (omod0 = h, omod1 = l, iiso = l), bcko = 64fso only figure 11. 24-bit msb-?st right-justi?d (omod0 = l, omod1 = h, iiso = l), bcko = 64fso only figure 12. msb-?st left-justi?d, 16-bit output (omod0 = h, omod1 = h, iiso = l), bcko = 64fso only figure 13. iis, 16-bit output (omod0 = h, omod1 = h, iiso = h), bcko = 64fso only lrco (fso) bcko (64fso) dout lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 19 18 17 lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lrco (fso) bcko (64fso) dout 24 23 22 21 lch rch 16 15 14 13 12 11 10 9 8 7 6 5 24 23 22 21 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 120 19 18 17 4 3 2 120 19 18 17 lrco (fso) bcko (64fso) dout lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lrco (fso) bcko (64fso) dout lch rch 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lrco (fso) bcko (64fso) dout
SM5950BM seiko npc corporation ?8 typical application circuits input interface connection example connection with a digital audio interface receiver (dir:cs8414) example output interface connection example connection to a digital audio interface transceiver (dit:cs8402a) deem imod0 lrci imod1 bcki di SM5950BM mcu co/f0 sel fsync cs12/fck sck sdata m3 m2 m1 m0 dir cs8414 5v tmod0 tmod1 iisi fs0 fs1 cu cbl fsync m2 m1 sck sdata dit cs8402a 5v level shifter (3.3v to 5v) 6.144mhz (128fso) omod0 lrco omod1 bcko dout iiso throu slave tmod0 SM5950BM m0 24.576mhz (512fso) external clock scko mck tmod1
SM5950BM seiko npc corporation ?9 connection to most interface transceiver (os8104) 5v fsy sck-src_fl sr0-d3 most os8104 omod0 lrco omod1 bcko dout iiso throu slave tmod0 SM5950BM 24.576mhz (512fso) scko rmck tmod1 /rd /wr par_cp par_src async pad0 pad1 5v
SM5950BM seiko npc corporation ?0 input/output pin equivalent circuits input pin circuit ? type1 pin name (number): lrci (1), bcki (2), di (3), tmod0 (4), rstn (5), iisi (7), imod0 (8), imod1 (9), deem (10), fs0 (11), tmod1 (15), scko (20), slave (21) input pin circuit ? type2 pin name (number): fs1 (12), dmute (13), omod1 (16), omod0 (17), iiso (18) input voltage max. 5.5v v dd : 3.3v 350 ? input voltage max. 5.5v v dd : 3.3v 350 ?
SM5950BM seiko npc corporation ?1 output pin circuit pin name (number): dout (22) input/output pin circuit pin name (number): bcko (23), lrco (24) v dd : 3.3v 350 ? input voltage max. 5.5v v dd : 3.3v 350 ?
SM5950BM seiko npc corporation ?2 nc0504ce 2007.11 please pay your attention to the following points at time of using the products shown in this document. the products shown in this document (hereinafter ?roducts? are not intended to be used for the apparatus that exerts harmful in?ence on human lives due to the defects, failure or malfunction of the products. customers are requested to obtain prior written agreeme nt for such use from seiko npc corporation (hereinafter ?pc?. customers shall be solely responsible for, and indemnify and hold npc free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. npc reserves the right to change the speci?ations of the products in order to improve the characteristic or reliability thereof. npc makes no claim o r warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. therefore, npc shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in t his document. any descriptions including applications, circuits, and the parameters of the products in this document are for reference to use the products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modi?ation. customers are requested not to export or re-export, directly or indirectly, the products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. seiko npc corporation 15-6, nihombashi-kabutocho, chuo-ku, tokyo 103-0026, japan telephone: +81-3-6667-6601 facsimile: +81-3-6667-6611 http://www.npc.co.jp/ email: sales @ npc.co.jp

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