View AT71-ATM1M60M-B0_993002.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

main features ? high sensitivity and high snr performance 1/2" cmos sensor total resolution of 1.3m (with 5 m square pixels) high data rate: 75 mpixels/s provides 60 frame/s at 1m resolution (for 1m60) cameralink ? data format (base configuration - 1 channel) flexible and easy to operate vi a serial communication control ? gain: 0 db to 18 db in 3 db steps ? dynamic range: 8, 10 or 12-bit data ? contrast expansion ? shutter time pogrammable ? subsampling: 1/4 and 1/16 resolution ? trigger mode: free-run or external trigger mode ? programmable roi ? test pattern column fpn correction programmable look-up table single power supply: dc 12 v to 24 v provided on hi rose-6 connector input ttl trigger signal and output ttl shutter signal on hirose-5 connector compact design: 44 44 45 mm (w, h, l) c-mount adapter high reliability - ce and fcc compliant product description this camera features an outstanding sens itivity and snr, even at maximal speeds. the roi allows to increase the frame rate (for instance, 175 fps in vga format 1m60). atmos? cameras are based on a rolling shutter cmos sensor. the configuration interface provides access to advanced functions (contrast expan- sion, image calibration, lut). the versatile and compact mechanical housing enables you to implement various configurations. these features combin ed with a compelling price, make atmos an attractive alterna- tive for users of megapixel cameras. applications high-speed, snr performance and reliability of this camera make it suitable for machine vision, especially: material inspection (e.g. glass, ic, pcb) robot guidance metrology and various applications like: microscopy surveillance demanding tasks cameralink ? areascan cameras atmos ? 1m60 atmos ? 1m30 preliminary 5429b?image?04/05
2 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 1. typical performances measured with light source 3200 k and ir filter warning : 1. when exposed to such illumination level the sensor might lock-up and should be reset see register software reset @ 206h, internal register mapping on page 17 table 1-1. camera typical performances sensor characteristics at maximum pixel rate 1m60 1m30 unit resolution h v 1312 1024 1312 1024 pixels pixel size (square) 5 5 5 5 m maximum frame rate 48 24 hz pixel rate 75 37.5 mhz camera performances bit depth 8, 10 or 12 bits spectral range 350?1000 nm linearity 2% in 5% and 95% of fsr prnu 1.5% rms fpn 0.1% rms responsivity 10000 (1) lsb/(lux.s) output rms noise dynamic range < 2.7 lsb rms > 63 db conversion factor 10 e-/ lsb dark current 1500 e-/s over illumination behavior 75 esat (2) mechanical and electrical interface size (w h l) 44 44 45 mm weight 115 g lens mount c-mount sensor alignment ? x, y = 250 ? z = 150 ?0 xy = 0.7 ? tilt z = 0-200 m m degree m power supply single 12 to 24 vdc power consumption < 2 w operating temperature 0 to 55 (non-condensing) c storage temperature -40 to 70 (non-condensing) c
3 5429b?image?04/05 [preliminary] atmos -1m60/1m30 figure 1-1. responsivity diagram figure 1-2. quantum efficiency 0 5 10 15 20 25 30 35 40 45 50 300 400 500 600 700 800 900 1000 1100 responsivity at 0 db gain nm lsb/( nj/cm 2 ) quantum efficiency 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 400 500 600 700 800 900 1000 wavelength (nm) qe (%)
4 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 2. standard conformity the cameras have been tested in the following conditions: camera with comple te atmel housing shielded power supply cable cameralink data transfer cable ref. 14b26-szlb-500-olc (3m?) linear ac-dc power supply atmel recommends using the same configurati on to ensure compliance with the following standards. 2.1 ce conformity the atmos cameras comply with the european directive 89/336/cee (en55022 a/cispr22 a, en55024, en61000-6-2). 2.2 fcc conformity atmos cameras comply with part 15 of fcc rules. operation is subject to the following two conditions: 1. this device may not cause harmful interference, and 2. this device must accept any interference received, including interference that may cause undesired operation. this equipment has been tested and found to comply with the limits for a class a digital device, pursuant to part 15 of the fcc rules. these limits are designed to provide reasonable protec- tion against harmful interference when the equipment is operated in a commercial environment. this equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. warning : changes or modifications to this unit not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment.
5 5429b?image?04/05 [preliminary] atmos -1m60/1m30 3. camera description figure 3-1. camera synoptic the camera is based on a single tap cmos sensor which delivers a 12-bit digital video signal at its output. an fpga has been implemented for image processing (fpn column correction, con- version lut, contrast expansion). the camera is powered by a single dc power supply from 12v to 24v. the functional interface (data and cont rol) is provided with the cameralink inter- face. the camera uses the base configuration of the cameralink standard. note: dval permanently tied to 1 (high) level. data can be delivered on a single channel or two de-multiplexed channels. the data format con- figuration might be in 12-bit, 10-bit, or 8-bit. it is possible to use external triggers with the camera (cc1 signal or ttl_io trigger input) in different trigger modes see ?synchronization modes? on page 6 the camera configuration and settings are done via the cameralink serial communica- tion. this interface is used for: gain and offset setting data output format synchronization modes: free-run or external trigger modes shutter time test pattern generation upload and download of correction data (fpn column correction, lut) cmos sensor microcontroller cameralink transceiver tx rx power supplies dc power camera link i/f sequencer controller data serial line trigger strobe, lval shutter fval
6 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 4. timing 4.1 synchronization modes the camera operates in rolling shutter mode. 4.1.1 optimal use of the rolling shutter as shown in the following timing diagrams, figure 4-1 , exposure does not happen at the same time for all lines, which can lead to image distortion when capturing fast moving objects. the way to bypass this, is to use the camera with a strobe light or a shutter element so that all the lines are exposed during the same time and no im age distortion is visible when capturing fast moving objects . the integration time for each line is: readout (+ programmable shutter time, when used). a shut- ter signal is provided to strobe a light source or to drive a shutter element. you can set the camera to operate in one of the following synchronization modes: periodic, triggered, triggered without full reset and itc. see register mode control @ 204h, internal register mapping on page 17 . 4.1.2 free-run mode (or periodic mode) principle : the camera operates in periodic mode. the period is defined by readout time (+ programmable shutter time, when used). valid data is forwarded to the cameralink interface during the next frame readout starting with the first line. i f shutter time is set to 0: the frame n is readout while the first line integrates for frame n+1. as soon as the frame n readout has ended starts the readout of frame n +1. figure 4-1. free-run mode chronogram line 1 integration (frame n) frame n readout line 1 readout and reset line n integration (frame n) line n readout and reset frame n+1 readout
7 5429b?image?04/05 [preliminary] atmos -1m60/1m30 if shutter time is set to > 0: readout is suspended between two consecutive frame readout and shutter output signal is acti- vated (programmable polarity) for a time configurable within 0 to tsh range by step of t1. figure 4-2. free-run mode and shutter chronogram the maximum frame rate of 48 frame/s for the 1m60 camera (or 24 frame/s for the 1m30 cam- era) is given in this mode with a shutter time set to 0. see register aperture shutter time @ 246h, internal register mapping on page 17 . 4.1.3 triggered mode principle: an external trigger starts the reset of the sensor, then snap and readout of a frame, the integration time is defined by readout time (+ programmable shutter time, when used). the trigger event initiate s the following sequence: stop of readout frame in progress and reset of readout pointer to line 1 readout of previous dummy frame and integration start of the frame n. the readout data of previous frame is not forwarded on cameralink interface (fval inactive) shutter output signal is activated during a time programmable within 0 to tsh range by step of t1 readout of frame n. the readout data is forwarded to the cameralink interface (fval active) starting with the first line readout of dummy frames (to prevent against large dark current integration) while the camera waits for the next trigger event table 4-1. shutter time values at free-run mode label description 1m60 1m30 tsh maximum shutter time (ms) 655 1310 t1 step duration (s) 10 20 line 1 integration (frame n ) readout and rese t line n integration (frame n) frame n programmable shutter time shutter line n readout and reset readout time readout frame n - 1 time out line 1
8 5429b?image?04/05 atmos -1m60/1m30 [preliminary] the trigger delay is a few s. the minimum pulse duration is 1s. the edge of trigger is pro- grammable. the source of trigger is se lectable between cameralink cc1 signal and ttl/io trigger input. the period is defined by readout time + programmable shutter time + readout time + wait. therefore the minimum period is 2 readout time. see register aperture shutter time @ 246h, internal register mapping on page 17 . figure 4-3. triggered mode chronogram 4.1.4 triggered mode without full reset principle : an external trigger starts the snap and readout of a frame, without resetting the sen- sor. the integration time is defined by readout time (+ programmable shutter time, when used). the trigger event initiate s the following sequence: stop of readout frame in progress and reset of readout pointer to line 1 shutter output signal is activated during a time programmable within 0 to tsh range by step of t1 readout of frame n. the readout data is forwarded to the cameralink interface (fval active) starting with the first line readout of dummy frames (to prevent against large dark current integration) while the camera waits for the next trigger event the trigger delay is a few s. the minimum pulse duration is 1s. the edge of trigger is pro- grammable. the source of trigger is selectable between cameralink cc1 signal and ttl_io trigger input. the period is defined by the programmable shutter time + readout time + wait. table 4-2. shutter time values at triggered mode label description 1m60 1m30 tsh maximum shutter time (ms) 655 1310 t1 step duration (s) 10 20 line 1 reset line 1 integration (frame n) frame n readout line n integration (frame n) line n reset line 1 readout and reset trigger n event trigger in programmable shutter time shutter out trigger delay fval line n readout and reset
9 5429b?image?04/05 [preliminary] atmos -1m60/1m30 therefore the minimum period is reduced to 1 readout time. as the integration time is not the same for all lines (in the following timing diagra m line n integration time is greater than line 1 integration time) this mode must be used with a pulsed light source or a shutter element. more- over any residual light when shutter output signal is inhibited must be avoided. the exposure time is defined by the shutter time and all the lines are exposed during the same time. see register aperture shutter time @ 246h internal register mapping on page 15 figure 4-4. triggered mode withou t full reset chronogram 4.1.5 itc mode principle : an external sync controls both the integration time and the frame rate. the trigger event initiate s the following sequence: stop of readout frame in progress and reset of readout pointer to line 1 shutter output signal is activated during a time defined by the high state of the itc signal readout of frame n. the readout data is forwarded to the cameralink interface (fval active) starting with the first line table 4-3. shutter time values at triggered mode without full reset label description 1m60 1m30 tsh maximum shutter time (ms) 655 1310 t1 step duration (s) 10 20 line1 reset line 1 integration (frame n) frame n readout line n integration (frame n) line n reset line 1 readout and reset trigger n event trigger in programmable shutter time shutter out trigger delay fva l line n readout and reset
10 5429b?image?04/05 atmos -1m60/1m30 [preliminary] readout of dummy frames (to prevent against large dark current integration) while the camera waits for the next trigger event the integration delay is a few s. the minimum pulse duration is 1s. the source of itc signal is selectable between cameralink cc1 signal and ttl_io trigger input. see register mode control @ 204h internal register mappingon on page 17 the period is defined by the itc signal period. as the integration time is not the same for all lines (in the following timing diagram line n integra- tion time is greater than line 1 integration time) this mode must be used with a pulsed light source or a shutter element. moreover any resi dual light when shutter output signal is inhibited must be avoided. the exposure time is defined by the itc signal high state time and all the lines are exposed during the same time figure 4-5. itc mode chronogram 4.2 ouput data timing line 1 reset line 1 integration (frame n) frame n readout line n integration (frame n) line n reset line 1 readout and reset trigger n event itc in shutter time shutter out trigger delay fval line n readout and reset table 4-4. timing values label description min typ max ts input setup to clock delay 1ns th output hold from clock delay 1ns
11 5429b?image?04/05 [preliminary] atmos -1m60/1m30 figure 4-6. output data chronogram lval strobe data first valid pixel last valid pixel ts th
12 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 5. camera features 5.1 region of interest the full resolution of the camera is 1312 pixels by 1024 lines.you might program a smaller reso- lution in order to reduce the readout time. you must be careful that depending on the sequencing mode, the exposure time can be re duced too.the authorized values for horizontal size are 32 to 1312 pixels. this value is rounded to the lower multiple of 16 pixels. the autho- rized values for vertical size are 32 to 1024 lines. this value is rounded to the lower multiple of 8 lines. see registers roi area @ 280h, 282h, 284h and 286h internal register mapping on page 17 . examples of frame rate versus resolution: 5.2 analog gain the analog gain can be adjusted by setting the gain register via the serial communication. gain adjusted from 0 db to 18 db: code 0 to 6 step 3 db nominal gain (factory configuration): 0 db see register sensor analog gain @ 240h, internal register mapping on page 17 . 5.3 subsampling ? subsampling 1: all pixels are readout (1312 1024) ? subsampling 2: two times lower resolution in both axes (656 512) ? subsampling 4: four times lower resolution in both axes (328 256) see register subsampling @ 288h, internal register mapping on page 17 . subsampling parameters might be combined with the roi. the minimal window size resulting from these combinations must be at least 32 32 pixels. this leads to the following table of min- imal roi size versus subsampling: 5.4 output format the data format available on the cameralink output interface is programmable via the serial interface. table 5-1. r.o.i performance roi size frame rate 1m60 (fps) frame rate 1m30 (fps) 1312 1024 48 24 1024 1024 60 30 640 480 175 85 table 5-2. subsampling minimum size subsampling minimum roi size 1 32 32 2 64 64 4 128 128
13 5429b?image?04/05 [preliminary] atmos -1m60/1m30 1. the pixel depth is set by default at 12-bit, it can be set to 10 or 8-bit. the assignment for each configuration comply with the specifications of the cameralink interface standard. see register mode control bits [3:2] @ 204h, internal register mapping page 17 . 2. in standard mode the camera provides output data on a single channel of the camer- alink output interface. you might program the camera in two outputs mode, only with the 1m60. pixel data is de-multiplexed (odd and even pixels) on ports a, b and c of the cameralink interface and strobe signal is divided by 2 (37.5 mhz). see register mode control bit [4] @ 204h,internal register mapping page 17 . 5.5 test pattern in normal mode, the digital video signal from the sensor is available on the cameralink output interface. for test purposes a digital pattern is generated and is available instead of the video signal in the cameralink output interface. the pattern can be fixed or sliding. the fixed digital pattern is ramp-up from 960 lsb code to 2271 lsb code (line width). the same pattern is shown for each line: figure 5-1. test pattern view the sliding pattern starts with the fixed pattern, the first code of each line is then incremented by two on each frame. it is useful to validate the connection to the acquisition system before the adjustment settings of the image capture. the subsampling parameter does not affect the pattern. see register mode control bits [1:0] @ 204h, internal register mapping on page 17 . 5.6 contrast expansion the digital gain and offset can be adjusted via the serial communication in order to focus on a particular part of the dynamic range. gain adjusted from x1 to x32.875: code 0 to 255 step 0.125 nominal gain (factory configuration): 1 see register digital gain @ 242h, internal register mapping on page 17 . offset adjusted from -4096 to +4095: code 0 to 8191 in 2's complement step 1 nominal offset (factory configuration): 0 see register digital offset @ 244h, internal register mapping on page 17 . see register processing control bits [1:0] @ 202h, internal register mapping on page 17 .
14 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 5.7 look- up table (lut) the look-up table is a conversion table which applies to the sensor data. at each input pixel value corresponds a single output value. this allows you to apply a correction table like a gamma correction for example. the look-up table might be generated by the camera by programming the gamma setting: gamma 0.125 to 7.875: code 1 to 63 (0 not admitted) you might also write your own correction table via the serial communication channel. four banks are available to store four distinct correction tables. see register lut coefficient save in dataflash @ 10dh, internal register mapping on page 17 . see register lut coefficient restore in data flash @ 10eh, internal register mapping on page 17 . see register processing control bit 2 @ 202h, internal register mapping on page 17 5.8 fixed pattern noise (fpn) correction the fixed pattern noise (fpn) is a spatial fluctuat ion of the sensor data particularly between suc- cessive columns. the purpose is to calculate an offset for each column of the frame in the darkness. the table of column offsets is stored in the internal memory. if the fpn correction is then enabled the offset values are subtracted to the value of the input pixel. two methods are available to realize this processing: the off-line calibration and the online correction. 5.9 off-line calibration a calibration step is required while the camera is in darkness condition. offset coefficients for each column are calculated on an average value measured on all 1024 lines. offset coefficients are 8-bit data. therefore to be efficient the pixel value should be always within the values 1lsb to 255 lsb. if not, the overflow / underflow flags are set in the status register. the calibration step must be done in full resolution and subsampling 1. calibration data can be saved in nonvol- atile memory and four distinct banks are reserved for this use. you might access to these banks in read or write mode. see register processing control bits [4:3] @ 202h, internal register mapping on page 17 . see register calibration control @ 200h, internal register mapping on page 17 . see register fpn coefficient save in dataflash @ 10bh, internal register mapping on page 17 . see register fpn coefficient restore in dataflash @ 10ch, internal register mapping on page 17 . 5.10 online correction no calibration step is required. when online corr ection is enabled the camera calculates the off- set coefficients for each colu mn on masked lines and then processes the input sensor data. these coefficients are updated at each frame. t he online correction applies only in subsampling 1. the calculated values are less accurate with these methods but unlike the off-line calibration do not depend on the settings like the analog gain. see register processing control bits [4:3] @ 202h, internal register mapping on page 17 . see register fpn coefficient save in dataflash @ 10bh,internal register mapping on page 17 .
15 5429b?image?04/05 [preliminary] atmos -1m60/1m30 see register fpn coefficient restore in dataflash @ 10ch, internal register mapping on page 17 . 5.11 processing synoptic figure 5-2. synoptic 5.12 led indicator the green led on the rear panel gives information on the internal state of the camera. on power up, after internal configuration, the led flashes on and has the following behavior (decreasing priority order): internal hardware error or configuration error: fast blinking waiting for external trigger (triggered and itc modes): slow blinking all other situation: continuous pixel_in coef_fp n offset mux c p t pixel_ou t pattern lut format gain
16 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 6. electrical interface 6.1 power supply it is recommended to insert a 1a fuse between the power supply and the camera. the voltage ripple of the power supply shall be below 50 mvp-p at bw = 50 mhz to have full camera performancei note: i = input, o = output, i/o = bi-directiona l signal, p = power/ground, nc = not connected 6.2 command and control the cameralink interface provides four lvds signals dedicated to camera control (cc1 to cc4). on the atmos, one of them is used to synchronize the camera on external events. note: i = input, o = output, i/o = bi-directiona l signal, p = power/ground, nc = not connected the ttl/i/o interface provides two ttl signals dedicated to camera control. note: i = input, o = output, i/o = bi-directiona l signal, p = power/ground, nc = not connected see register mode control @ 204h, internal register mapping on page 17 .video data. data and enable signals are provided on the cameralink interface. note: 1. i = input, o = output, i/o = bi-directiona l signal, p = power/ground, nc = not connected 2. note: dval, as defined in the cameralink standard, is not used. dval is permanently tied to 1 (high) level. table 6-1. power supply description signal name i/o type description pwr p - dc power input: +12 v to + 24 v gnd p - electrical and mechanical ground table 6-2. cameralink input description signal name i/o type description trig1 i rs644 cc1 - synchronization input table 6-3. ttl/io description signal name i/o type description trigger i 5 v-ttl external trigger input shutter o 3 v-ttl shutter output, maximum output current 1.6 ma table 6-4. camera link output description signal name i/o type description odd-d[11-0] o rs644 odd pixel data, odd-00 = lsb, odd-11 = msb even-d[11-0] o rs644 even pixel da ta, even-00 = lsb, even-11 = msb strobe o rs644 output data clock, data valid on the rising edge lval o rs644 line valid or line enable, active high signal fval o rs644 frame valid or frame enable, active high signal
17 5429b?image?04/05 [preliminary] atmos -1m60/1m30 6.3 serial communication the cameralink interface provides two lvds signal pairs for the communication between the camera and the frame grabber. this is an asynchronous serial communication based on rs-232 protocol. the configuration of the serial line is: full duplex/without handshaking 8-bit data, no parity bit, 1 stop bit 9600 bauds at power up, then programmable up to 115200 bauds 6.3.1 internal register table 6-5. cameralink serial communication description signal name i/o type description sertfg o rs644 differential pair for serial communication to the frame grabber sertc i rs644 differential pair for serial communication from the frame grabber table 6-6. internal register mapping start addr (hex) size dec) end addr (hex) access type processing internal task factory settings description 000 1 ro ro synchronization register for serial communication (value 00) 001 1 rw - 1 communication speed multiplier (9600 - 115,2k): volatile register 1, 2, 3, 4, 6, 8, 12 040 51 ro - hardware identifier 080 8 ro - firmware identifier 0c0 51 rw - user identifier 100 4 rw rw status (ref. camera status management) 104 4 wo - lock/unlock mode: advanced user/user 1: lock advanced user mode (into user mode) unlock key value: unlock user 108 1 ro - privilege level 1: advanced user mode 2: user mode 109 1 wo - current configuration save in eeprom 1: user settings (allowed only for advanced user mode) 2 to 4: user settings 10a 1 rw - 0 current configuration restore from eeprom 1 to 4: user settings
18 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 10b 1 wo - fpn coefficient save in dataflash 1 to 4 (1 allowed only for advanced user mode) 10c 1 rw - 1 fpn coefficient restore in dataflash 1 to 4 10d 1 wo - lut coefficient save in dataflash 1 to 4 (1 allowed only for advanced user mode) 10e 1 rw - 1 lut coefficient restore in dataflash 1 to 4 200 2 rw rw 0 calibration control [0] = off-line calibration enabled (0: disabled; 1: enabled) 202 2 rw - 0 processing control: [0] = offset correction enable (0: disabled; 1: enabled) [1] = gain correction enable (0: disabled; 1: enabled) [2] = look-up table correction enable (0: disabled; 1: enabled)[ [4:3] = fpn correction mode (00: disabled; 01: off-line fpn correction enabled; 11: on- line fpn correction enabled) 204 2 rw - 0 mode control: [1:0] = test pattern (00: disabled; 01: fixed test pattern; 10: dynamic test pattern) [3:2] = output format (00:12-bit; 01:10-bit; 10:8-bit) [4] = demux mode (for 1m60 then 0: disabled; 1: enabled) (for 1m30 then 0: disabled) [7:5] = synchronization mode (000: free- run; 001: external triggered; 010: external triggered without full reset; 011: integration time controlled); others reserved [8] = trigger source (0: cameralink; 1: external) [9] = trigger polarity (0:positive edge; 1: negative edge) [10] = shutter polarity output (0: positive edge; 1: negative edge) 206 1 wo software reset: 1 = camera reset table 6-6. internal register mapping (continued) start addr (hex) size dec) end addr (hex) access type processing internal task factory settings description
19 5429b?image?04/05 [preliminary] atmos -1m60/1m30 240 2 rw - 0 sensor analog gain: [3:0] = analog gain; value from 0 db (= 0) to 18 db (= 6) by step of 3 db 242 2 rw - 0 digital gain (extended dynamic range): [7:0] = gain; value from 1.000 (= 0) to 32.875 (= 255) in q 9.3 representation 244 2 rw - 0 digital offset (extended dynamic range): [12:0] = offset; value from -4096 to + 4095 in 2's complement 246 2 rw - 1 aperture shutter time: [15:0] = shutter time; value from 0 to 65535 (for 1m60: 0 to 655 ms by step of 10s) (for 1m30: 0 to 1310 ms by step of 20s) 248 2 rw - 1600 ers: [10:0] value from 0% (= 0,dark) to 100% (= 1600, clear) in q11.4 representation 280 8 287 rw roi area: addr 280, size 2, default 0: roi horizontal start value (0 to 1311) addr 282, size 2, default 0 roi vertical start value (0 to 1023) addr 284, size 2, default 1312 roi vertical size value from 32 to 1312 addr 286, size 2, default 1024 roi vertical size value from 32 to 1024 288 1 rw - 1 subsampling: [2:0] = subsampling (001: 1/1; 010: 1/4; 100: 1/16) 2c0 2 rw 50 hot pixel detection threshold: [10:0] = hot pixel threshold 2c2 2 rw 50 dead pixel detection threshold: [10:0] = dead pixel threshold 2c4 1 rw - 0 defective pixels control: [0] = hot pixel detection (0: disabled; 1: enabled [1] = dead pixel detection (0: disabled; 1: enabled) table 6-6. internal register mapping (continued) start addr (hex) size dec) end addr (hex) access type processing internal task factory settings description
20 5429b?image?04/05 atmos -1m60/1m30 [preliminary] note: ro: read only regist er, wo: write only register, rw: read & write register 6.3.2 camera settings memory atmos cameras have 5 ba nks to save settings: bank 0 contains the factory settings. this bank cannot be modified by the user bank 1 to 4 are used to store 4 different settings bank 1 might be protected by an advanced user (see register @ 104h). contact atmel for details 300 1 wo - gamma correction: [5:0] = gamma settings; value from 0.125 (= 1) to 7.875 (= 63) in q6.3 representation 1000 1312 151f rw - 0 fpn coefficien ts (8-bit): format: fpn [0]; fpn[1]; fpn [2];? 2000 8192 3fff rw - linear look-up table (4096 16-bit): format: lut [0]; lut [1]; ? ; lut [4095] value: 0 to 4095 table 6-6. internal register mapping (continued) start addr (hex) size dec) end addr (hex) access type processing internal task factory settings description
21 5429b?image?04/05 [preliminary] atmos -1m60/1m30 7. connector description all connectors are on the rear panel. better result s are obtained by using shielded cables (foil and braid shielded). note: cables for digital signals shall be twisted pairs. 7.1 power supply camera connector type: hirose hr10a-7r-6pb (male) cable connector type: hirose hr10a-7p-6s (female) figure 7-1. power supply pinout 7.2 cameralink connector standard cameralink cable sha ll be used to ensure the full electrical compatibility. camera connector type: mdr-26 (female) ref. 3m 10226-2210ve we recommend to use a cameralink standard shielded cable as 3m 14x26-szlb-xxx-0lc figure 7-2. cameralink pinout power connector : j01 signal pin signal pin pwr 1 gnd 4 nc 2 nc 5 pwr 3 gnd 6 1 2 3 6 5 4 receptacle viewed from camera back command and control connector : j02 signal pin signal pin gnd 1 gnd 14 x0- 2 x0+ 15 x1- 3 x1+ 16 x2- 4 x2+ 17 xclk- 5 xclk+ 18 x3- 6 x3+ 19 sertc+ 7 sertc- 20 sertfg- 8 sertfg+ 21 cc1- 9 cc1+ 22 cc2+ 10 cc2- 23 cc3- 11 cc3+ 24 cc4+ 12 cc4- 25 gnd 13 gnd 26
22 5429b?image?04/05 atmos -1m60/1m30 [preliminary] 7.3 ttl i/o camera connector type: hirose hr10a-7r-5sb (female) cable connector type: hirose hr10a-7p-5p (male) figure 7-3. ttl/io pinout ttl io connector : j03 signal pin signal pin trigger 1 gnd 4 gnd 2 nc 5 shutter 3 1 2 3 5 4 receptacle viewed from camera back
23 5429b?image?04/05 [preliminary] atmos -1m60/1m30 8. mechanical drawing note: (all dimensions are in mm) figure 8-1. front panel view figure 8-2. front panel mechanical drawing note: 1. a and b are mechanical reference plans 2. sensor alignment ? x, y refers to the optical axis 3. sensor alignment ?0 xy refers to the reference plans 44.75 12 3.75 22 38.5 2 x (m4 x 8) 4 x (m3 x 8) 1 - 32 un - 2a (c mount) first pixel of line 1 b a camera link power supply 44 35 sensor (on the 4 sides)
24 5429b?image?04/05 atmos -1m60/1m30 [preliminary] figure 8-3. rear panel figure 8-4. rear panel mechanical drawing 31.30 23 9.90 22.80 44 12-24v ttl io cameralink ?
25 5429b?image?04/05 [preliminary] atmos -1m60/1m30 9. ordering code delivery : atmos areascan cameras are delivered with: power supply connector hr10a-7p-6s ttl i/o connector hr10a-7p-5p cd-rom with: ? friendly software commcam ? documentation table 9-1. ordering code part number description AT71-ATM1M60M-B0 atmos 1m60 with housing + power supply connector + ttl i/o connector + cd-rom at71-atm1m30m-b0 atmos 1m30 with housing + power supply connector + ttl i/o connector + cd-rom
printed on recycled paper. 5429b?image?04/05 xm ? atmel corporation 2005 . all rights reserved. atmel ? , logo and combinations thereof, and dataflash ? are registered trademarks, and every- where you are sm , atmos ? and others are trademarks of atmel corporation or its subsidiaries. cameralink ? is the trademark of automated imaging association. other terms and pr oduct names may be trademarks of others. disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. atmel?s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature

▲Up To Search▲

Price & Availability of AT71-ATM1M60M-B0

	To Download AT71-ATM1M60M-B0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .