3D3418 monolithic 8-bit programmable delay line (series 3D3418 ? low noise) features ? all-silicon, low-power 3.3v cmos technology ? vapor phase, ir and wave solderable ? auto-insertable (dip pkg.) ? low ground bounce noise ? leading- and trailing-edge accuracy ? increment range: 0.25 through 7.5ns ? delay tolerance: 1% (see table 1) ? temperature stability : 3% typical (0c-70c) ? vdd stability : 1% typical (3.0v-3.6v) ? static idd: 1.3ma typical ? minimum input pulse w i dth: 10% of total delay ? programmable via 3-wire serial or 8-bit parallel interface packages 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 in ae so/p0 p1 p2 p3 p4 gnd vdd out md p7 p6 sc p5 si 3d 3418 d i p 3d 3418g g u ll w i ng 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 in ae so / p 0 p1 p2 p3 p4 gnd vdd out md p7 p6 sc p5 si 3d 34 18s sol (30 0 mil) f o r mechanical dimensions, click here . functional description the 3D3418 programmable 8-bit silicon delay line product family consists of 8-bit, user-progr ammable cmos silicon integrated circuits. delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps ranging from 250ps to 7.5ns inclusively. units hav e a typical inherent (address 0) delay of 20ns (see table 1). the input is reproduced at the output without inversion, shifted in time as per user selection. the 3D3418 is cmos-compatible, and features both rising- and falling-edge accuracy. the all-cmos 3D3418 integrated circuit has been designed as a reliable, economic alternative to hybrid ttl progra mmable delay lines. it is offered in a standard 16-pin auto-insertable dip and a space saving surface mount 16-pin soic. pin descriptions in signal input out signal output md mode select ae address enable p0-p7 parallel data input sc serial cloc k si serial data input so serial data output vcc +3.3 volts gnd ground table 1: part number specifications pa rt dela ys a nd tolera nces input restrictions number step 0 delay (ns) step 255 delay (ns) delay increment (ns) max operating frequency a b solute max oper freq min operating p.w. a b solute min oper p . w . 3D3418-0.25 19.5 3.0 83.25 4.0 0.25 0.15 6.25 mhz 90 mhz 80.0 ns 5.5 ns 3D3418-0.5 19.5 3.0 147.0 4.0 0.50 0.25 3.15 mhz 45 mhz 160.0 ns 11.0 ns 3D3418-1 19.5 3.0 274.5 5.0 1.00 0.50 1.56 mhz 22 mhz 320.0 ns 22.0 ns 3D3418-2 20.0 3.5 530.0 6.0 2.00 1.00 0.78 mhz 11 mhz 640.0 ns 44.0 ns 3D3418-3 20.0 3.5 785.0 8.0 3.00 1.50 0.52 mhz 7.5 mhz 960.0 ns 66.0 ns 3D3418-4 20.0 3.5 1040 9.0 4.00 2.00 0.39 mhz 5.5 mhz 1280.0 ns 88.0 ns 3D3418-5 20.0 3.5 1295 10 5.00 2.50 0.31 mhz 4.4 mhz 1600.0 ns 110.0 ns 3D3418-7.5 20.5 3.5 1933 15 7.50 3.75 0.21 mhz 2.9 mhz 2400.0 ns 165.0 ns notes: a n y delay increment betw een 0.25 and 7.5 ns not show n is also av ailable. a ll delay s referenced to input pin ? 2002 data delay dev i ces doc #02006 data delay devices, inc. 1 10/28/02 3 mt. prospect ave. clifton, nj 07013
3D3418 application notes the 8-bit programmable 3D3418 delay line architecture is comprised of a number of delay cells connected in series with their respective outputs multiplexed onto the delay out pin (out) by the user-selected programming data. each delay cell produces at its output a replica of the signal present at its input, shifted in time. input signal characteristics the frequency and/or pulse width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. the reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. therefore a maximum and an absolute maximum operating input frequency and a minimum and an absolute minimum operating pulse width have been specified. operating frequency the absolute maximum operating frequency specification, tabulated in table 1 , determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. the maximum operating frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed. to guarantee the table 1 delay accuracy for input frequencies higher than the maximum operating frequency , the 3D3418 must be tested at the user operating frequency. therefore, to facilitate production and device identification, the part number w ill include a custom reference designator identifying the intended frequency of operation. the programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. operating pulse width the absolute minimum operating pulse width (high or low) specification, tabulated in table 1 , determines the smallest pulse width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. the minimum operating pulse width (high or low) specification determines the smallest pulse width of the delay line input signal for which the output delay accuracy tabulated in table 1 is guaranteed. to guarantee the table 1 delay accuracy for input pulse width smaller than the minimum operating pulse width , the 3D3418 must be tested at the user operating pulse width. therefore, to facilitate production and device identification, the part number w ill include a custom reference designator identifying the intended frequency and duty cycle of operation. the programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy , if at all. nev e rtheless, it is strongly recommended that the engineering staff at data delay devices be consulted. special high accuracy requirements the table 1 delay and increment accuracy specifications are aimed at meeting the requirements of the majority of the applications encountered to date. however, some systems may place tighter restrictions on one accuracy parameter in favor of others. for example, a channel delay equalizing system is concerned in minimizing delay variations among the various channels. therefore, because the inter channel skew is a delay difference, the programmed delay tolerance may need to be considerably decreased, while the increment and its tolerance are of no consequence. the opposite is true for an under-sampled multi-channel data acquisition sy st em. doc #02006 data delay devices, inc. 2 10/28/02 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3D3418 doc #02006 data delay devices, inc. 3 10/28/02 3 mt. prospect ave. clifton, nj 07013 application notes (cont?d) the flexible 3D3418 architecture can be exploited to conform to these more demanding user-dictated accuracy constraints. however, to facilitate production and dev ice identification, the part number will include a custom reference designator identifying the user requested accuracy specifications and operating conditions. it is strongly recommended that the engineering staff at data delay devices be consulted. power supply and temperature considerations the delay of cmos integrated circuits is strongly dependent on power supply and temperature. the monolithic 3D3418 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. the thermal coefficient is reduced to 600 ppm/c , which is equivalent to a variation, over the 0c-70 c operating range, of r 3% from the room-temperature delay settings. the power supply coefficient is reduced, over the 3.0v- 3.6v operating range, to r 1% of the delay settings at the nominal 3.3vdc power supply and/or r 2ns , whichever is greater. it is essential that the power supply pin be adequately bypassed and filtered. in addition, the power bus should be of as low an impedance construction as possible. power planes are preferred. programmed delay (address) update a delay line is a memory device. it stores information present at the input for a time equal to the delay setting before presenting it at the output with minimal distortion. the 3D3418 8-bit programmable delay line can be represented by 256 serially connected delay elements (individually addressed by the programming data), each capable of storing data for a time equal to the device increment (step time). the delay line memory property, in conjunction with the operational requirem ent of ?instantaneously? connecting the delay element addressed by the programming data to the output, may inject spurious information ont o the output data stream. in order to ensure that spurious outputs do not occur, it is essential that the input signal be idle (held high or low) for a short duration prior to updating the programmed delay. this duration is given by the maximum programmable delay. satisfying this requirement allows the delay line to ?clear? itself of spurious edges. when the new address is loaded, the input signal can begin to switch (and the new delay will be valid) after a time given by t pdv or t edv (see section below). programmed delay (address) interface figure 1 illustrates the main functional blocks of the 3D3418 delay program interface. since the 3D3418 is a cmos design, all unused input pins must be returned to well defined logic levels, vcc or ground. transparent parallel mode (md = 1, ae = 1) the eight program pins p0 - p7 directly control the output delay. a change on one or more of the program pins will be reflected on the output delay after a time t pdv , as shown in figure 2. a register is required if the programming data is bused. latched parallel mode (md = 1, ae pulsed) the eight program pins p0 - p7 are loaded by the falling edge of the enable pulse, as shown in figure 3. after each change in delay value, a settling time t edv is required before the input is accurately delayed. serial mode (md = 0) while observing data setup ( t dsc ) and data hold ( t dhc ) requirements, timing data is loaded in msb-to-lsb order by the rising edge of the clock (sc) while the enable (ae) is high, as shown in figure 4. the falling edge of the enable (ae) activates the new delay value which is reflected at the output after a settling time t edv . as data is shifted into the serial data input (si), the previous contents of the 8-bit input register are shifted out of the serial output port pin (so) in msb-to-lsb order, thus allowing cascading of multiple devices by connecting the serial output pin (so) of the preceding device to the serial data input
3D3418 application notes (cont?d) pin (si) of the succeeding device, as illustrated in figure 5 . the total number of serial data bits in a cascade configuration must be eight times the number of units, and each group of eight bits must be transmitted in msb-to-lsb order. to initiate a serial read, enable (ae) is driven high. after a time t eqv , bit 7 (msb) is valid at the serial output port pin (so). on the first rising edge of the serial clock (sc), bit 7 is loaded with the value present at the serial data input pin (si), while bit 6 is presented at the serial output pin (so). to retrieve the remaining bits s e ven more rising edges must be generated on the serial clock line. the read operation is destructive. therefore, if it is desired that the original delay setting remain unchanged, the read data must be written back to the device(s) before the enable (ae) pin is brought low. pin 3, if unused, must be allow e d to float if the device is configured in the serial programming mode. pr o g r ammabl e de la y li ne la t c h 8 - bi t i n pu t r e g i st er md sc si a e in so out p0 p1 p2 p3 p4 p5 p6 p7 m o d e sel ec t sh ift c l o c k ser ial in pu t a d d r ess en abl e sig n al in sig n al o u t ser ial o u t p u t par al l e l in pu t s figur e 1 : func t i ona l bloc k dia g r a m pr evio u s val u e pr evio u s val u e ne w v a l ue ne w v a l ue t pd x t pd v par al l e l in pu t s p0 -p7 de l a y ti m e figur e 2 : n on- la t c he d pa r a lle l m ode ( m d =1 , a e =1 ) pr evio u s val u e ne w v a l ue ne w v a l ue t ed x t ed v par al l e l in pu t s p0 -p7 de l a y ti m e t ds e t dh e t ew en abl e (ae) figur e 3 : la t c he d pa r a lle l m ode ( m d =1 ) doc #02006 data delay devices, inc. 4 10/28/02 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3D3418 application notes (cont?d) ne w val u e ne w bi t 7 ne w bi t 0 ne w bi t 6 ol d bi t 7 ol d bi t 6 ol d bi t 0 en abl e (ae) cl ock (sc) ser ial in pu t ( si ) ser ial out p ut ( so ) de l a y ti m e t ew t es t cw t cw t eh t ds c t dh c t egv t cq v t cq x t eqz t ed v t ed x pr evio u s val u e figur e 4 : s e r i a l m ode ( m d =0 ) fr o m w r itin g devi ce to next devi ce si so sc a e 3d 3 4 1 8 3 d 3 41 8 3 d 3 41 8 f i g u r e 5: c a scadin g m u l t iple d e v i ces si so sc a e si so sc a e table 2: delay vs. programmed address programmed address nominal delay (ns) p a r a l l e l p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 3D3418 dash n u m b e r s e r i a l m s b l s b - . 2 5 - . 5 - 1 - 2 -5 st e p 0 0 0 0 0 0 0 0 0 1 9 . 5 0 1 9 . 5 1 9 . 5 2 0 20 st e p 1 0 0 0 0 0 0 0 1 1 9 . 7 5 2 0 . 0 2 0 . 5 2 2 25 st e p 2 0 0 0 0 0 0 1 0 2 0 . 0 0 2 0 . 5 2 1 . 5 2 4 30 st e p 3 0 0 0 0 0 0 1 1 2 0 . 2 5 2 1 . 0 2 2 . 5 2 6 35 st e p 4 0 0 0 0 0 1 0 0 2 0 . 5 0 2 1 . 5 2 3 . 5 2 8 40 st e p 5 0 0 0 0 0 1 0 1 2 0 . 7 5 2 2 . 0 2 4 . 5 3 0 45 st ep 2 5 3 1 1 1 1 1 1 0 1 8 2 . 7 5 1 4 6 . 0 2 7 2 . 5 5 2 6 1285 st ep 2 5 4 1 1 1 1 1 1 1 0 8 3 . 0 0 1 4 6 . 5 2 7 3 . 5 5 2 8 1290 st ep 2 5 5 1 1 1 1 1 1 1 1 8 3 . 2 5 1 4 7 . 0 2 7 4 . 5 5 3 0 1295 delay change 63.75 127.5 255 510 1275 doc #02006 data delay devices, inc. 5 10/28/02 3 mt. prospect ave. clifton, nj 07013
3D3418 device specifications table 3: absolute maximum ratings p a r a m e t e r s y m b o l m i n m a x u n i t s n o t e s dc supply voltage v dd - 0 . 3 7 . 0 v input pin voltage v in - 0 . 3 v dd + 0 . 3 v input pin current i in - 1 0 1 0 m a 2 5 c storage temperature t st rg - 5 5 1 5 0 c lead temperature t lead 3 0 0 c 1 0 s e c table 4: dc electrical characteristics (0c to 70c, 3.0v to 3.6v) p a r a m e t e r s y m b o l m i n t y p m a x units n o t e s static supply current* i dd 1 . 3 2 . 0 m a v dd = 3.6v high level input voltage v ih 2 . 0 v low level input voltage v il 0 . 8 v high level input current i ih - 0 . 1 0 . 0 0 . 1 a v ih = v dd low level input current i il - 0 . 1 0 . 0 0 . 1 a v il = 0v high level output current i oh - 8 . 0 - 6 . 0 m a v dd = 3.0v v oh = 2.4v low level output current i ol 6 . 0 7 . 5 m a v dd = 3.0v v ol = 0.4v output rise & fall time t r & t f 2 n s c ld = 5 pf *i dd (dy n ami c ) = c ld * v dd * f input capacitance = 10 pf ty pical w h ere: c ld = average capacitance load/line (p f) output load capacitance (c ld ) = 25 pf max f = input frequency (ghz) table 5: ac electrical characteristics (0c to 70c, 3.0v to 3.6v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t s n o t e s clock frequency f c 8 0 m h z enable width t ew 1 0 n s clock width t cw 1 0 n s data setup to clock t dsc 1 0 n s data hold from clock t dhc 3 n s data setup to enable t dse 1 0 n s data hold from enable t dhe 3 n s enable to serial output valid t eqv 2 0 n s enable to serial output high-z t eqz 2 0 n s clock to serial output valid t cqv 2 0 n s clock to serial output invalid t cqx 1 0 n s enable setup to clock t es 1 0 n s enable hold from clock t eh 1 0 n s parallel input valid to delay valid t pdv 2 0 4 0 n s 1 parallel input change to delay invalid t pdx 0 n s 1 enable to delay valid t edv 3 5 4 5 n s 1 enable to delay invalid t edx 0 n s 1 input pulse width t wi 8 % of total delay see table 1 input period period 20 % of total delay see table 1 input to output delay t plh , t phl ns see table 2 notes: 1 - refer to programmed delay (address) update section doc #02006 data delay devices, inc. 6 10/28/02 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com
3D3418 doc #02006 data delay devices, inc. 7 10/28/02 3 mt. prospect ave. clifton, nj 07013 silicon delay line automated testing test conditions input: output: am bient tem p erature: 25 o c 3 o c r load : 10k ? 10% supply voltage (vcc): 3.3v 0.1v c load : 5pf 10% input pulse: high = 3.3v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 ? max. 10k ? 470 ? 5pf dev i c e under te s t di gi t a l s c ope rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 1.25 x total delay period: per in = 2.5 x total delay note: the above conditions are for test only and do not in any way restrict the operation of the device. out tr i g in re f tr i g f i g u r e 6: t est s e t u p de v i ce unde r t est (d u t ) d i g i t a l sc o pe/ t i m e i n t e rv a l count e r pu l s e ge ne ra t o r out in com p ut e r sy st em pr in t e r figur e 7 : t i m i ng d i a g r a m t pl h t ph l per in pw in t ris e t fa l l 0. 6v 0. 6v 1. 5v 1. 5v 2. 4v 2. 4v 1. 5v 1. 5v v ih v il v oh v ol in p u t s ign a l ou tp u t s ign a l
|
