pid no. 18415b/0 1 of 2 amd a 29k ? family technical bulletin byte and half-word addressing in the am29030 and am29035 microprocessors epd systems engineering april 8, 1994 purpose this bulletin elaborates on byte and half word addressing for the am29030 and am29035 microprocessors. in addition, it provides a correction to a table in the am29030 and am29035 microprocessors users manual and data sheet . affected parts and documentation this bulletin affects the following parts: device revision am29030 microprocessor all am29035 microprocessor all this bulletin affects the following documentation: pid no. title 15723c am29030 and am29035 microprocessors users manual and data sheet byte and half-word addressing all 29k family processors use big-endian byte ordering for internal registers. however, the am29030 and am29035 processors can access external memory using big- or little-endian format. the byte order (bo) bit of the configuration register sets the endian orientation. big-endian orientation (bo=0) places the most significant bit (msb) of data at the address x..x00 and the least significant bit (lsb) of data at address x..x11. little-endian orientation (bo=1) places the msb at x..x11 and the lsb at x..x00. byte orientation general register memory location ("x..x00") big endian (bo=0) aa bb cc dd aa bb cc dd little endian (bo=1) aa bb cc dd dd cc bb aa for all external byte and half-word accesses, the selection of a byte within an external word is determined by the two lsbs of an address and the bo bit. the selection of a half-word within an external word is determined by the next-to-least significant bit of an address and the bo bit. additionally, the option field in load and store instructions determine byte, half-word, or word accesses for the processor. however, for the exbyte, exhw, exhws, inbyte, and inhw instructions, the byte pointer (bp) field of the alu status register determines the position of the half- word within the word. restated, when these five instructions are executed, the appropriate value of the bp field preempts the lsbs of the address to determine the position of the byte or half-word. finally, for all word and half-word accesses, the am29030 and am29035 processors will either ignore or force alignment in most cases. thus, half-word accesses are forced to be aligned to half-word boundaries. the processor will trap when an unaligned half-word access is attempted, which emulates the non-aligned access in trap code. the processor will perform unaligned byte accesses. (note that this assumes the cps:tu bit is set. if the cps:tu bit is clear, data memory alignment is ignored. this is described in more detail in section 3.3.7.3 of the users manual.) for big-endian orientation (bo=0), bytes are ordered within words such that a 00 in the bp field or in the least-significant address bits selects the high-order byte of a word; a 11, the low-order byte of a word. again, the bp field is only referenced for the exbyte, exhw, exhws, inbyte, and inhw instructions. for little-endian orientation (bo=1), a 00 in the bp field or in the two least-significant address bits selects the low-order byte of a word. a value of 11 selects the high-order byte. for a half-word access, only the msb of the bp field or the next-to-least-significant address bit selects the appropriate half-word. since the lsb of the bp field or the address bits do not determine the half-word selection, the alignment of half-word data types are
pid no. 18415b/0 2 of 2 positioned on half-word boundaries. specifically, if bo=0 and the bp field or least-significant address bits are 0x (where x can be anything), the high order half-word will be selected and so on. the following table summarizes the use of the bo, bp and least- significant address bits for byte and half-word accesses. bo bp/least significant address bits selected byte 0 00 high order byte 0 01 second highest order byte 0 10 second lowest order byte 0 11 low order byte 1 00 low order byte 1 01 second lowest order byte 1 10 second highest order byte 1 11 high order byte selected half-word 0 00 high order half-word 0 10 low order half-word 1 00 low order half-word 1 10 high order half-word there is a correction necessary to the am29030 and am29035 microprocessors user's manual and data sheet, 1993/1994. the table in section 10.4.4 on page 10-11 in the manual is correctly shown below. bo opt(2-0) a(1-0) bwe ??? (3-0) on write 0 001 00 0111 msb, big endian 0 001 01 1011 0 001 10 1101 0 001 11 1110 lsb, big endian 0 010 0x 0011 mshw, big endian 0 010 1x 1100 lshw, big endian 1 001 00 1110 lsb, little endian 1 001 01 1101 1 001 10 1011 1 001 11 0111 msb, little endian 1 010 0x 1100 lshw, little endian 1 010 1x 0011 mshw, little endian x 000 xx 0000 word access x 110 xx 1111 hardware development -all other writes- 0000 msb = most significant byte; lsb = least significant byte; mshw = most significant half-word; lshw = least significant half-word if you need assistance product support for the 29k family processors is available from our embedded processor division (epd) technical support hotlines located in the u.s. and in the u.k. assistance is available in the u.s. from 9:00 a . m . to 6:00 p . m . central time, monday through friday (except major holidays). in europe assistance is available during u.k. business hours. contact us at one of the following numbers: to reach the u.s. hotline from call u.s. 1-800-2929-amd u.k. 0-800-89-1455 japan 0031-11-1163 any other location +1-512-602-4118 = = toll applies. to reach the u.k. hotline from call u.k. (0)256-811101 france 0590-8621 germany 0130-813875 italy 1678-77224 any other location +44-(0)256-811101 = = toll applies. amd is a registered trademark, and 29k, am29030, and am29035 are trademarks of advanced micro devices, inc.
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