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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. document no. u13563ej2v0pm00 (2nd edition) date published march 1999 j cp(k) printed in japan 1998 8-bit single-chip microcontroller preliminary product information mos integrated circuit m m m m pd78f0701y the mark shows major revised points. the m pd78f0701y is a m pd780701y sub-series product of the 78k/0 series. the m pd78f0701y features a dcan controller and an iebus tm controller. it also features flash memory as internal rom. programs can be written into the flash memory without having to remove it from the board. the functions of the m m m m pd78f0701y are described in the following user's manuals. be sure to read these manuals when designing a system based on the m m m m pd78f0701y. m m m m pd780701y sub-series user's manual : u13781e 78k/0 series user's manual, instruction : u12326e features built-in iebus (inter equipment bus tm ) controller built-in dcan (direct storage controller area network) controller pin-compatible with masked rom versions (other than the v pp pin) flash memory : 60k bytes (supported for self-programming) internal high-speed ram : 1,024 bytes internal expansion ram : 2,048 bytes buffer ram for dcan : 288 bytes can be operated within the same power supply voltage ranges as masked rom versions (v dd = 3.5 to 5.5 v) remark for differences between flash memory versions and masked rom versions, see chapter 1 . applications car audio systems, etc. ordering information part number package m pd78f0701ygc-8bt 80-pin plastic qfp (14 14 mm) not all devices/types available in every country. please check with local nec representative for availability and additional information.
preliminary product information u13563ej2v0pm00 2 m m m m pd78f0701y 78k/0 series development the 78k/0 series products are shown below. the sub-series names are indicated in frames. ultra-low power consumption. this product includes a uart. pd780955 80-pin m this product includes a controller/driver for driving an automobile meter. pd780973 80-pin m pd780833y m pd78098b 80-pin 80-pin an iebus controller has been added to the pd78054. emi noise-reduced version m m pd78044f pd78044h pd780232 80-pin basic sub-series for fip driving. total indication output pins: 34 pd78083 pd780058 pd78058f pd78054 pd780065 pd780034a pd780034ay pd78014h pd78018f pd780208 pd780228 pd780308 pd78064b pd78064 pd780308y pd78064y pd780948 80-pin 80-pin 80-pin 64-pin 64-pin 80-pin 64-pin 64-pin 42-/44-pin 100-pin 100-pin 80-pin 100-pin 100-pin 100-pin 64-pin 100-pin compatible with bus interface for lcd driving for fip tm driving 78k/0 series the serial i/o of the pd78054 has been enhanced. emi noise-reduced versions emi noise-reduced versions of the pd78054 a uart and d/a converter have been added to the pd78018f and i/o has been enhanced. ram capacity of the pd780024a has been expanded. an a/d converter of the pd780024a has been enhanced. serial i/o of the pd78018f has been enhanced. emi noise-reduced version of the pd78018f basic sub-series for control this product includes a uart and can operate at a low voltage (1.8 v). the i/o and fip c/d of the pd78044f have been enhanced. total indication output pins: 53 the i/o and fip c/d of the pd78044h have been enhanced. total indication output pins: 48 80-pin this product is for panel control and includes the fip c/d. total indication output pins: 53 n-ch open-drain i/o ports have been added to the pd78044f. total indication output pins: 34 for inverter control this product includes an inverter control circuit and uart. emi noise-reduced version the sio of the pd78064 has been enhanced and rom and ram have been expanded. emi noise-reduced version of the pd78064 basic sub-series for lcd driving. these products include a uart. this product includes a dcan controller. for industrial meter control pd780958 100-pin for meter control this product includes a dcan and an iebus controller. this product includes a controller complying with j1850 (class 2). pd780701y 80-pin 100-pin pd78078 pd78070a pd78075b 100-pin 100-pin 100-pin for control products being mass-produced products under development y sub-series products are compatible with the i 2 c bus. a timer has been added to the pd78054 to enhance external interface functions. emi noise-reduced version of the pd78078 rom-less versions of the pd78078 the serial i/o of the pd78078y has been enhanced, and only selected functions are provided. pd78018fy pd78054y pd78058fy pd780058y pd780018ay pd78070ay pd78078y pd780988 m m m m m m m m m m m m m m m m m m m m m m mm m mm m mm pd780024a pd780024ay mm m m m m m m m m m mm m m m m m m m m
preliminary product information u13563ej2v0pm00 3 m m m m pd78f0701y functions item function flash memory 60k bytes high-speed ram 1,024 bytes extended ram 2,048 bytes internal memory buffer ram for dcan 288 bytes minimum instruction execution time on-chip minimum instruction execution time modification function 0.32 m s/0.64 m s/1.27 m s/2.54 m s/5.09 m s (operation with system clock r unning at 6.29 mhz) general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) instruction set 16-bit operations multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) bit manipulations (such as set, reset, test, and boolean operation) i/o ports total : 67 cmos i/o : 56 ttl input/cmos output : 8 n-ch open-drain i/o : 3 a/d converters 16 channels with 8-bit resolution power failure detection function serial interface three-wire serial i/o mode : 2 channels uart mode : 1 channel i 2 c bus mode : 1 channel timers 16-bit timer/event counters : 2 channels 8-bit timer/event counters : 3 channels watch timer : 1 channel watchdog timer : 1 channel timer output 5 lines (8-bit pwm output: 3 lines) dcan controller 1 channel iebus controller effective transmission rate: 18 kbps clock output 49.2 khz, 98.3 khz, 197 khz, 393 khz, 786 khz, 1.57 mhz, 3.15 mhz, 6.29 mhz (operation with system clock r unning at 6.29 mhz) buzzer output 0.768 khz, 1.54 khz, 3.07 khz, 6.14 khz (operation with system clock r unning at 6.29 mhz) maskable internal: 20, external: 8 nonmaskable internal: 1 vectored interrupt sources software 1 power supply voltage v dd = 3.5 to 5.5 v operating ambient temperature t a = -40 c to +85 c package 80-pin plastic qfp (14 14 mm)
preliminary product information u13563ej2v0pm00 4 m m m m pd78f0701y pin configuration (top view) 80-pin plastic qfp (14 14 mm) m pd78f0701ygc-8bt 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p90/ani8 p91/ani9 p92/ani10 p93/ani11 p94/ani12 p95/ani13 p96/ani14 p97/ani15 p70/ti52/to52 p71/sda0 p72/scl0 p73/to01 p74/ti001 p75/ti011 p76/ti50/to50 p77/ti51/to51 p00/intp0 p01/intp1 p02/intp2 p03/intp3 p66 p65 p64 p27/pcl p26/asck0 p25/txd0 p24/rxd0 p23/buz p07/intp7 p06/intp6 p05/intp5 p04/intp4 p22/sck31 p21/so31 p20/si31 p57 p56 p55 p54 p53 av ss p87/ani7 p86/ani6 p85/ani5 p84/ani4 p83/ani3 p82/ani2 p81/ani1 p80/ani0 av ref v ss1 v dd1 cpureg x1 x2 v pp reset ctxd/itx0 crxd/irx0 p67 p40 p41 p42 p43 p44 p45 p46 p47 p30/si30 p31/so30 p32/sck30 v dd0 v ss0 p33 p34/to00 p35/ti000 p36/ti010 p50 p51 p52 cautions 1. in normal operation mode, connect the v pp pin directly to the v ss0 or v ss1 pin. 2. connect the av ss pin to the v ss0 pin. 3. connect the av ref pin to the v dd0 pin.
preliminary product information u13563ej2v0pm00 5 m m m m pd78f0701y ani0-ani15 : analog input p90-p97 : port 9 asck0 : asynchronous serial clock pcl : programmable clock av ref : analog reference voltage reset : reset av ss : analog ground rxd0 : receive data (for uart0) buz : buzzer output sck30, sck31 : serial clock (for sio30, sio31) cpureg : regulator for cpu power supply scl0 : serial clock (for iic0) crxd : can receive data sda0 : serial data ctxd : can transmit data si30, si31 : serial input intp0-intp7 : interrupt from peripherals so30, so31 : serial output irx0 : iebus receive data ti000, ti010, ti001, itx0 : iebus transmit data ti011, ti50, ti51, p00-p07 : port 0 ti52 : timer input p20-p27 : port 2 to00, to01, to50, p30-p36 : port 3 to51, to52 : timer output p40-p47 : port 4 txd0 : transmit data (for uart0) p50-p57 : port 5 v dd0 , v dd1 : power supply p64-p67 : port 6 v pp : programming power supply p70-p77 : port 7 v ss0 , v ss1 : ground p80-p87 : port 8 x1, x2 : crystal
preliminary product information u13563ej2v0pm00 6 m m m m pd78f0701y block diagram 16-bit timer/ event counter 00 (tm00) to00/p34 ti000/p35 ti010/p36 serial interface 30 (sio30) si30/p30 so30/p31 sck30/p32 serial interface 31 (sio31) si31/p20 so31/p21 sck31/p22 rxd0/p24 txd0/p25 asck0/p26 intp0/p00- intp7/p07 i 2 c bus (iic0) uart (uart0) interrupt control (int29) scl0/p72 sda0/p71 16-bit timer/ event counter 01 (tm01) to01/p73 ti001/p74 ti011/p75 8-bit timer/ event counter 50 (tm50) ti50/to50/p76 ti51/to51/p77 ti52/to52/p70 8-bit timer/ event counter 51 (tm51) 8-bit timer/ event counter 52 (tm52) watch timer (wtn0) watchdog timer (wdt) 8 pcl/p27 buz/p23 clock output control buzzer output 78k/0 cpu core internal high-speed ram 1,024 bytes internal expansion ram 2,048 bytes flash memory 60k bytes port 0 p00-p07 8 port 2 p20-p27 8 port 3 p30-p36 7 port 4 p40-p47 8 port 5 p50-p57 8 port 6 p64-p67 4 port 7 p70-p77 8 port 8 p80-p87 8 port 9 a/d converter3 (ad3) (adctl3) iebus controller (iebus0) dcan ram 288 bytes p90-p97 8 16 ani0/p80- ani7/p87, ani8/p90- ani15/p97 av ss av ref itx0/ctxd irx0/crxd dcan controller (dcan) ctxd/itx0 crxd/irx0 system control voltage regulator reset x1 x2 v dd1 v dd0 v ss0 v pp cpureg v ss1
preliminary product information u13563ej2v0pm00 7 m m m m pd78f0701y contents 1. differences between the m m m m pd78f0701y and masked rom versions.............................8 2. pin functions................................................................................................................ .....................9 2.1 port pins ................................................................................................................... ....................................9 2.2 non-port pins ............................................................................................................... ..............................10 2.3 pin input/output circuits and handling of unused pins....................................................................... .12 3. selecting internal bus controllers (dcan and iebus) .................................................14 4. memory size select register (ims) .........................................................................................15 5. internal expansion ram size select register (ixs) ........................................................15 6. flash memory programming ....................................................................................................1 6 6.1 selecting the transmission method........................................................................................... ..............16 6.2 flash memory programming functions .......................................................................................... ........17 6.3 connecting the flashpro iii................................................................................................. ......................18 6.4 flash memory programming by self-writing .................................................................................... ......19 7. electrical characteristics ................................................................................................... .27 8. package drawings............................................................................................................. ...........40 appendix a development tools.................................................................................................. ...41 appendix b related documents .................................................................................................. ..45
preliminary product information u13563ej2v0pm00 8 m m m m pd78f0701y 1. differences between the m m m m pd78f0701y and masked rom versions the m pd78f0701y is a product provided with flash memory that enables writing, erasing, and rewriting of programs without being removed from the board. table 1-1 shows the differences between the flash memory version ( m pd78f0701y) and masked rom versions ( m pd780701y and m pd780702y). table 1-1. differences between the m m m m pd78f0701y and masked rom versions item m pd78f0701y m pd780701y m pd780702y internal rom type flash memory masked rom ic pin not provided provided v pp pin provided not provided built-in bus controller dcan controller and iebus controller dcan controller iebus controller tx pin dcan or iebus output (switched by software) dcan output iebus output rx pin dcan or iebus input (switched by software) dcan input iebus input electrical characteristics refer to the data sheet of individual products. caution the flash memory versions and masked rom versions have different noise immunity and noise radiation characteristics. do not use es products for evaluation when considering switching from flash memory versions to those using masked rom upon the transition from preproduction to mass-production. cs products (masked rom versions) should be used in this case.
preliminary product information u13563ej2v0pm00 9 m m m m pd78f0701y 2. pin functions 2.1 port pins (1/2) pin name i/o function when reset also used as p00-p07 i/o port 0 8-bit input/output port can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. input intp0-intp7 p20 si31 p21 so31 p22 sck31 p23 buz p24 rxd0 p25 txd0 p26 asck0 p27 i/o port 2 8-bit input/output port can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. input pcl p30 si30 p31 so30 p32 whether an on-chip pull-up resistor is to be used can be specified by software. sck30 p33 n-ch open-drain input/output port (15-v withstand voltage) can directly drive leds. - p34 to00 p35 ti000 p36 i/o port 3 7-bit input/output port can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. input ti010 p40-p47 i/o port 4 8-bit input/output port can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. when a falling edge is detected, the interrupt request flag (krif) is set to 1. input - p50-p57 i/o port 5 8-bit input/output port ttl-level input and cmos output can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. input - p64-p67 i/o port 6 4-bit input/output port can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. input -
preliminary product information u13563ej2v0pm00 10 m m m m pd78f0701y 2.1 port pins (2/2) pin name i/o function when reset also used as p70 whether an on-chip pull-up resistor is to be used can be specified by software. ti52/to52 p71 sda0 p72 n-ch open-drain input/output port (5-v withstand voltage) scl0 p73 to01 p74 ti001 p75 ti011 p76 ti50/to50 p77 i/o port 7 8-bit input/output port can be set to either input or output in 1-bit units. whether an on-chip pull-up resistor is to be used can be specified by software. input ti51/to51 p80-p87 i/o port 8 8-bit input/output port can be set to either input or output in 1-bit units. input ani0-ani7 p90-p97 i/o port 9 8-bit input/output port can be set to either input or output in 1-bit units. input ani8-ani15 2.2 non-port pins (1/2) pin name i/o function when reset also used as intp0-intp7 input external interrupt input for which effective edges (rising and/or falling edges) can be specified. input p00-p07 si30 p30 si31 input serial data input to serial interface input p20 so30 p31 so31 output serial data output to serial interface input p21 sda0 i/o serial data input/output to serial interface input p71 sck30 p32 sck31 p22 scl0 i/o serial clock input/output to serial interface input p72 rxd0 input serial data input to asynchronous serial interface input p24 txd0 output serial data output to asynchronous serial interface input p25 asck0 input serial clock input to asynchronous serial interface input p26 crxd input dcan controller (dcan) data input input irx0 ctxd output dcan controller (dcan) data output output itx0 irx0 input iebus controller (iebus0) data input input crxd itx0 output iebus controller (iebus0) data output output ctxd
preliminary product information u13563ej2v0pm00 11 m m m m pd78f0701y 2.2 non-port pins (2/2) pin name i/o function when reset also used as ti000 external count clock input to 16-bit timer (tm00) p35 ti010 external count clock input to 16-bit timer (tm00) p36 ti001 external count clock input to 16-bit timer (tm01) p74 ti011 external count clock input to 16-bit timer (tm01) p75 ti50 external count clock input to 8-bit timer (tm50) p76/to50 ti51 external count clock input to 8-bit timer (tm51) p77/to51 ti52 input external count clock input to 8-bit timer (tm52) input p70/to52 to00 16-bit timer (tm00) output p34 to01 16-bit timer (tm01) output p73 to50 8-bit timer (tm50) output p76/ti50 to51 8-bit timer (tm51) output p77/ti51 to52 output 8-bit timer (tm52) output input p70/ti52 pcl output clock output input p27 buz output buzzer output input p23 ani0-ani7 p80-p87 ani8-ani15 input a/d converter (ad3) analog input input p90-p97 av ref input a/d converter (ad3) reference voltage and analog power supply -- av ss - a/d converter (ad3) ground potential - - x1 input -- x2 - connected to crystal for system clock oscillation -- reset input system reset input input - cpureg - cpu supply voltage regulator. connect this pin to the v ss0 or v ss1 pin through a 0.1- m f capacitor. -- v dd0 - positive supply voltage for ports - - v dd1 - positive supply voltage (except ports and analog section) - - v ss0 - ground potential for ports - - v ss1 - ground potential (except ports and analog section) - - v pp - this pin applies a high voltage when a program is written or verified. in normal operation mode, connect this pin directly to the v ss0 or v ss1 pin. --
preliminary product information u13563ej2v0pm00 12 m m m m pd78f0701y 2.3 pin input/output circuits and handling of unused pins table 2-1 lists the types of input/output circuits for each pin and explains how unused pins are handled. figure 2-1 shows the configuration of each type of input/output circuit. table 2-1. types of input/output circuit for each pin and handling of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00/intp0-p07/intp7 connect these pins to the v ss0 pin via respective resistors. p20/si31 8-c p21/so31 5-h p22/sck31 8-c p23/buz 5-h p24/rxd0 8-c p25/txd0 5-h p26/asck0 8-c p27/pcl 5-h p30/si30 8-c p31/so30 5-h p32/sck30 8-c connect these pins to the v dd0 or v ss0 pin via respective resistors. p33 13-p connect this pin to the v dd0 pin via resistors. p34/to00 5-h p35/ti000 p36/ti010 8-c connect these pins to the v dd0 or v ss0 pin via respective resistors. p40-p47 5-h connect these pins to the v dd0 pin via respective resistors. p50-p57 5-t p64-p67 p70/ti52/to52 5-h connect these pins to the v dd0 or v ss0 pin via respective resistors. p71/sda0 p72/scl0 13-r connect these pins to the v dd0 pin via respective resistors. p73/to01 5-h p74/ti001 p75/ti011 p76/ti50/to50 p77/ti51/to51 8-c p80/ani0-p87/ani7 p90/ani8-p97/ani15 11-e i/o connect these pins to the v dd0 or v ss0 pin via respective resistors. crxd/irx0 2 input connect this pin to the v dd0 or v ss0 pin via resistors. ctxd/itx0 3-b output leave this pin open. reset 2 - av ref input connect this pin to the v dd0 pin. av ss connect this pin to the v ss0 pin. v pp - - connect this pin directly to the v ss0 or v ss1 pin.
preliminary product information u13563ej2v0pm00 13 m m m m pd78f0701y figure 2-1. pin input/output circuits in schmitt trigger input with hysteresis characteristics type 2 type 3-b type 8-c pull-up enable v dd0 p-ch p-ch v dd0 n-ch v ss0 in/out data output disable type 11-e type 5-h type 13-p type 5-t type 13-r p-ch v dd0 n-ch n-ch v ss0 in/out data output disable + - p-ch av ss v ref comparator (threshold voltage) input enable p-ch v dd0 n-ch v ss0 out data pull-up enable v dd0 p-ch p-ch v dd0 n-ch v ss0 in/out data output disable input enable n-ch v ss0 in/out output data output disable input enable n-ch v ss0 in/out output data output disable pull-up enable v dd0 p-ch p-ch v dd0 n-ch v ss0 in/out data output disable input enable ttl input
preliminary product information u13563ej2v0pm00 14 m m m m pd78f0701y 3. selecting internal bus controllers (dcan and iebus) the m pd78f0701y has two internal bus controllers: a dcan controller and iebus controller. these bus controllers cannot be used simultaneously. by default, the dcan controller is selected. the iebus controller is selected by making the iebus unit active (by setting bit 7 (eniebus) of the iebus control register 0 (brc0) to 1). the default statuses of the interrupt request signals and pins differ depending on which of the internal bus controllers is used. table 3-1 shows the default statuses of the interrupt request signals and pins. table 3-1. default statuses of interrupt request signals and pins item using dcan controller using iebus controller default status of ctxd/itx0 pin high level low level intcr intie1 intct intie2 interrupt request signals note intce none note the statuses of the flags corresponding to the interrupt signals also differ.
preliminary product information u13563ej2v0pm00 15 m m m m pd78f0701y 4. memory size select register (ims) the memory size select register (ims) selects the internal memory size. this register is set by an 8-bit memory manipulation instruction. reset input sets ims to cfh. caution use ims with its default value (cfh). do not set any other values for the ims. figure 4-1. format of memory size select register (ims) 7 ims symbol 6543210 ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 rom3 rom2 rom1 rom0 11 11 110 internal rom capacity selection internal high-speed ram capacity selection 60k bytes not to be set other settings 1,024 bytes not to be set other settings ram2 ram1 ram0 address when reset r/w fff0h cfh r/w 5. internal expansion ram size select register (ixs) the internal expansion ram size select register (ixs) selects the internal expansion ram capacity. this register is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets ixs to 0ch. caution set ixs to 08h as the default status of the program. because ixs is set to 0ch at a reset, set it to 08h after a reset. figure 5-1. format of internal expansion ram size select register (ixs) 7 ixs symbol 6543 210 ixram4 ixram3 ixram2 ixram1 ixram0 0 0 0 ixram4 ixram3 ixram2 ixram1 ixram0 0 1 0 00 internal expansion ram capacity selection 2,048 bytes not to be set other settings address when reset r/w fff4h 0ch r/w
preliminary product information u13563ej2v0pm00 16 m m m m pd78f0701y 6. flash memory programming the flash memory can be written even while the device is mounted on the target system (on-board write). to write a program into the flash memory, connect the dedicated flash writer (flashpro iii (model number: fl-pr3 and pg- fp3)) to both the host machine and target system. a program can also be written by using an adapter, for flash memory writing, connected to the flashpro iii. remark the fl-pr3 is manufactured by naito densei machida mfg. co., ltd. 6.1 selecting the transmission method the flashpro iii writes into flash memory by means of serial transmission. the transmission method to be used for writing is selected from those listed in table 6-1. to select a transmission method, use the format shown in figure 6-1, according to the number of v pp pulses listed in table 6-1. table 6-1. transmission methods transmission method number of channels pins number of v pp pulses si30/p30 so30/p31 sck30/p32 0 three-wire serial i/o 2 si31/p20 so31/p21 sck31/p22 1 i 2 c bus 1 sda0/p71 scl0/p72 4 uart 1 rxd0/p24 txd0/p25 8 caution to select a transmission method, always use the corresponding number of v pp pulses listed in table 6-1. figure 6-1. format of transmission method selection 12 n v pp pulses flash memory write mode 10 v v dd v ss v dd v ss reset v pp
preliminary product information u13563ej2v0pm00 17 m m m m pd78f0701y 6.2 flash memory programming functions flash memory writing and other operations can be performed by transmitting/receiving commands and data according to the selected transmission method. table 6-2 lists the main flash memory programming functions. table 6-2. main flash memory programming functions function description reset stops writing or detects communication synchronization. batch verify compares the entire contents of memory with the input data. batch internal verify compares the entire contents of memory in different modes. batch erase erases the entire contents of memory. batch blank check checks that the entire contents of memory have been erased. high-speed write writes to the flash memory according to the specified write start address and number of data bytes to be written. continuous write continues writing based on the information input by using the high-speed write function. batch prewrite writes 00h into the entire contents of memory. status checks the current operation mode and whether the operation has terminated. oscillation frequency setting inputs the frequency information of the resonator. erase time setting inputs the memory erase time. baud rate setting sets the communication rate in uart mode. i 2 c communication mode setting sets standard or high-speed mode upon communication via i 2 c. silicon signature read outputs the device name, memory capacity, and device block information.
preliminary product information u13563ej2v0pm00 18 m m m m pd78f0701y 6.3 connecting the flashpro iii the connection between the flashpro iii and m pd78f0701y varies with the transmission method. figures 6-2 to 6-4 show the connection for each transmission method. figure 6-2. flashpro iii connection in three-wire serial i/o mode v pp v dd reset sck so si gnd v pp v dd0 reset sck3n si3n so3n v ss0 flashpro iii pd78f0701y n = 0 or 1 m figure 6-3. flashpro iii connection in i 2 c bus mode v pp v dd reset sck si gnd v pp v dd0 reset scl0 sda0 v ss0 flashpro iii pd78f0701y m figure 6-4. flashpro iii connection in uart mode v pp v dd reset so si gnd v pp v dd0 reset rxd0 txd0 v ss0 flashpro iii pd78f0701y m
preliminary product information u13563ej2v0pm00 19 m m m m pd78f0701y 6.4 flash memory programming by self-writing the flash memory of the m pd78f0701y can be rewritten by a program. (1) configuration of flash memory figure 6-5 shows the configuration of the flash memory. figure 6-5. configuration of flash memory f7ffh f000h efffh normal operation mode internal extension ram are (2k bytes) flash memory area (60k bytes) flpmc 08h flpmc 09h self-writing mode internal extension ram are (2k bytes) flash memory area (60k bytes) f7ffh erase/write routine call erase/write firmware area (erase/write routine included) f000h efffh 0000h 0000h 9bffh 8000h * cannot be accessed by an ordinary instruction.
preliminary product information u13563ej2v0pm00 20 m m m m pd78f0701y (2) flash programming mode control register (flpmc) the flash programming mode control register (flpmc) is used to select an operation mode and check the status of the v pp pin. this register is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets flpmc to 08h. figure 6-6. format of flash programming mode control register (flpmc) flpmc symbol 000 0 0 1 vpp 1 vpp applied voltage of v pp pin the voltage necessary for erasing/writing flash memory is not applied to the v pp pin. a voltage higher than that on the v dd pin is applied to the v pp pin. 0 1 flspm0 operation mode selection normal operation mode self-writing mode 0 flspm0 7 65 432 10 address when reset r/w ffcdh 08h note 1 r/w note 2 notes 1. bit 2 changes depending on the level of the v pp pin. 2. bit 2 is a read-only bit. cautions 1. clear bits 1 and 4 to 7 to 0, and set bit 3 to 1. 2. the vpp bit indicates the status of the voltage applied to the v pp pin. when the vpp bit is "0", the voltage necessary for erasing/writing the flash memory is not applied to the v pp pin. however, the voltage necessary for erasing/writing is not always applied even when the vpp bit is "1". configure the hardware so that the necessary voltage is accurately applied to the v pp pin. to check whether the necessary voltage is also applied to the v pp pin by software, not only by hardware, use an external hardware detection circuit and its output signals.
preliminary product information u13563ej2v0pm00 21 m m m m pd78f0701y (3) self writing procedure the procedure for self writing the flash memory is as follows (see figure 6-7): (1) disable the interrupts. (2) set self-writing mode (flpmc = 09h). (3) select register bank 3. (4) specify the first address of the entry ram to the hl register. (5) v pp : on (on signal for power ic). (6) check the v pp level. (7) initialize the flash subroutine. (8) set the parameters. (9) control the flash memory (erasing, writing, etc.). (10) v pp : off (off signal for power ic). (11) normal operation mode (flpmc = 08h)
preliminary product information u13563ej2v0pm00 22 m m m m pd78f0701y figure 6-7. self-programming flowchart disable interrupts. (1) select register bank 3. (3) set parameter. (8) (9) ye s ye s ye s no no no ye s no v pp = 1? flash memory is abnormal. nth note less than n note pre-write erase error? write data. error? verify. error? (10) v pp : on (5) self-writing mode (flpmc = 09h) (2) normal operation mode (flpmc = 08h) (11) initialize flash subroutine. (7) (6) specify entry ram address. (4) v pp : off number of errors? note this differs depending on the user program.
preliminary product information u13563ej2v0pm00 23 m m m m pd78f0701y figure 6-8. self-writing timing reset cpu operation and program processing reset mode normal program processing flpmc 09h v pp on flash memory being written v pp = 10 v 0.3 v v pp off flpmc 08h normal operation mode self-writing mode mode setting erase write verify mode setting normal program processing normal operation mode reset mode 0 v 5 v 0 v 10 v 5 v 4.5 v v dd v pp 0.2 v dd 9.7 v 0 v 0.2 v dd 0.2 v dd 4.5 v
preliminary product information u13563ej2v0pm00 24 m m m m pd78f0701y (4) cpu resources the cpu resources used for self-writing the flash memory are as follows: register bank: bank3 (8 bytes) b register: status flag c register: function number hl register: entry ram area first address stack area: 16 bytes max. write data storage area: 1 to 256 bytes entry ram area: 32 bytes ram area used by self-writing subroutine. can be specified by user by using hl register. status flag 76543210 parameter setting error -- verify error write error - blank check error - (5) entry ram area table 6-3 shows the contents of the entry ram area. table 6-3. entry ram area offset value contents +0 reserved area (1 byte) +1 reserved area (1 byte) +2 flash memory start address (2 bytes) +4 flash memory end address (2 bytes) +6 number of bytes written to flash memory (1 byte) +7 write time data (1 byte) +8 erase time data (3 bytes) +11 reserved area (3 bytes) +14 write data storage buffer first address (2 bytes) +16 total number of blocks (1 byte) +17 total number of areas (1 byte) +18 : reserved area (14 bytes) example : when the value of the hl register in register bank 3 is 0fd00h 0fd00h: status 0fd02h: flash memory start address 0fd06h: number of bytes written to flash memory :
preliminary product information u13563ej2v0pm00 25 m m m m pd78f0701y the following explains the entry ram area in detail. (a) flash memory start address flash memory address value used for _flashbytewrite subroutine (b) flash memory end address flash memory address value used for _flashgetinfo subroutine (c) number of bytes written to flash memory area number and number of bytes written to flash memory (d) write time set one of the following values according to the operating frequency. f x (mhz) set value 1.00 to 1.28 20h 1.29 to 2.56 40h 2.57 to 5.12 60h 5.13 to 8.38 80h (e) erase time data set value = erase time (s) operating frequency/2 9 + 1 (erase time range: 0.5 to 20 s) example : when the erase time is two seconds and the operating frequency is 6.29 mhz set value = 2 6,291,456/512 + 1 = 24,577 (decimal) = 6001h (hexadecimal) (f) write data storage buffer first address this area stores the first address of the write data storage buffer area. the data (write data) in the ram addressed by using the data in this area is written into flash memory (_flashbytewrite subroutine). up to 256 bytes of write data can be specified with the data in this area as the first address. (g) total number of blocks total number of flash memory blocks stored by _flashgetinfo subroutine (h) total number of areas total number of flash memory areas stored by _flashgetinfo subroutine
preliminary product information u13563ej2v0pm00 26 m m m m pd78f0701y (6) self-writing subroutine table 6-4 lists the subroutines to be used for self-writing and their functions. table 6-4. self-writing subroutines function no. decimal hexa- decimal subroutine name function 0 00h _flashenv initializes flash subroutine. 1 01h _flashsetenv sets parameter. 2 02h _flashgetinfo reads flash memory information. 16 10h _flashareablankcheck blank check of specified area 32 20h _flashareaprewrit pre-write of specified area 48 30h _flashareaerase erases specified area 80 50h _flashbytewrite successive write in byte units 96 60h _flashareaiverify internal verification of specified area (7) configuration of self-writing circuit figure 6-9 shows the configuration of the self-writing circuit. figure 6-9. configuration of self-writing circuit v in = 11 to 13.5 v v out = 9.7 to 10.2 v v pp v ss output port v dd pd78f0701y 10 k v ss on/off output input power ic pc29s10, etc. m w 10 k w 3 m
preliminary product information u13563ej2v0pm00 27 m m m m pd78f0701y 7. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rated value unit v dd av ref v dd = av ref -0.3 to +6.5 v v pp -0.3 to +10.5 v supply voltage av ss -0.3 to +0.3 v v i1 p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, crxd/irx0, x1, x2, reset -0.3 to v dd + 0.3 v input voltage v i2 p33 n-ch open drain -0.3 to +16 v output voltage v o p00-p07, p20-p27, p30-p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, ctxd/itx0 -0.3 to v dd + 0.3 v analog input voltage v an p80-p87, p90-p97 analog input pin av ss - 0.3 to av ref + 0.3 and -0.3 to v dd + 0.3 v p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70, p73-p77, p80-p87, p90- p97, ctxd/itx0 per pin -10 ma high-level output current i oh total for all pins -30 ma peak value 20 ma p00-p07, p20-p27, p30-p32, p34- p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, ctxd/itx0 per pin rms value 10 ma peak value 30 ma p33 rms value 15 ma peak value 100 ma low-level output current i ol note total for all pins rms value 60 ma operating ambient temperature t a -40 to +85 c programming ambient temperature -10 to +55 c before 2,000 hours elapses after flash memory programming was performed -65 to +150 c storage temperature t stg after flash memory programming was performed and 2,000 hours or more has elapsed -65 to +125 c note to obtain the rms value, calculate [rms value] = [peak value] ? duty. caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values. remark unless otherwise specified, the characteristics of a dual-function pin are the same as those of the corresponding port pin.
preliminary product information u13563ej2v0pm00 28 m m m m pd78f0701y characteristics of the system clock oscillation circuit (t a = -40 c to +85 c, v dd = 3.5 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 6.29 note 2 mhz crystal v pp x2 x1 r1 c2 c1 oscillation settling time note 3 30 ms notes 1. only the characteristics of the oscillation circuit are indicated. 2. 6.29 = 6.291456 (mhz) 3. time required for oscillation to settle once a reset sequence ends or stop mode is deselected. caution when using the system clock oscillation circuit, observe the following conditions for the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the influence of the wiring capacitance. keep the wiring as short as possible. do not allow signal wires to cross one another. keep the wiring away from wires that carry a high, non-stable current. keep the grounding point of the capacitors at the same level as v ss1 . do not connect the grounding point to a grounding wire that carries a high current. do not extract a signal from the oscillation circuit.
preliminary product information u13563ej2v0pm00 29 m m m m pd78f0701y dc characteristics (t a = -40 c to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit v ih1 p21, p23, p25, p27, p31, p34, p40-p47, p64-p67, p73, p80-p87, p90-p97 0.7v dd v dd v v ih2 p00-p07, p20, p22, p24, p26, p30, p32, p35, p36, p70-p72, p74-p77, crxd/irx0, reset 0.8v dd v dd v v ih3 p50-p57 2.3 v dd v v ih4 p33 n-ch open drain 0.7v dd 15 v high-level input voltage v ih5 x1, x2 v dd - 0.5 v dd v v il1 p21, p23, p25, p27, p31, p34, p40-p47, p64-p67, p73, p80-p87, p90-p97 00.3v dd v v il2 p00-p07, p20, p22, p24, p26, p30, p32, p35, p36, p70-p72, p74-p77, crxd/irx0, reset 00.2v dd v v il3 p50-p57 0 0.75 v v il4 p33 n-ch open drain 0 0.3v dd v low-level input voltage v il5 x1, x2 0 0.4 v v oh1 i oh = -1 ma v dd - 1.0 v dd v high-level output voltage v oh2 i oh = -100 m a p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70, p73-p77, p80-p87, p90-p97, ctxd/itx0 v dd - 0.5 v dd v v ol1 i ol = 15 ma p33 0.4 2.0 v v ol2 i ol = 1.6 ma p71, p72 0.4 v v ol3 i ol = 1 ma 1.0 v low-level output voltage v ol4 i ol = 100 m a p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70, p73-p77, p80-p87, p90-p97, ctxd/itx0 0.5 v i lih1 p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, crxd/irx0, r eset 3 m a i lih2 v in = v dd x1, x2 20 m a high-level input leakage current i lih3 v in = 15 v p33 80 m a i lil1 p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, crxd/irx0, reset -3 m a i lil2 x1, x2 -20 m a low-level input leakage current i lil3 v in = 0 v p33 (during other than input instruction execution note ) -3 m a note during input instruction execution, a leakage current of -200 m a (max.) is input to p33 for one clock (during no wait). remark unless otherwise specified, the characteristics of a dual-function pin are the same as those of the corresponding port pin.
preliminary product information u13563ej2v0pm00 30 m m m m pd78f0701y dc characteristics (t a = -40 c to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit high-level output leakage current i loh v out = v dd p00-p07, p20-p27, p30-p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, ctxd/itx0 3 m a low-level output leakage current i lol v out = 0 v p00-p07, p20-p27, p30-p36, p40-p47, p50-p57, p64-p67, p70-p77, p80-p87, p90-p97, ctxd/itx0 -3 m a software pull-up resistor r 1 v in = 0 v p00-p07, p20-p27, p30-p32, p34-p36, p40-p47, p50-p57, p64-p67, p70, p73-p77 15 30 90 k w i dd1 6.29-mhz crystal oscillation operating mode 4.0 20 ma i dd2 6.29-mhz crystal oscillation halt mode note 2 500 1,000 m a power supply current note 1 i dd3 stop mode 0.1 30 m a notes 1. the current flowing through the v dd1 pin. the power supply current does not include the current flowing through the a/d converter and on-chip pull-up resistors. 2. during low-speed mode operation (when 04h is loaded into the processor clock control register (pcc)). the power supply current does not include the current for peripheral circuit operation. remark unless otherwise specified, the characteristics of a dual-function pin are the same as those of the corresponding port pin.
preliminary product information u13563ej2v0pm00 31 m m m m pd78f0701y ac characteristics (1) basic operations (t a = -40 c to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time (minimum instruction execution time) t cy system clock operation (at f x = 6.291456 mhz) 0.318 5.09 m s ti000, ti010, ti001, and ti011 input high/low level width t tih0 t til0 4/f sam + 0.25 note m s ti50, ti51, and ti52 input frequency f ti5 2 mhz ti50, ti51, and ti52 input high/low level width t tih5 t til5 200 ns interrupt request input high/low level width t inth t intl intp0 to intp7, p40 to p47 10 m s reset low level width t rsl 10 m s note f x /2, f x /4, or f x /64 can be selected as f sam by using bits 0 and 1 (prm0n0 and prm0n1) of the prescaler mode register 0n (prm0n). if the valid edge of ti00n is selected as the count clock, however, f sam = f x /8 (n = 0 or 1). t cy vs v dd (with system clock running) supply voltage v dd [v] 0 1.0 2.0 3.0 4.0 5.0 6.0 10.0 5.09 5.0 2.0 1.0 0.5 0.318 0.1 cycle time t cy [ s] guaranteed operating range m 3.5 5.5
preliminary product information u13563ej2v0pm00 32 m m m m pd78f0701y (2) serial interface (t a = -40 c to +85 c, v dd = 3.5 to 5.5 v) (a) three-wire serial i/o mode (sck30...internal clock output) parameter symbol conditions min. typ. max. unit sck30 cycle time t kcy1 1.9 m s sck30 high/low level width t kh1 t kl1 t kcy1 /2 - 50 ns si30 setup time (for sck30 - ) t sik1 100 ns si30 hold time (for sck30 - ) t ksi1 400 ns delay from sck30 to so30 output t kso1 c = 100 pf note 300 ns note c is the capacitance of the sck30 and so30 output line. (b) three-wire serial i/o mode (sck30...external clock input) parameter symbol conditions min. typ. max. unit sck30 cycle time t kcy2 800 ns sck30 high/low level width t kh2 t kl2 400 ns si30 setup time (for sck30 - ) t sik2 100 ns si30 hold time (for sck30 - ) t ksi2 400 ns delay from sck30 to so30 output t kso2 c = 100 pf note 300 ns note c is the capacitance of the so30 output line.
preliminary product information u13563ej2v0pm00 33 m m m m pd78f0701y (c) three-wire serial i/o mode (sck31...internal clock output) parameter symbol conditions min. typ. max. unit sck31 cycle time t kcy3 1.9 m s sck31 high/low level width t kh3 t kl3 t kcy1 /2 - 50 ns si31 setup time (for sck31 - ) t sik3 100 ns si31 hold time (for sck31 - ) t ksi3 400 ns delay from sck31 to so31 output t kso3 c = 100 pf note 300 ns note c is the capacitance of the sck31 and so31 output line. (d) three-wire serial i/o mode (sck31...external clock input) parameter symbol conditions min. typ. max. unit sck31 cycle time t kcy4 800 ns sck31 high/low level width t kh4 t kl4 400 ns si31 setup time (for sck31 - ) t sik4 100 ns si31 hold time (for sck31 - ) t ksi4 400 ns delay from sck31 to so31 output t kso4 c = 100 pf note 300 ns note c is the capacitance of the so31 output line.
preliminary product information u13563ej2v0pm00 34 m m m m pd78f0701y (e) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 38,836 bps (f) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck0 cycle time t kcy3 800 ns asck0 high/low level width t kh3 , t kl3 400 ns transfer rate 39,063 bps (g) i 2 c bus mode standard mode high-s peed mode parameter symbol min. max. min. max. unit scl0 clock frequency f scl 0 100 0 400 khz bus free time (between stop-start conditions) t buf 4.7 - 1.3 - m s hold time note 1 t hd:sta 4.0 - 0.6 - m s scl0 clock low level width t low 4.7 - 1.3 - m s scl0 clock high level width t high 4.0 - 0.6 - m s start/restart condition setup time t su:sta 4.7 - 0.6 - m s cbus-compatible master 5.0 - - - m s data hold time i 2 c bus t hd:dat 0 note 2 - 0 note 2 0.9 note 3 m s data setup time t su:dat 250 - 100 note 4 -ns sda0 and scl0 signal rising time t r - 1,000 - 300 ns sda0 and scl0 signal falling time t f - 300 - 300 ns stop condition setup time t su:sto 4.0 - 0.6 - m s pulse width of spikes controlled by the input filter t sp --050ns capacitive load of each bus line cb - 400 - 400 pf notes 1. in the start condition, the first clock pulse is generated after this period of time. 2. to fill the undefined area of the scl0 falling edge (at v ihmin. of the scl0 signal), the device needs to internally provide a hold time of at least 300 ns for the sda0 signal. 3. if the device does not extend the low hold time (t low ) of the scl0 signal, the maximum data hold time (t hd:dat ) only needs to be satisfied. 4. high-speed mode i 2 c bus can be used in standard mode i 2 c bus system. in this case, the following conditions must be satisfied: when the device does not extend the low hold time of the scl0 signal t su:dat 3 250 ns when the device extends the low hold time of the scl0 signal before scl0 is released (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: for standard mode i 2 c bus system), the next data bit must be sent onto the sda0 line.
preliminary product information u13563ej2v0pm00 35 m m m m pd78f0701y ac timing measurement points (except the x1 inputs) 0.8v dd 0.2v dd measurement points 0.8v dd 0.2v dd clock timing 1/f x t xl t xh x1 input v ih5 (min.) v il5 (max.) ti timing t tih0 t til0 ti000, ti010, ti001, ti011 1/f ti5 t til5 t tih5 ti50, ti51, ti52
preliminary product information u13563ej2v0pm00 36 m m m m pd78f0701y serial transfer timing three-wire serial i/o mode: sck30, sck31 t kln t kcyn t khn si30, si31 input data t ksin t sikn output data t kson so30, so31 n = 1-4 uart mode (external clock input): asck0 t kl5 t kcy5 t kh5 i 2 c bus mode: scl0 sda0 t hd:sta t buf t hd:dat t high t f t su:dat t su:sta t hd:sta t sp t su : sto t r stop condition start condition stop condition restart condition t low
preliminary product information u13563ej2v0pm00 37 m m m m pd78f0701y iebus 0 controller characteristics (t a = -40 c to +85 c, v dd = 3.5 to 5.5 v) parameter symbol conditions min. typ. max. unit iebus system clock frequency f s fixed to mode 1 6.29 mhz driver delay (from itx0 output to bus line) t dtx c = 50 pf note the m pc2590 is used as a driver/receiver. 1.5 m s receiver delay (from bus line to irx0 input) t drx the m pc2590 is used as a driver/receiver. 0.7 m s transmission delay on bus t dbus the m pc2590 is used as a driver/receiver. 0.85 m s note c is the load capacitance of the itx0 output line. remarks 1. although the iebus standard recommends the 6.0-mhz system clock frequency, the m pd78f0701y guarantees normal operation of the iebus controller at 6.29 mhz. 2. f s : system clock frequency of the iebus controller a/d converter characteristics (t a = -40 c to +85 c, v dd = av ref = 3.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 888bit total error note 0.6 % conversion time t conv 14 100 m s analog input voltage v ian av ss av ref v av ref resistance r airef t.b.d 28 t.b.d k w note no quantization error ( 0.2%) is included. this parameter is indicated as the ratio to the full-scale value.
preliminary product information u13563ej2v0pm00 38 m m m m pd78f0701y data memory stop mode low supply voltage data retention characteristics (t a = -40 c to +85 c) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 2.0 5.5 v data retention supply current i dddr v dddr = 2.0 v 0.1 10 m a release signal set time t srel 0 m s released by reset 2 17 /f x ms oscillation settling time t wait released by interrupt note ms note selection of 2 12 /f x , 2 14 /f x , 2 19 /f x , or 2 21 /f x is available by bits 0 to 2 (osts0 to osts2) of the oscillation settling time selection register (osts). data retention timing (stop mode release by reset) stop mode data retention mode t srel t wait internal reset operation halt mode v dddr stop instruction execution v dd reset operating mode data retention timing (standby release signal: stop mode release by interrupt signal) stop mode data retention mode t srel t wait halt mode stop instruction execution v dd standby release signal (interrupt request) v dddr operating mode
preliminary product information u13563ej2v0pm00 39 m m m m pd78f0701y interrupt request input timing intp0-intp7 t intl t inth reset input timing reset t rsl
preliminary product information u13563ej2v0pm00 40 m m m m pd78f0701y 8. package drawings 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. p80gc-65-8bt f 0.825 0.032 b 14.00 0.20 0.551 +0.009 e0.008 s 1.70 max. 0.067 max. m 0.17 0.007 +0.001 e0.003 +0.03 e0.07 +0.009 e0.008 c 14.00 0.20 0.551 +0.009 e0.008 a 17.20 0.20 0.677 0.008 g 0.825 0.032 h 0.32 0.06 0.013 +0.002 e0.003 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) k 1.60 0.20 0.063 0.008 l 0.80 0.20 0.031 +0.009 e0.008 n 0.10 0.004 p 1.40 0.10 0.055 0.004 q 0.125 0.075 0.005 0.003 r3 3 +7 e3 +7 e3 d 17.20 0.20 0.677 0.008 41 60 40 61 21 80 20 1 m s q r k m l a b c d j h i f g p n detail of lead end
preliminary product information u13563ej2v0pm00 41 m m m m pd78f0701y appendix a development tools the following development tools are available for developing systems using the m pd78f0701y. be sure to see notes described in (5) . (1) language processing software ra78k/0 assembler package used in common with the 78k/0 series cc78k/0 c compiler package used in common with the 78k/0 series df780701 note device file for the m pd780701y sub-series cc78k/0-l c compiler library source file used in common with the 78k/0 series note under development (2) flash memory write tools flashpro iii (model no. fl-pr3, pg-fp3) flash writer used only for microcontrollers with internal flash memory fa-80gc flash memory write adapter. connect this adapter to the flashpro iii. this adapter is dedicated to the 80-pin plastic qfp (gc-8bt type). floashpro iii controller program controlled by a personal computer and which is supported by flashpro iii. runs under windows tm 95, etc. (3) debugging tools when in-circuit emulator ie-78k0-ns is used ie-78k0-ns in-circuit emulator used in common with the 78k/0 series ie-70000-mc-ps-b power supply unit for the ie-78k0-ns ie-70000-98-if-c interface adapter required when a pc-9800 series computer (other than a notebook type) is used as the host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable required when a notebook-type computer is used as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter required when an ibm pc/at tm or compatible is used as the host machine (isa bus supported) ie-70000-pci-if interface adapter when using pc that incorporates pci bus as host machine ie-780701-ns-em1 note emulation board used to emulate the m pd780701y sub-series products np-80gc emulation probe dedicated to the 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket for connecting the target system board created for the 80-pin plastic qfp (gc-8bt type) with the np-80gc id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator used in common with the 78k/0 series df780701 note device file for the m pd780701y sub-series note under development
preliminary product information u13563ej2v0pm00 42 m m m m pd78f0701y when in-circuit emulator ie-78001-r-a is used ie-78001-r-a in-circuit emulator used in common with the 78k/0 series ie-70000-98-if-c interface adapter required when a pc-9800 series computer (other than a notebook type) is used as the host machine (c bus supported) ie-70000-pc-if-c interface adapter required when an ibm pc/at or compatible is used as the host machine (isa bus supported) ie-70000-pci-if interface adapter when using pc that incorporates pci bus as host machine ie-78000-r-sv3 interface adapter and cable required when an ews is used as the host machine ie-780701-ns-em1 note emulation board used to emulate the m pd780701y sub-series ie-78k0-r-ex1 emulation probe conversion board required when the ie-780701-ns-em1 is used with the ie-78001-r-a ep-78230gc-r emulation probe dedicated to the 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket for connecting the target system board created for the 80-pin plastic qfp (gc-8bt type) with the ep-78230gc-r id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator used in common with the 78k/0 series df780701 note device file for the m pd780701y sub-series note under development (4) real-time os rx78k/0 real-time os for the 78k/0 series mx78k0 os for the 78k/0 series (5) notes on using development tools id78k0-ns, id78k0, and sm78k0 are to be used in combination with df780701. cc78k/0 and rx78k/0 are to be used in combination with ra78k/0 and df780701. fl-pr3, fa-80gc, and np-80gc are manufactured by naito densei machida mfg. co., ltd. (044-822-3813). contact nec sales representatives for purchase. for third party development tools, refer to the 78k/0 series selection guide (u11126e). the host machines and oss supporting each software product are as follows: pc ews host machine [os] software pc-9800 series [windows] ibm pc/at and compatibles [japanese/english windows] hp9000 series 700 tm [hp-ux tm ] sparcstation tm [sunos tm , solaris tm ] news tm (risc) [news-os tm ] ra78k/0 o note o cc78k/0 o note o id78k0-ns o - id78k0 oo sm78k0 o - rx78k/0 o note o mx78k0 o note o note dos-based software
preliminary product information u13563ej2v0pm00 43 m m m m pd78f0701y package drawings of the conversion socket (ev-9200gc-80) and recommended pattern on boards figure a-1. package drawings of the ev-9200gc-80 (reference) a f d 1 no.1 pin index e ev-9200gc-80 b c m n o l k s r q p i h j g ev-9200gc-80-g0e item millimeters inches a b c d e f g h i j k l m o n p q r s 18.0 14.4 14.4 18.0 4-c 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-c 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f based on ev-9200gc-80 (1) package drawing (in mm) f
preliminary product information u13563ej2v0pm00 44 m m m m pd78f0701y figure a-2. recommended pattern for mounting the ev-9200gc-80 on boards (reference) a f d e c b g j k l h i 0.026 0.748=0.486 0.026 0.748=0.486 ev-9200gc-80-p1e item millimeters inches a b c d e f g h i j k l 19.7 15.0 15.0 19.7 6.0 0.05 6.0 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 0.65 0.02 19=12.35 0.05 0.65 0.02 19=12.35 0.05 f f +0.001 e0.002 +0.003 e0.002 +0.001 e0.002 +0.003 e0.002 +0.003 e0.002 +0.003 e0.002 +0.001 e0.001 +0.001 e0.002 f +0.001 e0.002 f f based on ev-9200gc-80 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution f
preliminary product information u13563ej2v0pm00 45 m m m m pd78f0701y appendix b related documents documents related to devices document no. document name japanese english m pd780701y sub-series user's manual u13781j u13781e m pd780701y, 780702y preliminary product information u13920j u13920e m pd78f0701y preliminary product information u13563j this manual 78k/0 series user's manual, instruction u12326j u12326e documents related to development tools (user's manual) document no. document name japanese english operation u11802j u11802e language u11801j u11801e ra78k0 assembler package structured assembly language u11789j u11789e ra78k series structured assembler preprocessor u12323j eeu-1402 operation u11517j u11517e cc78k0 c compiler language u11518j u11518e cc78k/0 c compiler application note programming know-how u13034j u13034e ie-78k0-ns to be created to be created ie-78001-r-a to be created to be created ie-78k0-r-ex1 to be created to be created ie-780701-ns-em1 to be created to be created ep-78230 eeu-985 eeu-1515 sm78k0 system simulator windows base reference u10181j u10181e sm78k series system simulator external parts user open interface specifications u10092j u10092e id78k0-ns integrated debugger windows base reference u12900j u12900e id78k0 integrated debugger ews base reference u11151j - id78k0 integrated debugger windows base guide u11649j u11649e id78k0 integrated debugger pc base reference u11539j u11539e
preliminary product information u13563ej2v0pm00 46 m m m m pd78f0701y documents related to software to be incorporated into the product (user's manual) document no. document name japanese english basic u11537j u11537e 78k/0 series real-time os installation u11536j u11536e os for 78k/0 series mx78k0 basic u12257j u12257e other documents document no. document name japanese english nec ic package manual (cd-rom) - c13388e semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e semiconductor device quality control/reliability handbook c12769j - guide for products related to micro-computer: other companies u11416j - caution the above documents may be revised without notice. use the latest versions when you design an application system.
preliminary product information u13563ej2v0pm00 47 m m m m pd78f0701y notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
preliminary product information u13563ej2v0pm00 48 m m m m pd78f0701y fip is a trademark of nec corporation. iebus and inter equipment bus are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. caution this product contains an i 2 c bus interface circuit. when using the i 2 c bus interface, notify its use to nec when ordering custom code. nec can guarantee the following only when the customer informs nec of the use of the interface: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
preliminary product information u13563ej2v0pm00 49 m m m m pd78f0701y regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
preliminary product information u13563ej2v0pm00 50 m m m m pd78f0701y [memo]
preliminary product information u13563ej2v0pm00 51 m m m m pd78f0701y [memo]
m m m m pd78f0701y some related documents may be preliminary versions. note that, however, what documents are preliminary is not indicated in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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