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1/23 SERCON816 january 2003 n single-chip controller for sercos interface n real time communication for industrial control systems n 8/16-bit bus interface, intel and motorola control signals n dual port ram with 2048 word *16-bit n data communications via optical fiber rings, rs 485 rings and rs 485 busses n maximum transmission rate of 16 mbaud with internal clock recovery n internal repeater for ring connections n full duplex operation n modulation of power of optical transmitter diode n automatic transmission of synchronous and data telegrams in the communication cycle n flexible ram configuration, communication data stored in ram (single or double buffer) or transfer via dma n synchronization by external signal n timing control signals n automatic service channel transmission n watchdog to monitor software and external synchronization signals n compatible mode to sercon410b sercos interface controller n 100-pin plastic flat-pack casing figure 1. SERCON816 block diagram bus interface telegram- processing timing- control clock re se t watc h- dog inter- rup t serial interface dma admux busm o de[ 1 : 0 ] buswidth byted ir sba ud sba ud 1 6 t m0/1 l_ errn rec a c t n idle int 0/1 cyc_clk con_clk div_clk sc lk sc lko 2 / 4 wdogn mclk rstn dmareqr/t dmaacknr/ t rx c rx d tx c t xd[6: 1] wrn d[15:0] a[15:0] busyn rd n alel aleh bhen mcsn0/1 pc sn 0 pc s1 optic a l transm itter/ receiver or rs-485 bus drive pqfp100 ordering numbers: serc816 serc816/tr sercos interface controller
SERCON816 2/23 table of contents 1 general description........................................................................................................... ......3 2 pin description ............................................................................................................... ....................5 3 electrical (dc and ac) characteristics ........................................................................................ ......7 3.1 absolute maximum ratings .................................................................................................... .7 3.2 recommended operating conditions ......................................................................................8 3.3 electrical characteristcs ........................................................................................8 3.4 power dissipation ........................................................................................................... .........9 3.4.1 power dissipation considerations....................................................................................9 3.5 ac electrical characteristics............................................................................................... ...10 3.5.1 clock input mclk.......................................................................................................... .10 3.5.2 clock input sclk .......................................................................................................... .11 3.5.3 address latch............................................................................................................. ....11 3.5.4 read access of control registers..................................................................................12 3.5.5 read access of dual port ram .....................................................................................13 3.5.6 write access to control registers..................................................................................14 3.5.7 write access to dual port ram ...................................................................................15 4 control registers and ram data structures....................................................................................1 6 4.1 control register addresses .................................................................................................. .16 4.2 data structures within the ram .............................................................................................1 6 4.2.1 telegram headers.......................................................................................................... 16 4.2.2 data containers........................................................................................................... ...17 4.2.3 end marker ................................................................................................................ .....18 4.2.4 service containers ........................................................................................................ .18 5 additional specifications, tools and support .................................................................................. .21 5.1 additional specifications ................................................................................................... .....21 5.2 hardware and software components ....................................................................................21 5.3 tools ....................................................................................................................... ...............21 6 package mechanical data: SERCON816 100 pin plastic quad flat pack package (pqfp100) ...............................................22
3/23 SERCON816 1 general description the sercos interface controller SERCON816 is an integrated circuit for sercos interface communication systems. the sercos interface is a digital interface for communication between systems which have to ex- change information cyclically at short, fixed intervals (62,5 s to 65 ms). it is appropriate for the synchronous operation of distributed control or test equipment (e.g. connection between drives and numeric control). a sercos interface communication system consists of one master and several slaves. these units are connected by a fiber optical ring. this ring starts and ends at the master. the slaves regenerate and repeat their received data or send their own telegrams. by this method the telegrams sent by the master are re- ceived by all slaves while the master receives data telegrams from the slaves. the optical fiber assures a reliable high-speed data transmission with excellent noise immunity. the sercos interface controller contains all the hardware-related functions of the sercos interface and considerably reduces the hardware costs and the computing time requirements of the microprocessor. it is the direct link between the electro-optical receiver and transmitter and the microprocessor that executes the control algorithms. the SERCON816 can be used both for sercos interface masters and slaves. the circuit contains the following functions (fig. 1): C interface to the microprocessor with a data bus width of 8 or 16 bits and with control lines according to intel or motorola standards. C a serial interface for making a direct connection with the optical receiver and transmitter of the fiber optic ring or with drivers to an electric ring or bus. data and clock regeneration, the repeater for ring topologies and the serial transmitter and receiver are integrated. the signals are monitored and test signals generated. the se- rial interface operates up to 16 mbaud without external circuitry. C a dual port ram (2048 * 16 bit) for control and communication data. the organization of the memory is flexible. C telegram processing for automatic transmission and monitoring of synchronous and data telegrams. only transmission data which is intended for the particular interface user is processed. the transmitted data is ei- ther stored in the internal ram (single or double buffer) or transferred via direct memory access (dma). the transmission of service channel information over several communication cycles is executed automatically. in addition to the sercos interface the SERCON816 can also be used for other real-time communica- tions tasks. as an alternative to the fiber optical ring also bus topologies with rs-485 signals are supported (fig. 4). the SERCON816 is therefore suitable for a wide range of applications. remark: the SERCON816 is based on the former sercon410b sercos interface controller. figure 2. SERCON816 pin configuration SERCON816 80 d12 d13 d14 d15 vdd 75 bhen a0 a1 70 vss a2 a3 a4 a5 a6 a7 65 vdd a8 a9 a10 a11 60 vss a12 a13 a14 a15 55 vdd alel aleh w rn 51 rdn vdd 1 sclk vss mclk sclk04 5 sclk02 test vdd outz ndtro rstn 10 rxc txc rxd vss 15 txd1 txd2 txd3 vdd txd4 20 txd5 txd6 vss wdogn idle 25 recactn vdd sbaud16 sbaud tm0 30 vss 81 d11 d10 d9 d8 85 vdd d7 d6 d5 d4 90 vss d3 d2 d1 d0 95 admux busmode0 busmode1 buswidth bytdir 100 50 vss pcs1 pcsn0 mcsn1 mcsn0 45 busyn int0 int1 vss dmaacktn 40 dmaackrn dmareqt dmareqr vdd div_clk 35 con_clk cyc_clk vss l_errn 31 tm1
SERCON816 4/23 figure 3. SERCON816 with ring connection (sercos interface) figure 4. SERCON816 with rs-485 bus connection p tx d rxd bus interface p tx d rxd bus interface p tx d rxd bus interface p bus interface master slave 1 slave 2 sla v e n fibre optical ring serc o n 8 1 6 serc o n 8 1 6 SERCON816 serc o n 8 1 6 p p p businterface businterface businterface p bus interface master sla ve 1 sla v e 2 sl a v e n sercring.cdr serc o n 8 1 6 serc o n 8 1 6 serc o n 8 1 6 SERCON816 idle idle idle idle
5/23 SERCON816 2 pin description table 1. SERCON816 i/o port function summary signal(s) pin(s) io function d15-0 77-80, 82-85, 87-90, 92-95 i/o data bus: for 8-bit-wide bus interfaces, data is wri tt en to and read via d7-0, for 16-bit-wide bus interfaces via d15-0. when admux is 1, the address which is stored in the address latch with alel and aleh is input via d15-0. alel, aleh 54, 53 i address latch enable, low and high, active high: they are only used when admux is 1. when alel/aleh is 1, the signals go from the data bus to the address bus, when alel/aleh = 0, they store the address. when admux is 0, alel/aleh have to be connected to vdd. rdn 51 i read: for the intel bus interface, data is read when rdn is 0. for the motorola bus interface, data is read or written to when rdn is 0 (busmode1 = 0) or rdn is 1 (busmode1 = 1). wrn 52 i write: for the intel bus interface, data is written to when wrn is 0. for the motorola bus interace, wrn selects read (wrn = 1) and write (wrn = 0) operations of the data bus. bhen 75 i byte high enable, active low: in the 16-bit bus mode, data is transferred via d15-8 when bhen is 0. mcsn0, mcsn1 46,47 i memory chip select, active low: to access the internal ram mcsn0 and mcsn1 must be 0. pcsn0, pcs1 48,49 i periphery chip select, active low (pcsn0) and active high (pcs1): to access the control registers pcsn0 must equal 0 and pcs1 must equal 1. busyn 45 o ram busy, active low: becomes active if an access to an address of the dual port ram is performed simultaneously to an access to the same memory location by the internal telegram processing. dmareqr 38 o dma request receive, active high: becomes active if data from the receive fifo can be read. at the beginning of the read operation of the last word of the receive fifo, dmareqr becomes inactive. dmaackrn 40 i dma acknowledge receive, active low: when dmaackrn is 0, the receive fifo is read, independent of the levels on a6-1 and the chip select signals. dmareqt 39 o dma request transmit, active high: becomes active when data can be written to the transmit fifo. dmareqt becomes inactive again at the beginning of the last write access to the transmit fifo. dmaacktn 41 i dma acknowledge transmit, active low: when dmaacktn is 0, the transmit fifo is written to when there is a bus write access independent of the levels on a6-1 and the chip select signals. admux 96 i address data bus: when admux is 0 a15-0 are the address inputs, when admux is 1 a15-0 are the outputs of the address latch. busmode0, busmode1 97,98 i bus mode: busmode0 = 0 turns on the intel bus interface (rdn = read, wrn = write), busmode0 = 1 selects the motorola interface (rdn = data strobe, wrn = read/write). busmode1 selects the 0-active data strobe (busmode1 = 0) or the 1-active data strobe (busmode1 = 1). buswidth 99 i bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). bytedir 100 i byte address sequence: when bytedir is 0, a0 = 0 addresses the lower 8 bits of a word (low byte first), when bytedir is 1, the upper 8 bits of a word are addressed (high byte first). int0, int1 44,43 o interrupts, active low or active high. interrupt sources and signal polarity are programmable. sbaud16 28 i baud rate and sercon410b compatible mode: sbaud and sbaud16 selects the baud rate for the serial interface. if sbaud16 is 1 the sercon410b compatible mode is selected. sbaud 29 i baud rate. can be overwritten by the microprocessor.
SERCON816 6/23 rxd 14 i receive data for the serial interface. rxc 12 o receive clock for the serial interface. output of the internally generated receive clock. recactn 26 o receive active, active low. indicates that the serial receiver is receiving a telegram. txd1 16 o transmit data. the pin can be switched to a high impedance state. txd6-2 22,21,20, 18,17 o transmit data or output port. the pins either output the serial data or can be used as parallel output ports. when they output transmit data, each pin can be switched to a high impedance state individually. txc 13 o transmit clock for the serial interface. output for the internally generated transmit clock. idle 25 o transmitter active, active low. when transmitting own data idle is 0. dmareqt 39 o dma request transmit, active high: becomes active when data can be written to the transmit fifo. dmareqt becomes inactive again at the beginning of the last write access to the transmit fifo. dmaacktn 41 i dma acknowledge transmit, active low: when dmaacktn is 0, the transmit fifo is written to when there is a bus write access independent of the levels on a6-1 and the chip select signals. admux 96 i address data bus: when admux is 0 a15-0 are the address inputs, when admux is 1 a15-0 are the outputs of the address latch. busmode0, busmode1 97,98 i bus mode: busmode0 = 0 turns on the intel bus interface (rdn = read, wrn = write), busmode0 = 1 selects the motorola interface (rdn = data strobe, wrn = read/write). busmode1 selects the 0-active data strobe (busmode1 = 0) or the 1-active data strobe (busmode1 = 1). buswidth 99 i bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1). bytedir 100 i byte address sequence: when bytedir is 0, a0 = 0 addresses the lower 8 bits of a word (low byte first), when bytedir is 1, the upper 8 bits of a word are addressed (high byte first). int0, int1 44,43 o interrupts, active low or active high. interrupt sources and signal polarity are programmable. sbaud16 28 i baud rate and sercon410b compatible mode: sbaud and sbaud16 selects the baud rate for the serial interface. if sbaud16 is 1 the sercon410b compatible mode is selected. sbaud 29 i baud rate. can be overwritten by the microprocessor. rxd 14 i receive data for the serial interface. rxc 12 o receive clock for the serial interface. output of the internally generated receive clock. recactn 26 o receive active, active low. indicates that the serial receiver is receiving a telegram. txd1 16 o transmit data. the pin can be switched to a high impedance state. txd6-2 22,21,20, 18,17 o transmit data or output port. the pins either output the serial data or can be used as parallel output ports. when they output transmit data, each pin can be switched to a high impedance state individually. txc 13 o transmit clock for the serial interface. output for the internally generated transmit clock. idle 25 o transmitter active, active low. when transmitting own data idle is 0. tm0, tm1 30,31 i turn on test generator: tm0 = 0 switches txd1-6 to contiuous signal light, tm1 = 0 switch-over to zero bit stream. the processor can overwrite the level of tm1-0. select repeater mode at reset time: tm1=0 and tm2=0 repeater off, all other repeater on. table 1. SERCON816 i/o port function summary (continued) signal(s) pin(s) io function
7/23 SERCON816 3 electrical (dc and ac) characteristics 3.1 absolute maximum ratings wdogn 24 o watchdog output (active low) l_errn 32 o line error, active low: goes low when signal distortion is too high or when the receive signal is missing. the operating mode is programmed by the processor. cyc_clk 34 i sercos interface cycle clock: cyc_clk synchronizes the communication cycles. the polarity is programmable. con_clk 35 o control clock: becomes active within a communication cycle. time, polarity and width are programmable. div_clk 36 o divided control clock: becomes active several times within a communication cycle or once in several communication cycles. number of pulses, start time, repetition rate and polarity are programmable, the pulse width is 1 m s. sclk 2 i serial clock for clock regeneration: the maximum frequency is 64 mhz. sclko2 6 o clock output: outputs the sclk clock divided by 2 or 1. sclko4 5 o clock output: outputs the sclk clock divided by 4 or 2. mclk 4 i master clock for telegram processing and timing control, frequency 12 to 64 mhz. rstn 10 i reset, active low. must be zero for at least 50 ns after power on. test 7 i test, active high. has to be tied to vss. outz 11 i puts outputs into high impedance state, active high: outz is 1 puts all pins into a high impedance state. the clocks are turned off and the circuit is reset. for the in-circuit test and for turning on the power-down mode. ndtro 9 o nand tree output. for the test at the semiconductor manufacturers and for the connection test after board production. ndtro is not set to a high impedance state. vss 3,15,23,33 ,42,50,60, 70,81,91 ground pins: vdd 1,8,19,27, 37,55,65, 76,86 power supply +5 v 5%. symbol parameter value unit v dd supply voltage -0.5 to 6.5 v v i input voltage -0.5 to v dd + 0.5 v v o output voltage -0.5 to v dd + 0.5 v t stg storage temperature -55 to +150 c table 1. SERCON816 i/o port function summary (continued) signal(s) pin(s) io function
SERCON816 8/23 3.2 recommended operating conditions notes: 1. only if pll is used (sbaud16=0) 2. for normal operation, during testing f mclk = 0 is possible symbol parameter min. max. unit t a operating temperature -40 85 c t j chip junction temperature -40 125 c v dd operating supply voltage 4.75 5.25 v f sclk clock frequency sclk 32 1 64 mhz f mclk clock frequency mclk 12 2 64 mhz 3.3 electrical characteristcs (v dd = 5v 5% t amb = -40 c to +85 c, unless otherwise specified) symbol parameter test condition min. typ. max. unit v il low level input voltage (ttl) all inputs 0.8 v v ih high level input voltage (ttl) all inputs 2.0 v v hyst schmitt trigger hysteresis l_errn, txd6-1, mclk, sclk, rstn, admux, busmode1-0, buswidth, bytedir, tm1-0, sbaud16, sbaud, test, outz, rxd, cyc_clk 0.4 0.7 v i il low level input current with pull- up d15-0, a15-0, txd6-1, admux, busmode1-0, bytedir, tm1- 0, sbaud16, sbaud, test, outz, rxd, cyc_clk, bhen, mcsn1-0, pcsn0, pcs1, dmaacktn, dmaackrn v i = v ss -40 -100 -240 m a i ih high level input current with pull- down mclk, sclk, rstn, aleh, alel v i = v dd 40 100 240 m a rup equivalent pull-up resistance v i = v ss 23 50 112.5 kohm rdn equivalent pull-down resistance v i = v dd 23 50 112.5 kohm v ol low level output voltage, all o- and i/o-pins except txd6-1, l_errn i oi = -4 ma 0.4 v v oh high level output voltage, all o- and i/o-pins except txd6-1, l_errn i oh = +4 ma 2.4 v
9/23 SERCON816 notes: 1. estimated 3.4.1 power dissipation considerations most of the current consumed by cmos devices is alternate current (ac) which is charging and discharg- ing the capacitances of the pins and internal nodes. the current consumption rises with the frequency at which the pins and internal nodes will toggle and with the capacitances connected to the pins of the device: p = f c v 2 (c=capacitance, v=voltage, f=frequency) for applications which require low power consumption or exceeds the maximum allowed power consump- tion the following is required: C connect unused pins to pull-up or pull-down resistors C minimize the capacitive load on the pins C reduce clock frequency of sclk and mclk C minimize accesses to the internal ram and control registers the maximum allowed power consumption is limited by the maximum allowed chip junction temperature and by the number of vcc/vdd pins. the chip junction temperature is influenced by the ambient temper- ature and the package thermal resistance. the ambient temperature could be influenced by the applica- tion through a good temperature management like heat sinks or ambient air cooling. v ol low level output voltage, pins txd6-1, l_errn i oi = -8 ma 0.4 v v oh high level output voltage, pins txd6-1, l_errn i oh = +8 ma 2.4 i oz tri-state output leakage v o = 0 v or v dd 1 m a i klu i/o latch-up current vv dd 200 ma v esd electrostatic protection leakage < 1 a, human body model 2000 v c pin pin capacitance 10 pf 3.4 power dissipation (v dd = 5v 5% t amb = -40 c to +85 c, unless otherwise specified) symbol parameter test condition min. typ. max. unit p d power dissipation 16 mbaud, mclk=64 mhz 850 1 mw p da maximum allowed power dissipation t a =+85, no air flow 1000 mw 3.3 electrical characteristcs (continued) (v dd = 5v 5% t amb = -40 c to +85 c, unless otherwise specified) symbol parameter test condition min. typ. max. unit
SERCON816 10/23 typical current consumption: measured at 5v (vcc/vdd) and 25c 3.5 ac electrical characteristics (c load = 50 pf, v dd = 5 v 5% t amb = -40 c to +85 c) 3.5.1 clock input mclk figure 5. timing of clock mclk and related outputs mode f sclk (mhz) f mclk (mhz) current (ma) 410b 64 32 30 816 64 32 80 symbol parameter min. typ. max. unit f mclk clock frequency mclk 12 64 mhz t mclk0 mclk low 6 ns t mclk1 mclk high 6 ns t mcld output delay rising edge mclk to dmareqr/t, con_clk, div_clk 20 ns f mclk baudrate 2 mbit/s 12 64 mhz f mclk baudrate 4 mbit/s 12 64 mhz mclk 1 / f mc lk t mclk0 t mcld t mclk1 dmareqr/t con_clk, div_clk
11/23 SERCON816 3.5.2 clock input sclk figure 6. timing of clock sclk 3.5.3 address latch figure 7. address latch symbol parameter min. typ. max. unit f sclk clock frequency sclk pll used (sbaud16=0) 32 64 mhz pll unused (sbaud16=1) 64 mhz t sclk0 sclk low 6 ns t sclk1 sclk high 6 ns symbol parameter min. typ. max. unit t alew pulse width alel, aleh 10 ns t alesu setup time d15-0 to falling edge aleh, alel 5 ns t alehd hold time falling edge aleh, alel to d15-0 5 ns t da delay from d15-0 to a15-0 20 ns sclk 1 / f sc lk t sc lk0 t sc lk1 aleh, alel d15-0 a1 5-0 t da t alew t alesu t alehd
SERCON816 12/23 3.5.4 read access of control registers figure 8. read access of control registers note: 1. setup time input signals to falling edge rdn (intel or motorola mode with low active strobe) or rising edge rdn (motorol a mode with high active strobe) symbol parameter min. typ. max. unit t asu setup time a6-0, (note 1) 10 ns setup time bhen, pcsn0, pcs1, dmaacknr, wrn (only motorola mode), (note 1) 0ns t ahd hold time a6-0, bhen, pcsn0, pcs1, dmaacknr, wrn (only motorola mode) to rising edge rdn (intel motorola mode with low active strobe) or falling edge rdn (motorola mode with high active strobe) 0ns t pa d access time a6-0, bhen, pcsn0, pcs1, dmaacknr, wrn (only motorola mode) to d15-0 valid 30 ns t prdd access time rdn to d15-0 valid 30 ns t rdz delay rdn to d15-0 high-z 20 ns t prq delay rdn to dmareqr low 20 ns a6-0, bhen pcsn0, pcs1, dmaacknr, wrn (motorola mode) rdn d15-0 dmareqr t pa d t prq t rdz t prd d t ahd t asu
13/23 SERCON816 3.5.5 read access of dual port ram figure 9. read access of dual port ram notes: 1. setup time input signals to falling edge rdn (intel or motorola mode with low active strobe) or rising edge rdn (motoro la mode with high active strobe) symbol parameter min. typ. max. unit t asu setup time a11-0, (note 1) 10 ns setup time mcsn0-1, if both signals are activated simultaneously. (note 1) 5ns setup time mcsn0-1, if one of these both signals is activated 10 ns earlier. (note 1) 0ns setup time bhen, wrn (only motorola mode), (note 1) 0 ns t ahd hold time a11-0, bhen, mcsn0-1, wrn (only motorola mode) to rising edge rdn (intel motorola mode with low active strobe) or falling edge rdn (motorola mode with high active strobe) 0ns t rdnclk cycle time of ram read clock sbaud16 = 1 (f rdnclk = f sclk ) 1 / f sclk sbaud16 = 0 (f rdnclk = 2 * f sclk ) 0.5 / f sclk t mrdd access time rdn to d15-0 valid 2 * t rdnclk + 30 ns t mbsy delay rdn to busyn low 15 ns t mbhd delay busyn high to d15-0 valid 2 * t rdnclk + 30 ns t rdz delay rdn to d15-0 high-z 20 ns t rd1 rdn and wrn high after end of read access 15 ns a10-0, bhen, mcsn0-1, wrn (m o t o ro la m o d e ) rd n d15-0 busyn t m bsy t mbhd t rdz t rd1 t mrdd t asu t ahd
SERCON816 14/23 3.5.6 write access to control registers figure 10. write access to control registers notes: 1. setup time input signals to falling edge wrn (intel mode) or rdn (motorola mode with low active strobe) or rising edge rdn (mo- torola mode with high active strobe) symbol parameter min. typ. max. unit t asu setup time a6-0, (note 1) 10 ns setup time bhen, pcsn0, pcs1, dmaacknr, wrn (only motorola mode), (note 1) 0ns t ahd hold time a6-0, bhen, pcsn0, pcs1, dmaacknt, wrn (only motorola mode) to rising edge wrn (intel mode) or rdn (motorola mode, strobe active low) or falling edge rdn (motorola mode, strobe active high) 0ns t pwrw pulse width wrn (intel mode) or rdn (motorola mode) 20 ns t dsu setup time d15-0 to end of write access 10 ns t dhd hold time d15-0 to end of write access 5 ns t prq delay wrn or rdn to dmareqt low 20 ns a6-0, bhen, pc sn 0 , pc s1 , dmaacknt , wrn (m o t o ro la m o d e ) wrn (intel mode) rdn (motorola mode) d15-0 dmareqt t prq t dhd t dsu t pwrw t ahd t asu
15/23 SERCON816 3.5.7 write access to dual port ram figure 11. write access to dual port ram notes: 1. setup time input signals to falling edge wrn (intel mode) or rdn (motorola mode with low active strobe) or rising edge rdn (mo- torola mode with high active strobe) symbol parameter min. typ. max. unit t asu setup time a11-0, (note 1) 10 ns setup time mcsn0-1, if both signals are activated simultaneously. (note 1) 5ns setup time mcsn0-1, if one of these both signals is activated 10 ns earlier. (note 1) 0 setup time bhen, wrn (only motorola mode), (note 1) 0 ns t ahd hold time a11-0, bhen, mcsn0-1, wrn (only motorola mode) to rising edge of wrn (intel mode) or rdn (motorola mode with low active strobe) or falling edge rdn (motorola mode with high active strobe) 0ns t mwrw pulse width wrn or rdn 20 ns t dsu setup time d15-0 to end of write access 10 ns t dhd hold time d15-0 after end of write access 5 ns t mbsy delay wrn or rdn (begin of write access) to busyn low 15 ns t mbhwh setup time busyn high to end of write access 15 ns t wr1 wrn and rdn high after end of write access 15 ns a10-0, bhen, mcsn0-1, wrn (m o t o ro la m o d e ) wrn (intel mode) rdn (motorola mode) d15-0 busyn t mbsy t mbhwh t mwrw t dsu t dhd t wr1 t asu t ahd
SERCON816 16/23 4 control registers and ram data structures 4.1 control register addresses the following table is an overview of the control registers. the address is the word address which is input by a6-1. to calculate the byte address, the value has to be multiplied by two. all control registers can be written to and read (r/w), with the exception of the control bits that initiate an action (w). the status registers can only be read (r). when control registers which contain bits that are not used or can only be read, are written to, these bits can be set to 0 or 1; they are not evaluated internally. if control registers are read with bits that are not used, these bits are set to 0. 4.2 data structures within the ram in this ram the first eleven words have a fixed meaning. the rest of the ram can be divided into data structures as required. 4.2.1 telegram headers a telegram header for receive telegram contains the following five control words: a6-1 bits name r/w value function 00h 0-15 version r 0010h circuit code ( 0010h ) 01h - 2ah 0-15 please refer to SERCON816 reference guide for a detailed description of the control registers. a10-1 contents 0-1 compt0-1: start of transmission blocks 0-1 2-9 scpt0-7: address service containers 0-7 10 nmsterr: error counter mst index bit name function 0 0-7 adr telegram address 8 dma data storage in the internal ram (dma = 0) or dma transfer (dma = 1) 9 dbuf data in the ram: single buffer (dbuf = 0) or double buffer (dbuf = 1) 10 val for single buffering (dma = 0, dbuf = 0) or dma transfer (dma = 1): telegram data is invalid (val = 0) or valid (val = 1); for double buffering (dma = 0, dbuf = 1): data in buffer 0 (val = 0) or buffer 1 (val = 1) is valid. modified by controller at beginning and end of receive telegrams. 11 achk telegrams are received if the address is valid (achk = 1) or independent on the received address (achk = 0). the received address is stored at adr. 12 tchk the time of receiving is checked (tchk = 1) or not checked (tchk = 0). 13 rerr the last telegram was free of error (rerr = 0) or errored or not received (rerr = 1). 14 0 marker bit for telegram header of receive telegram. 15 0 marker bit for telegram header. 1 0-15 trt time for the start of telegram in m s after end of mst. 2 0-15 tlen length of telegram in data words (not including address). 3 0-10 pt word address within the ram of the next telegram header or the end marker. 9-15 (not used) 4 0-15 nerr error counter
17/23 SERCON816 4.2.2 data containers a data container comprises one or two 16-bit control words as well as a variable number of data words. if the data is stored in the internal ram (dma = 0) and a single buffer is used (dbuf = 0), the data container has one buffer. using ram storage and double buffering (dbuf = 1), two data buffers are needed. in case of dma transfer (dma = 1) the data container only comprises the control words (fig. 12). the structure of the two control words depends on whether a telegram is transmitted or received: figure 12. structure of data containers index bit name function 0 0-9 len number of 16-bit data words of the data block. 10 svfl flag, whether data block uses service container (svfl = 1). 11-13 nsv number of service container, which is used (0 - 7). 14 scmaster processing of service container in slave mode (scmaster = 0) or master mode (scmaster = 1). 15 lastdc last data container of the telegram (1) or further data containers follow (0). 1 0-15 pos position of the data block within the telegram in number of words. the first data record of a telegram has pos = 0 (only in case of receive telegrams). control word 0 control word 0 control word 1 control word 0 control word 0 control word 1 control word 0 control word 0 control word 1 buffer buffer buffer 0 buffer 0 buffer 1 buffer 1 0 0 1 0 0 1 0 0 1 1 2 1 2 1 2 len + 1 len + 2 len + 1 len + 2 2* len + 1 2* len + 2 dma = 0, dbuf = 0 dma = 0, dbuf = 0 dma = 0, dbuf = 1 dma = 0, dbuf = 1 dma = 1 dma = 1 transm it telegra ms re c e ive telegra ms
SERCON816 18/23 4.2.3 end marker the end marker comprises two 16-bit words: 4.2.4 service containers a service container contains 5 control words and a buffer (buflen words, max. length 255) figure 13. structure of service container index bit name function 0 0-13 (not used) 14 1 marker bit for the end marker. 15 1 marker bit for the end marker. 1 0-15 tend time after end of mst at which the last telegram has ended (in m s). control word 0 control word 1 control word 2 control word 3 control word 4 write a nd read buffer 0 1 2 3 4 5 5+ buflen
19/23 SERCON816 for master mode (scmaster = 1) the control words are coded as follows: index bit name function 0 0 hs_mdt handshake-bit in mdt 1 l/s_mdt read/write in mdt 2 end_mdt end in mdt 3-5 elem_mdt data element type in mdt 6 setend end_mdt is to be set 7 m_busy service container waits for interaction of microprocessor (m_busy = 1) 8-9 ninfo_write number of info words in write buffer (1 to 4) 10-11 (not used) 12 int_err slave reports error 13 int_end_wrbuf end of write buffer is reached 14 int_end_rdbuf end of read buffer is reached 15 (not used) 1 0 hs_at handshake bit in at 1 busy_at busy bit in at 2 err_at error bit in at 3 cmd_at command modification bit in at 4-6 (not used) 7 recerr last transmission was correct (0) or erroneous (1) 8-9 ninfo_read number of info words in read buffer (1 to 4) 10-15 (not used) 2 0-7 wrdatpt pointer to present position in write buffer 8-15 wrdatlast pointer to last position in write buffer 3 0-7 rddatpt pointer to present position in read buffer 8-15 rddatlast pointer to last position in read buffer 4 0-7 err_cnt error counter 8 busy_cnt error counts differences of handshake (0) or busy cycles (1) 9 int_sc_err interrupt due to protocol error 10 int_hs_timeout interrupt due to handshake timeout 11 int_busy_timeout interrupt busy timeout 12 int_cmd slave has set command modification bit 13-15 (not used)
SERCON816 20/23 the coding of the five control words depends on the mode of the service channel. using the slave mode (scmaster = 0) they have the following structure: index bit name function 0 0 hs_at handshake bit in at 1 busy_at busy bit in at, also waiting for microprocessor interaction 2 err_at error bit in at 3 cmd_at command modification bit in at 4-6 elem data element of present transmission 7 l/s read (0)/write (1) of present transmission 8-9 ninfo_write number of info words in write buffer (1 to 4) 10-11 (not used) 12 int_elem_change master has modified data element or read/write 13 int_end_wrbuf end of write buffer is reached 14 int_end_rdbuf end of read buffer is reached 15 int_end_mdt master reports end via end_mdt-bit 1 0 hs_mdt handshake bit in mdt 1 l/s_mdt read/write in mdt 2 end_mdt end bit in mdt 3-5 elem_mdt data element in mdt 6 (not used) 7 recerr last transmission was correct (0) or erroneous (1) 8-9 ninfo_read number of info words in read buffer (1 to 4) 10-15 (not used) 2 0-7 wrdatpt pointer to present position in write buffer 8-15 wrdatlast pointer to last position in write buffer 3 0-7 rddatpt pointer to present position in read buffer 8-15 rddatlast pointer to last position in read buffer 4 0-8 (not used) 9 int_sc_err interrupt due to protocol error 10-15 (not used)
21/23 SERCON816 5 additional specifications, tools and support 5.1 additional specifications reference manual SERCON816 the reference manual (160 pages) for the SERCON816 asic contains a complete and very detailed spec- ification of the SERCON816 asic, including a description of the pinning of the controller, microprocessor interface, serial interface, telegram processing, master and slave modes, additional modes, control and ram data structures, programming examples, electrical and mechanical characteristics of the chip, differ- ences between SERCON816 and sercon410b controller. sercos interface specification the sercos interface specification (iec/en 61491) contains a detailed description of the transfer medi- um and physical layer, data transfer and data link layer, protocol structure and data contents, communi- cation phases, functional handling and error handling, list and description of identifier numbers. i/o functions are described in a separate document. 5.2 hardware and software components master and slave routines (driver software) for the SERCON816 controller are available from several sup- pliers world-wide. furthermore different boards for a wide range of computer interfaces are offered, includ- ing isa-, vme-, pci- and pc/104 bus systems. 5.3 tools different development and testing tools are available for sercos interface. these tools include bus monitors, configuration and simulation tools, as well as tools for conformance test- ing. for all specification and additional application notes please contact: interests group sercos interface e. v.
SERCON816 22/23 6 package mechanical data: SERCON816 100 pin plastic quad flat pack package (pqfp100) pqfp100 dim. mm inch min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.22 0.38 0.0087 0.015 c 0.13 0.23 0.005 0.009 d 22.95 23.20 23.45 0.903 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.85 0.742 e 0.65 0.026 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.35 0.486 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. stmicroelectronics acknowledges the trademarks of all companies referred to in this document. the st logo is a registered trademark of stmicroelectronics ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan -malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states. http://www.st.com 23/23 SERCON816

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