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hb56aw873e-5/6 64mb buffered fp dram dimm 8-mword 72-bit, 4k refresh, 1 bank module (9 pcs of 8m 8 components) ade-203-858a (z) rev.1.0 jul. 31, 1998 description the hb56aw873e belongs to 8 byte dimm (dual in-line memory module) family, and has been developed as an optimized main memory solution for 4 and 8 byte processor applications. the hb56aw873e is a 8m 72 dynamic ram module, mounted 9 pieces of 64-mbit dram (hm5165800) sealed in tsop package and 2 pieces of 16-bit bicmos line driver sealed in tssop package. an outline of the hb56aw873e is 168-pin socket type package (dual lead out). therefore, the hb56aw873e makes high density mounting possible without surface mount technology. the hb56aw873e provides common data inputs and outputs. decoupling capacitors are mounted beside each tsop on the its module board. features 168-pin socket type package (dual lead out) ? lead pitch: 1.27 mm single 3.3 v supply: 3.3 v 0.3 v high speed ? access time: t rac = 50/60 ns (max) ? access time: t cac = 18/20 ns (max) low power dissipation ? active mode: 4.41/3.76 w (max) ? standby mode (ttl): 100.8 mw (max) buffered input except ras and dq 4 byte interleave enabled, dual address input (a0/b0) fast page mode capability 4,096 refresh cycle: 64 ms 2 variations of refresh ? ras -only refresh ? cas -before- ras refresh
hb56aw873e-5/6 2 ordering information type no. access time package contact pad hb56aw873e-5 50 ns 168-pin dual lead out socket type gold HB56AW873E-6 60 ns pin arrangement 1 pin 85 pin 10 pin 94 pin 11 pin 95 pin 40 pin 124 pin 41 pin 125 pin 84 pin 168 pin front side back side pin arrangement pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 oe2 86 dq36 128 nc 3 dq1 45 re2 87 dq37 129 nc 4 dq2 46 ce4 88 dq38 130 nc 5 dq3 47 nc 89 dq39 131 nc 6v cc 48 we2 90 v cc 132 pde 7 dq4 49 v cc 91 dq40 133 v cc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 v ss 54 v ss 96 v ss 138 v ss
hb56aw873e-5/6 3 pin arrangement (cont) pin no. pin name pin no. pin name pin no. pin name pin no. pin name 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 v cc 101 dq49 143 v cc 18 v cc 60 dq24 102 v cc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 v ss 65 dq25 107 v ss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 v cc 68 v ss 110 v cc 152 v ss 27 we0 69 dq28 111 nc 153 dq64 28 ce0 70 dq29 112 nc 154 dq65 29 nc 71 dq30 113 nc 155 dq66 30 re0 72 dq31 114 nc 156 dq67 31 oe0 73 v cc 115 nc 157 v cc 32 v ss 74 dq32 116 v ss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 nc 81 pd5 123 nc 165 pd6 40 v cc 82 pd7 124 v cc 166 pd8 41 nc 83 id0 (v ss ) 125 nc 167 id1 (v ss ) 42 nc 84 v cc 126 b0 168 v cc
hb56aw873e-5/6 4 pin description pin name function a0 to a11, b0 address input (d0 to d8) : a0 to a11, b0 row address (d0 to d8) : a0 to a11, b0 column address (d0 to d8) : a0 to a10, b0 refresh address (d0 to d8) : a0 to a11, b0 dq0 to dq71 data-in/data-out re0 , re2 row address strobe ( ras ) ce0 , ce4 column address strobe ( cas ) we0 , we2 read/write enable oe0 , oe2 output enable v cc power supply v ss ground pd1 to pd8 presence detect id0, id1 id bit pde presence detect enable nc non connection presence detect pin assignment pde = low pde = high pin name pin no. 50 ns 60 ns all pd1 79 1 1 high-z pd2 163 0 0 high-z pd3 80 1 1 high-z pd4 164 1 1 high-z pd5 81 0 0 high-z pd6 165 0 1 high-z pd7 82 0 1 high-z pd8 166 0 0 high-z 1 : high level (driver output) 0 : low level (driver output)
hb56aw873e-5/6 5 block diagram re0 ce0 we0 oe0 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq32 dq33 dq34 dq35 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o cas ras we oe cas ras we oe cas ras we oe cas ras we oe cas ras we oe d0 d1 d2 d3 d4 re2 ce4 we2 oe2 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq64 dq65 dq66 dq67 dq68 dq69 dq70 dq71 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o cas ras we oe cas ras we oe cas ras we oe cas ras we oe d5 d6 d7 d8 a0 b0 a1 to a11 v cc v ss d0 to d4 d5 to d8 d0 to d8 d0 to d8, 16-bit line driver d0 to d8,16-bit line driver 0.22 m f 11 pcs pd1 to pd8 v cc v ss v cc v cc v cc v cc v ss v cc v ss v ss pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 * d0 to d8 : hm5165800 : 16-bit line driver
hb56aw873e-5/6 6 absolute maximum ratings parameter symbol value unit terminal voltage on any pin relative to v ss v t C0.5 to +4.6 v power supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation pt 10 w storage temperature range tstg C55 to +125 c dc operating conditions parameter symbol min typ max unit note supply voltage v cc 3.0 3.3 3.6 v 1, 2 v ss 000 v2 input high voltage v ih 2.0 v cc + 0.3 v 1 input low voltage v il C0.3 0.8 v 1 ambient temperature ta 0 70 c note: 1. all voltage referenced to v ss . 2. the supply voltage with all v cc pins must be on the same level. the supply voltage with all v ss pins must be on the same level.
hb56aw873e-5/6 7 dc characteristics 50 ns 60 ns parameter symbol min max min max unit test condition note operating current i cc1 1225 1045 ma t rc = min 1, 2 standby current i cc2 28 28 ma ttl interface ras , cas = v ih dout = high-z 14.5 14.5 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z ras -only refresh current i cc3 1225 1045 ma t rc = min 2 standby current i cc5 55 55 ma ras = v ih , cas = v il dout = enable 1 cas -before- ras refresh current i cc6 1225 1045 ma t rc = min fast page mode current i cc7 910 820 ma ras = v il , cas cycle, t pc = t pc min 1, 3 input leakage current i li C5 5 C5 5 m a 0 v vin v cc + 0.3 v output leakage current i lo C5 5 C5 5 m a 0 v vout v cc dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected, i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. measured with one sequential address change per fast page mode cycle, t pc . capacitance (ta = 25 c, v cc = 3.3 v 0.3 v) parameter symbol typ max unit notes input capacitance (address) c i1 20pf1 input capacitance ( cas , we , oe )c i2 20pf1 input capacitance ( ras )c i3 55pf1 i/o capacitance (dq) c i/o 20 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout.
hb56aw873e-5/6 8 ac characteristics (ta = 0 to 70 c, v cc = 3.3 v 0.3 v, v ss = 0 v) *1, *2, *19 test conditions input rise and fall times: 5 ns input levels: v il = 0 v, v ih = 3.0 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) 50 ns 60 ns parameter symbol min max min max unit notes random read or write cycle time t rc 90 110 ns ras precharge time t rp 30 40 ns cas precharge time t cp 8 10 ns ras pulse width t ras 50 10000 60 10000 ns cas pulse width t cas 13 10000 15 10000 ns row address setup time t asr 55ns row address hold time t rah 8 10 ns column address setup time t asc 00ns column address hold time t cah 8 10 ns ras to cas delay time t rcd 18 32 20 40 ns 3 ras to column address delay time t rad 13 20 15 25 ns 4 ras hold time t rsh 18 20 ns cas hold time t csh 50 60 ns cas to ras precharge time t crp 10 10 ns oe to din delay time t oed 18 20 ns 5 oe delay time from din t dzo 00ns6 cas delay time from din t dzc 00ns6 transition time (rise and fall) t t 3 50 3 50 ns 7
hb56aw873e-5/6 9 read cycle 50 ns 60 ns parameter symbol min max min max unit notes access time from ras t rac 50 60 ns 8, 9 access time from cas t cac 18 20 ns 9, 10, 17 access time from address t aa 30 35 ns 9, 11, 17 access time from oe t oea 18 20 ns 9 read command setup time t rcs 00ns read command hold time to cas t rch 00ns12 read command hold time to ras t rrh 00ns12 column address to ras lead time t ral 30 35 ns column address to cas lead time t cal 25 30 ns cas to output in low-z t clz 22ns output data hold time t oh 33ns output data hold time from oe t oho 33ns output buffer turn-off time t off 18 20 ns 13 output buffer turn-off to oe t oez 18 20 ns 13 cas to din delay time t cdd 18 20 ns 5 write cycle 50 ns 60 ns parameter symbol min max min max unit notes write command setup time t wcs 00ns14 write command hold time t wch 8 10 ns write command pulse width t wp 8 10 ns write command to ras lead time t rwl 18 20 ns write command to cas lead time t cwl 13 15 ns data-in setup time t ds 00ns15 data-in hold time t dh 13 15 ns 15
hb56aw873e-5/6 10 read-modify-write cycle 50 ns 60 ns parameter symbol min max min max unit notes read-modify-write cycle time t rwc 131 155 ns ras to we delay time t rwd 73 85 ns 14 cas to we delay time t cwd 36 40 ns 14 column address to we delay time t awd 48 55 ns 14 oe hold time from we t oeh 13 15 ns refresh cycle 50 ns 60 ns parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 ns cas hold time (cbr refresh cycle) t chr 8 10 ns we setup time (cbr refresh cycle) t wrp 55ns we hold time (cbr refresh cycle) t wrh 8 10 ns ras precharge to cas hold time t rpc 55ns fast page mode cycle 50 ns 60 ns parameter symbol min max min max unit notes fast page mode cycle time t pc 35 40 ns fast page mode ras pulse width t rasp 100000 100000 ns 16 access time from cas precharge t cpa 35 40 ns 9, 17 ras hold time from cas precharge t cprh 35 40 ns fast page mode read-modify-write cycle 50 ns 60 ns parameter symbol min max min max unit notes fast page mode read-modify-write cycle time t hprwc 76 85 ns we delay time from cas precharge t cpw 53 60 ns 14
hb56aw873e-5/6 11 refresh parameter symbol min unit notes refresh period t ref 64 ms 4096 cycles notes: 1. ac measurements assume t t = 5 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh or cas -before- ras refresh). 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. either t oed or t cdd must be satisfied. 6. either t dzo or t dzc must be satisfied. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 8. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 9. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 10. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 11. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 12. either t rch or t rrh must be satisfied for a read cycles. 13. t off (max) and t oez (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), and t awd 3 t awd (min), or t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t ds , t dh are referred to cas leading edge in early write cycles and to we leading edge in delayed write or read-modify-write cycles. 16. t rasp defines ras pulse width in fast page mode cycles. 17. access time is determined by the longest among t aa , t cac and t cpa . 18. in delayed write or read-modify-write cycles, oe must disable output buffer prior to applying data to the device. 19. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc /v ss line noise, which causes to degrade v ih min/v il max level. 20. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hb56aw873e-5/6 12 timing waveform *20 read cycle ras cas address we dout oe din t csh t rc t ras t rp t crp t rcd t rsh t cas t t t rad t ral t cal t cah t asr row column t rah t rcs t rch t rrh t cdd high-z dout t dzo t oed t rac t oea t aa t cac t clz t oh t off t oho t oez t dzc t asc
hb56aw873e-5/6 13 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din t wcs wcs (min) high-z* t cas
hb56aw873e-5/6 14 delayed write cycle *18 address cas ras we din oe dout t rc t ras t rp t csh t rcd t rsh t cas t crp t t column row t asr t rah t asc t cah t rcs t cwl t rwl t wp t dzc t ds t dh t dzo t oed t oeh t clz t oez high-z invalid dout din high-z
hb56aw873e-5/6 15 read-modify-write cycle *18 address ras din dout oe we t rwc t ras t rp t crp t cas t rcd t t t rad t asr t rah t asc t cah column row t rcs t cwd t cwl t awd t rwd t rwl t wp t dzc t dh t ds din high-z t dzo t oed t oeh t oea t cac t aa t rac t oho t oez t clz dout high-z cas
hb56aw873e-5/6 16 ras -only refresh cycle ras cas address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off
hb56aw873e-5/6 17 cas -before- ras refresh cycle ras cas we address dout high-z t off t wrp t wrh t wrp t wrh t cp t rpc t csr t chr t cp t rpc t csr t chr t crp t rp t ras t rc t rc t rp t ras t rp t t
hb56aw873e-5/6 18 fast page mode read cycle we din oe dout address ras t rasp t cprh t rp t t t csh t rcd t cas t cp t cas t pc t rsh t cp t cas t crp t ral t cal t cah asc t t asc t t cal t cal t asc t t rad t asr t rah tt rch t rch tt t rrh t rch t cdd high-z t dzc t cdd t dzc t cdd t dzc high-z high-z t dzo t oed t oed t dzo tt oed t oh t aa t oh t aa t oh t cpa t cpa t rac t aa t oea t oea t oea t oho t oho t oho t cac t clz t oez t off t cac t clz t oez t off t cac t clz t oez t off dout n dout 2 dout 1 row column 1 column 2 column n cah cah rcs rcs rcs dzo cas
hb56aw873e-5/6 19 fast page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t pc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t wch t wcs t wch t wcs t wch t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas
hb56aw873e-5/6 20 fast page mode delayed write cycle *18 we din oe dout address ras t rasp t rp t crp t rsh t cas t pc t cas t cas t csh t rcd t t t cp t cp t asc t cah t asc t cah t asc t cah t rad t asr t rah t rcs t rcs t rcs t rwl t cwl t cwl t cwl t wp t wp t wp t dzc t ds t dzc t ds t ds t dzc t dh t dh t dh t dzo t oed t dzo t oed t dzo t oed t oeh t oeh t oeh t oez t clz t clz t oez t clz t oez invalid dout invalid dout invalid dout din 1 din 2 din n column n column 2 column 1 row high-z cas
hb56aw873e-5/6 21 fast page mode read-modify-write cycle *18 we din oe dout address ras t rasp t crp t cp t prwc t t t rcd t cas t cp t cas t cas t rad t asr t asc t asc t asc t rah t cah t cah t cah t cwl t cpw t cwl t cpw t cwl t rwd t awd t awd t awd t cwd t rcs t cwd t rcs t cwd t rcs t wp t wp t wp t ds t dzc t ds t dzc t ds t dzc t dh t dh t dh t dzo t dzo t dzo t oeh t oeh t oeh t aa t rac t oez t clz dout n dout 2 dout 1 din 1 din 2 din n column n column 2 column 1 t rp row t rwl t oho t oea t cac t oez t clz t oho t oea t cac t cpa t oez t clz t oho t oea t cac t cpa high-z t oed t oed t oed aa t aa t t rsh cas
hb56aw873e-5/6 22 physical outline hb56aw873e series 6.35 0.250 3.175 0.125 detail b and c detail a 0.25 max 2.54 min 0.010 max 0.100 min 3.125 0.125 0.123 0.005 1.27 0.050 3.00 133.35 0.118 5.250 127.35 5.014 3.00 0.118 8.89 11.43 36.83 54.61 0.350 0.450 2.150 1.450 a b c 1 84 front side back side 1.27 0.10 4.00 min 0.157 min 0.050 0.004 4.00 max 0.157 max 85 4.00 0.157 17.78 0.700 25.40 1.000 168 2 ? f 3.00 2 ? f 0.118 1.00 0.05 0.039 0.002 2.00 0.10 0.079 0.004 component area (front) component area (back) unit: mm inch
hb56aw873e-5/6 23 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca 94005-1897 tel: <1> (800) 285-1601 fax: <1> (303) 297-0447 for further information write to:
hb56aw873e-5/6 24 revision record rev. date contents of modification drawn by approved by 0.0 nov. 19, 1997 initial issue (referred to hm5164800/hm5165800 series rev. 0.0) s.tsukui k.yoshizaki 1.0 jul. 31, 1998 deletion of preliminary (referred to hm5164800/hm5165800 series rev. 1.0)

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