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monochip slic optimised for wll & isdn-ta applications implement all key features of the borsht function single supply (5.5 to 15.8v) built in dc/dc converter control- ler. soft battery reversal with pro- grammable transition time. on-hook transmission. programmable off-hook detector threshold metering pulse generation and fil- ter integrated ringing integrated ring trip parallel control interface (3.3v logic level) programmable constant current feed surface mount package integrated thermal protection -40 to +85c operating range description the stlc3055 is a slic device specifically de- signed for wll (wireless local loop) and isdn- terminal adaptors. one of the distinctive charac- teristic of this device is the ability to operate with a single supply voltage (from +5.5v to +15.8v) and self generate the negative battery by means of an on chip dc/dc converter controller that drives an external mos switch. the battery level is properly adjusted depending on the operating mode. a useful characteristic for september 2000 ? d0 d1 d2 det rttx cac iltf rd iref rlim rth csvr cvcc vpos bgnd tip ring vbat agnd tx rx zac1 zac rs zb cttx1 cttx2 fttx ckttx supervision ttx proc ac proc reference stage line driver crev input logic and decoder output logic volt. vcc vss agnd output reg. status and functions clk rsense gate vf dc/dc conv. dc proc vbat block diagram tqfp44 ordering numbers: STLC3055Q STLC3055Qtr stlc3055 wll & isdn-ta subscriber line interface circuit 1/22
these applications is the integrated ringing gener- ator. the control interface is a parallel type with open drain output and 3.3v logic levels. the metering pulses are generated on chip start- ing from two logic signals (0, 3.3v) one define the metering pulse frequency and the other the me- tering pulse duration. an on chip circuit then pro- vides the proper shaping and filtering. metering pulse amplitude and shaping (rising and decay time) can be programmed by external compo- nents. a dedicated cancellation circuit avoid pos- sible codec input saturation due to metering pulse echo. constant current feed can be set from 20ma to 40ma. off-hook detection threshold is program- mable from 5ma to 9ma. the device, developed in bcd100ii technology (100v process), operates in the extended tem- perature range and integrates a thermal protec- tion that sets the device in power down when tj exceeds 140c. absolute maximum ratings symbol parameter value unit v pos positive supply voltage -0.4 to +17 v a/bgnd agnd to bgnd -1 to +1 v v dig pin d0, d1, d2, det, ckttx -0.4 to 5.5 v t j max. junction temperature 150 c v btot (1) vbtot=|vpos|+|vbat|. (total voltage applied to the device supply pins). 100 v (1) vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see external components table page 10) 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 n.c. res pd d1 d0 d2 cttx2 cttx1 ckttx n.c. det rttx fttx rx zac1 rs zac zb cac tx vf clk vbat1 crev n.c. tip n.c. n.c. n.c. ring n.c. vbat bgnd rlim agnd cvcc rsense gate vpos csvr iltf rd iref rth d97tl279a 12 13 14 15 16 pin connection description (continued) stlc3055 2/22
thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient typ. 60 c/w pin description n. name function 25 vpos positive supply input ranging from 5.5v to 15.8v. 34 bgnd battery ground, must be shorted with agnd. 27 agnd analog ground, must be shorted with bgnd. 16 zac ac impedance synthesis. 15 zac1 rx buffer output, the ac impedance is connected from this node to zac. 17 rs protection resistors image (the image resistor is connected from this node to zac). 18 zb balance network for 2 to 4 wire conversion (the balance impedance zb is connected from this node to agnd. za impedance is connected from this node to zac1). 20 tx 4 wire output port (tx output). the signal is referred to agnd. if connected to single supply codec input it must be dc decoupled with proper capacitor. 14 rx 4 wire input port (rx input); 300k w input impedance. this signal is referred to agnd. if connected to single supply codec output it must be dc decoupled with proper capacitor. 19 cac ac feedback input, ac/dc split capacitor (cac). 32 iltf transversal line current image output. 41 tip 2 wire port; tip wire (ia is the current sourced from this pin). 37 ring 2 wire port; ring wire (ib is the current sunk into this pin). 28 rlim constant current feed programming pin (via rlim). rlim should be connected close to this pin and pcb layout should avoid noise injection on this pin. 30 rth off-hook threshold programming pin (via rth). rth should be connected close to this pin and pcb layout should avoid noise injection on this pin. 29 iref internal bias current setting pin. rref should be connected close to this pin and pcb layout should avoid noise injection on this pin. 43 crev reverse polarity transition time control. one proper capacitor connected between this pin and agnd is setting the reverse polarity transition time. this is the same transition time used to shape the "trapezoidal ringing" during ringing injection. 31 rd dc feedback and ring trip input. rd should be connected close to this pin and pcb layout should avoid noise injection on this pin. operating range symbol parameter value unit v pos positive supply voltage 5.5 to +15.8 v a/bgnd agnd to bgnd -100 to +100 v v dig pin d0, d1, d2, det, ckttx, pd -0.25 to 5.25 v t op ambient operating temperature range -40 to +85 c v bat (1) self generated battery voltage -74 max. v (1) vbat is self generated by the on chip dc/dc converter and can be programmed via rf1 and rf2. rf1 and rf2 shall be selected in order to fulfil the a.m limits (see external components table page 10) stlc3055 3/22
functional description the stlc3055 is a device specifically developed for wll and isdn-ta applications. it is based on a slic core, on purpose optimised for these applications, with the addition of a dc/dc converter controller to fulfil the wll and isdn-ta design requirements. the slic performs the standard feeding, signal- ling and transmission functions. it can be set in three different operating modes via the d0, d1, d2 pins of the control logic inter- face (0 to 3.3v logic levels). the loop status is carried out on the det pin (active low). the det pin is an open drain output to allow easy interfacing with both 3.3v and 5v logic levels. the four possible slics operating modes are: power down high impedance feeding (hi-z) active ringing table 1 shows how to set the different slic oper- ating modes. table 1. slic operating modes. pd d0 d1 d2 operating mode 0 0 0 x power down 1 0 0 x h.i. feeding (hi-z) 1010active normal pola rity 1011active reverse pola rity 1110active ttx inje ction (n.p.) 1111active ttx inje ction (r.p.) 1 1 0 0/1 ring (d2 bit toggles @ fring) n. name function 4 pd power down input. normally connected to cvcc (or to logic level high). can be used to set tip and ring terminals in open circuit setting pd=0 and d0=d1=0. 26 cvcc internal positive voltage supply filter. 35 vbat regulated battery voltage self generated by the device via dc/dc converter. must be shorted to vbat1. 23 gate driver for external power mos transistor. 21 vf feedback input for dc/dc converter controller. 22 clk power switch controller clock (typ. 125khz). from version marked stlc3055 a5, this pin can also be connected to cvcc or agnd. when the clk pin is connected to cvcc an internal auto-oscillation is internally generated and it is used instead of the external clock. when the clk pin is connected to agnd, the gate output is disabled. 24 rsense voltage input for current sensing. rsense should be connected close to this pin and vpos pin. the pcb layout should minimize the extra resistance introduced by the copper tracks. 1 d0 control interface: input bit 0. 2 d1 control interface: input bit 1. 3 d2 control interface: input bit 2. 8 det logic interface output of the supervision detector (active low). 33 csvr battery supply filter capacitor. 12 rttx metering pulse cancellation buffer output. ttx filter network should be connected to this point. if not used should be left open. 13 fttx metering pulse buffer input this signal is sent to the line and used to perform ttx filtering. 10 cttx1 metering burst shaping external capacitor. 11 cttx2 metering burst shaping external capacitor. 9 ckttx metering pulse clock input (12 khz or 16khz square wave). 44 vbat1 frame connection. must be shorted to vbat. 5 res reserved, must be connected to agnd. 6, 7,36, 38,39, 40,42 nc not connected. pin description (continued) stlc3055 4/22
the dc/dc converter controller is driving an ex- ternal power mos transistor (p-channel) in order to generate the negative battery voltage needed for device operation. the dc/dc converter controller is synchronised with an external clk (125khz typ.). from version marked stlc3055 a5, it can be synchronised to an internal clock generated when the pin clk is connected to cvcc. one sensing resistor in series to vpos supply allows to fix the maximum allowed input peak current. this feature is implemented in order to avoid overload on vpos supply in case of line transient (ex. ring trip detection). the typical value is obtained for a sensing resis- tor equal to 110m w that will guarantee an aver- age current consumption from vpos < 700ma. when in on-hook the self generated battery volt- age is set to a predefined value. this value can be adjusted via one external resis- tor (rf1) and it is typical -50v. when ring mode is selected this value is increased to -70v typ. once the line goes in off-hook condition, the dc/dc converter automatically adjust the gener- ated battery voltage in order to feed the line with a fixed dc current (programmable via rlim) opti- mising in this way the power dissipation. operating modes power down dc characteristic & supervision when this mode is selected the slic is switched off and the tip and ring pins are in high imped- ance. also the line detectors are disabled there- fore the off-hook condition cannot be detected. this mode can be selected in emergency condi- tion when it is necessary to cut any current deliv- ered to the line. this mode is also forced by stlc3055 in case of thermal overload (tj > 140c). in this case the device goes back to the previous status as soon as the junction temperature de- crease under the hysteresis threshold. ac characteristics the 2w port is set in high impedance, the tx output buffer is a low impedance output, no ac transmission is possible. high impedance feeding (hi-z) dc characteristic & supervision this operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum. the output voltage in on-hook condition is equal to the self generated battery voltage (-50v typ). when off-hook occurs the det becomes active (low logic level). the off-hook threshold in hi-z mode is the same value as programmed in active mode. the dc characteristic in hi-z mode is just equal to the self generated battery with 2x(1500w+rp) in series (see fig.1), where rp is the external pro- tection resistance. ac characteristics the ac impedance shown at the 2w port (tip/ring) is the same as the dc one. the tip/ring ac impedance will be 2x(1500 w + rp) or high impedance. active dc characteristics & supervision when this mode is selected the stlc3055 pro- vides both dc feeding and ac transmission. the stlc3055 feeds the line with a constant cur- rent fixed by rlim (20ma to 40ma range). the on-hook voltage is typically 40v allowing on-hook transmission; the self generated vbat is -50v typ. if the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the stlc3055 behaves like a 40v voltage source with a series impedance equal to the protection resistors 2xrp (typ. 2x41 w ) plus the internal resistance. fig. 2 shows the typical dc characteristic in active mode. vbat il vl vbat (-50v) 2x(r1+rp) slope: 2x(r1+rp) (r1=1500ohm) figure 1. dc characteristic in hi-z mode. stlc3055 5/22
the line status (on/off hook) is monitored by the slics supervision circuit. the off-hook threshold can be programmed via the external resistor r th in the range from 5ma to 9ma. independently on the programmed constant cur- rent value, the tip and ring buffers have a cur- rent source capability limited to 70ma typ. moreover the power available at vbat is control- led by the dc/dc converter that limits the peak current drawn from the vpos supply. the maxi- mum allowed current peak is set by the r sense resistor and it is typically 900mapk. ac characteristics the slic provides the standard slic transmis- sion functions: input impedance synthesis: can be real or complex and is set by a scaled (x50) external zac impedance. transmit and receive: the ac signal present on the 2w port (tip/ring) is transferred to the tx output with a -6db gain and from the rx in- put to the 2w port with a 0db gain. 2 to 4 wire conversion: the balance imped- ance can be real or complex, the proper can- cellation is obtained by means of two external impedance za and zb. once in active mode (d1=1) the slic can oper- ate in different states setting properly d0 and d2 control bits (see also table 2). table 2. slic states in active mode d0 d1 d2 operating mode 0 1 0 active normal polarity 0 1 1 active reverse polarity 1 1 0 active ttx injection (n.p.) 1 1 1 active ttx injection (r.p.) polarity reversal the d2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. this means that the tip and ring wire ex- change their polarities following a ramp transition (see fig.3). the transition time is controlled by an external capacitor crev. this capacitor is also setting the shape of the ringing trapezoidal wave- form. when the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (crev). metering pulse injection (ttx) the metering pulses circuit consist of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the har- monic distortion of the output signal. the metering pulse is obtained starting from two logic signals: ckttx: is a square wave at the ttx fre- quency (12 or 16khz) and should be perma- nently applied to the ckttx pin or at least for all the duration of the ttx pulse (including ris- ing and decay phases). d0: enable the ttx generation circuit and de- fine the ttx pulse duration. this two signals are then processed by a dedi- cated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (sqttx) (see fig.4). both the amplitude and the envelope of the squarewave (sqttx) can be programmed by means of external components. in particular the amplitude is set by the two resistors rlv and the il ilim vl vbat (-50v) 10v 2rp (20 to 40ma) figure 2. dc characteristic in active mode gnd tip ring dv/dt set by crev 4v typ. 40v typ on-hook figure 3. tip/ring typical transition from direct to reverse polarity stlc3055 6/22
shaping by the capacitor cs. the waveform so generated is then filtered and injected on the line. the low pass filter can be obtained using the inte- grated buffer op1 connected between pin fttx (op1 non inverting input) and rttx (op1 output) (see fig.4) and implementing a "sallen and key" configuration. depending on the external components count it is possible to build an optimised application de- pending on the distortion level required. in par- ticular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see fig.4). the circuit showed in the "application diagram" is related to the simple first order filter. once the shaped and filtered signal is obtained at rttx buffer output it is injected on the tip/ring pins with a +6db gain. it should be noted that this is the nominal condi- tion obtained in presence of ideal ttx echo can- cellation (obtained via proper setting of rttx and cttx). in addition the effective level obtained on the line will depend on the line impedance, the protection resistor value and the series switch (sw1 or sw2) on resistance. in the typical application (ttx line impedance =200 w , rp = 41 w , sw1,2 on resistance = 9 w and ideal ttx echo cancellation) the metering pulse level on the line will be 1.33 times the level applied to the rttx pin. as already mentioned the metering pulse echo cancellation is obtained by means of two external components (rttx and cttx) that should match the line impedance at the ttx frequency. this simple network has a double effect: synthesise a low output impedance at the tip/ring pins at the ttx frequency. cut the eventual ttx echo that will be trans- ferred from the line to the tx output. ringing when this mode is selected stlc3055 self gen- erate an higher negative battery (-70v typ.) in or- der to allow a balanced ringing signal of typically 65vpeak. in this condition both the dc and ac feedback loop are disabled and the slic line drivers oper- ate as voltage buffers. the ring waveform is obtained toggling the d2 control bit at the desired ring frequency. this bit in fact controls the line polarity (0=direct; 1=re- verse). as in the active mode the line voltage transition is performed with a ramp transition, ob- taining in this way a trapezoidal balanced ring waveform (see fig.5). the shaping is defined by the crev external capacitor. selecting the proper capacitor value it is possible to get different crest factor values. the following table shows the crest factor values cttx1 cttx2 cs rlv rlv sqttx burst d0 ckttx shaping generator square wave pulse metering sinusoidal wave pulse metering rttx fttx low pass filter - + op1 cfl r1 r2 c2 c1 required external components vs. filter order. figure 4. metering pulse generation circuit. order cfl r1 c! r2 c2 thd 1 x 13% 2 xxxx6% 3xxxxx3% stlc3055 7/22
obtained with a 20hz and 25hz ring frequency and with 1ren. this value are valid either with european or usa specification: crev crest factor @20hz crest factor @25hz 22nf 1.2 1.26 27nf 1.25 1.32 33nf 1.33 not significant (*) (*) distorsion already less than 10%. the ring trip detection is performed sensing the variation of the ac line impedance from on hook (relatively high) to off-hook (low). this particular ring trip method allows to operate without dc off- set superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. it should be noted that such a method is opti- mised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500 w ). once ring trip is detected, the det output is acti- vated (logic level low), at this point the card con- troller or a simple logic circuit should stop the d2 toggling in order to effectively disconnect the ring signal and then set the stlc3055 in the proper operating mode (normally active). ring level in presence of more tele- phone in parallel as already mentioned above the maximum cur- rent that can be drawn from the vpos supply is controlled and limited via the external rsense. this will limit also the power available at the self generated negative battery. if for any reason the ringer load will be too high the self generated battery will drop in order to keep the power consumption to the fixed limit and therefore also the ring voltage level will be re- duced. in the typical application with r sense = 110m w the peak current from vpos is limited to about 900ma, which correspond to an average current of 700ma max. in this condition the stlc3055 can drive up to 3ren with a ring frequency fr=25hz (1ren = 1800 w + 1.0 m f, european standard). in order to drive up to 5ren (1ren= 6930 w + 8 m f, us standard) it is necessary to modify the external components as follows: crev = 15nf rd = 2.2k w power on requirements in order to avoid damage to the device when vpos is first applied it is recommended to keep all the logic inputs to a low logic level (0v) until vpos is >5.5v. in case this power up sequence cannot be guar- anteed its recommended to connect a shottky di- ode (bat46 or equivalent) between vbat and bgnd see figure below. gnd tip ring dv/dt set by crev 2.5v typ. 65v typ. vbat 2.5v typ. figure 5. tip/ring typical ringing waveform bat46 bgnd vbat stlc3055 figure 6. shottky diode connection stlc3055 8/22
layout recommendation a properly designed pcb layout is a basic issue to guarantee a correct behaviour and good noise performances. particular care must be taken on the ground con- nection and in this case the star configuration al- lows surely to avoid possible problems (see appli- cation diagram fig. 7). the ground of the power supply (vpos) has to be connected to the center of the star, lets call this point pgnd. this point should show a resis- tance as low as possible, that means it should be a ground plane. noise sources can be identified in not enough good grounds, not enough low impedance sup- plies and parasitic coupling between pcb tracks and high impedance pins of the device. in particular to avoid noise problems the layout should prevent any coupling between the dc/dc converter components and analog pins that are referred to agnd (ex: rd, iref, rth, rlim, vf). as a first reccomendation the components cv, l, d1, cvpos, rsense should be kept as close as possible to each other and isolated from the other components. additional improvements can be obtained: decoupling the center of the star from the ana- log ground of stlc3055 using small chokes. adding a capacitor in the range of 100nf be- tween vpos and agnd in order to filter the switch frequency on vpos. external components list in order to properly define the external compo- nents value the following system parameters have to be defined: the ac input impedance shown by the slic at the line terminals "zs" to which the return loss measurement is referred. it can be real (typ. 600 w ) or complex. the ac balance impedance, it is the equiva- lent impedance of the line "zl" used for evalu- ation of the trans-hybrid loss performances (2/4 wire conversion). it is usually a complex impedance. the value of the two protection resistors rp in series with the line termination. the line impedance at the ttx frequency "zlttx". the metering pulse level amplitude measured at line termination "v lottx ". in case of low or- der filtering, v lottx represents the amplitude (vrms) of the fundamental frequency compo- nent. (typ 12 or 16khz). pulse metering envelope rise and decay time constant " t ". the slope of the ringing waveform " d v tr / d t ". the value of the constant current limit current "ilim". the value of the off-hook current threshold "i th ". the value of the ring trip rectified average threshold current "i rth ". the value of the required self generated nega- tive battery "v batr " in ring mode (max value is 70v). this value can be obtained from the desired ring peak level + 5v. the value of the maximum current peak sunk from vpos "ipk". stlc3055 9/22
external components name function formula typ. value rref bias setting current rref = 1.3/ibias ibias = 50 m a 26k w 1% csvr negative battery filter csvr = 1/(2 p fp 1.8m w ) fp = 50hz 1.5nf 10% 100vl rd ring trip threshold setting resistor rd = 100/i rth 2k w < rd < 5k w 4.12k w 1% @ irth = 24ma cac ac/dc split capacitance 22 m f 20% 15vl @ rd = 4.12k w rp line protection resistor rp > 30 w 41 w 1% rs protection and series switches resistance image rs = 100 (rp + 9 w )5k w @ rp = 41 w zac two wire ac impedance zac = 50 (zs - 2rp - 18 w )25k w 1% @ zs = 600 w za (1) slic impedance balancing network za = 50 zs 30k w 1% @ zs = 600 w zb (1) line impedance balancing network zb = 50 zl 30k w 1% @ zl = 600 w ccomp ac feedback loop compensation ccomp = 1/(2 p fo 100 (rp+9 w )) fo = 250khz 120pf 10% 10vl @ rp = 41 w ch trans-hybrid loss frequency compensation ch = ccomp 120pf 10% 10vl rlim current limiting programming rlim = 1300/ilim 32.5k w < rlim < 65k w 52.3k w 1% @ ilim = 25ma rth off-hook threshold programming (active mode) rth = 260/i th 27k w < rth < 52k w 28.7k w 1% @i th = 9ma crev reverse polarity transition time programming crev = (1/3750) d t/ d v tr ) 22nf 10% 10v @ 12v/ms rttx (3) pulse metering cancellation resistor rttx = 50re[(zlttx+2rp+18 w )] 15k w @zlttx = 200 w real cttx (3) pulse metering cancellation capacitor cttx = 1/{50 2 p fttx[-lm(zlttx)]} 100nf 10% 10v (2) @ zlttx = 200 w real rlv pulse metering level resistor rlv = 63.3 10 3 a v lottx a = (|zlttx + 2rp + 18 w |/|zlttx|) 27k w 1% @ v lottx = 275mvrms cs pulse metering shaping capacitor cs = t /(2 rlv) 100nf 10% 10v @ t = 6ms, rlv = 27.1k w cfl pulse metering filter capacitor cfl = 2/(2 p fttx rlv) 1nf 10% 10v @fttx = 12khz rlv = 27k w rdd pull up resistors 100k w cvcc internally supply filter capacitor 100nf 20% 10v cvpos positive supply filter capacitor with low impedance for switch mode power supply 100 m f(4) cv battery supply filter capacitor with low impedance for switch mode power supply 100 m f 20% 100v (5) cvb high frequency noise filter 470nf 20% 100vl stlc3055 10/22
name function formula typ. value crd (6) high frequency noise filter 100nf 10% 15vl q1 dc/dc converter switch p ch. mos transistor rds(on) 1.2 w ,vds = -100v total gate charge=20nc max. with vgs=4.5v and vds=1v id>500ma possible choiches: irf9510 or irf9520 or irf9120 or equivalent d1 dc/dc converter series diode vr > 100v, t rr 50ns smbyw01-200 or equivalent rsense dc/dc converter peak current limiting rsense = 100mv/i pk 110m w @i pk = 900ma l (8) dc/dc converter inductor dc resistance 0.1 w (9) l=125 m h rfp1304pv (manuf.: all inductive) or sumida cdrh125 or equivalent cf1 dc/dc converter feedback loop stability 220pf to 470pf (10) rf1 negative battery programming level 250k w 125 m h (9) for high efficiency in hi-z mode coil resistance @125khz must be <3ohm (10) function of this capacitor is to introduce a zero at the resonance frequency for loop stab ility. in case some parasitic resistance are alr eady present in the loop (coil, cvbat, pcb layout), the presence of this capacitor can degrade the device noise performances; in thi s case cf1 should be removed being the loop stability already guaranteed by the parasitic resistance. external components (continued) stlc3055 11/22
zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat q1 rf1 clk crev crev d96tl275d csvr stlc3055 d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cs cfl rlv rlv ttx clock cttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx rttx supply gnd agnd bgnd suggested ground lay-out vdd cvb crd cf1 pgnd figure 6. application diagram. zac rs za zb ccomp tx zac1 zac zb tx control interface d0 d1 d2 bgnd cvcc cac cac iref rref gate vbat q1 rf1 clk crev crev d98tl380b csvr stlc3055 d0 d1 d2 det det iltf rlim rlim rth rth csvr rp tip agnd vpos vpos ch rsense d1 rx rx rs cttx2 rttx cvcc rsense rf2 cv vf l clk rp ring tip ring cvpos rdd rd rd ckttx cttx1 fttx supply gnd agnd bgnd suggested ground lay-out vdd cvb crd cf1 pgnd figure 7. application diagram without metering pulse generation. stlc3055 12/22
electrical characteristics test conditions: v pos = 6.0v, agnd = bgnd, normal polarity, t amb = 25c. external components as listed in the "typical values" column of external components table. note: testing of all parameter is performed at 25c. characterisation as well as design rules used allow correlation of tested performances at other temperatures. all parameters listed here are met in the oper- ating range: -40 to +85c. dc characteristics symbol parameter test condition min. typ. max. unit v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = 0 to 85c 44 50 v v lohi line voltage il = 0, hi-z (high impedance feeding) t amb = -40 to 85c 42 48 v v loa line voltage il = 0, active t amb = 0 to 85c 33 40 v v loa line voltage il = 0, active t amb = -40 to 85c 31 37 v ilim lim. current programming range active mode 20 40 ma ilima lim. current accuracy active mode. rel. to programmed value 20ma to 40ma -10 10 ma rfeed hi feeding resistance hi-z (high impedance feeding) 2.4 3.6 k w zrx rx port input impedance 280 k w ac characteristics l/t long. to transv. (see appendix for test circuit) rp = 41 w , 1% tol., active n. p., r l = 600 w (*) f = 300 to 3400hz 48 50 db t/l transv. to long. (see appendix for test circuit) rp = 41 w , 1% tol., active n. p., r l = 600 w (*) f = 300 to 3400hz 40 45 db t/l transv. to long. (see appendix for test circuit) rp = 41 w , 1% tol., active n. p., r l = 600 w (*) f = 1khz 48 53 db 2wrl 2w return loss 300 to 3400hz, active n. p., r l = 600 w (*) 22 26 db thl trans-hybrid loss 300 to 3400hz, 20log|vrx/vtx|, active n. p., r l = 600 w (*) 30 db ovl 2w overload level at line terminals on ref. imped. active n. p., r l = 600 w (*) 10 dbm txoff tx output offset active n. p., r l = 600 w (*) -150 150 mv g24 transmit gain abs. 0dbm @ 1020hz, active n. p., r l = 600 w (*) -6.4 -5.6 db g42 receive gain abs. 0dbm @ 1020hz, active n. p., r l = 600 w (*) -0.4 0.4 db g24f tx gain variation vs. freq. rel. 1020hz; 0dbm, 300 to 3400hz, active n. p., r l = 600 w (*) -0.12 0.12 db stlc3055 13/22
symbol parameter test condition min. typ. max. unit g42f rx gain variation vs. freq. rel. 1020hz; 0dbm, 300 to 3400hz, active n. p., r l = 600 w (*) -0.12 0.12 db v2wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = 0 to +85c -73 -68 dbmp v2wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = -40 to +85c -68 dbmp v4wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = 0 to +85c -75 -70 dbmp v4wp idle channel noise at line psophometric filtered active n. p., r l = 600 w (*) t amb = -40 to +85c -75 dbmp thd total harmonic distortion active n. p., r l = 600 w (*) -46 db vttx metering pulse level on line active - ttx zl = 200 w fttx = 12khz 200 250 mvrms clkfreq clk operating range -10% 125 10% khz ring vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 w + 1.0 m f t amb = 0 to +85c 45 49 vrms vring line voltage ring d2 toggling @ fr = 25hz load = 3ren; crest factor = 1.25 1ren = 1800 w + 1.0 m f t amb = -40 to +85c 44 48 vrms detectors iofftha off/hook current threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 10.5 ma roftha off/hook loop resistance threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 3.4 k w iontha on/hook current threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 6ma rontha on/hook loop resistance threshold act. mode, rth = 28.7k w 1% (prog. ith = 9ma) 8k w ioffthi off/hook current threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 10.5 ma roffthi off/hook loop resistance threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 800 w ionthi on/hook current threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 6ma ronthi on/hook loop resistance threshold hi z mode, rth = 28.7k w 1% (prog. ith = 9ma) 8k w electrical characteristics (continued) (*) r l : line resistance stlc3055 14/22
symbol parameter test condition min. typ. max. unit irt ring trip detector threshold range ring 20 50 ma irta ring trip detector threshold accuracy ring -15 15 % trtd ring trip detection time ring tbd ms td dialling distortion active -1 1 ms rlrt (1) loop resistance 500 w thal tj for th. alarm activation 160 c digital interface inputs: d0, d1, d2, pd, clk outputs: det vih in put high voltage 2 v vil input low voltage 0.8 v iih input high current -10 10 m a iil input low current -10 10 m a vol output low voltage iol = 1ma 0.45 v psrr and power consumption pserrc power supply rejection vpos to 2w port vripple = 100mvrms 50 to 4000hz 26 36 db ivpos vpos supply current @ ii = 0 hi-z on-hook active on-hook, ring (line open) 52 93 120 60 115 140 ma ma ma ipk peak current limiting accuracy ring off-hook rsense = 110m w -20% 950 +20% mapk electrical characteristics (continued) (1) rlrt = maximum loop resistance (incl. telephone) for correct ring trip detection. stlc3055 15/22
appendix a stlc3055 test circuits referring to the application diagram shown in fig. 7 of the stlc3055 datasheet and using as external components the typ. values specified in the "external components" table (page 13) find below the proper configuration for each measurement. all measurements requiring dc current termination should be performed using "wandel & goltermann dc loop holding circuit gh-1" or equivalent. tip ring rx tx stlc3055 application circuit w&g gh1 zref e vs 1kohm 1kohm 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm 100 m f figure a1. 2w return loss 2wrl = 20log(|zref + zs|/|zref-zs|) = 20log(e/2vs) tip ring rx tx stlc3055 application circuit w&g gh1 vrx vtx 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm figure a2. thl trans hybrid loss thl = 20log|vrx/vtx| stlc3055 16/22
tip ring rx tx stlc3055 application circuit w&g gh1 e vtx 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm figure a3. g24 transmit gain g24 = 20log|2vtx/e| tip ring rx tx stlc3055 application circuit w&g gh1 vrx vl 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm figure a4. g42 receive gain g42 = 20log|vi/vrx| tip ring rx tx stlc3055 application circuit w&g gh1 vl 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm vn vpos ~ figure a5. psrrc power supply rejection vpos to 2w port pssrc = 20log|vn/vl| stlc3055 17/22
tip ring rx tx stlc3055 application circuit w&g gh1 vcm vl 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 m f 300ohm 100 m f impedance matching better than 0.1% figure a6. l/t longitudinal to transversal conversion l/t = 20log|vcm/vl| 600ohm tip ring rx tx stlc3055 application circuit vcm w&g gh1 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 300ohm 100 m f 300ohm 100 m f impedance matching better than 0.1% vrx figure a7. t/l transversal to longitudinal conversion t/l = 20log|vrx/vcm| tip ring rx tx stlc3055 application circuit fttx (12 or 16khz) vlttx 200ohm ckttx figure a8. vttx metering pulse level on line stlc3055 18/22
tip ring rx tx stlc3055 application circuit w&g gh1 vl psophometric filtered 100 m f 100 m f 100ma dc max zin = 100k 200 to 6khz 600ohm vtx psophometric filtered figure a9. v2wp and w4wp: idle channel psophometric noise at line and tx. v2wp = 20log|vl/0.774l|; v4wp = 20log|vtx/0.774l| appendix b stlc3055 overvoltage protection tip ring bgnd vbat rp1 rp2 rp1 rp2 rp2: fuse or ptc 2 x sm4t39rx stlc3055 tip ring figure b1. simplified configuration for indoor overvoltage protection tip bgnd vbat rp1 rp2 rp2: fuse or ptc 2 x sm4t39rx stlc3055 tip ring rp1 rp2 ring lcp1511 figure b2. standard overvoltage protection configuration for k20 compliance stlc3055 19/22
appendix c typical state diagram for stlc3055 operation tj>tth pd=0, d0=d1=0 pd=1, d0=d1=0 power down hi-z feeding off hook detection active off hook on hook detection for t>tref active on hook ringing ring burst d0=1, d1=0, d2=0/1 ring trip detection normally used for on hook transmission ring pause d0=0, d1=1, d2=0 ring burst off hook detection d0=0, d1=1, d2=0 on hook condition note: all state transitions are under the microprocessor control. figure c1. stlc3055 20/22
stlc3055 21/22
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsib ility for the cons equences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics ? 2000 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com stlc3055 22/22

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