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opa2684 www.ti.com copyright ?2002, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. sbos239b ?april 2002 ?revised november 2002 low-power, dual current-feedback operational amplifier features minimal bandwidth change versus gain 170mhz bandwidth at g = +2 > 120mhz bandwidth to gain > +10 low distortion: < C82dbc at 5mhz high output current: 120ma single +5v to +12v supply operation dual 2.5 to 6.0v supply operation low supply current: 3.4ma total v+ v o v i err r g r f z (s) i err + low-power amplifier 1 of 2 channels description the opa2684 provides a new level of performance in low- power, wideband, current-feedback (cfb) amplifiers. this cfb plus amplifier is among the first to use an internally closed-loop input buffer stage that enhances performance significantly over earlier low-power cfb amplifiers. while retaining the benefits of very low power operation, this new architecture provides many of the benefits of a more ideal cfb amplifier. the closed-loop input stage buffer gives a very low and linearized impedance path at the inverting input to sense the feedback error current. this improved inverting input impedance retains exceptional bandwidth to much higher gains and improves harmonic distortion over earlier solutions limited by inverting input linearity. beyond simple high-gain applications, the opa2684 cfb plus amplifier per- mits the gain setting element to be set with considerable applications short-loop adsl co driver low-power broadcast video drivers differential equalizing filters differential saw filter post amplifier multichannel summing amplifiers professional cameras adc input drivers freedom from amplifier bandwidth interaction. this allows frequency response peaking elements to be added, multiple input inverting summing circuits to have greater bandwidth, and low-power line drivers to meet the demanding require- ments of studio cameras and broadcast video. the output capability of the opa2684 also sets a new mark in performance for low-power, current-feedback amplifiers. delivering a full 4vp-p swing on 5v supplies, the opa2684 also has the output current to support > 3vp-p into 50 ? loads. this minimal output headroom requirement is comple- mented by a similar 1.2v input stage headroom giving exceptional capability for single +5v operation. the opa2684 s low 3.4ma supply current is precisely trimmed at +25 c. this trim, along with low shift over temperature and supply voltage, gives a very robust design over a wide range of operating conditions. 6 3 0 3 6 9 12 15 18 21 24 normalized gain (3db/div) r f = 800 ? g = 100 g = 50 g = 20 g = 10 g = 2 g = 1 10 mhz 100 200 bw (mhz) vs gain g = 5 patent pending o p a 2 6 8 4 production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
opa2684 2 sbos239b www.ti.com specified package temperature package ordering transport product package-lead designator (1) range marking number media, quantity opa2684 so-8 d 40 c to +85 c opa2684 OPA2684ID rails, 100 """"" OPA2684IDr tape and reel, 2500 opa2684 sot23-8 dcn 40 c to +85 c a84 OPA2684IDcnt tape and reel, 250 """"" OPA2684IDcnr tape and reel, 3000 absolute maximum ratings (1) power supply ............................................................................... 6.5v dc internal power dissipation ................................. see thermal information differential input voltage .................................................................. 1.2v input voltage range ............................................................................ v s storage temperature range: id, idbv ......................... 40 c to +125 c lead temperature (soldering, 10s) .............................................. +300 c junction temperature (t j ) ........................................................... +175 c esd rating: human body model (hbm) ........................................ 2000v charged device model (cdm) .................................. 1500v note: (1) stresses above these ratings may cause permanent damage. exposure to absolute maximum conditions for extended periods may degrade device reliability. package/ordering information electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. pin configuration opa2684 related products singles duals triples quads features opa684 opa2683 opa3684 opa2684 low-power cfb plus opa691 opa2691 opa3691 high slew rate cfb opa685 > 500mhz cfb top view so top view sot note: (1) for the most current specifications, and package information, refer to our web site at www.ti.com. 1 2 3 4 8 7 6 5 +v s out b in b +in b out a in a +in a v s opa2684 1 2 3 4 8 7 6 5 out a in a +in a v s +v s out b in b +in b a84 pin 1
opa2684 3 sbos239b www.ti.com ac performance (see figure 1) small-signal bandwidth (v o = 0.5vp-p) g = +1, r f = 800 ? 250 mhz typ c g = +2, r f = 800 ? 170 120 118 117 mhz min b g = +5, r f = 800 ? 138 mhz typ c g = +10, r f = 800 ? 120 mhz typ c g = +20, r f = 800 ? 95 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o = 0.5vp-p, r f = 800 ? 19 16 14 14 mhz min b peaking at a gain of +1 r f = 800 ? , v o = 0.5vp-p 1.4 4.8 5.9 6.3 db max b large-signal bandwidth g = +2, v o = 4vp-p 90 mhz typ c slew rate g = 1, v o = 4v step 780 675 650 575 v/ sminb g = +2, v o = 4v step 750 680 660 656 v/ sminb rise-and-fall time g = +2, v o = 0.5v step 3 ns typ c g = +2, v o = 4v step 3.8 ns typ c harmonic distortion g = +2, f = 5mhz, v o = 2vp-p 2nd-harmonic r l = 100 ? 67 59 59 58 dbc max b r l 1k ? 82 66 65 65 dbc max b 3rd-harmonic r l = 100 ? 70 66 65 65 dbc max b r l 1k ? 84 82 81 81 dbc max b input voltage noise f > 1mhz 3.7 4.1 4.2 4.4 nv/ hz max b noninverting input current noise f > 1mhz 9.4 11 12 12.5 pa/ hz max b inverting input current noise f > 1mhz 17 18 18.5 19 pa/ hz max b differential gain g = +2, ntsc, v o = 1.4vp, r l = 150 ? 0.04 % typ c differential phase g = +2, ntsc, v o = 1.4vp, r l = 150 ? 0.02 deg typ c channel-to-channel isolation f = 5mhz 70 db typ c dc performance (4) open-loop transimpedance gain (z ol ) v o = 0v, r l = 1k ? 355 160 155 153 k ? min a input offset voltage v cm = 0v 1.5 3.8 4.4 4.6 mv max a average offset voltage drift v cm = 0v 12 12 v/ cmax b noninverting input bias current v cm = 0v 5.0 11 12.5 13 amaxa average noninverting input bias current drift v cm = 0v 25 30 na/ cmax b inverting input bias current v cm = 0v 5.0 17 18.5 19.5 amaxa average inverting input bias current drift v cm = 0v 35 40 na /c max b input common-mode input range (5) (cmir) 3.75 3.65 3.65 3.6 v min a common-mode rejection ratio (cmrr) v cm = 0v 60 53 52 52 db min a noninverting input impedance 50 || 2 k ? || pf typ c inverting input resistance ( r i ) open-loop, dc 4.0 ? typ c output voltage output swing 1k ? load 4.1 3.9 3.9 3.8 v min a current output, sourcing v o = 0 160 130 125 120 ma min a current output, sinking v o = 0 120 C 100 95 90 ma min a closed-loop output impedance g = +2, f = 100khz 0.006 ? typ c power supply specified operating voltage 5 v typ c maximum operating voltage range 6 6 6vmaxa max quiescent current v s = 5v 3.4 3.6 3.9 3.9 ma max a min quiescent current v s = 5v 3.4 3.2 3.1 2.9 ma min a power-supply rejection ratio ( psrr) input referred 60 54 53 53 db typ a temperature range specification: id, idcn 40 to +85 c typ c thermal resistance, ja junction-to-ambient dso-8 125 c/w typ c dcn sot23-8 150 c/w typ c notes: (1) junction temperature = ambient for +25 c tested specifications. (2) junction temperature = ambient at low temperature limit, junction temperature = ambient +2 c at high temperature limit for over temperature tested specifications. (3) test levels: (a) 100% tested at +25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (4) current is considere d positive out-of-node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits. OPA2684ID, idcn 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (1) 70 c (2) +85 c (2) units max level (3) typ min/max over temperature electrical characteristics: v s = 5v boldface limits are tested at +25 c. r f = 800 ? , r l = 100 ? , and g = +2 , (see figure 1 for ac performance only), unless otherwise noted.
opa2684 4 sbos239b www.ti.com ac performance (see figure 3) small-signal bandwidth (v o = 0.5vp-p) g = +1, r f = 1.0k ? 140 mhz typ c g = +2, r f = 1.0k ? 110 86 85 82 mhz min b g = +5, r f = 1.0k ? 100 mhz min c g = +10, r f = 1.0k ? 90 mhz typ c g = +20, r f = 1.0k ? 75 mhz typ c bandwidth for 0.1db gain flatness g = +2, v o < 0.5vp-p, r f = 1.0k ? 21 12 11 10 mhz min b peaking at a gain of +1 r f = 1.0k ? , v o < 0.5vp-p 0.5 2.6 3.4 3.7 db max b large-signal bandwidth g = 2, v o = 2vp-p 86 mhz typ c slew rate g = 2, v o = 2v step 380 300 290 280 v/ sminb rise-and-fall time g = 2, v o = 0.5v step 4.3 ns typ c g = 2, v o = 2vstep 4.8 ns typ c harmonic distortion g = 2, f = 5mhz, v o = 2vp-p 2nd-harmonic r l = 100 ? to v s /2 65 60 59 59 dbc max b r l 1k ? to v s /2 84 62 61 61 dbc max b 3rd-harmonic r l = 100 ? to v s /2 65 64 63 63 dbc max b r l 1k ? to v s /2 74 70 70 69 dbc max b input voltage noise f > 1mhz 3.7 4.1 4.2 4.4 nv/ hz max b noninverting input current noise f > 1mhz 9.4 11 12 12.5 pa/ hz max b inverting input current noise f > 1mhz 17 18 18.5 19 pa/ hz max b differential gain g = +2, ntsc, v o = 1.4vp, r l = 150 ? 0.04 % typ c differential phase g = +2, ntsc, v o = 1.4vp, r l = 150 ? 0.07 deg typ c channel-to-channel isolation f = 5mhz 70 db typ c dc performance (4) open-loop transimpedance gain (z ol ) v o = v s /2, r l = 1k ? to v s /2 355 160 155 153 k ? min a input offset voltage v cm = v s /2 1.0 3.3 3.9 4.1 mv max a average offset voltage drift v cm = v s /2 12 12 v/ cmax b noninverting input bias current v cm = v s /2 5 11 12.5 13 amaxa average noninverting input bias current drift v cm = v s /2 25 30 na/ cmax b inverting input bias current v cm = v s /2 5 13 14.5 16 amaxa average inverting input bias current drift v cm = v s /2 25 30 na /c max b input least positive input voltage (5) 1.25 1.32 1.35 1.38 v max a most positive input voltage (5) 3.75 3.68 3.65 3.62 v min a common-mode refection ratio (cmrr) v cm = v s /2 58 52 51 51 db min a noninverting input impedance 50 || 1 k ? || pf typ c inverting input resistance (r i ) open-loop 4.4 ? typ c output most positive output voltage r l = 1k ? to v s /2 4.10 3.9 3.9 3.8 v min a least positive output voltage r l = 1k ? to v s /2 0.9 1.1 1.1 1.2 v max a current output, sourcing v o = v s /2 80 65 60 55 ma min a current output, sinking v o = v s /2 70 55 50 45 ma min a closed-loop output impedance g = +2, f = 100khz 0.006 ? typ c power supply specified single-supply operating voltage 5 v typ c max single-supply operating voltage range 12 12 12 v max a max quiescent current v s = +5v 2.9 3.1 3.1 3.1 ma max a min quiescent current v s = +5v 2.9 2.6 2.4 2.3 ma min a power-supply rejection ratio (+psrr) input referred 58 db typ c temperature range specification: id, idbv 40 to +85 c typ c thermal resistance, ja junction-to-ambient dso-8 125 c/w typ c dcn sot23-8 150 c/w typ c notes: (1) junction temperature = ambient for +25 c tested specifications. (2) junction temperature = ambient at low temperature limit, junction temperature = ambient +1 c at high temperature limit for over temperature tested specifications. (3) test levels: (a) 100% tested at +25 c. over temperature limits by characterization and simulation. (b) limits set by characterization and simulation. (c) typical value only for information. (4) current is considere d positive out-of-node. v cm is the input common-mode voltage. (5) tested < 3db below minimum specified cmr at cmir limits. electrical characteristics: v s = +5v boldface limits are tested at +25 c. r f = 1k ? , r l = 100 ? , and g = +2 , (see figure 3 for ac performance only), unless otherwise noted. OPA2684ID, idcn 0 c to C 40 c to min/ test parameter conditions +25 c +25 c (1) 70 c (2) +85 c (2) units max level (3) typ min/max over temperature
opa2684 5 sbos239b www.ti.com typical characteristics: v s = 5v at t a = +25 c, g = +2, r f = 800 ? , and r l = 100 ? , unless otherwise noted. 6 3 0 3 6 9 12 15 18 frequency (mhz) 1 200 10 100 noninverting small-signal frequency response normalized gain (3db/div) v o = 0.5vp-p r f = 800 ? see figure 1 g = 1 g = 2 g = 50 g = 20 g = 10 g = 5 g = 100 3 0 3 6 9 12 frequency (mhz) 1 200 10 100 inverting small-signal frequency response normalized gain (3db/div) v o = 0.5vp-p r f = 800 ? see figure 2 g = 1 g = 10 g = 16 g = 5 g = 2 9 6 3 0 3 frequency (mhz) 1 200 10 100 noninverting large-signal frequency response gain (db) g = +2 r l = 100 ? see figure 1 v o = 1vp-p v o = 0.5vp-p v o = 5vp-p v o = 2vp-p 3 0 3 6 9 12 frequency (mhz) 1 200 10 100 inverting large-signal frequency response gain (db) g = 1 r l = 100 ? v o = 0.5vp-p see figure 2 2vp-p 1vp-p 5vp-p noninverting pulse response time (10ns/div) output voltage (200mv/div) output voltage (400mv/div) 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 large-signal right scale small-signal left scale see figure 1 g = +2 inverting pulse response time (10ns/div) output voltage (200mv/div) output voltage (400mv/div) 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 large-signal right scale small-signal left scale see figure 2 g = 1
opa2684 6 sbos239b www.ti.com typical characteristics: v s = 5v (cont.) at t a = +25 c, g = +2, r f = 800 ? , and r l = 100 ? , unless otherwise noted. harmonic distortion vs load resistance 100 1k load resistance ( ? ) harmonic distortion (dbc) 50 55 60 65 70 75 80 85 90 v o = 2vp-p f = 5mhz g = +2 see figure 1 2nd-harmonic 3rd-harmonic 50 60 70 80 90 frequency (mhz) 0.1 20 110 harmonic distortion vs frequency harmonic distortion (dbc) v o = 2vp-p r l = 100 ? see figure 1 2nd-harmonic 3rd-harmonic harmonic distortion vs output voltage 0.5 1 5 output voltage (vp-p) harmonic distortion (dbc) 50 60 70 80 90 f = 5mhz r l = 100 ? 2nd-harmonic 3rd-harmonic 5mhz harmonic distortion vs supply voltage 2.5 3 3.5 4 4.5 5 5.5 6 supply voltage ( v) harmonic distortion (dbc) 50 60 70 80 90 v o = 2vp-p r l = 100 ? 2nd-harmonic 3rd-harmonic harmonic distortion vs noninverting gain noninverting gain (v/v) harmonic distortion (dbc) 11020 50 55 60 65 70 75 80 85 90 2nd-harmonic 3rd-harmonic see figure 1 harmonic distortion vs inverting gain 11020 inverting gain ? (v/v) ? harmonic distortion (dbc) 50 55 60 65 70 75 80 85 90 2nd-harmonic 3rd-harmonic see figure 2
opa2684 7 sbos239b www.ti.com typical characteristics: v s = 5v (cont.) at t a = +25 c, g = +2, r f = 800 ? , and r l = 100 ? , unless otherwise noted. 100 10 1 frequency (hz) 100 10m 1k 10k 100k 1m input voltage and current noise density voltage noise (nv/ hz) current noise (pa/ hz) noninverting current noise 9.4pa/ hz voltage noise 3.7nv/ hz inverting current noise 17pa/ hz 2-tone, 3rd-order intermodulation distortion 8 7 6 5 4 3 2 145 3 2 1 0678 power at load (p o each tone, dbm) 3rd-order spurious level (dbc) 50 60 70 80 90 50 ? +5v 5v 50 ? 50 ? p i p o 800 ? 800 ? opa2684 20mhz 10mhz 5mhz 1mhz 50 40 30 20 10 0 c load (pf) 1 100 10 r s vs c load r s ( ? ) 0.5db peaking 9 6 3 0 3 6 frequency (mhz) 1 300 10 100 small-signal bandwidth vs c load normalized gain (db) 5pf 800 ? 1k ? opa2684 r s v o +5v 5v 50 ? c l 800? v i 12pf 100pf 50pf 75pf 20pf 33pf 1k ? is optional cmrr and psrr vs frequency 10 2 10 3 10 4 10 5 10 6 10 7 10 8 frequency (hz) power-supply rejection ratio (db) common-mode rejection ratio (db) 70 60 50 40 30 20 10 0 cmrr +psrr psrr open-loop transimpedance gain and phase 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 frequency (hz) open-loop transimpedance gain (db ? ) 120 100 80 60 40 20 0 open-loop phase ( ) 0 30 60 90 120 150 180 20log (z ol ) z ol
opa2684 8 sbos239b www.ti.com typical characteristics: v s = 5v (cont.) at t a = +25 c, g = +2, r f = 800 ? , and r l = 100 ? , unless otherwise noted. 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 number of 150 ? video loads 14 23 composite video differential gain/phase differential gain (%) differential phase ( ) gain = +2 ntsc, positive video dg dp output current and voltage limitations 150 100 50 0 50 100 150 i o (ma) v o (v) 5 4 3 2 1 0 1 2 3 4 5 1w power limit each channel r l = 100 ? r l = 5 0 ? r l = 500 ? 1w power limit typical dc drift over ambient temperature 50 25 0 25 50 75 100 125 ambient temperature ( c) input bias currents ( a) and offset voltage (mv) 4 3 2 1 0 1 2 3 4 input offset voltage noninverting input bias current inverting input bias current supply and output current vs ambient temperature 50 25 25 0 50 75 100 125 ambient temperature ( c) output current (ma) 200 175 150 125 100 supply current (ma) sourcing output current sinking output current supply current 3.8 3.6 3.4 3.2 3 settling time 0102030405060 time (ns) error to final value (%) 0.05 0.04 0.03 0.02 0.01 0 0.01 0.02 0.03 0.04 0.05 2v step see figure 1 closed-loop output impedance vs frequency frequency (hz) 100k 1m 1k 10k 100 10m 100m output impedance ( ? ) 100 10 1 0.01 0.001 800 ? z o 800 ? 1/2 opa2684
opa2684 9 sbos239b www.ti.com typical characteristics: v s = 5v (cont.) at t a = +25 c, g = +2, r f = 800 ? , and r l = 100 ? , unless otherwise noted. noninverting overdrive recovery time (100ns/div) input voltage (0.8v/div) output voltage (1.6v/div) 4.0 3.2 2.4 1.6 0.8 0 0.8 1.6 2.4 3.2 4.0 8.0 6.4 4.8 3.2 1.6 0 1.6 3.2 4.8 6.4 8.0 see figure 1 input voltage left-scale output voltage right-scale inverting overdrive recovery time (100ns/div) input voltage (1.6v/div) output voltage (1.6v/div) 8.0 6.4 4.8 3.2 1.6 0 1.6 3.2 4.8 6.4 8.0 8.0 6.4 4.8 3.2 1.6 0 1.6 3.2 4.8 6.4 8.0 see figure 2 input voltage left-scale output voltage right-scale input and output range vs supply voltage supply voltage (v) 4 3 2 5 6 input and output voltage range (v) 6 5 4 3 2 1 0 1 2 3 4 5 6 input voltage range output voltage range
opa2684 10 sbos239b www.ti.com 55 60 65 70 75 80 85 load resistance ( ? ) 10 1k 100 differential distortion vs load resistance harmonic distortion (dbc) v o = 4vp-p g d = 2 f = 5mhz 3rd-harmonic 2nd-harmonic 55 60 65 70 75 80 85 differential distortion vs frequency frequency (mhz) 110 harmonic distortion (dbc) 3rd-harmonic 2nd-harmonic v o = 4vp-p g d = 2 r l = 100 ? 55 60 65 70 75 80 85 differential distortion vs output voltage output voltage (vp-p) 110 harmonic distortion (dbc) 3rd-harmonic 2nd-harmonic f = 5mhz g d = 2 r l = 100 ? 1/2 opa2684 r g 800 ? +5v 1/2 opa2684 r g r l v i 800 ? v o 5v g d = 804 ? r g 6 3 0 3 6 9 12 15 18 21 24 frequency (mhz) 1 200 10 100 differential small-signal frequency response normalized gain (db) v o = 200mvp-p g = 2 g = 20 g = 10 g = 5 g = 1 9 6 3 0 3 6 9 12 15 18 frequency (hz) 1 200 10 100 differential large-signal frequency response normalized gain (db) g d = 2 r l = 100 ? v o = 0.2vp-p v o = 1vp-p v o = 2vp-p v o = 5vp-p differential performance test circuit typical characteristics: v s = 5v (cont.) at t a = +25 c, g = +2, r f = 800 ? , r l = 100 ? , unless otherwise noted.
opa2684 11 sbos239b www.ti.com 6 3 0 3 6 9 12 15 18 frequency (mhz) 1 200 10 100 noninverting small-signal frequency response normalized gain (3db/div) g = 100 see figure 3 g = 50 r f = 1k ? g = 1 g = 2 g = 5 g = 20 g = 10 3 0 3 6 9 12 frequency (mhz) 1 200 10 100 inverting small-signal frequency response normalized gain (3db/div) see figure 4 r f = 1.0k ? g = 1 g = 10 g = 20 g = 5 g = 2 9 6 3 0 3 frequency (mhz) 1 200 10 100 noninverting large-signal frequency response gain (db) 0.2vp-p 1vp-p 0.5vp-p 2vp-p typical characteristics: v s = +5v at t a = +25 c, v s = 5v, g = +2, r f = 1.0k ? , and r l = 100 ? , unless otherwise noted. 3 0 3 6 9 12 frequency (mhz) 1 200 10 100 inverting large-signal frequency response gain (db) v o = 0.2vp-p v o = 1vp-p v o = 0.5vp-p v o = 2vp-p noninverting pulse response time (10ns/div) output voltage (200mv/div) output voltage (400mv/div) 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 large-signal right scale small-signal left scale see figure 3 inverting pulse response time (10ns/div) output voltage (200mv/div) output voltage (400mv/div) 0.4 0.3 0.2 0.1 0 0.1 0.2 0.3 0.4 1.6 1.2 0.8 0.4 0 0.4 0.8 1.2 1.6 large-signal right scale small-signal left scale see figure 4
opa2684 12 sbos239b www.ti.com typical characteristics: v s = +5v (cont.) at t a = +25 c, v s = 5v, g = +2, r f = 1.0k ? , and r l = 100 ? , unless otherwise noted. harmonic distortion vs load resistance 100 1k load resistance ( ? ) harmonic distortion (dbc) 50 55 60 65 70 75 80 85 90 v o = 2vp-p f = 5mhz see figure 3 3rd-harmonic 2nd-harmonic 50 60 70 80 90 frequency (mhz) 0.1 20 110 harmonic distortion vs frequency harmonic distortion (dbc) v o = 2vp-p r l = 100 ? see figure 3 2nd-harmonic 3rd-harmonic 50 60 70 80 90 output voltage (vp-p) 0.5 3 12 harmonic distortion vs output voltage harmonic distortion (dbc) 2nd-harmonic 3rd-harmonic see figure 3 2-tone, 3rd-order intermodulation distortion 15 14 13 12 11 10 6 5 7 8 9 4 3 power at load (each tone, dbm) 3rd-order spurious level (dbc) 50 60 70 80 90 see figure 3 10mhz 20mhz 5mhz supply and output current vs temperature 50 25 0 25 50 75 125 ambient temperature ( c) output current (ma) 100 90 80 70 60 50 2.9 2.8 2.7 2.6 2.5 2.4 supply current (ma) 100 supply current right-scale sourcing output current left-scale sinking output current left-scale 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 number of 150 ? video loads 14 23 composite video differential gain/phase differential gain (%) differential phase ( ) dp dg g = +2 ntsc, positive video
opa2684 13 sbos239b www.ti.com typical characteristics: v s = +5v (cont.) at t a = +25 c, v s = 5v, g = +2, r f = 1.0 ? , and r l = 100 ? , unless otherwise noted. 1/2 opa2684 1/2 opa2684 0.01 f 0.01 f r g r g r l 1k ? 1k ? +5v +2.5v +2.5v v o v i g d = 1k ? r g 6 3 0 3 6 9 12 15 18 21 24 frequency (mhz) 1 200 10 100 differential small-signal frequency response normalized gain (db) v o = 200mvp-p r l = 100 ? g = 2 g = 20 g = 10 g = 5 g = 1 9 6 3 0 3 6 9 12 15 18 frequency (mhz) 1 200 10 100 differential large-signal frequency response normalized gain (db) g d = 2 r l = 100 ? v o = 5vp-p v o = 2vp-p v o = 1vp-p v o = 200mvp-p 55 60 65 70 75 80 85 load resistance ( ? ) 10 1k 100 differential distortion vs load resistance harmonic distortion (dbc) v o = 4vp-p g d = 2 f = 5mhz 3rd-harmonic 2nd-harmonic 55 60 65 70 75 80 85 differential distortion vs frequency frequency (mhz) 110 harmonic distortion (dbc) 3rd-harmonic 2nd-harmonic v o = 2vp-p r l = 100 ? 55 60 65 70 75 80 85 differential distortion vs output voltage output voltage (vp-p) 110 harmonic distortion (dbc) 3rd-harmonic 2nd-harmonic differential performance test circuit
opa2684 14 sbos239b www.ti.com figure 1. dc-coupled, g = +2v/v, bipolar supply speci- fications and test circuit. figure 2. dc-coupled, g = 1v/v, bipolar supply specifi- cations and test circuit. applications information low-power, current-feedback operation the dual channel opa2684 gives a new level of perfor- mance in low-power, current-feedback op amps. using a new input stage buffer architecture, the opa2684 cfb plus amplifier holds nearly constant ac performance over a wide gain range. this closed-loop internal buffer gives a very low and linearized impedance at the inverting node, isolating the amplifier s ac performance from gain element variations. this allows both the bandwidth and distortion to remain nearly constant over gain, moving closer to the ideal current- feedback performance of gain bandwidth independence. this low-power amplifier also delivers exceptional output power it s 4v swing on 5v supplies with > 100ma output drive gives excellent performance into standard video loads or doubly-terminated 50 ? cables. this dual-channel device can provide adequate drive for several emerging differential driver applications with exceptional power efficiency. single +5v supply operation is also supported with similar band- widths but reduced output power capability. for lower quies- cent power in a dual cfb plus amplifier, consider the opa2683 while for higher output power in a dual current-feedback op amp, consider the opa2691 or opa2677. figure 1 shows the dc-coupled, gain of +2, dual power- supply circuit used as the basis of the 5v electrical and typical characteristics for each channel. for test purposes, the input impedance is set to 50 ? with a resistor to ground, and the output impedance is set to 50 ? with a series output resistor. voltage swings reported in the characteristics are taken directly at the input and output pins while load powers (dbm) are defined at a matched 50 ? load. for the circuit of figure 1, the total effective load will be 100 ? || 1600 ? = 94 ? . gain changes are most easily accomplished by simply re- setting the r g value, holding r f constant at its recommended value of 800 ? . figure 2 shows the dc-coupled, gain of 1v/v, dual power- supply circuit used as the basis of the inverting typical characteristics for each channel. inverting operation offers several performance benefits. since there is no common- mode signal across the input stage, the slew rate for inverting operation is typically higher and the distortion performance is slightly improved. an additional input resistor, r m , is included in figure 2 to set the input impedance equal to 50 ? . the parallel combination of r m and r g set the input impedance. as the desired gain increases for the inverting configuration, r g is adjusted to achieve the desired gain, while r m is also adjusted to hold a 50 ? input match. a point will be reached where r g will equal 50 ? , r m is removed, and the input match is set by r g only. with r g fixed to achieve an input match to 50 ? , increasing r f will increase the gain. this will, however, reduce the achievable bandwidth as the feedback resistor increases from its recommended value of 800 ? . if the source does not require an input match to 50 ? , either adjust r m to get the desired load, or remove it and let the r g resistor alone provide the input load. these circuits show 5v operation. the same circuit can be applied with bipolar supplies from 2.5v to 6v. internal supply independent biasing gives nearly the same perfor- mance for the opa2684 over this wide range of supplies. generally, the optimum feedback resistor value (for nomi- nally flat frequency response at g = +2) will increase in value as the total supply voltage across the opa2684 is reduced from 5v. see figure 3 for the ac-coupled, single +5v supply, gain of +2v/v circuit configuration used as a basis only for the +5v electrical and typical characteristics for each channel. the key requirement of broadband single-supply operation is to maintain input and output signal swings within the useable voltage ranges at both the input and the output. the circuit of figure 3 establishes an input midpoint bias using a simple resistive divider from the +5v supply (two 10k ? resistors) to the noninverting input. the input signal is then ac-coupled r f 800 ? 1/2 opa2684 +5v 5v 50 ? r m 50 ? r g 800 ? 50 ? source 50 ? load v i 0.1 f 6.8 f 0.1 f 6.8 f + + r f 800 ? 1/2 opa2684 +5v 5v 50 ? r m 53.6 ? r g 800 ? 50 ? load 50 ? source 0.1 f6.8 f 0.1 f6.8 f + + v i
opa2684 15 sbos239b www.ti.com figure 3. ac-coupled, g = +2v/v, single-supply specifi- cations and test circuit. figure 4. ac-coupled, g = 1v/v, single-supply specifi- cations and test circuit. figure 5. noninverting differential i/o amplifier. into this midpoint voltage bias. the input voltage can swing to within 1.25v of either supply pin, giving a 2.5vp-p input signal range centered between the supply pins. the input impedance of figure 3 is set to give a 50 ? input match. if the source does not require a 50 ? match, remove this and drive directly into the blocking capacitor. the source will then see the 5k ? load of the biasing network. the gain resistor (r g ) is ac-coupled, giving the circuit a dc gain of +1, which puts the noninverting input dc bias voltage (2.5v) on the output as well. the feedback resistor value has been adjusted from the bipolar 5v supply condition to re-optimize for a flat frequency response in +5v only, gain of +2, operation. on a single +5v supply, the output voltage can swing to within 1.0v of either supply pin while delivering more than 70ma output current giving 3v output swing into 100 ? (8dbm maximum at a matched 50 ? load). the circuit of figure 3 shows a blocking capacitor driving into a 50 ? output resistor then into a 50 ? load. alternatively, the blocking capacitor could be removed if the load is tied to a supply midpoint or to ground if the dc current required by the load is acceptable. figure 4 shows the ac-coupled, single +5v supply, gain of 1v/v circuit configuration used as a basis for the +5v typical characteristics for each channel. in this case, the midpoint dc bias on the noninverting input is also decoupled with an additional 0.1 f decoupling capacitor. this reduces the source impedance at higher frequencies for the noninverting input bias current noise. this 2.5v bias on the noninverting input pin appears on the inverting input pin and, since r g is dc blocked by the input capacitor, will also appear at the output pin. one advantage to inverting opera- tion is that since there is no signal swing across the input stage, higher slew rates and operation to even lower supply voltages is possible. to retain a 1vp-p output capability, operation down to a 3v supply is allowed. at a +3v supply, the input stage is saturated, but for the inverting configuration of a current-feedback amplifier, wideband operation is re- tained even under this condition. the circuits of figure 3 and 4 show single-supply operation at +5v. these same circuits may be used up to single supplies of +12v with minimal change in the performance of the opa2684. differential interface applications dual op amps are particularly suitable to differential input to differential output applications. typically, these fall into either analog-to-digital converter (adc) input interface or line driver applications. two basic approaches to differential i/o are noninverting or inverting configurations. since the output is differential, the signal polarity is somewhat meaningless the noninverting and inverting terminology applies here to where the input is brought into the opa2684. each has its advantages and disadvantages. figure 5 shows a basic starting point for noninverting differential i/o applications. r f 1k ? 1/2 opa2684 +5v 50 ? 50 ? load 50 ? source 0.1 f 6.8 f + 10k ? 10k ? r m 50 ? r g 1k ? 0.1 f 0.1 f 0.1 f v i r f 1k ? 1/2 opa2684 +5v 50 ? 50 ? load 50 ? source 0.1 f 0.1 f 6.8 f + r g 1k ? 10k ? 10k ? 0.1 f v i 0.1 f r m 52.3 ? ? r f 800 ? 1/2 opa2684 +v cc v cc r g v o 1/2 opa2684 v i
opa2684 16 sbos239b www.ti.com figure 6. inverting differential i/o amplifier. figure 7. single to differential conversion. this approach provides for a source termination impedance that is independent of the signal gain. for instance, simple differential filters may be included in the signal path right up to the noninverting inputs without interacting with the gain setting. the differential signal gain for the circuit of figure 5 is: a d = 1 + 2 r f /r g since the opa2684 is a cfb plus amplifier, its bandwidth is principally controlled with the feedback resistor value, figure 5 shows the recommended value of 800 ? . the differential gain, however, may be adjusted with considerable freedom using just the r g resistor. in fact, r g may be a reactive network providing a very isolated shaping to the differential frequency response. since the inverting inputs of the opa2684 are very low impedance closed-loop buffer outputs, the r g element does not interact with the amplifier s bandwidth, wide ranges of resistor values and/or filter elements may be inserted here with minimal amplifier bandwidth interaction. various combinations of single-supply or ac-coupled gain can also be delivered using the basic circuit of figure 5. common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1 since an equal dc voltage at each inverting node creates no current through r g . this circuit does show a common-mode gain of 1 from input to output. the source connection should either remove this common-mode signal if undesired (using an input trans- former can provide this function), or the common-mode voltage at the inputs can be used to set the output common- mode bias. if the low common-mode rejection of this circuit is problem, the output interface may also be used to reject that common-mode. for instance, most modern differential input adc s reject common-mode signals very well while a line driver application through a transformer will also attenu- ate the common-mode signal through to the line. figure 6 shows a differential i/o stage configured as an inverting amplifier. in this case, the gain resistors (r g ) become part of the input resistance for the source. this provides a better noise performance than the noninverting configuration but does limit the flexibility in setting the input impedance separately from the gain. the two noninverting inputs provide an easy common-mode control input. this is particularly easy if the source is ac-coupled through either blocking caps or a transformer. in either case, the common-mode input voltages on the two noninverting inputs again have a gain of 1 to the output pins giving particularly easy common-mode control for single- supply operation. the opa2684 used in this configuration does constrain the feedback to the 800 ? region for best frequency response. with r f fixed, the input resistors may be adjusted to the desired gain but will also be changing the input impedance as well. the high frequency common-mode gain for this circuit from input to output will be the same as for the signal gain. again, if the source might include an undesired common-mode signal, that could be rejected at the input using blocking caps (for low frequency and dc common-mode) or a transformer coupling. dc-coupled single to differential conversion the previous differential output circuits were set up to re- ceive a differential input as well. a simple way to provide a dc-coupled single to differential conversion using a dual op amp is shown in figure 7. here, the output of the first stage is simply inverted by the second to provide an inverting version of a single amplifier design. this approach works well for lower frequencies but will start to depart from ideal differential outputs as the propagation delay and distortion of the inverting stage adds significantly to that present at the noninverting output pin. r f 800 ? r f 800 ? r g r g 1/2 opa2684 +v cc v cc v cm v cm v o 1/2 opa2684 v i 800 ? 12vp-p differential 800 ? 1/2 opa2684 +5v 5v 800 ? 160 ? 1/2 opa2684 50 ? 1vp-p the circuit of figure 7 is set up for a single-ended gain of 6 to the output of the first amplifier then an inverting gain of 1 through the second stage to provide a total differential gain of 12. see figure 8 for the ssbw for the circuit of figure 7. large-signal distortion at 12vp-p output into the 100 ? differ- ential load is 80dbc.
opa2684 17 sbos239b www.ti.com figure 8. small-signal bandwidth for figure 7. figure 9. low-power, differential i/o, 4th-order butterworth active filter. differential active filter the opa2684 can provide a very capable gain block for low- power active filters. the dual design lends itself very well to differential active filters. where the filter topology is looking for a simple gain function to implement the filter, the noninverting configuration is preferred to isolate the filter elements from the gain elements in the design. figure 9 shows an example of a very low power 10mhz 3rd-order butterworth low-pass sallen-key filter. often, these filters are designed at an amplifier gain of 1 to minimize amplifier bandwidth interaction with the desired filter shape. since the opa2684 shows minimal bandwidth change with gain, this would not be a constraint in this design. the example of 24 21 18 15 12 9 6 3 frequency (mhz) 1 200 10 100 single to differential conversion gain (db) v i v o 1/2 opa2684 1/2 opa2684 232 ? 50 ? 75pf 22pf 100pf 232 ? 50 ? 100pf 800 ? 20 ? 20 ? 800 ? 5v +5v 357 ? 357 ? 400 ? figure 9 designs the filter for a differential gain of 5 using the opa2684. the resistor values have been adjusted slightly to account for the amplifier bandwidth effects. while this circuit is bipolar, using 5v supplies, it can easily be adapted to single-supply operation. this is typically done by providing a supply midpoint reference at the noninverting inputs then adding dc blocking caps at each input and in series with the amplifier gain resistor, r g . this will add two real zeroes in the response transforming the circuit into a bandpass. figure 10 shows the frequency response for the filter of figure 9. 14 11 8 5 2 1 4 frequency (mhz) 120 10 10mhz, 3rd-order butterworth, low pass, frequency response differential gain (db) figure 10. frequency response for 10mhz, 3rd-order butterworth low-pass filter.
opa2684 18 sbos239b www.ti.com figure 11. single-supply differential adc driver. figure 12. measured harmonic distortion for the circuit of figure 11. single-supply, high gain differential adc driver where a very low power differential i/o interface to a mod- erate performance adc is required, the circuit of figure 11 may be considered. the circuit builds on the inverting differ- ential i/o configuration of figure 6 by adding the input transformer and the output low-pass filter. the input trans- former provides a single-to-differential conversion where the input signal is still very low power it also provides a gain of 2 and removes any common-mode signal from the inputs. this single +5v design sets a midpoint bias from the supply at each of the noninverting inputs. this circuit also includes optional 500 ? pull-down resistors at the output. with a 2.5v dc common-mode operating point (set by v cm ), this will add 5ma to ground in the output stage. this essentially powers up the npn side of the output stage significantly reducing distortion. it is important for good 2nd- order distortion to connect the grounds of these two resistors at the same point to minimize ground plane current for the differential output signal. figure 12 shows the measured 2nd- and 3rd-harmonic distortion for the circuit of figure 11 with and without the pull-down resistors. less than 65dbc distortion is possible through 5mhz with- out the pull-down current while this extends to 10mhz using the two 500 ? pull-down resistors. synthetic impedance dsl line driver the need for very low power dsl line drivers is well sup- ported by the opa2684 with its high (> 100ma) output current, low (< 1.2v) headroom, and low supply current (3.4ma). to further improve power efficiency, simple differ- ential line drivers are often modified to produce a portion of the output impedance through positive feedback. this reduces the voltage swing loss in the remaining discrete matching resistor leaving more of the available voltage swing at the input of the transformer. this typically will allow the transformer turns ratio to be reduced, reducing the peak output current required. all of this together can reduce the power dissipated in the line driver while delivering a low distortion dsl signal to the line. 1/2 opa2684 1/2 opa2684 c l 0.1 f 800 ? 800 ? +5v r s r s 200 ? 200 ? 500 ? adc optional optional 10k ? 10k ? 50 ? source 14.7db noise figure gain = 8v/v 18.1db 1:2 v cm v cm 500 ? 50 60 70 80 90 frequency (mhz) 120 10 distortion vs frequency distortion (dbc) 2vp-p output 3rd-harmonic 2nd-harmonic no pull-down 3rd-harmonic 2nd-harmonic 5ma/ch pull-down see figure 13 for an example design for a +12v single- supply shdsl4 line driver where only 27% of the output impedance is implemented with the physical (18.2 ? ) output resistors with the remaining 73% implemented with positive feedback. this synthetic output impedance circuit feeds back the transformer input voltage to the opposite inverting nodes.
opa2684 19 sbos239b www.ti.com figure 13. synthetic output impedance xdsl driver. board literature part request product package number number OPA2684ID so-8 dem-opa26xu sbou003 OPA2684IDcn sot23-8 dem-opa26xe sbou001 table i. evaluation module ordering information. design-in tools demonstration boards two pc boards are available to assist in the initial evaluation of circuit performance using the opa2684 in its two package styles. both of these are available free as an unpopulated pc board delivered with descriptive documentation. the sum- mary information for these boards is shown in table i. this example takes a 2vp-p maximum differential input to a 12.67vp-p maximum differential voltage on a 135 ? line using a 1:1 transformer. for a nominal line at maximum target power, each output swings a maximum 8vp-p delivering a peak 47ma current, on a 12v supply this leaves 2v head- room on each output with a total amplifier power dissipation of 163mw. figure 14 shows the distortion for a full scale (12.67vp-p on the line) and 1/2 scale sinusoid signal from 100khz to 1mhz. macromodels computer simulation of circuit performance using spice is often useful when analyzing the performance of analog circuits and systems. this is particularly true for higher speed designs where parasitic capacitance and inductance can have a major effect on circuit performance. a spice model for the opa2684 is available in the product folder on the ti web site (www.ti.com). this is the single channel model for the opa684 simply use two of these to implement an opa2684 simulation. these models do a good job of predict- ing small-signal ac and transient performance under a wide variety of operating conditions. they do not do as well in predicting the harmonic distortion or dg/dp characteristics. these models do not attempt to distinguish between the package types in their small-signal ac performance. operating suggestions setting resistor values to optimize bandwidth any current-feedback op amp like the opa2684 can hold high bandwidth over signal-gain settings with the proper adjustment of the external resistor values. a low-power part like the opa4684 typically shows a larger change in band- width due to the significant contribution of the inverting input impedance to loop-gain changes as the signal gain is changed. figure 15 shows a simplified analysis circuit for any current- feedback amplifier. figure 14. harmonic distortion for figure 13. r f v o r g r i z (s) i err i err v i figure 15. current-feedback transfer function analysis circuit. 65 70 75 80 85 90 95 frequency (mhz) 0.1 1 differential distortion vs frequency harmonic distortion (dbc) 3rd-harmonic v l = 6.3vp-p 3rd-harmonic v l = 12.7vp-p 2nd-harmonic v l = 12.7vp-p 2nd-harmonic v l = 6.3vp-p r p 1.07k ? r f 800 ? r o 18.2 ? +12v 1/2 opa2684 1/2 opa2684 r f 800 ? r o 18.2 ? 12.67vp-p 135 ? v 2 max r p 1.07k ? 1:1 2k ? +6v 2k ? +6v r g 931 ? 2vp-p max
opa2684 20 sbos239b www.ti.com the key elements of this current-feedback op amp model are: ? buffer gain from the noninverting input to the inverting input r i ? buffer output impedance i err ? feedback error current signal z(s) ? frequency dependent open-loop transimpedance gain from i err to v o the buffer gain is typically very close to 1.00 and is normally neglected from signal gain considerations. it will, however, set the cmrr for a single op amp differential amplifier configuration. for the buffer gain < 1.0, the cmrr = 20 log(1 ). the closed-loop input stage buffer used in the opa2684 gives a buffer gain more closely approaching 1.00 and this shows up in a slightly higher cmrr than previous current-feedback op amps. r i , the buffer output impedance, is a critical portion of the bandwidth control equation. the opa2684 reduces this element to approximately 4.0 ? using the loop gain of the closed-loop input buffer stage. this significant reduction in output impedance, on very low power, contributes signifi- cantly to extending the bandwidth at higher gains. a current-feedback op amp senses an error current in the inverting node (as opposed to a differential input error volt- age for a voltage-feedback op amp) and passes this on to the output through an internal frequency dependent transimpedance gain. the typical characteristics show this open-loop transimpedance response. this is analogous to the open-loop voltage gain curve for a voltage-feedback op amp. developing the transfer function for the circuit of figure 15 gives equation 1: v v r r rr r r z ng rrng z ng r r o i f g fi f g s fi s f g = + ? ? ? ? ? ? + ++ ? ? ? ? ? ? = + + =+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 1 1 1 1 () () this is written in a loop-gain analysis format where the errors arising from a non-infinite open-loop gain are shown in the denominator. if z(s) were infinite over all frequencies, the denominator of equation 1 would reduce to 1 and the ideal desired signal gain shown in the numerator would be achieved. the fraction in the denominator of equation 1 determines the frequency response. equation 2 shows this as the loop-gain equation. z rrng loop gain s fi () + = if 20 log(r f + ng r i ) were drawn on top of the open-loop transimpedance plot, the difference between the two would be the loop gain at a given frequency. eventually, z(s) rolls off to equal the denominator of equation 2, at which point the loop gain has reduced to 1 (and the curves have intersected). this point of equality is where the amplifier s closed-loop frequency response given by equation 1 will start to roll off, and is exactly analogous to the frequency at which the noise gain equals the open-loop voltage gain for a voltage-feed- back op amp. the difference here is that the total impedance in the denominator of equation 2 may be controlled some- what separately from the desired signal gain (or ng). the opa2684 is internally compensated to give a maximally flat frequency response for r f = 800 ? at ng = 2 on 5v supplies. that optimum value goes to 1.0k ? on a single +5v supply. normally, with a current-feedback amplifier, it is possible to adjust the feedback resistor to hold this band- width up as the gain is increased. the cfb plus architecture has reduced the contribution of the inverting input impedance to provide exceptional bandwidth to higher gains without adjusting the feedback resistor value. the typical character- istics show the small-signal bandwidth over gain with a fixed feedback resistor. putting a closed-loop buffer between the noninverting and inverting inputs does bring some added considerations. since the voltage at the inverting output node is now the output of a locally closed-loop buffer, parasitic external capacitance on this node can cause frequency response peaking for the transfer function from the noninverting input voltage to the inverting node voltage. while it is always important to keep the inverting node capacitance low for any current-feedback op amp, it is critically important for the opa2684. external layout capacitance in excess of 2pf will start to peak the frequency response. this peaking can be easily reduced by then increasing the feedback resistor value but it is prefer- able, from a noise and dynamic range standpoint, to keep that capacitance low, allowing a close to nominal 800 ? feedback resistor for flat frequency response. very high parasitic capacitance values on the inverting node (> 5pf) can possibly cause input stage oscillation that cannot be filtered by a feedback element adjustment. an added consideration is that at very high gains, 2nd-order effects in the inverting output impedance cause the overall response to peak up. if desired, it is possible to retain a flat frequency response at higher gains by adjusting the feed- back resistor to higher values as the gain is increased. since the exact value of feedback that will give a flat frequency response at high gains depends strongly in inverting and output node parasitic capacitance values, it is best to experi- ment in the specific board with increasing values until the desired flatness (or pulse response shape) is obtained. in general, increasing r f (and adjusting r g then to the desired gain) will move towards flattening the response, while de- creasing it will extend the bandwidth at the cost of some peaking. the opa684 data sheet gives an example of this optimization of r f versus gain. output current and voltage the opa2684 provides output voltage and current capabili- ties that can support the needs of driving doubly-terminated 50 ? lines. for a 100 ? load at the gain of +2, (see figure 1), the total load is the parallel combination of the 100 ? load and (1) (2)
opa2684 21 sbos239b www.ti.com the 1.6k ? total feedback network impedance. this 94 ? load will require no more than 40ma output current to support the 3.8v minimum output voltage swing specified for 100 ? loads. this is well under the specified minimum +120/ 90ma specifications over the full temperature range. the specifications described above, though familiar in the industry, consider voltage and current limits separately. in many applications, it is the voltage current, or v-i product, which is more relevant to circuit operation. refer to the output voltage and current limitations plot in the typical characteristics. the x- and y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. the four quadrants give a more detailed view of the opa2684 s output drive capabilities. superimposing resistor load lines onto the plot shows the available output voltage and current for specific loads. the minimum specified output voltage and current over temperature are set by worst-case simulations at the cold temperature extreme. only at cold startup will the output current and voltage decrease to the numbers shown in the electrical characteristic tables. as the output transistors deliver power, their junction temperatures will increase, de- creasing their v be s (increasing the available output voltage swing) and increasing their current gains (increasing the available output current). in steady-state operation, the avail- able output voltage and current will always be greater than that shown in the over-temperature specifications since the output stage junction temperatures will be higher than the minimum specified operating ambient. to maintain maximum output stage linearity, no output short- circuit protection is provided. this will not normally be a problem since most applications include a series matching resistor at the output that will limit the internal power dissipa- tion if the output side of this resistor is shorted to ground. however, shorting the output pin directly to the adjacent positive power-supply pin (8 pin packages) can destroy the amplifier. if additional short-circuit protection is required, consider a small-series resistor in the power-supply leads. this will, under heavy output loads, reduce the available output voltage swing. a 5 ? series resistor in each power- supply lead will limit the internal power dissipation to less than 1w for an output short-circuit, while decreasing the available output voltage swing only 0.25v for up to 50ma desired load currents. always place the 0.1 f power-supply decoupling capacitors after these supply current limiting resistors directly on the supply pins. driving capacitive loads one of the most demanding and yet very common load conditions for an op amp is capacitive loading. often, the capacitive load is the input of an adc, including additional external capacitance which may be recommended to im- prove adc linearity. a high-speed, high open-loop gain amplifier like the opa2684 can be very susceptible to de- creased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. when the amplifier s open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. several external solutions to this problem have been suggested. when the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. this does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. the additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability. the typical characteristics show the recommended r s vs c load and the resulting frequency response at the load. the 1k ? resistor shown in parallel with the load capacitor is a measurement path and may be omitted. the required series resistor value may be reduced by increasing the feedback resistor value from its nominal recommended value. this will increase the phase margin for the loop gain, allowing a lower series resistor to be effective in reducing the peaking due capacitive load. spice simulation can be effectively used to optimize this approach. parasitic capacitive loads greater than 5pf can begin to degrade the performance of the opa2684. long pc board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. always consider this effect carefully, and add the recommended series resistor as close as possible to the opa2684 output pin (see board layout guidelines). distortion performance the opa2684 provides very low distortion in a low-power part. the cfb plus architecture also gives two significant areas of distortion improvement. first, in operating regions where the 2nd-harmonic distortion due to output stage nonlinearities is very low (frequencies < 1mhz, low output swings into light loads) the linearization at the inverting node provided by the cfb plus design gives 2nd-harmonic distor- tions that extend into the 90dbc region. previous current- feedback amplifiers have been limited to approximately 85dbc due to the nonlinearities at the inverting input. the second area of distortion improvement comes in a distortion performance that is largely gain independent. to the extent that the distortion at a particular output power is output stage dependent, 3rd-harmonics particularly, and to a lesser ex- tend 2nd-harmonic distortion, is constant as the gain is increased. this is due to the constant loop gain versus signal gain provided by the cfb plus design. as shown in the typical characteristics, while the 3rd-harmonic is constant with gain, the 2nd-harmonic degrades at higher gains. this is largely due to board parasitic issues. slightly imbalanced load return currents will couple into the gain resistor to cause a portion of the 2nd-harmonic distortion. at high gains, this imbalance has more gain to the output giving increased 2nd-harmonic distortion. relative to alternative amplifiers with < 2ma supply current, the opa2684 holds much lower distortion at higher frequen- cies (> 5mhz) and to higher gains. generally, until the fundamental signal reaches very high frequency or power levels, the 2nd-harmonic will dominate the distortion with a
opa2684 22 sbos239b www.ti.com lower 3rd-harmonic component. focusing then on the 2nd- harmonic, increasing the load impedance improves distortion directly. remember that the total load includes the feedback network in the noninverting configuration (see figure 1) this is the sum of r f + r g , while in the inverting configuration it is just r f . also, providing an additional supply decoupling capacitor (0.1 f) between the supply pins (for bipolar opera- tion) improves the 2nd-order distortion slightly (3db to 6db). in most op amps, increasing the output voltage swing in- creases harmonic distortion directly. a low-power part like the opa2684 includes quiescent boost circuits to provide the full-power bandwidth shown in the typical characteristics. these act to increase the bias in a very linear fashion only when high slew rate or output power are required. this also acts to actually reduce the distortion slightly at higher output power levels. the typical characteristics show the 2nd- harmonic holding constant from 500mvp-p to 5vp-p outputs while the 3rd-harmonics actually decrease with increasing output power. the opa2684 has an extremely low 3rd-order harmonic distortion, particularly for light loads and at lower frequen- cies. this also gives low 2-tone, 3rd-order intermodulation distortion as shown in the typical characteristics. since the opa2684 includes internal power boost circuits to retain good full-power performance at high frequencies and out- puts, it does not show a classical 2-tone, 3rd-order intermodulation intercept characteristic. instead, it holds rela- tively low and constant 3rd-order intermodulation spurious levels over power. the typical characteristics show this spurious level as a dbc below the carrier at fixed center frequencies swept over single-tone power at a matched 50 ? load. these spurious levels drop significantly (> 12db) for lighter loads than the 100 ? used in that plot. converter inputs for instance will see 82dbc 3rd-order spurious to 10mhz for full-scale inputs. for even lower 3rd-order intermodulation distortion to much higher frequencies, consider the opa2691. noise performance wideband current-feedback op amps generally have a higher output noise than comparable voltage-feedback op amps. the opa2684 offers an excellent balance between voltage and current noise terms to achieve low output noise in a low power amplifier. the inverting current noise (17pa/ hz ) is lower most other current-feedback op amps while the input voltage noise (3.7nv/ hz ) is lower than any unity-gain stable, comparable slew rate, voltage-feedback op amp. this low input voltage noise was achieved at the price of higher noninverting input current noise (9.4pa/ hz ). as long as the ac source impedance looking out of the noninverting node is less than 200 ? , this current noise will not contribute signifi- cantly to the total output noise. the op amp input voltage noise and the two input current noise terms combine to give low output noise under a wide variety of operating conditions. figure 16 shows the op amp noise analysis model with all the noise terms included. in this model, all noise terms are taken to be noise voltage or current density terms in either nv/ hz or pa/ hz . the total output spot noise voltage can be computed as the square root of the sum of all squared output noise voltage contributors. equation 3 shows the general form for the output noise voltage using the terms shown in figure 16. (3) e e i r ktr ng i r ktr ng o ni bn ss bi f f =+ ( ) + ? ? ? ? + ( ) + 2 2 2 2 44 dividing this expression by the noise gain (ng = (1 + r f /r g )) will give the equivalent input referred spot noise voltage at the noninverting input as shown in equation 4. (4) e e i r ktr ir ng ktr ng nnibn ss bi f f =+ ( ) ++ ? ? ? ? ? ? + 2 2 2 4 4 evaluating these two equations for the opa2684 circuit and component values (see figure 1) will give a total output spot noise voltage of 16.3nv/ hz and a total equivalent input spot noise voltage of 8.2 nv/ hz . this total input referred spot noise voltage is higher than the 3.7nv/ hz specification for the op amp voltage noise alone. this reflects the noise added to the output by the inverting current noise times the feedback resistor. as the gain is increased, this fixed output noise power term contributes less to the total output noise and the total input referred voltage noise given by equation 4 will approach just the 3.7nv/ hz of the op amp itself. for example, going to a gain of +20 in the circuit of figure 1, adjusting only the gain resistor to 42.1 ? , will give a total input referred noise of 3.9nv/ hz . a more complete description of op amp noise analysis can be found in ti application note ab-103, noise analysis for high-speed op amps (sboa066), located at www.ti.com. dc accuracy and offset control a current-feedback op amp like the opa2684 provides exceptional bandwidth in high gains, giving fast pulse settling but only moderate dc accuracy. the electrical characteris- tics show an input offset voltage comparable to high slew rate voltage-feedback amplifiers. the two input bias currents, 4kt r g r g r f r s opa681 i bi e o i bn 4kt = 1.6e 20j at 290 k e rs e ni 4 ktr s 4ktr f figure 16. op amp noise analysis model.
opa2684 23 sbos239b www.ti.com however, are somewhat higher and are unmatched. whereas bias current cancellation techniques are very effective with most voltage-feedback op amps, they do not generally re- duce the output dc offset for wideband current-feedback op amps. since the two input bias currents are unrelated in both magnitude and polarity, matching the source impedance looking out of each input to reduce their error contribution to the output is ineffective. evaluating the configuration of figure 1, using worst-case +25 c input offset voltage and the two input bias currents, gives a worst-case output offset range equal to: (ng v os ) + (i bn r s /2 ng) (i bi r f ) where ng = noninverting signal gain = (2 3.8mv) (11 a 25 ? 2) (800 ? 17ma) = 7.6mv + 0.55mv 13.6mv = 21.75mv while the last term, the inverting bias current error, is dominant in this low-gain circuit, the input offset voltage will become the dominant dc error term as the gain exceeds 5v/v. where improved dc precision is required in a high- speed amplifier, consider the opa656 single and opa2822 dual voltage-feedback amplifiers. thermal analysis the opa2684 will not require external heatsinking for most applications. maximum desired junction temperature will set the maximum allowed internal power dissipation as de- scribed below. in no case should the maximum junction temperature be allowed to exceed 175 c. operating junction temperature (t j ) is given by t a + p d ja . the total internal power dissipation (p d ) is the sum of quiescent power (p dq ) and additional power dissipated in the output stage (p dl ) to deliver load power. quiescent power is simply the specified no-load supply current times the total supply voltage across the part. p dl will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to 1/2 of either supply voltage (for equal bipolar supplies). under this condition p dl = v s 2 /(4 r l ) where r l includes feedback network loading. note that it is the power in the output stage and not into the load that determines internal power dissipation. as an absolute worst-case example, compute the maximum t j using an OPA2684IDcn (sot23-8 package) in the circuit of figure 1 operating at the maximum specified ambient temperature of +85 c with both outputs driving a grounded 100 ? load to 2.5v dc . p d = 10v 3.9ma + 2 (5 2 /(4 (100 ? || 1.6k ? ))) = 172mw maximum t j = +85 c + (0.172w 150 c/w) = 111 c this maximum operating junction temperature is well below most system level targets. most applications will be lower than this since an absolute worst-case output stage power in both channels simultaneously was assumed in this calculation. board layout guidelines achieving optimum performance with a high-frequency am- plifier like the opa2684 requires careful attention to board layout parasitics and external component types. recommen- dations that will optimize performance include: a) minimize parasitic capacitance to any ac ground for all of the signal i/o pins. parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. to re- duce unwanted capacitance, a window around the sig- nal i/o pins should be opened in all of the ground and power planes around those pins. otherwise, ground and power planes should be unbroken elsewhere on the board. b) minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1 f decoupling capacitors. at the device pins, the ground and power-plane layout should not be in close proximity to the signal i/o pins. avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capaci- tors. the power-supply connections should always be decoupled with these capacitors. an optional supply de- coupling capacitor (0.01 f) across the two power sup- plies (for bipolar operation) will improve 2nd-harmonic distortion performance. larger (2.2 f to 6.8 f) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. these may be placed somewhat farther from the device and may be shared among several devices in the same area of the pc board. c) careful selection and placement of external compo- nents will preserve the high -frequency performance of the opa2684. resistors should be a very low reac- tance type. surface-mount resistors work best and allow a tighter overall layout. metal film and carbon composi- tion axially-leaded resistors can also provide good high- frequency performance. again, keep their leads and pc- board trace length as short as possible. never use wirewound type resistors in a high-frequency applica- tion. since the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. other network compo- nents, such as noninverting input termination resistors, should also be placed close to the package. the fre- quency response is primarily determined by the feed- back resistor value as described previously. increasing its value will reduce the peaking at higher gains, while decreasing it will give a more peaked frequency re- sponse at lower gains. the 800 ? feedback resistor used in the electrical characteristics at a gain of +2 on 5v supplies is a good starting point for design. note that an 800 ? feedback resistor, rather than a direct short, is required for the unity-gain follower application. a cur- rent-feedback op amp requires a feedback resistor even in the unity-gain follower configuration to control stability.
opa2684 24 sbos239b www.ti.com figure 17. internal esd protection. d) connections to other wideband devices on the board may be made with short direct traces or through on- board transmission lines. for short connections, con- sider the trace and the input to the next device as a lumped capacitive load. relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. estimate the total capacitive load and set r s from the plot of recom- mended rs vs c load . low parasitic capacitive loads (< 5pf) may not need an r s since the opa2684 is nominally compensated to operate with a 2pf parasitic load. if a long trace is required, and the 6db signal loss intrinsic to a doubly-terminated transmission line is ac- ceptable, implement a matched impedance transmis- sion line using microstrip or stripline techniques (consult an ecl design handbook for microstrip and stripline layout techniques). a 50 ? environment is normally not necessary on board, and in fact a higher impedance environment will improve distortion, as shown in the distortion versus load plots. with a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the opa2684 is used, as well as a terminating shunt resistor at the input of the destina- tion device. remember also that the terminating imped- ance will be the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. the high output voltage and current capability of the opa2684 allows multiple destination devices to be handled as separate transmission lines, each with their own series and shunt terminations. if the 6db attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. treat the trace as a capacitive load in this case and set the series resistor value as shown in the plot of rs vs c load . this will not preserve signal integrity as well as a doubly-terminated line. if the input impedance of the destination device is low, there will be some signal attenuation due to the voltage divider formed by the series output into the terminating imped- ance. e) socketing a high-speed part like the opa2684 is not recommended . the additional lead length and pin-to- pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable fre- quency response. best results are obtained by soldering the opa2684 onto the board. input and esd protection the opa2684 is built using a very high-speed complemen- tary bipolar process. the internal junction breakdown volt- ages are relatively low for these very small geometry de- vices. these breakdowns are reflected in the absolute maxi- mum ratings table where an absolute maximum 13v across the supply pins is reported. all device pins have limited esd protection using internal diodes to the power supplies as shown in figure 17. these diodes provide moderate protection to input overdrive voltages above the supplies as well. the protection diodes can typically support 30ma continuous current. where higher currents are possible (e.g., in systems with 15v supply parts driving into the opa2684), current-limiting series resistors should be added into the two inputs. keep these resistor values as low as possible since high values degrade both noise performance and frequency response. external pin +v cc v cc internal circuitry
opa2684 25 sbos239b www.ti.com package drawings d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 C 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
opa2684 26 sbos239b www.ti.com package drawings (cont.) dcn (r-pdso-g8) plastic small-outline c 4202106/a 03/01 3,00 2,80 3,00 2,60 1,50 1,75 area 0,28 0,45 0 C 10 0,09 0,20 1,30 0,90 0,10 0,60 index 0,00 0,15 C a C 0,65 0,90 1,45 1,95 ref notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. foot length measured reference to flat foot surface parallel to datum a. d. package outline exclusive of mold flash, metal burr and dambar protrusion/intrusion. e. package outline inclusive of solder plating. f. a visual index feature must be located within the cross-hatched area.
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