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intel ? 860 chipset: 82860 memory controller hub (mch) datasheet may 2001 document number: 290713-001 r
r 2 intel ? 82860 mch datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel?s terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel? 82860 memory controller hub may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. i 2 c is a two-wire communications bus/protocol developed by philips. smbus is a subset of the i 2 c bus/protocol and was developed by intel. implementations of the i 2 c bus/protocol may require licenses from various entities, including philips electronics n.v. and north american philips corporation. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed by calling 1-800-548-4725 or by visiting intel?s website at http:// www.intel.com. intel and intel xeon are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2001, intel corporation
r intel ? 82860 mch datasheet 3 contents 1 introduction ................................................................................................................... .....13 1.1 terminology ..........................................................................................................13 1.2 reference documents ..........................................................................................15 1.3 intel ? 860 chipset system architecture ................................................................16 1.4 intel ? 82860 mch overview .................................................................................18 1.4.1 processor interface ...............................................................................19 1.4.2 memory interface ..................................................................................20 1.4.3 agp interface........................................................................................22 1.4.4 hub interface_a ....................................................................................22 1.4.5 hub interface_b and hub interface_c ..................................................23 1.4.6 mch clocking .......................................................................................23 1.4.7 system interrupts ..................................................................................24 1.4.8 powerdown flow ...................................................................................24 2 signal description............................................................................................................. .25 2.1 host interface signals...........................................................................................27 2.2 rambus* channel a .............................................................................................30 2.3 rambus* channel b .............................................................................................31 2.4 hub interface_a signals .......................................................................................32 2.5 hub interface_b ....................................................................................................32 2.6 hub interface_c....................................................................................................32 2.7 agp interface signals...........................................................................................33 2.7.1 agp addressing signals .......................................................................33 2.7.2 agp flow control signals .....................................................................34 2.7.3 agp status signals ...............................................................................34 2.7.4 agp strobes .........................................................................................35 2.7.5 agp/pci signals-semantics .................................................................36 2.8 clocks, reset, and miscellaneous ........................................................................39 2.9 voltage references, pll power...........................................................................40 2.10 strap signals.........................................................................................................41 2.11 pin states during reset ........................................................................................41 3 register description ..........................................................................................................4 5 3.1 register terminology............................................................................................45 3.2 pci configuration space access..........................................................................46 3.3 i/o mapped registers ...........................................................................................49 3.3.1 conf_addr?configuration address register ..................................49 3.3.2 conf_data?configuration data register.........................................50 3.4 host-hub interface_a bridge device registers (device 0) .................................51 3.4.1 vid?vendor identification register (device 0) ....................................53 3.4.2 did?device identification register (device 0).....................................53 3.4.3 pcicmd?pci command register (device 0) .....................................54 3.4.4 pcists?pci status register (device 0).............................................55 3.4.5 rid?revision identification register (device 0)..................................56
r 4 intel ? 82860 mch datasheet 3.4.6 subc?sub-class code register (device 0).......................................56 3.4.7 bcc?base class code register (device 0)........................................56 3.4.8 mlt?master latency timer register (device 0) .................................57 3.4.9 hdr?header type register (device 0) ..............................................57 3.4.10 apbase?aperture base configuration register (device 0) ...............57 3.4.11 svid?subsystem vendor id register (device 0)................................58 3.4.12 sid?subsystem id register (device 0)...............................................59 3.4.13 capptr?capabilities pointer register (device 0) .............................59 3.4.14 gar[0:15]?rdram* device group architecture register (device 0) 60 3.4.15 mchcfg?mch configuration register (device 0).............................61 3.4.16 fdhc?fixed dram hole control register (device 0)........................63 3.4.17 pam[0:6]?programmable attribute map registers (device 0) ...........63 3.4.18 gba[0:15]?rdram* device group boundary address register (device 0) ..............................................................................................67 3.4.19 rdps?rdram* device pool sizing register (device 0)....................68 3.4.20 drd?rdram* device register data register (device 0)..................69 3.4.21 ricm?rdram* device initialization control management register (device 0) ..............................................................................................69 3.4.22 smram?system management ram control register (device 0) .....71 3.4.23 esmramc?extended system management ram control register (device 0) ..............................................................................................72 3.4.24 acapid?agp capability identifier register (device 0).......................73 3.4.25 agpstat?agp status register (device 0) .......................................74 3.4.26 agpcmd?agp command register (device 0)..................................75 3.4.27 agpctrl ? agp control register.......................................................76 3.4.28 apsize?aperture size (device 0) .......................................................76 3.4.29 attbase?aperture translation table base register (device 0)......77 3.4.30 amtt?agp interface multi-transaction timer register (device 0) ...77 3.4.31 lptt?low priority transaction timer register (device 0) .................78 3.4.32 rdtr?rdram* device timing register (device 0) ..........................79 3.4.33 tom?top of low memory register (device 0) ...................................80 3.4.34 errsts?error status register (device 0) .........................................81 3.4.35 errcmd?error command register (device 0) .................................83 3.4.36 smicmd?smi command register (device 0) ....................................85 3.4.37 scicmd?sci command register (device 0) .....................................86 3.4.38 dramrc?rdram* device refresh control register (device 0) ......86 3.4.39 skpd?scratchpad data (device 0).....................................................88 3.4.40 derrctl_sts?dram error control/status register (device 0) ....88 3.4.41 eap?error address pointer register (device 0) .................................89 3.4.42 misc_cntl?miscellaneous control register (device 0) ...................89 3.5 agp bridge registers (device 1) .........................................................................90 3.5.1 vid1?vendor identification register (device 1) ..................................91 3.5.2 did1?device identification register (device 1)...................................91 3.5.3 pcicmd1?pci-pci command register (device 1)............................92 3.5.4 pcists1?pci-pci status register (device 1)....................................93 3.5.5 rid1?revision identification register (device 1)................................94 3.5.6 subc1?sub-class code register (device 1).....................................94 3.5.7 bcc1?base class code register (device 1)......................................94 3.5.8 mlt1?master latency timer register (device 1) ...............................95 3.5.9 hdr1?header type register (device 1) ............................................95 3.5.10 pbusn1?primary bus number register (device 1) ...........................95 3.5.11 sbusn1?secondary bus number register (device 1) ......................96 3.5.12 subusn1?subordinate bus number register (device 1)..................96 3.5.13 smlt1?secondary master latency timer register (device 1) .........97
r intel ? 82860 mch datasheet 5 3.5.14 iobase1?i/o base address register (device 1) ...............................98 3.5.15 iolimit1?i/o limit address register (device 1) ................................98 3.5.16 ssts1?secondary pci-pci status register (device 1) .....................99 3.5.17 mbase1?memory base address register (device 1) ......................100 3.5.18 mlimit1?memory limit address register (device 1) .......................101 3.5.19 pmbase1?prefetchable memory base address register (device 1) ............................................................................................102 3.5.20 pmlimit1?prefetchable memory limit address register (device 1)103 3.5.21 bctrl1?pci-pci bridge control register (device 1) ......................104 3.5.22 errcmd1?error command register (device 1) .............................105 3.6 hub interface_b bridge registers (device 2) .....................................................106 3.6.1 vid2?vendor identification register (device 2) ................................107 3.6.2 did2?device identification register (device 2).................................107 3.6.3 pcicmd2?pci-pci command register (device 2)..........................108 3.6.4 pcists2?pci-pci status register (device 2)..................................109 3.6.5 rid2?revision identification register (device 2)..............................110 3.6.6 subc2?sub-class code register (device 2)...................................110 3.6.7 bcc2?base class code register (device 2)....................................110 3.6.8 mlt2?master latency timer register (device 2) .............................111 3.6.9 hdr2?header type register (device 2) ..........................................111 3.6.10 pbusn2?primary bus number register (device 2) .........................111 3.6.11 sbusn2?secondary bus number register (device 2) ....................112 3.6.12 subusn2?subordinate bus number register (device 2)................112 3.6.13 smlt2?secondary master latency timer register (device 2) .......112 3.6.14 iobase2?i/o base address register (device 2) .............................113 3.6.15 iolimit2?i/o limit address register (device 2) ..............................113 3.6.16 ssts2?secondary pci-pci status register (device 2) ...................114 3.6.17 mbase2?memory base address register (device 2) ......................115 3.6.18 mlimit2?memory limit address register (device 2) .......................116 3.6.19 pmbase2?prefetchable memory base address register (device 2) ............................................................................................117 3.6.20 pmlimit2?prefetchable memory limit address register (device 2)118 3.6.21 bctrl2?pci-pci bridge control register (device 2) ......................119 3.6.22 errcmd2?error command register (device 2) .............................121 3.7 hub interface_c bridge registers (device 3).....................................................122 3.7.1 vid3?vendor identification register (device 3) ................................123 3.7.2 did3?device identification register (device 3).................................123 3.7.3 pcicmd3?pci-pci command register (device 3)..........................124 3.7.4 pcists3?pci-pci status register (device 3)..................................125 3.7.5 rid3?revision identification register (device 3)..............................126 3.7.6 subc3?sub-class code register (device 3)...................................126 3.7.7 bcc3?base class code register (device 3)....................................126 3.7.8 mlt3?master latency timer register (device 3) .............................127 3.7.9 hdr3?header type register (device 3) ..........................................127 3.7.10 pbusn3?primary bus number register (device 3) .........................127 3.7.11 sbusn3?secondary bus number register (device 3) ....................128 3.7.12 subusn3?subordinate bus number register (device 3)................128 3.7.13 smlt3?secondary master latency timer register (device 3) .......128 3.7.14 iobase3?i/o base address register (device 3) .............................129 3.7.15 iolimit3?i/o limit address register (device 3) ..............................129 3.7.16 ssts3?secondary pci-pci status register (device 3) ...................130 3.7.17 mbase3?memory base address register (device 3) ......................131 3.7.18 mlimit3?memory limit address register (device 3) .......................132
r 6 intel ? 82860 mch datasheet 3.7.19 pmbase3?prefetchable memory base address register (device 3) ............................................................................................133 3.7.20 pmlimit3?prefetchable memory limit address register (device 3)134 3.7.21 bctrl3?pci-pci bridge control register (device 3) ......................135 3.7.22 errcmd3?error command register (device 3) .............................137 4 system address map.......................................................................................................139 4.1 memory address ranges ...................................................................................139 4.1.1 vga and mda memory space............................................................142 4.1.2 pam memory spaces..........................................................................143 4.1.3 isa hole memory space .....................................................................143 4.1.4 tseg smm memory space ................................................................144 4.1.5 i/o apic memory space .....................................................................144 4.1.6 system bus interrupt memory space..................................................144 4.1.7 high smm memory space...................................................................144 4.1.8 agp aperture space (device 0 bar) .................................................145 4.1.9 agp memory and prefetchable memory.............................................145 4.1.10 hub interface_b memory and prefetchable memory ..........................145 4.1.11 hub interface_c memory and prefetchable memory..........................145 4.1.12 hub interface_a subtractive decode ..................................................146 4.2 agp memory address ranges...........................................................................146 4.2.1 agp dram graphics aperture ...........................................................146 4.3 system management mode (smm) memory range...........................................147 4.3.1 smm space definition .........................................................................147 4.3.2 smm space restrictions .....................................................................148 4.4 i/o address space..............................................................................................148 4.5 mch decode rules and cross-bridge address mapping ..................................149 4.5.1 hub interface_a decode rules...........................................................149 4.5.2 hub interface_b decode rules...........................................................149 4.5.3 hub interface_c decode rules...........................................................149 4.5.4 agp interface decode rules ..............................................................150 5 memory interface.............................................................................................................15 1 5.1 direct rdram* device organization and configuration ....................................154 5.1.1 rules for populating direct rdram* devices ....................................154 5.1.2 direct rdram* device cmos signals ...............................................156 5.1.3 direct rdram* device core refresh .................................................158 5.2 direct rdram* device command encoding .....................................................158 5.2.1 row packet (rowa/rowr)..............................................................158 5.2.2 column packet (colc/colx)............................................................160 5.2.3 data packet.........................................................................................162 5.3 direct rdram* device register programming..................................................162 5.4 direct rdram* device operating states ...........................................................162 5.5 direct rdram* device operating pools ............................................................164 5.6 direct rdram* device power management......................................................164 5.7 data integrity.......................................................................................................165 5.8 direct rdram* device array thermal management .........................................166 6 electrical characteristics .................................................................................................167 6.1 absolute maximum ratings ................................................................................167 6.2 thermal characteristics......................................................................................168
r intel ? 82860 mch datasheet 7 6.3 power characteristics .........................................................................................168 6.4 i/o interface signal groupings............................................................................169 6.5 dc characteristics ..............................................................................................171 7 ballout and package information.....................................................................................177 7.1.1 ballout information ..............................................................................177 7.2 intel ? 82860 mch package information .............................................................191 7.3 chipset interface trace length compensation ..................................................192 7.3.1 mch rsl trace length compensation..............................................193 7.3.1.1 mch rsl normalized trace length data.........................194 7.3.2 mch system bus signal normalized trace length data ...................195 7.3.3 mch 16-bit hub interface normalized trace length..........................197 7.3.3.1 mch 16-bit hub interface_b normalized trace length data........................................................................197 7.3.3.2 mch 16-bit hub interface_c normalized trace length data........................................................................198 8 testability.................................................................................................................... .....199 8.1 xor test mode initialization ..............................................................................200 8.2 xor chains ........................................................................................................200
r 8 intel ? 82860 mch datasheet figures figure 1. intel ? 860 chipset system block diagram .........................................................17 figure 2. mch signal diagram..........................................................................................26 figure 3. pam register attribute bits ................................................................................65 figure 4. system address map .......................................................................................139 figure 5. detailed dos compatible area address map .................................................140 figure 6. detailed extended memory range address map ............................................141 figure 7. single channel-pair mode................................................................................152 figure 8. multiple channel-pair mode .............................................................................153 figure 9. direct rdram* devices sideband cmos signal configuration on rambus* channel a.................................................................................................................156 figure 10. mch ballout with agp and hub interface ball names (top view ? left side) ............................................................................................178 figure 11. mch ballout with agp and hub interface ball names (top view ? right side) ..........................................................................................179 figure 12. mch ballout topside view (looking through the top of the package) ............180 figure 13. mch package dimensions ............................................................................191 figure 14. xor-tree chain (high level view) ...............................................................199
r intel ? 82860 mch datasheet 9 tables table 1. maximum memory supported .............................................................................20 table 2. supported direct rdram* devices ....................................................................21 table 3. mch processor system bus-to-rac ratio.........................................................23 table 4. mch processor-to-agp/hub interface ratio ......................................................24 table 5. pin states during reset .......................................................................................42 table 6. mch configuration space (device 0) .................................................................51 table 7. pam registers.....................................................................................................65 table 8. valid trcd and tcac combinations for 300 mhz and 400 mhz .........................79 table 9. mch configuration space (device 1) .................................................................90 table 10. mch configuration space (device 2) .............................................................106 table 11. mch configuration space (device 3) .............................................................122 table 12. smm space address ranges .........................................................................147 table 13. direct rdram* device grouping....................................................................155 table 14. sideband cmos signal description................................................................156 table 15. cmd signal value decode ..............................................................................157 table 16. rowa packet for activating (sensing) a row (i.e., av = 1) ...........................159 table 17. rowr packet for other operations (i.e., av = 0) ..........................................159 table 18. row packet encodings....................................................................................160 table 19. colc packet...................................................................................................161 table 20. colc packet field encodings ........................................................................161 table 21. colm packet and colx packet field encodings..........................................162 table 22. data packet .....................................................................................................162 table 23. dram operating states ..................................................................................163 table 24. direct rdram* device power management states .......................................164 table 25. absolute maximum ratings.............................................................................167 table 26. intel ? 860 chipset package thermal resistance............................................168 table 27. dc characteristics functional operating range (vcc1_8 = 1.8v 5%; tdie = 110 c) ..........................................................................................................168 table 28. signal groups ..................................................................................................169 table 29. dc characteristics at vcc1_8 = 1.8v 5% ....................................................171 table 30. mch alphabetical ballout list .........................................................................181 table 31. example nominalization table ........................................................................192 table 32. mch ? l pkg data for rambus* channel a and rambus channel b ................194 table 33. mch system bus signal normalized trace length data per group ..............195 table 34. mch system bus signal normalized trace length data per group ..............196 table 35. mch 16-bit hub interface_b signal normalized trace length data ..............197 table 36. mch 16-bit hub interface_c signal normalized trace length data..............198 table 37. xor chain 1 ...................................................................................................200 table 38. xor chain 2 ...................................................................................................202 table 39. xor chain 3 ...................................................................................................204 table 40. xor chain 4 ...................................................................................................205 table 41. xor chain 5 ...................................................................................................207 table 42. xor chain 6 ...................................................................................................208 table 43. xor chain 7 ...................................................................................................210 table 44. xor chain 8 ...................................................................................................211
r 10 intel ? 82860 mch datasheet revision history revision number description revision date -001 initial release. may 2001
r intel ? 82860 mch datasheet 11 intel ? 82860 mch features supports intel ? xeon? processors ? 100 mhz system bus ? 200 mhz address bus ? 400 mhz data bus ? system bus interrupt delivery ? agtl+ bus driver technology with integrated agtl termination resistors direct rdram* device support ? two rambus* channels operating in lock- step at 300 mhz and 400 mhz ? maximum memory bandwidth of 3.2 gb/s ? 128-/144-mb (1-kb page size) and 256-/288-mb (2-kb page size) direct rdram device densities ? supports a maximum memory address decode space of 16 gb ? maximum memory -1 gb using 128-/144-mb direct rdram devices -2 gb using 256-/288-mb direct rdram devices -4 gb using two intel ? 82803aa mrh-rs ? up to 8 simultaneous open pages ? direct rdram device subsystem thermal management ? ecc operation (single-bit error correction and multiple-bit error detection) hub interface_a to ich2 ? 266 mb/s point-to-point hub interface to ich2 with parity ? interrupt related messages ? power management events as messages ? smi, sci, and serr error indication messages ? supports normal and enhanced termination modes hub interface_b and hub interface_c ? 533 mb/s point-to-point 16-bit hub interfaces with parity ? 66 mhz base clock running 4x ( 533mb/s) data transfers ? 36-bit addressing on inbound transactions only (maximum 16-gb memory decode space) accelerated graphics port (agp) interface ? supports a single agp device (either via a connector or on the motherboard) ? supports agp 2.0 including 4x agp data transfers and 2x/4x fast write protocol ? 1.5 v agp signaling levels ? 32 deep agp request queue ? agp address translation mechanism with integrated fully associative 20 entry tlb ? delayed transaction support for agp-to- dram frame# semantic reads system interrupts ? supports only system bus interrupt delivery mechanism ? supports interrupts signaled as upstream memory writes from hub interface_a?c ? supports peer msi between hub interface_a?c ? provides redirection for ipi and upstream interrupts to the system bus power management ? smram space remapping to a0000h ? supports extended smram space above 256 mb, additional tseg from top of low memory ? smram accesses from agp or hub interfaces are not allowed ? pc99/2001 suspend to dram support ? acpi rev 1.0 compliant power management ? apm rev 1.2 compliant power management package ? 42.5 x 42.5 mm 1012olga i/o device support ? ich2 ? intel ? p64h (16-bit hub interface-to- optional 64-bit/66 mhz pci bus hub)
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introduction r intel ? 82860 mch datasheet 13 1 introduction the intel ? 860 chipset is a high-bandwidth chipset designed for workstation platforms based on the intel ? xeon? processor. the chipset contains two main components and additional optional components that provide expansion capability. the intel ? 82860 memory controller hub (mch) provides the chipset?s system bus interface, memory controller, agp interface, hub interface for i/o, and two hub interface ports for pci bus expansion. this document describes the intel 82860 memory controller hub (mch). section 1.3, intel ? 860 chipset system architecture, provides an overview of each of the components of the intel 860 chipset. 1.1 terminology term description agp accelerated graphics port. the mch contains an agp that supports agp 2.0 compliant components only with 1.5 v signaling level. pipe# and sba addressing cycles and their associated data phases are generally referred to as agp transactions. frame# cycles over the agp bus are generally referred to as agp/pci transactions. core the internal base logic in the mch. dbi dynamic bus inversion dp dual-processor full reset a full mch reset is defined in this document when rstin# is asserted. gart graphics aperture re-map table. table in memory containing the page re-map information used during agp aperture address translations. gtlb graphics translation look-aside buffer. a cache used to store frequently used gart entries. host this term is used synonymously with processor. hub interface_a the proprietary hub interface that ties the mch to the ich2. in this document hub interface cycles originating from or destined for the primary pci interface on the ich2 is generally referred to as hub interface_a cycles. hub interface_b and hub interface_c the proprietary hub interface that ties the mch to the intel p64h. cycles originating from or destined for any target on one of these hub interfaces are described as hub interface_b and hub interface_c cycles respectively. ich2 intel ? 82801ba i/o controller hub (ich2). the i/o controller hub component that contains the primary pci interface, lpc interface, usb, ata-100, ac?97, and other i/o functions. it communicates with the mch over a proprietary interface called hub interface_a. ipi inter processor interrupt mch the memory controller hub component that contains the processor interface, dram controller, and agp interface. it communicates with the i/o controller hub (ich2) and other i/o controller hubs over proprietary interfaces called the hub interface.
introduction r 14 intel ? 82860 mch datasheet term description intel ? mrh-r the memory repeater hub (for direct rdram* devices) component that allows the system to expand the number of available rambus* channels. each intel mrh-r connects one primary rambus channel to two subordinate rambus channels . msi message signaled interrupts. msi allows a device to request interrupt service via a standard memory write transaction instead of through a hardware signal. normal vs enhanced mode the normal routing distance for a hub interface is a few inches. enhanced mode allows the user the flexibility to have the hub interface farther apart. intel ? p64h the bus controller hub component that has a 16-bit hub interface on its primary side and a configurable 64-bit, 66 mhz pci interface on the secondary side. it connects to any one of the intel 82860 mch?s 16-bit hub interfaces. pci_a the physical pci bus that is driven directly by the ich2 component. it supports 5 v, 32-bit, 33 mhz pci 2.2 compliant components. communication between pci_a and the mch occurs over hub interface_a. note: even though it is referred to as pci_a it is not pci bus #0 from a configuration standpoint. rac rambus* asic cell. the rac is a library macrocell used in asic controller designs to interface the core logic of a cmos asic device to the rambus channel. it is the embedded cell designed by rambus that interfaces with the direct rdram* devices using rsl signaling. the rac communicates with the rmc. rmc rambus* memory controller. the rmc is a block of digital logic residing on a rambus-based controller ic to drive and manage the memory transactions of a rambus memory system. this is the logic that directly interfaces to the rac. rsl rambus signaling level. rsl is a multi-drop, bidirectional bus connection signaling technology. operating up to a ghz transfer rate, rsl uses low swing signaling, a common reference voltage and precise clocking to transfer two bits per clock cycle. rambus* channel the rambus channel consists of a two-byte wide data path capable of transferring data and address information at rates of 800mhz and beyond. the rambus channel has defined mechanical and electrical interfaces and consists of a memory controller, rdram devices, drcg and all interconnect components. system bus processor-to-mch interface. the system bus runs at 400 mhz from a 100 mhz quad-pumped clock. it includes source synchronous transfers for address and data, and system bus interrupt delivery. up uni-processor
introduction r intel ? 82860 mch datasheet 15 1.2 reference documents document document number intel ? xeon? processor and intel ? 860 chipset platform design guide 298252 intel ? 82801ba i/o controller hub (ich2 ) and intel ? 82801bam i/o controller hub (ich2-m ) datasheet 290687 intel ? 860 chipset thermal considerations application note (ap-721) 292269 intel ? 82806aa pci 64 hub (p64h) datasheet 298025 intel ? 82803aa memory repeater hub for rdram (mrh-r) datasheet 298022 intel ? 82802ab/ac firmware hub (fwh) datasheet 290658 intel ? xeon? processor datasheet note: see the intel ? xeon? processor and intel ? 860 chipset platform design guide for an expanded set of related documents.
introduction r 16 intel ? 82860 mch datasheet 1.3 intel ? 860 chipset system architecture the intel 860 chipset is optimized for the intel xeon processor. the intel 860 chipset allows flexibility for dual-processor configurations with a 100 mhz system bus (400 mhz data bus). the intel 860 chipset consists of two main components: intel 82860 memory controller hub (mch), and intel ? 82801ba i/o controller hub (ich2). architectural expansion is provided with the memory expansion card and pci 64-bit hub. the intel 82803aa memory repeater hub (intel mrh-r) provides memory expansion capabilities for rambus* channels. the intel ? 82806aa pci 64 hub (intel p64h) provides pci bridging functions between the hub interface_b?c and pci bus. the intel 860 chipset components are interconnected via an interface called ?hub interface? providing efficient communication between the chipset components. additional hardware platform features, supported by intel 860 chipset, include agp 4x, direct rdram* devices, ultra dma/100/66/33, low pin count interface (lpc), integrated lan controller, and universal serial bus (usb). the intel 860 chipset architecture removes the requirement for the isa expansion bus that was traditionally integrated into the i/o subsystem of pcisets/agpsets. this eliminates many conflicts experienced when installing legacy isa hardware and drivers. the intel 860 chipset is also acpi compliant and supports full-on, stop grant, suspend to disk, and soft-off power management states. through the use of an appropriate lan device, the intel 860 chipset also supports wake-on-lan * for remote administration and troubleshooting.
introduction r intel ? 82860 mch datasheet 17 figure 1. intel ? ? ? ? 860 chipset system block diagram intel ? 82860 memory controller hub (mch) hub interface_a mec (main memory) rdram devices intel ? mrh-r intel mrh-r i/f hub interface_b hub interface_c intel? p64h intel p64h pci 64/66 pci 64/66 i/o controller hub intel ? 82801ba (ich2) sys_blk_860 pci bus 4 usb ports; 2 hc) ac'97 codec(s) (optional) ac'97 2.2 lpc i/f fwh flash bios pci slots gpio lan connect pci agent super i/o keyboard, mouse, fd, pp, sp, ir shaded units are intel? 860 chipset components. ultraata/100 4 ide drives rambus* channel a rambus channel b agp pro 4x agp graphics controller processor system bus processor rdram devices rdram* devices rdram devices 82801ba i/o controller hub (ich2) the ich is a highly integrated multifunctional i/o controller hub that provides the interface to the pci bus and integrates many of the functions needed in today?s pc platforms. the mch and ich communicate over a dedicated hub interface. intel 82801ba (ich2) functions and capabilities include: ? pci rev 2.2 compliant with support for 33 mhz pci operations ? supports up to 6 request/grant pairs (pci slots) ? power management logic support ? enhanced dma controller, interrupt controller, and timer functions ? integrated ide controller; ultra ata/100/66/33 ? usb host interface; 2 host controllers and supports 4 usb ports ? integrated lan controller
introduction r 18 intel ? 82860 mch datasheet ? system management bus (smbus) compatible with most i 2 c devices; ich2 has both bus master and slave capability ? intel ? audio codec '97 component specification v2.2 -compliant (ac?97) link for audio and telephony codecs; up to 6 channels (ich2) ? low pin count (lpc) interface ? fwh interface (fwh flash bios support) ? alert on lan* (aol and aol2) intel ? 82803aa memory repeater hub (intel ? mrh-r) the intel mrh-r supports multiple rambus channels from an ?expansion channel.? expansion channel is the interconnect between the mch and the intel mrh-r. each intel mrh-r can support up to two ?stick? channels. the intel mrh-r acts as a pass-thro ugh logic with fixed delay for read and write accesses from expansion channels to rambus channels. the intel mrh-r features include: ? maximum of 1 gb memory per channel ? refresh and precharge on a channel upon request from memory controller ? core logic gating to minimize power consumption ? clock generation for direct rambus* clock generator (drcg) ? integrated smbus controller to read/write data from/to spd eeprom on the rimms intel ? 82806aa pci 64 hub (intel ? p64h) the pci-64 hub (intel p64h)) is a peripheral chip that performs pci bridging functions between the hub interface and the pci bus and is used as an integral part of the intel 860 chipset. the intel p64h has a 16-bit primary hub interface to the mch and a secondary 64-bit pci bus interface. the 64-bit interfaces inter-operate transparently with either 64-bit or 32-bit devices. the intel p64h is fully compliant with the pci local bus specification, revision 2.2 . the intel p64h functions include: ? integrated pci low skew clock driver ? i/o apic 1.4 intel ? 82860 mch overview the intel 82860 memory controller hub (mch) provides the processor interface, dram interface, agp interface, and hub interfaces in an intel 860 chipset-based platform. the mch uses a 1012 olga package and its capabilities include: ? supports single or dual intel ? xeon? processor configurations at 100 mhz (400 mhz data bus) ? parity protection on the system data, address/request, and response bus signals ? agtl+ host bus with integrated termination supporting 32-bit host addressing ? supports ioq depth of 8 ? dual rambus channels support 300 and 400 mhz direct rdram device operation
introduction r intel ? 82860 mch datasheet 19 ? 4-gb direct rdram device support ? 1.5 volt agp interface with 4x sba/data transfer and 2x/4x fast write capability ? agp serr# signal ? 8-bit, 66 mhz 4x hub interface_a to ich2 ? two 16-bit, 66 mhz 4x hub interfaces ? advanced power management logic ? distributed arbitration for highly concurrent operation 1.4.1 processor interface the intel 82860 mch supports the intel xeon processor system bus interface. the primary enhancements over the p6 bus protocol are: ? source synchronous double-pumped address ? source synchronous quad-pumped data ? system bus interrupt delivery the mch supports a 64-byte cache line size. up to two processors can be used at a system bus frequency of 100 mhz (400 mhz data bus). the mch supports a 1:1 host-to-direct rdram device frequency ratio (400 mhz data bus to 400 mhz direct rdram device). the mch integrates agtl+ termination resistors on all of the agtl+ signals. system bus dynamic bus inversion (dbi) is supported. the mch provides 36-bit host addressing, allowing the processor to access the entire 16 gb of the mch?s memory address space. the mch has an 8-deep in-order queue permitting up to eight outstanding pipelined address requests on the host bus. host-initiated i/o cycles are positively decoded to agp, hub interface_b, hub interface_c, or mch configuration space. host-initiated i/o cycles are subtractively decoded to hub interface_a. host-initiated memory cycles are positively decoded to agp, hub interface_b, hub interface_c, or main memory and are again subtractively decoded to hub interface_a if under 4 gb. agp semantic memory accesses initiated from agp to main memory are not snooped on the host bus. main memory accesses initiated from agp using pci semantics and from any hub interface to main memory are snooped on the system bus. memory accesses whose addresses lie within the agp aperture are translated using the agp address translation table, regardless of the originating interface.
introduction r 20 intel ? 82860 mch datasheet the intel 82860 mch generates and checks parity for data, address/request, and response signals on the processor bus. the type of error protection and the responses of the mch are described in the following table. signal name protection error response dep[3:0]# parity host data parity: the intel 82860 mch can be configured to generate an serr message when it detects a host data parity error. ap[1:0]# parity address parity: the intel 82860 mch can be configured to generate an serr message when it detects a host address/request parity error. since the mch does not implement the system bus error phase, the erroneous transaction will proceed to completion. rsp# parity response parity: the intel 82860 mch does not detect errors on the response signals, since they are always mch-driven. correct response parity is driven in all phases. 1.4.2 memory interface the mch directly supports two channels of direct rdram device memory operating in lock-step using rsl technology. the mch rambus channels run at 300 mhz and 400 mhz and supports 128/144 and 256/288mb technology direct rdram devices. the page size for 128/144 mb direct rdram devices is 1 kb; for 256/288mb devices, the page size is 2 kb. up to eight pages can be open simultaneously. a maximum of 64 direct rdram devices are supported on the paired channels without external logic. each expander adds two stick channels to the main channel, which yields a total of eight rambus channels. table 1 shows the maximum direct rdram device array size and the minimum increment size for the various direct rdram device densities supported. warning: memory repeater hubs run at 400 mhz only. table 1. maximum memory supported direct rdram* device technology directly supported maximum supported via expanders 1 (max 1 per channel) maximum 128/144 mbit 1 gb 2 gb 256/288 mbit 2 gb 4 gb the mch provides optional ecc error checking for direct rdram device data integrity. during direct rdram device writes, ecc is generated on a qword (64-bit) basis. during direct rdram device reads and the read of the data that underlies partial writes, the mch supports detection of single-bit and multiple-bit errors, and will correct single-bit errors when correction is enabled.
introduction r intel ? 82860 mch datasheet 21 table 2. supported direct rdram* devices device tech device quantity no. of banks page size 128 mbit 4,8,16 16d 1 kb 128/144 mbit 4,8,16 2x16d 1 kb 288 mbit 4,8,16 16d 2 kb 256/288 mbit 2,4,8,16 2x16d 2 kb direct rdram* device thermal management the relatively high power dissipation needs of direct rdram device devices necessitate a mch mechanism capable of putting a number of memory devices into a power-saving mode. direct rdram devices may be in one of three power-management states: active, standby, or nap. the intel 82860 mch implements direct rdram device nap mode. in ?pool? mode, two queues are used inside the mch: the ?a? pool contains references to device pairs that are currently in the active mode while the ?b? pool contains references to device pairs that are in the standby mode. all devices that are found in neither pool are napping or in standby. the ?a? pool may hold between 1 and 8 device pairs, while the ?b? pool may be configured to contain between 1 and 16 device pairs. this allows the power consumption to be tuned. the intel 82860 mch also implements a mode in which all devices are turned on and it is assumed that proper system design will provide adequate cooling. this means that all devices that are not in pool ?a? or ?b? are in standby mode. two failsafe mechanisms are supported that protect the direct rdram devices from thermal overload. one mechanism relies on external thermal sensors to assert the overt# pin. the other mechanism polls the thermal indicator bits in the direct rdram devices themselves. when either mechanism is activated, the mch immediately exits the ?all devices on? mode and reverts to whatever pool mode has been programmed by system software. in summary the mch direct rdram device thermal management includes: ? pool mode keeps direct rdram device power dissipation within pre-configured bounds ? from 1?8 device pairs in active pool ? from 0?16 device pairs in standby pool ? remainder of device pairs in nap or standby pool ? sw may change pool size dynamically ? overtemp condition detected based on external signal or polling thermal sensor bits in direct rdram devices
introduction r 22 intel ? 82860 mch datasheet 1.4.3 agp interface a single agp component or connector (not both) is supported by the intel 82860 mch?s agp interface. the agp interface supports agp 2.0 including 1x/2x/4x agp signaling and 2x/4x fast writes. agp semantic cycles to dram are not snooped on the host bus. pci semantic cycles to dram are snooped on the host bus. the mch supports pipe# or sba[7:0] agp address mechanisms, but not both simultaneously. either the pipe# or the sba[7:0] mechanism must be selected during system initialization. agp semantic (pipe# or sba initiated) accesses to memory are not snooped. pci semantic (frame# initiated) accesses to memory are snooped. there is delayed transaction support for agp-to-main memory frame# semantic reads that cannot be serviced immediately. both upstream and downstream addressing is limited to 32 bits for agp and agp/pci transactions. the mch contains a 32-deep agp requests queue. high priority accesses are supported. all accesses from the agp interface that fall within the graphics aperture address range pass through an address translation mechanism with a fully associative 20 entry tlb. accesses between agp and hub interface_a are limited to memory writes originating from hub interface_a destined for the agp bus. the agp interface is clocked from a dedicated 66 mhz clock (66in). the agp-to-host/core interface is asynchronous. note: the agp buffers operate only in 1.5 v mode. they are not 3.3 v safe. 1.4.4 hub interface_a the 8-bit hub interface_a connects the mch to the ich2. virtually all communication between the mch and the ich2 occurs over hub interface_a. hub interface_a runs at 66 mhz; this provides a 266mb/s point-to-point hub interface to ich2 with parity. in addition to the normal traffic types (e.g., hub interface_a -to- agp memory writes, hub interface_a-to-dram, and processor-to-hub interface_a) the following communication also occurs over hub interface_a: ? interrupt related messages ? power management events as messages ? smi, sci, and serr error indication messages it is assumed that hub interface_a is always connected to an ich2.
introduction r intel ? 82860 mch datasheet 23 1.4.5 hub interface_b and hub interface_c the mch supports two full time 16-bit hub interfaces. the two dedicated 16-bit hub interfaces (interface_b, interface_c) run at 66 mhz and provide 266 mb/s (533mb/s) bandwidth with parity. peer-to-peer accesses between any 16-bit hub interface (b?c) are limited to memory writes. the 16-bit hub interfaces may or may not be connected to a device. the mch detects the presence of a device by sampling the hlx[11] input signals. if a hub interface device is not present, its configuration register space is hidden from configuration software. if hub interface_c is used, then hub interface_b must be populated with an intel 82806aa (p64h) component. interface_b and interface_c traffic types include: ? memory writes between any 16-bit hub interfaces ? hub interface_b and hub interface_c - to - agp memory writes ? hub interface_b and hub interface_c - to - dram ? processor-to- hub interface_b and hub interface_c ? messaging ? msi interrupt messages ? serr error indication 1.4.6 mch clocking the mch has the following clock input pins: ? differential bclk0/bclk1 for the host interface ? 66 mhz clock input for the agp and hub interface_a ? differential ctm/ctm# and cfm/cfm# for each of the two racs. clock synthesizer chip(s) are responsible for generating the system host clocks, agp and hub interface clocks, pci clocks, and direct rdram device clocks. the mch provides two pairs of feedback signals to the direct rambus* clock generator (drcg) chips to keep the host and direct rdram device clocks aligned. the host speed is 100 mhz (300/400 mhz data bus). the speed for direct rdram device is 300 mhz or 400 mhz. the mch does not require any relationship between the hclkin host clock and the 66 mhz clock generated for agp and hub interfaces; they are asynchronous to each other. the agp and hub interfaces (a?c) run at a constant 66 mhz base frequency. the hub interfaces run at 4x; agp transfers can be 1x/2x/4x. table 3 and table 4 indicate the frequency ratios between the various interfaces. table 3. mch processor system bus-to-rac ratio direct rdram* device speed (mhz) rac i/f frequency (mhz) processor system bus frequency intel? xeon? processor 100 mhz (400 mhz data bus) 300 100 3:4 400 100 1:1
introduction r 24 intel ? 82860 mch datasheet table 4. mch processor-to-agp/hub interface ratio agp/hub interface unit frequency (mhz) processor system bus frequency intel? xeon? processor 100 mhz (400 mhz data bus) agp: 66 mhz asynchronous hub interface_a: 66 mhz asynchronous hub interface_b?c: 66 mhz asynchronous 1.4.7 system interrupts the mch supports both intel ? 8259 and intel xeon processor system bus interrupt delivery mechanisms. the serial apic interrupt mechanism is not supported. the intel 8259 support consists of flushing inbound hub interface_a write buffers when an interrupt acknowledge cycle is forwarded from the system bus to hub interface_a. support for the intel xeon processor system bus interrupt delivery is new to the intel 82860 mch. ioxapic and pci msi interrupts are generated as memory writes. the mch decodes upstream memory writes to the range 0fee0_0000h?0feef_ffffh from any of the hub interface_a?c interfaces as messaged based interrupts. the mch forwards these memory writes, along with the associated write data, to the system bus as an interrupt message transaction. note that since this address does not decode as part of main memory, the write cycle and the write data do not get forwarded to direct rdram device via the write buffer. the mch provides the response and trdy# for all interrupt message cycles including the ones originating from the mch. the mch supports interrupt re-direction for inter-processor interrupts (ipis) as well as upstream interrupt memory writes. for message based interrupts system write buffer coherency is maintained by relying on strict ordering of memory writes. the mch ensures that all memory writes received from a given interface prior to an interrupt message memory write are delivered to the system bus for snooping in the same order that they occur on the given interface. 1.4.8 powerdown flow since the mch is powered down during str, the mch cannot maintain any state information when exiting str. this means that the entire initialization process when exiting str must be performed by the bios via accesses to the ricm register. entry into str (acpi s3) is initiated by the operating system (os) based on detecting a lack of system activity. the os unloads all system device drivers as part of the process of entering str. the os then writes to the pm1_cnt i/o register in the ich2 to actually trigger the transition into str. the ich2 responds by eventually generating the go c3 message to the mch via hub interface_a.
signal description r intel ? 82860 mch datasheet 25 2 signal description this section provides a detailed description of mch signals. the signals are arranged in functional groups according to their associated interface (see figure 2). the states of all of the signals during reset are provided in section 2.11, ?pin states during reset? . the ?#? symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present after the signal name the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin i/o bi-directional input/output pin s/t/s sustained tri-state. this pin is driven to its inactive state prior to tri-stating. as/t/s active sustained tri-state. this applies to some of the hub interface signals. this pin is weakly driven to its last driven value. the signal description also includes the type of buffer used for the particular signal: agtl+ open drain agtl+ interface signal. refer to the agtl+ i/o specification for complete details. the mch integrates agtl+ termination resistors. agp agp interface signals. these signals are compatible with agp 2.0 1.5v signaling environment dc and ac specifications. the buffers are not 3.3 v tolerant. cmos cmos buffers. rsl rambus signaling level interface signal. refer to the latest direct rdram* component specification published by rambus for complete details. note: processor address and data bus signals are logically inverted signals (i.e., the actual values are inverted from what appears on the system bus). all system bus control signals follow normal convention; that is, a 0 indicates an active level (low voltage) if the signal is followed by # symbol and a 1 indicates an active level (high voltage) if the signal has no # suffix.
signal description r 26 intel ? 82860 mch datasheet figure 2. mch signal diagram hdvref[3:0] havref[1:0] ccvref cha_ref[1:0] chb_ref[1:0] gref_0 gref_1 hlref_a hlref_b hlref_c hlrcomp_a hlrcomp_b hlrcomp_c grcomp hrcomp[1:0] hswng[1:0] hswng_b hswng_c hl1_8 g_swng vcc1_8 vcc1_8rac vddq vtt vss block_dia_860 dqa_a[8:0] dqb_a[8:0] rq_a[7:5] rq_a[4:0] ctm_a, ctm_a# cfm_a, cfm_a# exp_a[1:0] cmd_a sck_a sio_a agp interface sba[7:0] pipe# st[2:0] rbf# wbf# ad_stb[1:0], ad_stb[1:0]# sbstb, sbstb# g_serr# g_frame# g_irdy# g_trdy# g_stop# g_devsel# g_req# g_gnt# g_ad[31:0] g_c/be[3:0]# g_par host interface ha[35:3]# hd[63:0]# ads# ap[1:0]# berr# bnr# bpri# dbsy# defer# drdy# hit# hitm# hlock# hreq[4:0]# htrdy# rs[2:0]# cpurst# br0# dp[3:0]# dbi[3:0]# hadstb[1:0]# hdstbp[3:0]/hdstbn[3:0] rsp# bclk[1:0] 66in cha_rclkout / chb_rclkout cha_hclkout / chb_hclkout rstin# overt# testin# clocks and reset hub interface a hl_a[11:0] hla_stb, hla_stb# system memory direct rdram* device interface a dqa_b[8:0] dqb_b[8:0] rq_b[7:5] rq_b[4:0] ctm_b, ctm_b# cfm_b, cfm_b# exp_b[1:0] cmd_b sck_b sio_b system memory direct rdram device interface b voltage refernce, pll power hub interface b hl_b[19:0] hlb_stb, hlb_stb# hub interface c hl_c[19:0] hlc_stb, hlc_stb#
signal description r intel ? 82860 mch datasheet 27 2.1 host interface signals signal name type description ads# i/o agtl+ address strobe: the system bus owner asserts ads# to indicate the first of two cycles of a request phase. ap[1:0]# i/o agtl+ address parity: the ap[1:0]# lines are driven by the request initiator and provide parity protection for the request phase signals. ap[1:0]# are common clock signals and are driven one common clock after the request phase. first add. sub-phase second add. sub-phase ap0# ha[35:24]# ha[23:3]#, hreq[4:0]# ap1# ha[23:3]#, hreq[4:0]# ha[35:24]# address parity is correct if there is an even number of electrically low signals (low voltage) in the set consisting of the covered signals plus the parity signal. note that the mch only connects to ha[35:3]#. the mch assumes ha[43:36]# to be electrically high (high voltage) when checking and generating address parity. the mch may be configured to send a serr message to the ich2 over hub interface_a when it detects an error on one of the ap[1:0]# signals. berr# i/o agtl+ bus error: this signal is not functional. the berr# pin on the mch does contain internal pull-ups; thus, it should be connected to the processor berr# signal to provide system bus termination. bnr# i/o agtl+ block next request: used to block the current request bus owner from issuing a new request. this signal is used to dynamically control the system bus pipeline depth. bpri# o agtl+ bus priority request: the mch is the only priority agent on the system bus. it asserts this signal to obtain the ownership of the address bus. this signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the hlock# signal was asserted. br0# i/o agtl+ bus request 0#: the mch pulls the processor bus? br0# signal low during cpurst#. the processor samples this signal on the active-to- inactive transition of cpurst#. the minimum setup time for this signal is 4 hclks. the minimum hold time is 2 clocks and the maximum hold time is 20 hclks. br0# should be tristated after the hold time requirement has been satisfied. cpurst# o agtl+ cpu reset: the cpurst# pin is an output from the mch. the mch asserts cpurst# while rstin# (pcirst# from ich2) is asserted and for approximately 1 ms after rstin# is deasserted. the cpurst# allows the processors to begin execution in a known state. note: the ich2 must provide processor frequency select strap set-up and hold times around cpurst#. this requires strict synchronization between mch cpurst# deassertion and ich2 driving the straps. dbsy# i/o agtl+ data bus busy: used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# o agtl+ defer: signals that the mch will terminate the transaction currently being snooped with either a deferred response or with a retry response.
signal description r 28 intel ? 82860 mch datasheet signal name type description dp[3:0]# i/o agtl+ 4x host data parity: the dp[3:0]# signals provide parity protection for hd[63:0]#. the dp[3:0]# signals are common clock signals and are driven one common clock after the data phases they cover. dp[3:0]# are driven by the same agent driving hd[63:0]#. 1 st data 2 nd data 3 rd data 4 th data phase phase phase phase hd[15:0]#, dbi0# dp3# dp2# dp1# dp0# hd[31:16]#, dbi1# dp0# dp3# dp2# dp1# hd[47:32]#, dbi2# dp1# dp0# dp3# dp2# hd[63:48]#, dbi3# dp2# dp1# dp0# dp3# data parity is correct if there is an even number of electrically low signals (low voltage) in the set consisting of the covered signals plus the parity signal. dbi[3:0]# i/o agtl+ 4x dynamic bus inversion: these signals are driven along with the hd[63:0]# signals. they indicate if the associated signals are inverted. dbi[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16-bit group never exceeds 8. dbi3# = hd[63:48]# dbi2# = hd[47:32]# dbi1# = hd[31:16]# dbi0# = hd[15:0]# drdy# i/o agtl+ data ready: asserted for each cycle that data is transferred. ha[35:3]# i/o agtl+ 2x host address bus: ha[35:3]# connect to the processor address bus. during processor cycles, the ha[35:3]# are inputs. the mch drives ha[35:3]# during snoop cycles on behalf of hub interface and agp/secondary pci initiators. ha[35:3]# are transferred at 2x rate. note that the address is inverted on the system bus. after reset, the value on ha7# is sampled by all system bus agents, including the mch, on the rising edge of cpurst#. its latched value determines the maximum ioq depth mode supported on the system bus. if ha7# is sampled low, the ioq depth on the bus is one. if ha7# is sampled high, the ioq depth on the bus is the maximum of 12. when the ioq depth on the bus is set to 12, the mch limits the number of queued transactions by asserting bnr#, since the mch has an ioq of depth 8. hadstb[1:0]# i/o agtl+ 2x host address strobe: hadstb[1:0]# are the source synchronous strobes used to transfer ha[35:3]# and hreq[4:0]# at the 2x transfer rate. hadstb0# = ap0#, ha[16:3]#, hreq[4:0]# hadstb1# = ap1#, ha[35:17]# hd[63:0]# i/o agtl+ 4x host data: these signals are connected to the processor data bus. in enhanced mode hd[63:0]# are transferred at 4x rate. note that the data signals are inverted on the system bus.
signal description r intel ? 82860 mch datasheet 29 signal name type description hdstbp[3:0]# hdstbn[3:0]# i/o agtl+ 4x differential host data strobes: these are the differential source synchronous strobes used to transfer hd[63:0]# and dbi[3:0]# at the 4x transfer rate. hdstbp3#, hdstbn3# = hd[63:48]#, dbi3# hdstbp2#, hdstbn2# = hd[47:32]#, dbi2# hdstbp1#, hdstbn1# = hd[31:16]#, dbi1# hdstbp0#, hdstbn0# = hd[15:0]#, dbi0# hit# i/o agtl+ hit: this signal indicates that a caching agent holds an unmodified version of the requested line. it is, also, driven in conjunction with hitm# by the target to extend the snoop window. hitm# i/o agtl+ hit modified: hitm# indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. hitm# is, also, driven in conjunction with hit# to extend the snoop window. hlock# i agtl+ host lock: all system bus cycles sampled with the assertion of hlock# and ads#, until the negation of hlock#, must be atomic (i.e., no hub interface or agp snoopable access to dram are allowed when hlock# is asserted by the processor). hreq[4:0]# i/o agtl+ 2x host request command: these signals define the attributes of the request. in enhanced mode hreq[4:0]# are transferred at 2x rate. hreq[4:0]# are asserted by the requesting agent during both halves of request phase. in the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second half the signals carry additional information to define the complete transaction type. htrdy# o agtl+ host target ready: htrdy# indicates that the target of the processor transaction is able to enter the data transfer phase. rs[2:0]# o agtl+ response status: rs[2:0]# indicate the type of response according to the following the table: 000 = idle state 001 = retry response 010 = deferred response 011 = reserved (not driven by mch) 100 = hard failure (not driven by mch) 101 = no data response 110 = implicit writeback 111 = normal data response rsp# o agtl+ response parity: rsp# provides parity protection for the rs[2:0]# signals. it is always driven by the mch and must be valid on all clo cks. res ponse parity is correct if there are an even number of low signals (low voltage) in the set consisting of the rs[2:0]# signals and the rsp# signal itself. the mch may be configured to send an serr message to the ich2 over hub interface_a when it detects an error on the rsp# signal.
signal description r 30 intel ? 82860 mch datasheet 2.2 rambus* channel a signal name type description dqa_a[8:0] i/o rsl direct rdram* device data (a): data signals used for read and write operations on rambus* channel a. dqb_a[8:0] i/o rsl direct rdram device data (a): data signals used for read and write operations on rambus channel a. rq_a[7:5] o rsl row access control (a): three request package pins containing control and address information for row accesses. note: rq_a[7:5] are sometimes referred to as the ?row_a[2:0]? signals. rq_a[4:0] o rsl column access control (a): five request package pins containing control and address information for column accesses. note: rq_a[4:0] are sometimes referred to as the ?col_a[4:0]? signals. ctm_a i rsl clock to master (a): ctm_a is one of the two differential transmit clock signals used for direct rdram device operations on rambus channel a. it is an input to the mch and is generated from an external clock synthesizer. ctm_a# i rsl clock to master compliment (a): ctm_a# is one of the two differential transmit clock signals used for direct rdram device operations on rambus channel a. it is an input to the mch and is generated from an external clock synthesizer. cfm_a o rsl clock from master (a): cfm_a is one of the two differential receive clock signals used for direct rdram device operations on rambus channel a. it is an output from the mch. cfm_a# o rsl clock from master compliment( a): cfm_a# is one of the two differential receive clock signals used for direct rdram device operations on rambus channel a. it is an output from the mch. exp_a[1:0] o rsl expansion (a): these signals are used to communicate to an external direct rdram device repeater on rambus channel a. the repeater increases the maximum memory size supported by the mch. cmd_a o cmos command (a): command output to the direct rdram device devices used for power mode control, configuring the sio daisy chain, and framing sio operations. sck_a o cmos serial clock (a): this signal provides clocking for register accesses and selects rambus channel a devices for power management. sio_a i/o cmos serial input/output (a): this signal is a bi-directional serial data signal used for device initialization, register operations, power mode control, and device reset.
signal description r intel ? 82860 mch datasheet 31 2.3 rambus* channel b signal name type description dqa_b[8:0] i/o rsl direct rdram* device data (b): data signals used for read and write operations on rambus* channel b. dqb_b[8:0] i/o rsl direct rdram device data (b): data signals used for read and write operations on rambus channel b. rq_b[7:5] o rsl row access control (b): three request package pins containing control and address information for row accesses. note: rq_b[7:5] are sometimes referred to as the ?row_b[2:0]? signals. rq_b[4:0] o rsl column access control (b): five request package pins containing control and address information for column accesses. note: rq_b[4:0] are sometimes referred to as the ?col_b[4:0]? signals. ctm_b i rsl clock to master (b): ctm_b is one of the two differential transmit clock signals used for direct rdram device operations on rambus channel b. it is an input to the mch and is generated from an external clock synthesizer. ctm_b# i rsl clock to master compliment (b): ctm_b# is one of the two differential transmit clock signals used for direct rdram device operations on rambus channel b. it is an input to the mch and is generated from an external clock synthesizer. cfm_b o rsl clock from master (b): cfm_b is one of the two differential receive clock signals used for direct rdram device operations on rambus channel. it is an output from the mch. cfm_b# o rsl clock from master compliment (b): cfm_b# is one of the two differential receive clock signals used for direct rdram device operations on rambus channel b. it is an output from the mch. exp_b[1:0] o rsl expansion (b): these signals are used to communicate to an external direct rdram device repeater on rambus channel b. the repeater increases the maximum memory size supported by the mch. cmd_b o cmos command (b): cmd_b is a command output to the direct rdram device devices used for power mode control, configuring the sio daisy chain, and framing sio operations. sck_b o cmos serial clock (b): this signal provides clocking for register accesses and selects rambus channel b devices for power management. sio_b i/o cmos serial input/output (b): sio_b is a bi-directional serial data signal used for device initialization, register operations, power mode control, and device reset.
signal description r 32 intel ? 82860 mch datasheet 2.4 hub interface_a signals signal name type description hl_a[11:0] i/o cmos hub interface_a signals: signals used for the hub interface. hla_stb i/o cmos hub interface_a strobe: one of two differential strobe signals used to transmit or receive packet data over hub interface_a. hla_stb# i/o cmos hub interface_a strobe compliment: one of two differential strobe signals used to transmit or receive packet data over hub interface_a. 2.5 hub interface_b signal name type description hl_b[19:0] i/o cmos hub interface_b signals: signals used for the hub interface. hlb_stb[1:0] i/o cmos hub interface_b strobe: one of two differential strobe signals used to transmit or receive packet data over hub interface_b. hlb_stb[1:0]# i/o cmos hub interface_b strobe compliment: one of two differential strobe signals used to transmit or receive packet data over hub interface_b. 2.6 hub interface_c signal name type description hl_c[19:0] i/o cmos hub interface_c signals: signals used for the hub interface. hlc_stb[1:0] i/o cmos hub interface_c strobe: one of two differential strobe signals used to transmit or receive packet data over hub interface_c. hlc_stb[1:0]# i/o cmos hub interface_c strobe compliment: one of two differential strobe signals used to transmit or receive packet data over hub interface_c.
signal description r intel ? 82860 mch datasheet 33 2.7 agp interface signals 2.7.1 agp addressing signals signal name type description pipe# i agp pipeline: during pipe# operation: this signal is asserted by the agp master to indicate a full width address is to be enqueued on by the target using the ad bus. one address is placed in the agp request queue on each rising clock edge while pipe# is asserted. when pipe# is deasserted, no new requests are queued across the ad bus. during sba operation: not used. during frame# operation: not used. n ote: initial agp designs may not use pipe# (i.e., pci only 66 mhz). therefore, an 8 k ? pull-up resistor connected to this pin is required on the motherboard. sba[7:0] i agp side-band addressing: during pipe# operation: not used. during sba operation: these signals are used by the agp master (graphics component) to place addresses in the agp request queue. the sba bus and ad bus operate independently (i.e., transaction can proceed on the sba bus and the ad bus simultaneously). during frame# operation: not used. note: these signals implement internal pull-ups with a nominal value of 8 k ? . when agp is not enabled, these pull-ups are disabled. note: the above table contains two mechanisms to queue requests by the agp master. note that the master can only use one mechanism. the master may not switch methods without a full reset of the system. when pipe# is used to queue addresses, the master is not allowed to queue addresses using the sba bus. for example, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. this change of modes is not a dynamic mechanism; rather, it is a static decision when the device is first being configured after reset.
signal description r 34 intel ? 82860 mch datasheet 2.7.2 agp flow control signals signal name type description rbf# i agp read buffer full: during pipe# and sba operation: read buffer full indicates if the master is ready to accept previously requested low priority read data. when rbf# is asserted, the mch is not allowed to initiate the return low priority read data. that is, the mch can finish returning the data for the request currently being serviced; however, it cannot begin returning data for the next request. rbf# is only sampled at the beginning of a cycle. if the agp master is always ready to accept return read data, then it is not required to implement this signal. during frame# operation: not used. wbf# i agp write-buffer full: during pipe# and sba operation: write buffer full indicates if the master is ready to accept fast write data from the mch. when wbf# is asserted, the mch is not allowed to drive fast write data to the agp master. wbf# is only sampled at the beginning of a cycle. if the agp master is always ready to accept fast write data, then it is not required to implement this signal. during frame# operation: not used. 2.7.3 agp status signals signal name type description st[2:0] o agp status bus: during pipe# and sba operation: provides information from the arbiter to an agp master on what it may do. st[2:0] only have meaning to the master when its g_gnt# is asserted. when g_gnt# is deasserted, these signals have no meaning and must be ignored. refer to the agp interface specification revision 2.0 for further explanation of the st[2:0] values and their meanings. during frame# operation: these signals are not used during frame#- based operation, except that a ?111? indicates that the master may begin a frame# transaction.
signal description r intel ? 82860 mch datasheet 35 2.7.4 agp strobes signal name type description ad_stb0 i/o (s/t/s) agp ad bus strobe-0: during 1x operation: not used. during 2x operation: during 2x operation, this signal provides timing for the g_ad[15:0] and g_c/be[1:0]# signals. the agent that is providing the data will drive this signal. during 4x operation: during 4x operation, this is one-half of a differential strobe pair that provides timing information for the g_ad[15:0] and g_c/be[1:0]# signals. ad_stb0# i/o (s/t/s) agp ad bus strobe-0 compliment: during 1x operation: not used. during 2x operation: not used. during 4x operation: during 4x operation, this is one-half of a differential strobe pair that provides timing information for the g_ad[15:0] and g_c/be[1:0]# signals. the agent that is providing the data will drive this signal. ad_stb1 i/o (s/t/s) agp ad bus strobe-1: during 1x operation: not used. during 2x operation: during 2x operation, this signal provides timing for the g_ad[16:31] and g_c/be[2:3]# signals. the agent that is providing the data will drive this signal. during 4x operation: during 4x operation, this is one-half of a differential strobe pair that provides timing information for the g_ad[16:31] and g_c/be[2:3]# signals. the agent that is providing the data will drive this signal. ad_stb1# i/o (s/t/s) agp ad bus strobe-1 compliment during 1x operation: not used. during 2x operation: not used. during 4x operation: during 4x operation, this is one-half of a differential strobe pair that provides timing information for the g_ad[16:31] and g_c/be[2:3]# signals. the agent that is providing the data will drive this signal. sb_stb i agp sba bus strobe: during 1x operation: not used. during 2x operation: during 2x operation, this signal provides timing for the sba bus signals. the agent that is driving the sba bus will drive this signal. during 4x operation: during 4x operation, this is one-half of a differential strobe pair that provides timing information for the sba bus signals. the agent that is driving the sba bus will drive this signal.
signal description r 36 intel ? 82860 mch datasheet signal name type description sb_stb# i agp sba bus strobe compliment: during 1x operation: not used. during 2x operation: not used. during 4x operation: during 4x operation, this is one-half of a differential strobe pair that provides timing information for the sba bus signals. the agent that is driving the sba bus will drive this signal. 2.7.5 agp/pci signals-semantics for transactions on the agp interface carried using agp frame# protocol these signals operate similar to their semantics in the pci 2.1 specification. the role of all agp frame# signals is described below. signal name type description g_frame# i/o s/t/s agp frame: during pipe# and sba operation: not used. during fast write operation: g_frame# is used to frame transactions as an output from the mch during fast writes. during frame# operation: g_frame# is an output when the mch acts as an initiator on the agp interface. g_frame# is asserted by the mch to indicate the beginning and duration of an access. g_frame# is an input when the mch acts as a frame#-based agp target. as a frame#-based agp target, the mch latches the g_c/be[3:0]# and the g_ad[31:0] signals on the first clock edge on which it samples g_frame# active. g_irdy# i/o s/t/s agp initiator ready: during pipe# and sba operation: not used while enqueueing requests via agp sba and pipe#, but used during the data phase of pipe# and sba transactions. during frame# operation: g_irdy# is an output when mch acts as a frame#-based agp initiator and an input when the mch acts as a frame#-based agp target. the assertion of g_irdy # indicates the current frame#-based agp bus initiator?s ability to complete the current data phase of the transaction. during fast write operation: g_irdy# indicates the agp compliant master is ready to provide all write data for the current transaction. once g_irdy# is asserted for a write operation, the master is not allowed to insert wait states. the master is never allowed to insert a wait-state during the initial data transfer (32 bytes) of a write transaction. however, it may insert wait states after each 32-byte block is transferred.
signal description r intel ? 82860 mch datasheet 37 signal name type description g_trdy# i/o s/t/s agp target ready: during pipe# and sba operation: not used while enqueueing requests via agp sba and pipe#, but used during the data phase of pipe# and sba transactions. during frame# operation: g_trdy# is an input when the mch acts as an agp initiator and an output when the mch acts as a frame#-based agp target. the assertion of g_trdy# indicates the target?s ability to complete the current data phase of the transaction. during fast write operation: g_trdy# indicates the agp compliant target is ready to receive write data for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. the target is allowed to insert wait states after each block (32 bytes) is transferred on write transactions. note: for agp fast writes, if an agp master (acting as a pci target) asserts g_trdy# before the first throttling point, the system will hang. g_stop# i/o s/t/s agp stop: during pipe# and sba operation: not used. during frame# operation: g_stop# is an input when the mch acts as a frame#-based agp initiator and an output when the mch acts as a frame#-based agp target. g_stop# is used for disconnect, retry, and abort sequences on the agp interface. g_devsel# i/o s/t/s agp device select: during pipe# and sba operation: not used. during frame# operation: g_devsel#, when asserted, indicates that a frame#-based agp target device has decoded its address as the target of the current access. the mch asserts g_devsel# based on the dram address range being accessed by a pci initiator. as an input it indicates whether any device on the bus has been selected. during fast write operation: g_devsel# is used when the transaction cannot complete during the block data transfer. g_req# i agp request: during sba operation: not used. during pipe# and frame# operation: g_req#, when asserted, indicates that a frame# or pipe# based agp master is requesting use of the agp interface. this signal is an input into the mch. g_gnt# o agp grant: during sba, pipe# and frame# operation: g_gnt# along with the information on the st[2:0] signals (status bus) indicates how the agp interface will be used next. refer to the agp interface specification revision 2.0 for further explanation of the st[2:0] values and their meanings. this signal requires an external pull-up of 8.2 k ? .
signal description r 38 intel ? 82860 mch datasheet signal name type description g_ad[31:0] i/o agp address/data bus: during pipe# and frame# operation: g_ad[31:0] are used to transfer both address and data information on the agp interface. during sba operation: g_ad[31:0] are used to transfer data on the agp interface. g_c/be[3:0]# i/o agp command/byte enable: during frame# operation: during the address phase of a transaction, g_c/be[3:0]# define the bus command. during the data phase, g_c/be[3:0]# are used as byte enables. the byte enables determine which byte lanes carry meaningful data. the commands issued on the g_c/be[3:0]# signals during frame# based agp are the same c/be[3:0]# command described in the pci 2.1 specification. during pipe# operation: when an address is enqueued using pipe#, the g_c/be[3:0]# signals carry command information. refer to the agp 2.0 interface specification, revision 2.0 for the definition of these commands. the command encoding used during pipe# based agp is different than the command encoding used during frame# based agp cycles (or standard pci cycles on a pci bus). during sba operation: not used. g_par i/o agp parity: during frame# operation: this signal is driven by the mch when it acts as a frame#-based agp initiator during address and data phases for a write cycle, and during the address phase for a read cycle. g_par is driven by the mch when it acts as a frame# based agp target during each data phase of a frame# based agp memory read cycle. even parity is generated across g_ad[31:0] and g_c/be[3:0]#. during sba and pipe# operation: this signal is not used during sba and pipe# operation. g_serr# i agp serr#: the g_serr# signal is used by a pci device to signal an error on a pci device attached to agp/pci. the mch may be configured to send a serr message to the ich2 upon the assertion of g_serr#. note: pcirst# from the ich2 is connected to rstin# and is used to reset agp interface logic within the mch. the agp agent will also use pcirst# provided by the ich2 as an input to reset its internal logic. the lock# signal is not supported on the agp interface (even for pci operations). perr# signal is not supported on the agp interface.
signal description r intel ? 82860 mch datasheet 39 2.8 clocks, reset, and miscellaneous signal name type description bclk[1:0] i cmos differential host clock in: these pins receive a differential host clock from the external clock synthesizer. this clock is used by all of the mch logic that is in the host clock domain. 66in i cmos 66 mhz clock in: this pin receives a 66 mhz clock from the clock synthesizer. the agp and hub interface_a?c clock domains use this clock. note: this clock input is 3.3 v tolerant. cha_rclkout/ chb_rclkout o cmos direct rdram* device clock out: this pin provides divided down versions of the direct rdram device clock as feedback to the direct rdram device clock synthesizers for phase alignment. note: this pin will only be driven to 1.8 v. cha_hclk0ut/ chb_hclkout o cmos host clock out: this pin provides divided down versions of the host clock as feedback to the direct rdram device clock synthesizers for phase alignment. note: this pin will only be driven to 1.8 v. rstin# i cmos reset in: when asserted this signal will asynchronously reset the mch logic. this signal is connected to the pcirst# output of the ich2. all agp output and bi-directional signals will also tri-state compliant to pci revision 2.0 and 2.1 specifications. this input should have a schmidt trigger to avoid spurious resets. note: this input needs to be 3.3 v tolerant. testin# i cmos test input: testin# is used for manufacturing and board level test purposes. this signal is internally pulled up to vddq. overt# i cmos overtemperature condition: this signal, when asserted, indicates that the direct rdram devices have exceeded the system designer?s target maximum temperature. the mch?s response to this signal is to shift the direct rdram device controller into the throttling/pool mode placed into the dps register. software should program this register with a value that is more conservative than the current value in order to make the overt# pin useful. it is internally pulled up to vddq.
signal description r 40 intel ? 82860 mch datasheet 2.9 voltage references, pll power signal name type description hdvref[3:0] host data reference voltage. reference voltage input for the 4x data signals of the host agtl+ interface. connect to 2/3 vtt with 2% tolerance. havref[1:0] host address reference voltage. reference voltage input for the 2x address signals of the host agtl+ interface. connect to 2/3 vtt with 2% tolerance. ccvref host common clock reference voltage. reference voltage input for the common clock signals of the host agtl+ interface. connect to 2/3 vtt with 2% tolerance. cha_ref[1:0] rambus* channel a reference: reference voltage input for the rambus channel a rsl interface. chb_ref[1:0] rambus channel b reference: reference voltage input for the rambus channel b rsl interface. gref_0 agp: reference voltage input for the agp interface. gref_1 agp: reference voltage input for the agp interface. hlref_a hub interface_a reference: reference voltage input for the hub interface_a. normal mode: connect to 1/2 vcc1_8 with 2% tolerance enhanced mode: connect to 2/3 vcc1_8 with 2% tolerance hlref_b hub interface_b reference: reference voltage input for the hub interface_b. connect to 2/3 vcc1_8 with 2% tolerance. hlref_c hub interface_c reference: reference voltage input for the hub interface_c. connect to 2/3 vcc1_8 with 2% tolerance. hlrcomp_a i/o cmos compensation for hub interface_a: this signal is used to calibrate the hub interface_a i/o buffers. normal mode: connect to 39 ? 1% or 40 ? 2% pull-down enhanced mode: connect to 30 ? 1% pull-down hlrcomp_b i/o cmos compensation for hub interface_b: this signal is used to calibrate the hub interface_b i/o buffers. refer to the intel ? xeon? processor and intel ? 860 chipset platform design guide for proper connections. hlrcomp_c i/o cmos compensation for hub interface_c: this signal is used to calibrate the hub interface_c i/o buffers. refer to the intel ? xeon? processor and intel ? 860 chipset platform design guide for proper connections. grcomp i/o cmos compensation for agp: this signal is used to calibrate agp buffers. connect to a 39 ? with a 1% tolerance or a 40 ? with a 2% tolerance pull-down. hrcomp[1:0] i/o cmos compensation for host: this signal is used to calibrate the host agtl+ i/o buffers. connect to 20.75 ? with a 1% tolerance pull-down. hswng[1:0] i cmos host compensation reference voltage: reference voltage input for the compensation logic. connect to 1/3 vtt with a 2% tolerance.
signal description r intel ? 82860 mch datasheet 41 signal name type description hlswng_b i cmos hub interface_b compensation reference voltage: reference voltage input for the compensation logic. connect to 1/3 vcc1_8 with a 2% tolerance. hlswng_c i cmos hub interface_c compensation reference voltage: reference voltage input for the compensation logic. connect to 1/3 vcc1_8 with a 2% tolerance. hl1_8 i cmos connect to vcc1_8 g_swng i cmos agp compensation reference voltage: reference voltage input for the compensation logic. hooked to gref_0. vcc1_8 power: the 1.8 v power input pins vcc1_8rac power: the 1.8 v rac power pins vddq power: the power supply input for the agp i/o supply (1.5 v) vtt power: the agtl+ bus termination voltage inputs vss ground 2.10 strap signals this table indicates the strap options invoked by various mch signal pins. pin strap name description buspark system bus bus parking this signal is reflected on ha15# to configure the processor(s) in system bus parking enabled mode. this signal has an internal pull-up to vddq. bus parking should be enabled for single processor systems and disabled for dual processor systems. hla_enh# hub interface_a enhanced mode enable this signal is used as the hl_a normal/enhanced mode operation strap. this signal has an internal pull-up to vddq. 2.11 pin states during reset table 5 indicates the mch signal pin states during reset assertion. z tri-state outputs iso isolate inputs in inactive state s strap sampled on rstin# rising edge h driven high l driven low d drive outputs to functional logic level i input active u undefined ? indeterminate
signal description r 42 intel ? 82860 mch datasheet table 5. pin states during reset signal name state during rstin# assertion host interface cpurst# l ha[35:8,6:3]# z/i ha7# z/i/s hadstb[1:0]# z/i hd[63:0]# z/i hdstbp[3:0]# z/i hdstbn[3:0]# z/i dbi[3:0]# z/i ads# z/i bnr# z/i bpri# z/i dbsy# z/i defer# z/i drdy# z/i hit# z/i hitm# z/i hlock# z/i hreq[4:0]# z/i htrdy# z/i rs[2:0]# z/i br0# z/i ap[1:0]# z/i rsp# z/i dp[3:0]# z/i hdvref[3:0] i havref[1:0] i ccvref i hrcomp[1:0] z hswng[1:0] i rambus* channel a dqa_a[8:0] z dqb_a[8:0] z rq_a[7:0] z ctm_a i signal name state during rstin# assertion ctm_a# i cfm_a z cfm_a# z exp_a[1:0] z sck_a l cmd_a z sio_a z cha_ref[1:0] i rambus channel b chb_dqa[8:0] z chb_dqb[8:0] z chb_rq[7:0] z chb_ctm i chb_ctm# i chb_cfm z chb_cfm# z exp_b[1:0] z chb_sck l chb_cmd z chb_sio z chb_ref[1:0] i agp pipe# i sba[7:0] iso rbf# i wbf# i g_req# i st[2:0] l g_gnt# h ad_stb[1:0] z ad_stb[1:0]# z sb_stb i sb_stb# i g_ad[31:0] l/i g_c/be[3:0]# l/i signal name state during rstin# assertion g_frame# z/i g_irdy# z/i g_trdy# z/i g_stop# z/i g_devsel# z/i g_par l/i g_serr# i hub interface_a (normal mode) hl_a11 l/i hl_a10 l/i hl_a9 l/i hl_a8 l hl_a[7:4] l/i hl_a[3:0] z hla_stb l/i hla_stb# h hlrcomp_a z hlref_a i hub interface_a (enhanced mode) hl_a11 z/i hl_a10 z/i hl_a9 l/i hl_a8 h hl_a[7:4] z/i hl_a[3:0] z/i hla_stb z/i hla_stb# z/i hlrcomp_a z hlref_a i
signal description r intel ? 82860 mch datasheet 43 signal name state during rstin# assertion hub interface_b (enhanced mode) hl_b19 z/i hl_b18 z/i hl_b17 l/i hl_b16 h hl_b[15:0] z/i hlb_stb[1:0] z/i hlb_stb[1:0]# z/i hlrcomp_b z hlref_b i signal name state during rstin# assertion hub interface_c (enhanced mode) hl_c19 z/i hl_c18 z/i hl_c17 l/i hl_c16 h hl_c[15:0] z/i hlc_stb[1:0] z/i hlc_stb[1:0]# z/i hlrcomp_c z hlref_c i signal name state during rstin# assertion clocks and misc. bclk[1:0] i 66in i cha_hclkout d chb_hclkout d cha_rclkout d chb_rclkout d rstin# i testin# i
signal description r 44 intel ? 82860 mch datasheet this page is intentionally left blank.
register description r intel ? 82860 mch datasheet 45 3 register description the mch contains two sets of software accessible registers, accessed via the host i/o address space: ? control registers i/o mapped into the host i/o space, which control access to pci and agp configuration space (see section titled i/o mapped registers ) ? internal configuration registers residing within the mch are partitioned into two logical device register sets (?logical? since they reside within a single physical device). the first register set is dedicated to host-hub interface bridge functionality (controls pci_a such as dram configuration, other chip-set operating parameters and optional features). the second register block is dedicated to host-agp bridge functions (controls agp interface configurations and operating parameters). the mch supports pci configuration space accesses using the mechanism denoted as configuration mechanism #1 in the pci specification. the mch internal registers (i/o mapped, and configuration registers) are accessible by the host. the registers can be accessed as byte, word (16-bit), or dword (32-bit) quantities, with the exception of conf_addr, which can only be accessed as a dword. all multi-byte numeric fields use ?little-endian? ordering (i.e., lower addresses contain the least significant parts of the field). 3.1 register terminology term description ro read only . if a register is read only, writes to this register have no effect. r/w read/write . a register with this attribute can be read and written. r/w/l read/write/lock . a register with this attribute can be read, written, and locked. r/wc read/write clear . a register bit with this attribute can be read and written. however, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect. r/wo read/write once. a register bit with this attribute can be written to only once after power up. after the first write, the bit becomes read only. l lock. a register bit with this attribute becomes read only after a lock-bit is set. reserved bits some of the mch registers described in this section contain reserved bits. these bits are labeled ?reserved?. software must deal correctly with fields that are reserved. on reads, software must use appropriate ma sks to extract the defi ned bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note that software does not need to perform read, merge, write operation for the configuration address (conf_addr) register.
register description r 46 intel ? 82860 mch datasheet term description reserved registers in addition to reserved bits within a register, the mch contains address locations in the configuration space that are marked ?reserved?. when a ?reserved? register location is read, a random value is returned. (?reserved? registers can be 8-, 16-, or 32-bit in size). registers that are marked as ?reserved? must not be modified by system software. writes to ?reserved? registers may cause system failure. default value upon a reset upon a full reset, the mch sets all of its internal configuration registers to predetermined default states. some register values at reset are determined by external strapping options. the default state represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the dram configurations, operating parameters and optional system features that are applicable, and to program the mch registers accordingly. 3.2 pci configuration space access hub interface_a physically connects the mch and ich2. from a configuration standpoint, hub interface_a is logically pci bus #0. as a result, all devices internal to the mch and ich2 appear to be on pci bus #0. the system?s primary pci expansion bus is physically attached to the ich2 and, from a configuration perspective, appears to be a hierarchical pci bus behind a pci-to-pci bridge and therefore has a programmable pci bus number. note that the primary pci bus is referred to as pci_a in this document and is not pci bus #0 from a configuration standpoint. the agp and 16-bit hub interface ports appear to system software to be real pci busses behind pci-to-pci bridges resident as devices on pci bus #0. the mch contains up to four pci devices within a single physical component. the configuration registers for the six devices are mapped as devices residing on pci bus #0. ? device 0: host-hub interface_a bridge/dram controller. logically this appears as a pci device residing on pci bus #0. physically device 0 contains the standard pci registers, dram registers, the graphics aperture controller, and other mch specific registers. ? device 1: host-agp bridge. logically this appears as a ?virtual? pci-to-pci bridge residing on pci bus #0. physically device 1 contains the standard pci-to-pci bridge registers and the standard agp configuration registers (including the agp i/o and memory address mapping). ? device 2: host-hub interface_b bridge. logically this bridge appears to be a pci-to-pci bridge device residing on pci bus #0. physically, device 2 contains the standard pci-to-pci registers. ? device 3: host-hub interface_c bridge. logically this bridge appears to be a pci-to-pci bridge device residing on pci bus #0. physically, device 3 contains the standard pci-to-pci registers.
register description r intel ? 82860 mch datasheet 47 the following table shows the device # assignment for the various internal mch devices: mch function bus #0, device # function # dram controller/8-bit hub interface_a controller device 0 function #0 host-to-agp bridge (virtual p2p) device 1 function #0 host-to-16-bit hub interface_b bridge (p2p) device 2 function #0 host-to-16-bit hub interface_c bridge (p2p) device 3 function #0 the mch automatically detects if devices are connected to hub interface_b or hub interface_c by sampling the hl[11] signal on the rising edge of rstin#. when a hub interface is unpopulated, the associated configuration register space is hidden, returning all 1s for all registers just as if the cycle terminated with a master abort on pci. if hub interface_c is used, then hub interface_b must be populated with an intel p64h. note: physical pci bus #0 does not exist. the hub interface_a and the internal devices in the mch and ich2 logically constitute pci bus #0 to configuration software. standard pci bus configuration mechanism the pci bus defines a slot based ?configuration space? that allows each device to contain up to eight functions with each function containing up to 256, 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the mch. the pci specification defines two mechanisms to access configuration space, mechanism #1 and mechanism #2. the mch supports only mechanism #1. the configuration access mechanism makes use of the conf_addr register and conf_data register. to reference a configuration register a dword i/o write cycle is used to place a value into conf_addr that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. conf_addr[31] must be 1 to enable a configuration cycle. conf_data then becomes a window into the four bytes of configuration space specified by the contents of conf_addr. any read or write to conf_data will result in the mch translating the conf_addr into the appropriate configuration cycle. the mch is responsible for translating and routing the processor?s i/o accesses to the conf_addr and conf_data registers to internal mch configuration registers, hub interface_a?c or agp. routing configuration accesses the mch supports up to four bus interfaces: hub interface_a?c, and agp. pci configuration cycles are selectively routed to one of these interfaces. the mch is responsible for routing pci configuration cycles to the proper interface. pci configuration cycles to ich2 internal devices and primary pci (including downstream devices) are routed to the ich2 via hub interface_a. pci configuration cycles to one of the 16-bit hub interfaces are routed to hub interface_b?c. agp configuration cycles are routed to agp. the agp interface is treated as a separate pci bus from
register description r 48 intel ? 82860 mch datasheet the configuration point of view. routing of configuration accesses to hub interface_b?c and agp is controlled via the standard pci-pci bridge mechanism using information contained within the primary bus number, the secondary bus number, and the subordinate bus number registers of the corresponding pci-pci bridge device. logical pci bus #0 configuration mechanism the mch checks the bus number (bits 23:16) and the device number fields of the conf_addr register. if the bus number field of conf_addr is 0, the configuration cycle is targeting a pci bus #0 device. ? the host-hub interface_a bridge entity within the mch is hardwired as device 0 on pci bus #0. ? the host-agp bridge entity within the mch is hardwired as device 1 on pci bus #0. ? the host-hub interface_b bridge entity within the mch is hardwired as device 2 on pci bus #0. ? the host-hub interface_c bridge entity within the mch is hardwired as device 3 on pci bus #0. configuration cycles to any of the mch?s internal devices are confined to the mch and not sent over hub interface_a. accesses to disabled mch internal devices, or devices #7 to #31 will be forwarded over hub interface_a as type 0 configuration cycles. primary pci and downstream configuration mechanism if the bus number in the conf_addr is non-zero, and is less than the values programmed into any of the internal mch device?s secondary bus number registers or greater than the values programmed into the subordinate bus number registers, the mch will generate a type 1 hub interface_a configuration cycle. the ich2 compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its p2p bridges to determine if the configuration cycle is meant for primary pci or a downstream pci bus. agp bus configuration mechanism from the chipset configuration perspective, agp is seen as pci bus interfaces residing on a secondary bus side of the ?virtual? pci-pci bridges referred to as the mch host-agp bridge. on the primary bus side, the ?virtual? pci-pci bridge is attached to pci bus #0. therefore, the primary bus number register is hardwired to 0. the ?virtual? pci-pci bridge entity converts type #1 pci bus configuration cycles on pci bus #0 into type 0 or type 1 configuration cycles on the agp interface. type 1 configuration cycles on pci bus #0 that have a bus number that matches the secondary bus number of one of the mch?s ?virtual? p2p bridges will be translated into type 0 configuration cycles on the agp interface. if the bus number is non-zero, greater than the value programmed into the secondary bus number register, and less than or equal to the value programmed into the subordinate bus number register, the mch will generate a type 1 pci configuration cycle on agp.
register description r intel ? 82860 mch datasheet 49 3.3 i/o mapped registers the mch contains a set of registers that reside in the host i/o address space ? the configuration address (conf_addr) register and the configuration data (conf_data) register. the configuration address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window. 3.3.1 conf_addr?configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: read/write size: 32 bits conf_addr is a 32-bit register that can be accessed only as a dword. a byte or word reference will ?pass through? the configuration address register and hub interface_a onto the pci bus as an i/o cycle. the conf_addr register contains the bus number, device number, function number, and register number for which a subsequent configuration access is intended. bit descriptions 31 configuration enable (cfge). 1 = enable 0 = disable 30:24 reserved. these bits are read only and have a value of 0. 23:16 bus number. when the bus number is programmed to 00h the target of the configuration cycle is a hub interface agent (mch, ich2, etc.). the configuration cycle is forwarded to hub interface_a if the bus number is programmed to 00h and the mch is not the target (the device number is 4). if the bus number is non-zero and matches the value programmed into the secondary bus number register of device 1, a type 0 pci configuration cycle will be generated on agp. if the bus number is non-zero, greater than the value in the secondary bus number register of device 1 and less than or equal to the value programmed into the subordinate bus number register of device 1 a type 1 pci configuration cycle will be generated on agp. if the bus number is non-zero and matches the value programmed into the secondary bus number register of device 2?3 a type 0 pci configuration cycle will be generated on the corresponding hub interface_b?c. if the bus number is non-zero, and less than or equal to the value programmed into the subordinate bus number register of device 2?3 a type 1 pci configuration cycle will be generated on the corresponding hub interface_b?c. if the bus number is non-zero, and does not fall within the ranges enumerated by device 1?3?s secondary bus number or subordinate bus number register, then a hub interface_a type 1 configuration cycle is generated.
register description r 50 intel ? 82860 mch datasheet bit descriptions 15:11 device number. this field selects one agent on the pci bus selected by the bus number. when the bus number field is ?00? the mch decodes the device number field. the mch is always device number 0 for the host-hub interface_a bridge entity, device number 1 for the host-agp entity, and device number 2?3 for the host-hub interface_b?c entities respectively. therefore, when the bus number = 0 and the device number = 0?3, the internal mch devices are selected. if the bus number is non-zero and matches the value programmed into the secondary bus number register, a type 0 pci configuration cycle will be generated on agp. the mch decodes the device number field [15:11] and asserts the appropriate gad signal as an idsel. for pci-to-pci bridge translation, one of the 16 idsels is generated. when bit 15 = 0, bits [14:11] are decoded to assert a signal ad[31:16] idsel. gad16 is asserted to access device 0, gad17 for device 1, and so forth up to device 15 for which will assert ad31. all device numbers higher than 15 cause a type 0 configuration access with no idsel asserted, which will result in a master abort reported in the mch?s ?virtual? pci-pci bridge registers. for bus numbers resulting in hub interface_a?c configuration cycles, the mch propagates the device number field as a[15:11]. for bus numbers resulting in agp/pci_b type 1 configuration cycles, the device number is propagated as gad[15:11]. 10:8 function number. this field is mapped to gad[10:8] during agp configuration cycles and a[10:8] during hub interface_a?c configuration cycles. this allows the configuration registers of a particular function in a multi-function device to be accessed. the mch ignores configuration cycles to its internal devices if the function number is not equal to 0. 7:2 register number . this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to gad[7:2] during agp configuration cycles and a[7:2] during hub interface_a?c configuration cycles. 1:0 reserved 3.3.2 conf_data?configuration data register i/o address: 0cfch default value: 00000000h access: read/write size: 32 bits conf_data is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by conf_data is determined by the contents of conf_addr. bit descriptions 31:0 configuration data window (cdw). if bit 31 of conf_addr is 1, any i/o access to the conf_data register will be mapped to configuration space using the contents of conf_addr.
register description r intel ? 82860 mch datasheet 51 3.4 host-hub interface_a bridge device registers (device 0) table 6 shows the address map and describes the access attributes for the device 0 configuration space. an ?s? in the default value field means that a strap determines the power-up default value for that bit. table 6. mch configuration space (device 0) address offset register symbol register name default value access 00?01h vid vendor identification 8086h ro 02?03h did device identification 2531h ro 04?05h pcicmd pci command register 0006h ro, r/w 06?07h pcists pci status register 0090h ro, r/wc 08h rid revision identification 04h ro 0ah subc sub-class code 00h ro 0bh bcc base class code 06h ro 0dh mlt master latency timer 00h ro 0eh hdr header type 00h ro 10?13h apbase aperture base configuration 00000008h ro, r/w 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 34h capptr capabilities pointer a0h ro 40?4fh gar[0:15] rdram* device group architecture register [0:15] 80h ro, r/w 50?51h mchcfg mch configuration 000000000 0000s00b ro, r/w 52?57h ? reserved ? ? 58h fdhc fixed dram hole control 00h ro, r/w 59?5fh pam[0:6] programmable attribute map [0:6] 00h ro, r/w 60?61h gba0 rdram device group boundary address 0 0001h ro, r/w 62?63h gba1 rdram device group boundary address 1 0001h ro, r/w 64?65h gba2 rdram device group boundary address 2 0001h ro, r/w 66?67h gba3 rdram device group boundary address 3 0001h ro, r/w 68?69h gba4 rdram device group boundary address 4 0001h ro, r/w 6a?6bh gba5 rdram device group boundary address 5 0001h ro, r/w 6c?6dh gba6 rdram device group boundary address 6 0001h ro, r/w 6e?6fh gba7 rdram device group boundary address 7 0001h ro, r/w
register description r 52 intel ? 82860 mch datasheet address offset register symbol register name default value access 70?71h gba8 rdram device group boundary address 8 0001h ro, r/w 72?73h gba9 rdram device group boundary address 9 0001h ro, r/w 74?75h gba10 rdram device group boundary address a 0001h ro, r/w 76?77h gba11 rdram device group boundary address b 0001h ro, r/w 78?79h gba12 rdram device group boundary address c 0001h ro, r/w 7a?7bh gba13 rdram device group boundary address d 0001h ro, r/w 7c?7dh gba14 rdram device group boundary address e 0001h ro, r/w 7e?7fh gba15 rdram device group boundary address f 0001h ro, r/w 80?87h ? reserved ? ? 88h rdps rdram device pool sizing register 10h ro, wo, l 90?93h drd rdram device register data 00000000h r/w 94?97h ricm rdram device initialization control management 00000000h ro, r/w 98?9bh ? reserved ? ? 9dh smram system management ram control 02h ro, r/w, l 9eh esmramc extended system management ram control 38h ro, r/w, r/wc, l 9fh ? reserved ? ? a0?a3h acapid agp capability identifier 00200002h ro a4?a7h agpstat agp status register 1f000217h ro a8?abh agpcmd agp command register 00000000h ro, r/w b0?b3h agpctrl agp control register 00000000h ro, r/w b4h apsize aperture size 00h ro, r/w b8?bbh attbase aperture translation table 00000000h ro, r/w bch amtt agp mtt control register 00h ro, r/w bdh lptt agp low priority transaction timer register 00h ro, r/w beh rdt rdram device timing 00h r/w bf?c3h ? reserved ? ? c4?c5h tom top of low memory register 0000h r/w c6?c7h ? reserved ? ? c8?c9h errsts error status register 0000h r/wc ca?cbh errcmd error command register 0000h r/w cc?cdh smicmd smi command register 0000h ro, r/w ce?cfh scicmd sci command register 0000h ro, r/w d0?dbh ? reserved ? ? dc?ddh dramrc rdram device refresh control 0000h ro, r/w
register description r intel ? 82860 mch datasheet 53 address offset register symbol register name default value access de?dfh skpd scratchpad data 0000h r/w e2?e3 derrctl dram error control register 0000h ro e4?e7h eap dram error data register 00000000h ro e8?f3h ? reserved ? ? f4?f7h misc_cntl miscellaneous control register 0000f874h r/w f8?ffh ? reserved ? ? 3.4.1 vid?vendor identification register (device 0) address offset: 00?01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register, combined with the device identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel. intel vid = 8086h. 3.4.2 did?device identification register (device 0) address offset: 02?03h default value: 2531h attribute: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number. this is a 16-bit value assigned to the mch host-hub interface_a bridge function #0.
register description r 54 intel ? 82860 mch datasheet 3.4.3 pcicmd?pci command register (device 0) address offset: 04?05h default: 0006h access: read/write, read only size 16 bits since mch device 0 does not physically reside on pci0 many of the bits are not implemented. writes to bits that are not implemented have no affect. bit descriptions 15:10 reserved 9 fast back-to-back?ro. not implemented; hardwired to 0. this bit controls whether or not the master can do fast back-to-back write. since device 0 is strictly a target this bit is not implemented. 8 serr enable (serre)?r/w. this bit is a global enable bit for device 0 serr messaging. the mch does not have an serr# signal. the mch communicates the serr# condition by sending an serr message to the ich2. 1 = enable. mch is enabled to generate serr messages over hub interface_a for specific device 0 error conditions that are individually enabled in the errcmd register. the error status is reported in the errsts and pcists registers. 0 = disable. note: this bit only controls serr message for the device 0. devices 1-5 have their own serre bits to control error reporting for error conditions occurring on their respective devices. 7 address/data stepping?ro. not implemented; hardwired to 0. 6 parity error enable (perre)?r/w. 1 = mch will generate an serr message over hub interface_a to the ich2 when an address or data parity error is detected by the mch on hub interface_a (dpe set in pcists). 0 = mch does not take any action when it detects a parity error on hub interface_a. 5 vga palette snoop?ro. not implemented; hardwired to 0. 4 memory write and invalidate enable (mwie)?ro. not implemented; hardwired to 0. 3 special cycle enable(sce)?ro. not implemented; hardwired to 0. 2 bus master enable (bme)?ro. not implemented; hardwired to 1. the mch is always enabled as a master on hub interface_a. 1 memory access enable (mae)?ro. not implemented; hardwired to 1.the mch always allows access to main memory. 0 i/o access enable (ioae)?ro. not implemented; hardwired to 0.
register description r intel ? 82860 mch datasheet 55 3.4.4 pcists?pci status register (device 0) address offset: 06?07h default value: 0090h access: read only, read/write clear size: 16 bits pcists is a 16-bit status register that reports the occurrence of error events on devices on the hub interface (device 0s). since mch device 0 is the host-to-hub interface_a bridge, many of the bits are not implemented. bit description 15 detected parity error (dpe)?r/wc . 1 = mch detects a parity error on hub interface_a. 0 = software clears this bit by writing a 1 to it. 14 signaled system error (sse)?r/wc . 1 = device 0 generates an serr message over hub interface_a for any enabled device 0 error condition. device 0 error conditions are enabled in the pcicmd and errcmd registers. device 0 error flags are read/reset from the pcists or errsts registers. 0 = software sets sse to 0 by writing a 1 to this bit. 13 received master abort status (rmas)?r/wc . 1 = mch generates a hub interface_a request that receives a master abort completion packet or master abort special cycle. 0 = software sets sse to 0 by writing a 1 to this bit. 12 received target abort status (rtas)?r/wc. 1 = mch generates a hub interface_a request that receives a target abort completion packet or target abort special cycle. 0 = software sets sse to 0 by writing a 1 to this bit. 11 signaled target abort status (stas)?ro. not implemented; hardwired to 0. the mch will not generate a target abort hub interface_a completion packet or special cycle. 10:9 devsel timing (devt) . hardwired to 00. hub interface does not comprehend devsel# protocol. 8 master data parity error detected (dpd)?ro. hardwired to 0. perr signaling and messaging are not implemented by the mch. 7 fast back-to-back (fb2b)?ro . hardwired to 1. 6:5 reserved 4 capability list (clist)?ro. 1 = indicates to the configuration software that this device/function implements a list of new capabilities. a list of new capabilities is accessed via register capptr at configuration address offset 34h. register capptr contains an offset pointing to the start address within configuration space of this device where the agp capability standard register resides. 3:0 reserved
register description r 56 intel ? 82860 mch datasheet 3.4.5 rid?revision identification register (device 0) address offset: 08h default value: 04h access: read only size: 8 bits this register contains the revision number of the mch device 0. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number. this is an 8-bit value that indicates the revision identification number for the mch device 0. a-3 stepping = 04h. 3.4.6 subc?sub-class code register (device 0) address offset: 0ah default value: 00h access: read only size: 8 bits this register contains the sub-class code for the mch device 0. bit description 7:0 sub-class code (subc) . this is an 8-bit value that indicates the category of bridge for the mch. 00h = host bridge. 3.4.7 bcc?base class code register (device 0) address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the mch device 0. bit description 7:0 base class code (basec) . this is an 8-bit value that indicates the base class code for the mch. 06h = bridge device.
register description r intel ? 82860 mch datasheet 57 3.4.8 mlt?master latency timer register (device 0) address offset: 0dh default value: 00h access: read only size: 8 bits the hub interface does not comprehend the concept of master latency timer. therefore, this register is not implemented. bit description 7:0 these bits are hardwired to 0. writes have no effect. 3.4.9 hdr?header type register (device 0) offset: 0eh default: 00h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit description 7:0 this read only field always returns 0s when read and writes have no affect. 3.4.10 apbase?aperture base configuration register (device 0) offset: 10?13h default: 00000008h access: read/write, read only size: 32 bits the apbase is a standard pci base address register that is used to set the base of the graphics aperture. the standard pci configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to 0 or behave as hardwired to 0). to allow for flexibility (of the aperture), an additional register called apsize is used as a ?back-end? register to control which bits of the apbase will behave as hardwired to 0. this register will be programmed by the mch specific bios code that will run before any of the generic configuration software is run. note: bit 9 of the mchcfg register is used to prevent accesses to the aperture range before configuration software initializes this register and the appropriate translation table structure has been established in the main memory.
register description r 58 intel ? 82860 mch datasheet bit description 31:28 upper programmable base address bits?r/w. these bits are used to locate the range size selected via lower bits 27:4. default = 0000 27:22 lower ?hardwired?/programmable base address bits?r/w. these bits behave as a ?hardwired? or as programmable depending on the contents of the apsize register as defined below: 27 26 25 24 23 22 aperture size r/w r/w r/w r/w r/w r/w 4 mb r/w r/w r/w r/w r/w 0 8 mb r/w r/w r/w r/w 0 0 16 mb r/w r/w r/w 0 0 0 32 mb r/w r/w 0 0 0 0 64 mb r/w 0 0 0 0 0 128 mb 0 0 0 0 0 0 256 mb bits 27:22 are controlled by the bits 5:0 of the apsize register in the following manner: ? if bit apsize[5]=0, apbase[27]=0. if apsize[5]=1, apbase[27]=r/w. the same applies correspondingly to other bits. ? default for apsize[5:0]=000000b forces default apbase[27:22] =000000b (i.e., all bits respond as hardwired to 0). this provides a default to the maximum aperture size of 256 mb. the mch specific bios is responsible for selecting smaller size (if required) before pci configuration software runs and establishes the system address map. 21:4 hardwired to 0. this forces minimum aperture size selected by this register to be 4 mb. 3 prefetchable?ro. this bit is hardwired to 1 to identify the graphics aperture range as prefetchable (i.e., there are no side effects on reads, the device returns all bytes on reads regardless of the byte enables, and the mch may merge processor writes into this range without causing errors). 2:1 type?ro. these bits determine addressing type and they are hardwired to 00 to indicate that the address range defined by the upper bits of this register can be located anywhere in the 32-bit address space. 0 memory space indicator?ro. hardwired to 0 to identify aperture range as a memory range. 3.4.11 svid?subsystem vendor id register (device 0) offset: 2c?2dh default: 0000h access: read/write once size: 16 bits this value is used to identify the vendor of the subsystem. bit description 15:0 subsystem vendor id. the default value is 00h. this field should be programmed during boot- up. after this field is written once, it becomes read only.
register description r intel ? 82860 mch datasheet 59 3.4.12 sid?subsystem id register (device 0) offset: 2e?2fh default: 0000h access: read/write once size: 16 bits this value is used to identify a particular subsystem. bit description 15:0 subsystem id (r/wo). the default value is 00h. this field should be programmed during boot- up. after this field is written once, it becomes read only. 3.4.13 capptr?capabilities pointer register (device 0) offset: 34h default: agp?a0h access: read only size: 8 bits the capptr provides the offset that is the pointer to the location where the agp standard registers are located. bit description 7:0 pointer to the start of agp standard register block. this pointer indicates where software can find the beginning of the agp register block. the value in this field is a0h when the agp interface is configured for agp mode.
register description r 60 intel ? 82860 mch datasheet 3.4.14 gar[0:15]?rdram* device group architecture register (device 0) address offset: 40?4fh default value: 80h access: read/write, read only size: 8 bits/register this 8-bit register defines the #of banks and dram technology of each device group in the rambus channel. there are 16 gar registers (gar0?gar15) that are used to define 16 groups for the rambus channel. bit description 7:6 device page size (dps). this field defines the page size of the each device in the corresponding group. 00 = reserved 01 = reserved 10 = 1 kb 11 = 2 kb 5 reserved 4 device banks (db). this field defines the number of bank architecture in each device in the group. 0 = 16 dependent banks 1 = 32 dependent banks arranged in two groups of 16 dependent banks (i.e., 2x16) 3 reserved 2:1 device dram technology (ddt). this field defines the dram technology of each device in the group. 00 = reserved 01 = 128/144mbit 10 = 256/288mbit 11 = reserved 0 reserved
register description r intel ? 82860 mch datasheet 61 3.4.15 mchcfg?mch configuration register (device 0) offset: 50?51h default: 0000_0000_ 0000_0s00b access: read/write once, read/write, read only size: 16 bits bit description 15:13 number of stop grant cycles?r/w. number of stop grant transactions expected on the host bus before a stop grant acknowledge packet is sent to the ich2. this field is programmed by the bios after it has enumerated the processors and before it has enabled stop clock generation in the ich2. note that each enabled thread within each processor will generate stop grant acknowledge transactions. bits[15:13] hl_a stop grant generated after 000 1 system bus stop grant (default) 001 2 system bus stop grants 010 3 system bus stop grants 011 4 system bus stop grants 100 5 system bus stop grants 101 6 system bus stop grants 110 7 system bus stop grants 111 8 system bus stop grants 12 reserved 11 direct rdram* device frequency?r/w. these bits are written by the bios after polling the direct rdram devices and finding the least common denominator speed. 0 = 300 mhz (default) 1 = 400 mhz 10 reserved 9 aperture access global enable?r/w. this bit is used to prevent access to the graphics aperture from any port (host, hub interface_a, hub interface_b, hub interface_c, or agp) before configuration software establishes the aperture range and appropriate translation table in the main dram has been initialized. it must be set after system is fully configured for aperture accesses. 1 = enable 0 = disable (default) 8:7 dram data integrity mode (ddim)?r/w. these bits select one of two dram data integrity modes. 00 = non-ecc (byte-wise writes supported, rdram device only) (default) 01 = reserved 10 = ecc mode (generation and error checking/correction) 11 = reserved 6 reserved
register description r 62 intel ? 82860 mch datasheet bit description 5 mda present (mdap)?r/w. this bit works with the vga enable bit in the bctrl register of device 1?3 to control the routing of host-initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set when the vga enable bit is not set in either device 1?3. if the vga enable bit is set, accesses to io address range x3bch?x3bfh are forwarded to hub interface_a. mda resources are defined as follows: memory: 0b0000h?0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes the i/o locations listed above, or their aliases, will be forwarded to the hub interface_a even if the reference includes i/o locations not listed above. refer to the system address map section of this document for further information. 4:3 reserved 2 in-order queue depth (ioqd)?ro. this bit reflects the value sampled on ha7# on the deassertion of the cpurst#. it indicates the depth of the host bus in-order queue (i.e., level of host bus pipelining). if ioqd is set to 1 (i.e., ha7# sampled 1, undriven on the host bus), then the depth of the host bus in-order queue is configured to the maximum allowed by the host bus protocol (i.e., 12). note that the mch has an 8-deep ioq and asserts bnr# on the bus to limit the number of queued bus transactions to 8. if the ioqd bit is set to 0 (ha7# is sampled 0, asserted), then the depth of the host bus in-order queue is set to 1 (i.e., no pipelining support on the host bus). note: ha7# is not driven by the mch during cpurst#. if an ioq size of 1 is desired, ha7# must be driven low during cpurst# by an external source. 1 apic memory range disable (apicdis)?rw. 1 = disable. the mch forwards accesses to the ioapic regions to the appropriate interface, as specified by the memory and pci configuration registers. 0 = enable. the mch sends cycles between 0_fec0_0000 and 0_fec7_ffff to hub interface_a; accesses between 0_fec8_0000 and 0_fec8_0fff are sent to hub interface_b; accesses between 0_fec8_1000 and 0_fec8_1fff are sent to hub interface_c. 0 reserved
register description r intel ? 82860 mch datasheet 63 3.4.16 fdhc?fixed dram hole control register (device 0) address offset: 58h default value: 00h access: read/write, read only size: 8 bits this 8-bit register controls a fixed dram hole. bit description 7 hole enable (hen). this field enables a memory hole in dram space. host cycles matching an enabled hole are passed on to ich2 through the hub interface. the hub interface cycles matching an enabled hole will be ignored by the mch. note that a selected hole is not re-mapped. 0 = disable (no hole) 1 = enable. hole at 15 mb?16 mb (1 mb) 6:0 reserved. 3.4.17 pam[0:6]?programmable attribute map registers (device 0) address offset: 59?5fh default value: 00h attribute: read/write, read only size: 8 bits the mch allows programmable memory attributes on 13 legacy memory segments of various sizes in the 640-kb to 1-mb address range. seven programmable attribute map (pam) registers are used to support these features. cacheability of these areas is controlled via the mtrr registers in the processor. two bits are used to specify memory attributes for each memory segment. these bits apply to host initiator only access to the pam areas. mch will forward to main memory for any agp, pci or hub interface_a?c initiated accesses to the pam areas. these attributes are: ? re ( read enable) . when re = 1, the host read accesses to the corresponding memory segment are claimed by the mch and directed to main memory. conversely, when re = 0, the host read accesses are directed to pci0. ? we ( write enable) . when we = 1, the host write accesses to the corresponding memory segment are claimed by the mch and directed to main memory. conversely, when we = 0, the host write accesses are directed to pci0. the re and we attributes permit a memory segment to be read only, write only, read/write, or disabled. for example, if a memory segment has re = 1 and we = 0, the segment is read only. each pam register controls two regions, typically 16 kb in size. each of these regions has a 4-bit field. the four bits that control each region have the same encoding and are defined in the following table.
register description r 64 intel ? 82860 mch datasheet bits [7, 3] reserved bits [6, 2] reserved bits [5, 1] we bits [4, 0] re description x x 0 0 disabled. dram is disabled and all accesses are directed to the hub interface_a. the mch does not respond as a pci target for any read or write access to this area. x x 0 1 read only . reads are forwarded to dram and writes are forwarded to the hub interface_a for termination. this write protects the corresponding memory segment. the mch will respond as an agp or the hub interface_a target for read accesses but not for any write accesses. x x 1 0 write only . writes are forwarded to dram and reads are forwarded to the hub interface for termination. the mch will respond as an agp or hub interface_a target for write accesses but not for any read accesses. x x 1 1 read/write . this is the normal operating mode of main memory. both read and write cycles from the host are claimed by the mch and forwarded to dram. the mch will respond as an agp or the hub interface_a target for both read and write accesses. at the time that a hi or agp accesses to the pam region may occur, the targeted pam segment must be programmed to be both readable and writeable. as an example, consider bios that is implemented on the expansion bus. during the initialization process, bios can be shadowed in main memory to increase the system performance. when bios is shadowed in main memory, it should be copied to the same address location. to shadow bios, the attributes for that address range should be set to write only. bios is shadowed by first doing a read of that address. this read is forwarded to the expansion bus. the host then does a write of the same address, which is directed to main memory. after bios is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. table 7 and figure 3 show the pam registers and the associated attribute bits.
register description r intel ? 82860 mch datasheet 65 figure 3. pam register attribute bits pam re we re r r we r r 76543210 pam 6 pam5 pam4 pam3 pam2 pam1 pam0 read enable (r/ w 1=enable 0=disable write enable (r/w) 1=enable 0=disable reserved reserved read enable (r/w) 1=enable 0=disable write enable (r/w) 1=enable 0=disable reserved reserved 5fh 5eh 5dh 5ch 5bh 5ah 59h offset table 7. pam registers pam reg attribute bits memory segment comments offset pam0[3:0] reserved 59h pam0[7:4] r r we re 0f0000h?0fffffh bios area 59h pam1[3:0] r r we re 0c0000h?0c3fffh isa add-on bios 5ah pam1[7:4] r r we re 0c4000h?0c7fffh isa add-on bios 5ah pam2[3:0] r r we re 0c8000h?0cbfffh isa add-on bios 5bh pam2[7:4] r r we re 0cc000h?0cffffh isa add-on bios 5bh pam3[3:0] r r we re 0d0000h?0d3fffh isa add-on bios 5ch pam3[7:4] r r we re 0d4000h?0d7fffh isa add-on bios 5ch pam4[3:0] r r we re 0d8000h?0dbfffh isa add-on bios 5dh pam4[7:4] r r we re 0dc000h?0dffffh isa add-on bios 5dh pam5[3:0] r r we re 0e0000h?0e3fffh bios extension 5eh pam5[7:4] r r we re 0e4000h?0e7fffh bios extension 5eh pam6[3:0] r r we re 0e8000h?0ebfffh bios extension 5fh pam6[7:4] r r we re 0ec000h?0effffh bios extension 5fh
register description r 66 intel ? 82860 mch datasheet for details on overall system address mapping scheme see the system address map section of this document. ? dos application area (00000h?9fffh): the dos area is 640 kb and is divided into two parts. the 512 kb area at 0 to 7ffffh is always mapped to the main memory controlled by the mch. the 128 kb address range from 080000 to 09ffffh can be mapped to pci0 or to main memory. by default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to pci0) via mch fdhc configuration register. ? video buffer area (a0000h?bffffh): attribute bits do not control this 128 kb area. the host -initiated cycles in this region are always forwarded to either pci0 or agp unless this range is accessed in smm mode. routing of accesses is controlled by the legacy vga control mechanism of the ?virtual? pci-pci bridge device embedded within the mch. this area can be programmed as smm area via the smram register. when used as a smm space, this range cannot be accessed from the hub interface or agp. ? expansion area (c0000h?dffffh): this 128 kb area is divided into eight 16 kb segments that can be assigned with different attributes via pam control register as defined by table 7. ? extended system bios area (e0000h?effffh): this 64 kb area is divided into four 16 kb segments that can be assigned with different attributes via pam control register as defined by table 7. ? system bios area (f0000h?fffffh): this area is a single 64 kb segment that can be assigned with different attributes via pam control register as defined by the table above.
register description r intel ? 82860 mch datasheet 67 3.4.18 gba[0:15]?rdram* device group boundary address register (device 0) address offset: 60?7fh default: 0001h access: read/write size 16 bits/register this register is locked and becomes read only when the d_clk bit in the smram register is set. this is done to improve smm security. the direct rdram device-pairs are logically arranged into groups. there are eight groups when the mch is configured for single channel-pair mode operation (no repeater hubs), and there are four groups for multiple channel-pair mode operation (with repeater hubs). each group requires a separate gba register. the gba registers define group id and the upper and lower addresses for each group in a channel-pair. contents of bits 0:10 of this register represent the boundary addresses in 16-mb granularity. for example, a value of 01h indicates that the programmed group applies to memory below 16 mb. only the first eight gba registers are used in single channel-pair mode. all 16 gba registers are used in multiple channel-pair mode. note that gba15 must always contain the group boundary address that points to the tom, whether the mch is being used in single channel-pair mode or multiple channel-pair mode. 60?61h gba0 = total memory in group0 (in 16 mb) 62?63h gba1 = total memory in group0 + group1 (in 16 mb) 64?65h gba2 = total memory in group0 + group1 + group2 (in 16 mb) 66?67h gba3 = total memory in group0 + group1 + group2 + group3 (in 16 mb) 7e?7fh gba15 = total memory in group0 + group1 + group2 + ? + group15 (in 16 mb) bit description 15:14 channel id (chid). reflects the id of the rambus* channel described by this gba entry. this field is only used when intel ? mrh-r is present. 13:11 group id (gid). this 3-bit value is used to identify a logical group of direct rdram* devices. this value and appropriate address bits are used to generate the device rdram_d device id. note: all device-pairs populated in a group must be of the same memory technology. 10:0 group boundary address (gba). this 11-bit value is compared against address lines a[34:24] to determine the upper address limit of a particular group of devices (i.e., gba minus previous gba = group size).
register description r 68 intel ? 82860 mch datasheet 3.4.19 rdps?rdram* device pool sizing register (device 0) address offset: 88h default value: 10h access: read only, write once, lock size: 8 bits bit description 7 pool lock (lock). 1 = rdps register is read only. 0 = rdps register is read/write. 6 reserved 5 reinitialize direct rdram* device pools (poolinit). when the poolinit bit is set, the direct rdram device pools are reinitialized to the default value contained in this register. as long as this bit is 0, the other fields in this register may be modified without changing the behavior of the pools. only when this bit is set or when a thermal over-temperature condition occurs are the values programmed into this register re-examined by the pool logic. following a write of 1 to this bit, the new pool sizes will take effect and the dram interface logic will perform any operations (e.g., nap?ing devices) necessary to comply with the new pool constraints. when these compliance operations are completed and the mch is operating with the new pool settings, the poolinit bit is cleared to 0. software can poll the bit to check for completion of the pool mode transition prior to proceeding with test cases. note: while over-temperature conditions (during overt# or current calibration) do cause new pool values to be loaded, they do not have any effect on the contents of this bit. 4 pool c operating mode (pcs). 1 = all devices found neither in pool a nor in pool b are assumed to be in nap mode. 0 = all devices in pool c are assumed to be in standby mode. note: even though this bit defaults to 1 (which is pool c nap mode), the mch functionally defaults to pool c standby mode. this bit must be written to a 1 to invoke pool c nap mode. 3:2 pool a capacity (pac). this field defines the maximum number of direct rdram devices that can reside in pool a at a time. 00 = 1 01 = 2 10 = 4 11 = 8 1:0 pool b capacity (pbc). this field defines the maximum number of direct rdram devices that can reside in pool b at a time. 00 = 1 01 = 4 10 = 8 11 = 16
register description r intel ? 82860 mch datasheet 69 3.4.20 drd?rdram* device register data register (device 0) address offset: 90?93h default value: 0000h access: read/write size: 32 bits bit description 31:0 register data (rd). bits 31:0 contain the 32 bits of data to be written to a direct rdram* device register or the data read from a direct rdram device register as a result of iop execution. data will be valid when the iio bit of the ricm register has transitioned from 1 to 0. bits 31:16 apply to rambus* channel a and bits 15:0 apply to rambus channel b. 3.4.21 ricm?rdram* device initialization control management register (device 0) address offset: 94?97h default value: 00000000h access: read/write, read only size: 32 bits bit description 31:30 reserved 29:28 time to powerup (tpu). this field defines the total powerdown exit time for direct rdram* devices and corresponds to the direct rdram* device (pdna+tpdnb) timing. 00 = 42.0 s 01 = 34.5 s 10 = 27.0 s 11 = 19.5 s 27 initialization complete (ic). this bit is for hardware use. 1 = bios sets this bit to 1 after the initialization of the direct rdram device memory array is complete. 26:25 reserved 24 mrh-r present (mrhrp). 1 = this bit is asserted by software when it detects the presence of memory repeater hub for direct rdram device in the system. 23 initiate initialization operation (iio). the software must check to see if this bit is 0 before writing to it. 1 = execution of the initialization operation specified by iop starts. 0 = after the execution is completed, the mch clears this bit to 0. the operations that specify register data read from the direct rdram device will have the data valid in drd register when this is cleared to 0. 22 reserved
register description r 70 intel ? 82860 mch datasheet bit description 21:20 channel id (cid). this field specifies the channel address for which the initialization or the channel reset operation is initialed. 19 broadcast address (ba). 1 = initialization operation (iop) is broadcast to all devices. when this bit is set to 1, the dsa field is don?t care. 18:10 device register address (dra). this field specifies the register address for the registers read and write operations. 9:5 serial device/channel address (sdca). this 5-bit field specifies the serial device id of the direct rdram* device to which the initialization operation is targeted for the next sio command to be sent by mch. 4:0 initialization opcode (iop). this field specifies the initialization operation to be done on direct rdram devices. 00000 = rdram register read 10000 = rdram current calibration 00001 = rdram register write 10001 = rdram sio reset 00010 = rdram set reset 10010 = rdram powerdown exit 00011 = reserved 10011 = rdram powerdown entry 00100 = rdram set fast clock mode 10100 = rdram nap entry 00101 = rdram temperature calibrate enable 10101 = rdram nap exit 00110 = rdram temperature calibrate 10110 = rdram refresh 00111 = reserved 10111 = rdram precharge 01000 = mrh redirect next sio 11000 = manual current calibr. of mch rac 01001 = mrh stick sio reset 11001 = mch rac load rac a config. reg. 01010 = reserved 11010 = mch rac load rac b config. reg. 01011 = rdram clear reset 11011 = initialize mch rac 01100 = reserved 11100 = mch rac current calibration 01101 = reserved 11101 = mch rac thermal calibration 01110 = reserved 11110 = reserved 01111 = reserved 11111 = powerup all sequence
register description r intel ? 82860 mch datasheet 71 3.4.22 smram?system management ram control register (device 0) address offset: 9dh default value: 02h access: read/write, read only, lock size: 8 bits the smramc register controls how accesses to compatible and extended smram spaces are treated. the open, close, and lock-bits function only when g_smrame bit is set to a 1. also, the open bit must be reset before the lock-bit is set. a system device must not access the system management mode (smm) space through the graphic aperture gtlb. bit description 7 reserved 6 smm space open (d_open). 1 = open. when d_open=1 and d_lck=0, the smm space dram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software should ensure that d_open=1 and d_cls=1 are not set at the same time. when d_lck is set to a 1, d_open is reset to 0 and becomes read only. 0 = not open 5 smm space closed (d_cls). 1 = closed. smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space dram. this will allow smm software to reference ?through? smm space to update the display even when smm is mapped over the vga range. software should ensure that d_open=1 and d_cls=1 are not set at the same time. 0 = not closed note: that the d_cls bit only applies to compatible smm space. 4 smm space locked (d_lck). 1 = when d_lck is set to 1 then d_open is reset to 0 and d_lck, d_open, c_base_seg, h_smram_en, tseg_sz and tseg_en become ?read only?. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience with security. the bios can use the d_open function to initialize smm space and then use d_lck to ?lock down? smm space in the future so that no application software (or bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. 0 = can only be cleared by a full reset. 3 global smram enable (g_smrame). 1 = enable. compatible smram functions are enabled, providing 128 kb of dram accessible at the a0000h address while in smm (ads# with smm decode). to enable extended smram function this bit has to be set to 1. 0 = disable note: once d_lck is set, this bit becomes read only. 2:0 compatible smm space base segment (c_base_seg)?ro. this field indicates the location of smm space. ?smm dram? is not remapped. it is simply ?made visible? if the conditions are right to access smm space, otherwise the access is forwarded to the hub interface. c_base_seg is hardwired to 010 to indicate that the mch supports the smm space at a0000h? bffffh.
register description r 72 intel ? 82860 mch datasheet 3.4.23 esmramc?extended system management ram control register (device 0) address offset: 9eh default value: 38h access: read only, read/write, read/write clear, lock size: 8 bits the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mb. bit description 7 h_smram_en (h_smrame)?r/w. this bit controls the smm memory space location (i.e., above 1 mb or below 1 mb). 1 = when g_smrame is 1, the high smram memory space is enabled. smram accesses from feda0000h to fedbffffh are remapped to dram address 000a0000h?000bffffh. note: once d_lck is set, this bit becomes read only. 6 e_smram_err (e_smerr)?r/wc. 1 = the host accesses the defined memory ranges in extended smram (high memory and t-segment) while not in smm space and with the d-open bit = 0. 0 = it is software?s responsibility to clear this bit. the software must write a 1 to clear this bit. 5 smram_cache (sm_cache)?r/o. hardwired to 1. 4 smram_l1_en (sm_l1)?ro. hardwired to 1. 3 smram_l2_en (sm_l2)?ro. hardwired to 1. 2:1 tseg_sz[1:0] (t_sz)?r/w. this field selects the size of the tseg memory block if enabled. this memory is taken from the top of dram space (i.e., tom - tseg_sz), which is no longer claimed by the memory controller (all accesses to this space are sent to the hub interface if tseg_en is set). this field decodes as follows: 00 = (tom - 128 kb) to tom 01 = (tom - 256 kb) to tom 10 = (tom - 512 kb) to tom 11 = (tom - 1 mb) to tom note: once d_lck is set, this bit becomes read only. 0 tseg_en (t_en)?r/w. enabling of smram memory (tseg, 128 kb, 256 kb, 512 kb or 1 mb of additional smram memory) for extended smram space only. 1 = enable. when g_smrame =1 and tseg_en = 1, the tseg is enabled to appear in the appropriate physical address space. 0 = disable. note: once d_lck is set, this bit becomes read only.
register description r intel ? 82860 mch datasheet 73 3.4.24 acapid?agp capability identifier register (device 0) address offset: a0?a3h default value: 00200002h access: read only size: 32 bits this register provides standard identifier for agp capability. bit description 31:24 reserved 23:20 major agp revision number. these bits provide a major revision number of agp specification to which this version of mch conforms. this field is hardwired to value of ?0010b? (i.e., implying rev 2.x). 19:16 minor agp revision number. these bits provide a minor revision number of agp specification to which this version of mch conforms. this number is hardwired to value of ?0000? (i.e., implying revision x.0) note: together with major revision number this field identifies mch as an agp revision 2.0 - compliant device. 15:8 next capability pointer. agp capability is the first and the last capability described via the capability pointer mechanism and therefore these bits are hardwired to 0 to indicate the end of the capability linked list. 7:0 agp capability id. this field identifies the linked list item as containing agp registers. this field has a value of 0000_0010b assigned by the pci sig.
register description r 74 intel ? 82860 mch datasheet 3.4.25 agpstat?agp status register (device 0) address offset: a4?a7h default value: 1f000217h access: read only size: 32 bits this register reports agp device capability/status. bit description 31:24 requests (rq). this field is hardwired to 1fh to indicate a maximum of 32 outstanding agp command requests can be handled by the mch. this field contains the maximum number of agp command requests the mch is configured to manage. default =1fh to allow a maximum of 32 outstanding agp command requests. 23:10 reserved. 9 side band addressing (sba). hardwired to 1. this bit indicates that the mch supports side band addressing. 8:6 reserved 5 greater than 4 gb addressing (4gb). hardwired to 0. this bit indicates that the mch does not support addresses greater than 4 gb. 4 fast writes (fw). hardwired to 1. this bit indicates that the mch supports fast writes from the host to the agp master. 3 reserved 2:0 rate. after reset the mch reports its data transfer rate capability. bit 0 identifies if agp device supports 1x data transfer mode, bit 1 identifies if agp device supports 2x data transfer mode, bit 2 identifies if agp device supports 4x data transfer mode. 1x, 2x, and 4x data transfer modes are supported by the mch and therefore this bit field has a default value = 111. note: the selected data transfer mode applies to both the ad bus and sba bus. it also applies to fast writes, if they are enabled.
register description r intel ? 82860 mch datasheet 75 3.4.26 agpcmd?agp command register (device 0) address offset: a8?abh default value: 00000000h access: read/write, read only size: 32 bits this register provides control of the agp operational parameters. bit description 31:10 reserved 9 side band addressing enable (sba_en). 1 = enable. 0 = disable. 8 agp enable. when this bit is reset to 0, the mch ignores all agp operations, including the sync cycle. any agp operations received while this bit is set to 1 will be serviced even if this bit is reset to 0. if this bit transitions from a 1 to a 0 on a clock edge in the middle of an sba command being delivered in 1x mode the command will be issued. when this bit is set to 1, the mch responds to agp operations delivered via pipe#, or to operations delivered via sba (if sba_en=1). 1 = enable. 0 = disable. 7:6 reserved 5 greater than 4 gb addressing enable (4gb_en). hardwired to 0. the mch, as an agp target, does not support addressing greater than 4 gb. 4 fast write enable (fw_en). 1 = mch uses the fast write protocol for memory write transactions from the mch to the agp master. fast writes will occur at the data transfer rate selected by the data rate bits (2:0) in this register. when this bit is cleared, or when the data rate bits are set to 1x mode, the memory write transactions from the mch to the agp master use standard pci protocol. 0 = disable 3 reserved. 2:0 data rate. the settings of these bits determine the agp data transfer rate. one ( and only one ) bit in this field must be set to indicate the desired data transfer rate. the same bit must be set on both master and target. bit 0 = 1x bit 1 = 2x bit 2 = 4x configuration software will update this field by setting only one bit that corresponds to the capability of agp master (after that capability has been verified by accessing the same functional register within the agp masters? configuration space.) note: this field applies to the ad and sba buses. it also applies to fast writes, if they are enabled.
register description r 76 intel ? 82860 mch datasheet 3.4.27 agpctrl ? agp control register address offset: b0?b3h default value: 00000000h access: read/write size: 32 bits this register provides for additional control of the agp interface. bit description 31:8 reserved 7 gtlb enable (and gtlb flush control). 1 = enable. selects normal operations of the graphics translation lookaside buffer. 0 = disable. gtlb is flushed by clearing the valid bits associated with each entry. (default) 6:0 reserved 3.4.28 apsize?aperture size (device 0) address offset: b4h default value: 00h access: read/write size: 8 bits this register determines the effective size of the graphics aperture used for a particular mch configuration. this register can be updated by the mch specific bios configuration sequence before the pci standard bus enumeration sequence takes place. if the register is not updated, a default value will select an aperture of maximum size (i.e., 256 mb). the size of the table that will correspond to a 256 mb aperture is not practical for most applications; therefore, these bits must be programmed to a smaller practical value that will force adequate address range to be requested via apbase register from the pci configuration software. bit description 7:6 reserved 5:0 graphics aperture size (apsize). each bit in apsize[5:0] operates on similarly ordered bits in apbase[27:22] of the aperture base configuration register. when a particular bit of this field is 0, it forces the similarly ordered bit in apbase[27:22] to behave as ?hardwired? to 0. when a particular bit of this field is set to 1, it allows corresponding bit of the apbase[27:22] to be read/write accessible. only the following combinations are allowed: 5 4 3 2 1 0 aperture size 1 1 1 1 1 1 4 mb 1 1 1 1 1 0 8 mb 1 1 1 1 0 0 16 mb 1 1 1 0 0 0 32 mb 1 1 0 0 0 0 64 mb 1 0 0 0 0 0 128 mb 0 0 0 0 0 0 256 mb default for apsize[5:0]=000000b forces default apbase[27:22] =000000b (i.e., all bits respond as ?hardwired? to 0). this provides maximum aperture size of 256mb. as another example, programming apsize[5:0]=111000b hardwires apbase[24:22]=000b and while enabling apbase[27:25] as read/write programmable.
register description r intel ? 82860 mch datasheet 77 3.4.29 attbase?aperture translation table base register (device 0) address offset: b8?bbh default value: 00000000h access: read/write size: 32 bits this register provides the starting address of the graphics aperture translation table base located in the main memory. this value is used by the mch graphics aperture address translation logic (including the gtlb logic) to obtain the appropriate address translation entry required during the translation of the aperture address into a corresponding physical dram address. the attbase register may be dynamically changed. note: the address provided via attbase is 4-kb aligned. bit description 31:12 aperture translation table base address (att_ba). this field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory. note: this field should only be modified when the gtlb has been disabled. 11:0 reserved 3.4.30 amtt?agp interface multi-transaction timer register (device 0) address offset: bch default value: 00h access: read/write size: 8 bits amtt is an 8-bit register that controls the amount of time that the mch arbiter allows an agp master to perform multiple back-to-back transactions. the mch amtt mechanism is used to optimize the performance of the agp master (using pci protocol) that performs multiple back-to- back transactions to fragmented memory ranges (and as a consequence it can not use long burst transfers). the amtt mechanism applies to the host-agp transactions as well and it guarantees to the processor a fair share of the agp interface bandwidth. the number of clocks programmed in the amtt represents the guaranteed time slice (measured in 66 mhz clocks) allotted to the current agent (either agp master or host bridge) after which the agp arbiter will grant the bus to another agent. the default value of amtt is 00h and disables this function. the amtt value can be programmed with 8-clock granularity. for example, if the amtt is programmed to 18h, the selected value corresponds to the time period of 24 agp (66 mhz) clocks. bit description 7:3 multi-transaction timer count value. the number programmed in this field represents the guaranteed time slice (measured in eight 66 mhz clock granularity) allotted to the current agent (either agp master or mch) after which the agp arbiter will grant the bus to another agent. 2:0 reserved.
register description r 78 intel ? 82860 mch datasheet 3.4.31 lptt?low priority transaction timer register (device 0) address offset: bdh default value: 00h access: read/write size: 8 bits lptt is an 8-bit register similar in function to amtt. this register is used to control the minimum tenure on the agp for low priority data transaction (both reads and writes) issued using pipe# or sb mechanisms. the number of clocks programmed in the lptt represents the guaranteed time slice (measured in 66 mhz clocks) allotted to the current low priority agp transaction data transfer state. this does not necessarily apply to a single transaction but it can span over multiple low-priority transactions of the same type. after this time expires, the agp arbiter may grant the bus to another agent if there is a pending request. the lptt does not apply in the case of high-priority request where ownership is transferred directly to high-priority requesting queue. the default value of lptt is 00h and disables this function. the lptt value can be programmed with 8-clock granularity. for example, if the lptt is programmed to 10h, then the selected value corresponds to the time period of 16 agp (66 mhz) clocks. bit description 7:3 low priority transaction timer count value. the number of clocks programmed in these bits represents the guaranteed time slice (measured in eight 66 mhz clock granularity) allotted to the current low priority agp transaction data transfer state. 2:0 reserved
register description r intel ? 82860 mch datasheet 79 3.4.32 rdtr?rdram* device timing register (device 0) address offset: beh default value: 00h access: read/write size: 8 bits this 8-bit register defines the timing parameters for all devices in the rambus channel. the bios programs this register with the ?least common denominator? values after reading configuration registers of each device in the rambus channel. this register applies to the entire dram array. bit description 7:6 row to column delay (trcd). this field defines the minimum interval between opening a row and column operation on that row in units of direct rambus clo cks. 00 = reserved 01 = 7 rclks 10 = 9 rclks 11 = reserved note: when using an intel ? mrh-r, this field should be set to 10 (9 rclks). 5 reserved 4:0 rdram* total cas access delay (trdram). this field defines the minimum round trip propagation time of the rambus* channel in units of direct rdram device clo cks. this value includes the cas access time, the channel delay time, or any intel mrh-r delay time. trdram = tcac + trdly ? trdram has a minimum value of 8 rclks since the supported direct rdram device tcac = 8 rclks. ? trdly is the total channel delay time and should include the channel delay time of the direct rdram device in the mch direct rdram device interface, the intel mrh-r propagation delay time, and the channel delay time of the direct rdram device in the intel mrh-r direct rdram device interface. ? the minimum trdram value for use with the intel mrh-r is 14 direct rdram device clks (tcac of 8 + mrh-r delay of 6). the maximum trdram value for use with intel mrh-r is 19 direct rdram device clks (tcac of 8 + mrh-r delay of 6 + total channel delay of 5). table 8. valid trcd and tcac combinations for 300 mhz and 400 mhz direct rdram device * frequency (rclk) trcd in rclks tcac in rclks 300 mhz 7 8 400 mhz 9 8 400 mhz 7 8
register description r 80 intel ? 82860 mch datasheet 3.4.33 tom?top of low memory register (device 0) address offset: c4h default value: 0100h access: read/write size: 16 bits a memory hole is present under normal operating conditions from tom up to the 4-gb address where tom is the top of low memory register. this hole is used to access devices present behind hub interfaces_a?c, the agp bus, the memory-mapped apic register, and the boot bios area just below 4 gb. if the total amount of main memory is less than 4 gb, then the addresses (i.e., not their ?values?) indicated by the tom and gba15 (or tom and srba7) registers will be identical. note: that this register must be set to a value of 0100h (16 mb) or greater. bit description 15:4 top of low memory (tom). this register contains the address that corresponds to bits 31 to 20 (1-mb granularity) of the maximum dram memory address that lies below 4 gb. configuration software should set this value to either the maximum amount of memory in the system or to the minimum address allocated for pci memory or the graphics aperture, whichever is smaller. programming example: c00h = 3 gb (assuming that gar15 is set > 4 gb): ? an access to 0_c000_0000h or above (but < 4 gb) will be considered above the tom; therefore, the access is not to dram. it may go to agp or one of the hub interfaces and will subtractively decode to hub interface_a. ? an access to 0_bfff_ffffh and below will be considered below the tom and go to dram. note: locked accesses that cross tom are illegal and should not be performed. 3:0 reserved
register description r intel ? 82860 mch datasheet 81 3.4.34 errsts?error status register (device 0) address offset: c8?c9h default value: 0000h access: read/write clear size: 16 bits this register is used to report various error conditions via the hub interface messages to the ich2. an, serr, smi, or sci error message may be generated via hub interface_a on a 0-to-1 transition of any of these flags, when enabled, in the pcicmd/errcmd, smicmd, or scicmd registers respectively. these bits are set, regardless of whether or not the serr is enabled and generated. bit description 15 fsb request parity error (fsbrpar). 1 = mch detected a parity error on either the address or request signals of the system bus. 0 = software must write a 1 to clear this bit. 14 system bus data parity error (fsbdpar). 1 = mch detected a data parity error on the system bus. 0 = software must write a 1 to clear this bit. 13 system bus address strobe glitch detected (fsbagl). 1 = mch detected a glitch on one of the address strobes. 0 = software must write a 1 to clear this bit. 12 system bus data strobe glitch detected (fsbdgl). 1 = mch detected a glitch on one of the data strobes. 0 = software must write a 1 to clear this bit. 11 reserved 10 external thermal sensor throttle (etst). 1 = mch detected a rising edge on the overt# or the direct rdram* devices report an over temperature conditions. the overt# should be used to receive an interrupt from an external thermal sensor when the sensor has been tripped. 0 = software must write a 1 to clear this bit. 9 lock to non-dram memory flag (lckf). 1 = a host-initiated lock cycle targeting non-dram memory space occurred. 0 = software must write a 1 to clear this bit. 8 system bus address above tom (fsbatom). 1 = mch detected an address above 4 gb and above the top of low memory. 0 = software must write a 1 to clear this bit. 7 reserved
register description r 82 intel ? 82860 mch datasheet bit description 6 serr on hub interface_a target abort (tahla). 1 = mch detected that an mch originated hub interface_a cycle was terminated with a target abort completion packet or special cycle. 0 = software must write a 1 to clear this bit. 5 mch detects unimplemented hub interface_a special cycle (hiausc). 1 = mch detected an unimplemented special cycle on the hub interface_a. 0 = software must write a 1 to clear this bit. 4 agp access outside of graphics aperture flag (oogf). 1 = an agp access occurred to an address that is outside of the graphics aperture range. 0 = software must write a 1 to clear this bit. 3 invalid agp access flag (iaaf). 1 = an agp access was attempted outside of the graphics aperture and either to the 640 kb?1 mb range or above the tom. 0 = software must write a 1 to clear this bit. 2 invalid graphics aperture translation table entry (ittef). 1 = an invalid translation table entry was returned in response to an agp access to the graphics aperture. 0 = software must write a 1 to clear this bit. 1 multiple-bit dram ecc error flag (dmerr). 1 = a memory read data transfer had an uncorrectable multiple-bit error. when this bit is set, the address, channel number, and device number that caused the error are logged in the eap register. once this bit is set, the eap, cn, dn, and es fields are locked until the processor clears this bit by writing a 1. software uses bits [1:0] to detect whether the logged error address is for single- or multiple-bit error. 0 = once software completes the error processing, a value of 1 is written to this bit field to clear the value (back to 0) and unlock the error logging mechanism. 0 single-bit dram ecc error flag (dserr). 1 = a memory read data transfer had a single-bit correctable error and the corrected data was sent for the access. when this bit is set, the address, channel number, and device number that caused the error are logged in the eap register. once this bit is set, the eap, cn, dn, and es fields are locked to further single-bit error updates until the processor clears this bit by writing a 1. a multiple-bit error that occurs after this bit is set will overwrite the eap, cn, and dn fields with the multiple-bit error signature and the mef bit will also be set. 0 = software must write a 1 to clear this bit and unlock the error logging mechanism.
register description r intel ? 82860 mch datasheet 83 3.4.35 errcmd?error command register (device 0) address offset: ca?cbh default value: 0000h access: read/write size: 16 bits this register enables various errors to generate a serr message via the hub interface_a. since the mch does not have an serr# signal, serr messages are passed from the mch to the ich2 over the hub interface. when a bit in this register is set, a serr message will be generated on hub interface_a when the corresponding flag is set in the errsts register. the actual generation of the serr message is globally enabled for device 0 via the pci command register. note: an error can generate one and only one error message via the hub interface_a. it is software?s responsibility to make sure that when an serr error message is enabled for an error condition, smi and sci error messages are disabled for that same error condition. bit description 15 serr on system bus request parity error (hbrerr). 1 = enable. generation of the hub interface_a serr message is enabled for the parity errors on the address or request signals of the system bus. 0 = disable. 14 serr on system bus data parity error (hbderr). 1 = enable. data parity errors on the system bus will cause the mch to send an serr message over hub interface_a to the ich2. 0 = disable. 13 serr on system bus address strobe glitch (aglerr). 1 = enable. mch will generate a hub interface_a serr message when a glitch is detected on one of the system bus address strobes. 0 = disable. 12 serr on system bus data strobe glitch (dglerr). 1 = enable. mch will generate a hub interface_a serr message when a glitch is detected on one of the system bus data strobes. 0 = disable. 11 reserved 10 serr on external thermal sensor trip (therm_serr). 1 = enable. generation of the hub interface_a serr message is enabled when the mch has detected a rising edge on the overt# or the direct rdram* devices report an over- temperature conditions. 0 = disable. 9 serr on non-dram lock (lckerr). 1 = enable. mch will generate a hub interface_a serr special cycle when a processor lock cycle is detected that does not hit dram. 0 = disable.
register description r 84 intel ? 82860 mch datasheet bit description 8 serr on host bus access above tom (hbatomerr). 1 = enable. mch will generate hub interface_a serr special cycle when the processor generates an access above 4 gb and above the tom. 0 = disable. 7 reserved 6 serr on target abort on hub interface_a exception (tahla_serr). 1 = enable. generation of the hub interface_a serr message is enabled when an mch- originated hub interface_a cycle is completed with ?target abort? completion packet or special cycle status. 0 = disable. 5 serr on detecting hub interface_a unimplemented special cycle (hiauscerr). serr messaging for device 0 is globally enabled in the pcicmd register. 1 = enable. mch generates an serr message over hub interface_a when an unimplemented special cycle is received on the hub interface. 0 = disable. the mch does not generate an serr message for this event. 4 serr on agp access outside of graphics aperture (oogf_serr). 1 = enable. generation of the hub interface_a serr message is enabled when an agp access occurs to an address outside of the graphics aperture. 0 = disable. 3 serr on invalid agp access (iaaf_serr). 1 = enable. generation of the hub interface_a serr message is enabled when an agp access occurs to an address outside of the graphics aperture and either to the 640 kb ? 1 mb range or above the tom. 0 = disable. 2 serr on invalid translation table entry (ittef_serr). 1 = enable. generation of the hub interface_a serr message is enabled when an invalid translation table entry was returned in response to an agp access to the graphics aperture. 0 = disable. 1 serr multiple-bit dram ecc error (dmerr_serr). 1 = enable. generation of the hub interface_a serr message is enabled when the mchdram controller detects a multiple-bit error. 0 = disable. for systems not supporting ecc, this bit must be disabled. 0 serr on single-bit ecc error (dserr). 1 = enable. generation of the hub interface_a serr message is enabled when the mch dram controller detects a single-bit error. 0 = disable. for systems that do not support ecc, this bit must be disabled.
register description r intel ? 82860 mch datasheet 85 3.4.36 smicmd?smi command register (device 0) address offset: cc?cdh default value: 0000h access: read/write, read only size: 16 bits this register enables various errors to generate a smi message via the hub interface_a. note: an error can generate one and only one error message via the hub interface_a. it is software?s responsibility to make sure that when an smi error message is enabled for an error condition, serr and sci error messages are disabled for that same error condition. bit description 15:2 reserved 1 smi on multiple-bit dram ecc error (dmerr_smi). 1 = enable. generation of the hub interface_a smi message is enabled when the mch dram controller detects a multiple-bit error. 0 = disable. for systems not supporting ecc, this bit must be disabled. 0 smi on single-bit ecc error (dserr_smi). 1 = enable. generation of the hub interface_a smi message is enabled when the mch dram controller detects a single-bit error. 0 = disable. for systems that do not support ecc, this bit must be disabled.
register description r 86 intel ? 82860 mch datasheet 3.4.37 scicmd?sci command register (device 0) address offset: ce?cfh default value: 0000h access: read/write, read only size: 16 bits this register enables various errors to generate a sci message via the hub interface_a. note: an error can generate one and only one error message via the hub interface_a. it is software?s responsibility to make sure that when an sci error message is enabled for an error condition, serr and smi error messages are disabled for that same error condition. bit description 15:2 reserved. 1 sci on multiple-bit dram ecc error (dmerr_sci). 1 = enable. generation of the hub interface_a sci message is enabled when the mch dram controller detects a multiple-bit error. 0 = disable. for systems not supporting ecc, this bit must be disabled. 0 sci on single-bit ecc error (dserr_sci). 1 = enable. generation of the hub interface_a sci message is enabled when the mch dram controller detects a single-bit error. 0 = disable. for systems that do not support ecc, this bit must be disabled. 3.4.38 dramrc?rdram* device refresh control register (device 0) address offset: dc?ddh default value: 0000h access: read only, read/write size: 16 bits this register is loaded by configuration software with the refresh timings for all rambus channels present in the system. the value placed into this register should represent the least common denominator of all of the devices on the specified channel pair. note: the refresh rate for a channel is programmed to that of the device with the fastest refresh rate on that channel. that is, if a channel has a mix of 128/144 mbit (3.9 s) and 256/288 mbit (1.95 s) technology devices, the refresh rate for the channel will be programmed to 1.95 s.
register description r intel ? 82860 mch datasheet 87 bit description 15:12 reserved. 11:9 dram refresh rate for rambus* channel pair #3 (drr3). the dram refresh rate is adjusted according to the frequency selected by this field. note that refresh is also disabled via this field, and that disabling refresh results in the eventual loss of dram data. this field is programmed by the bios after collecting configuration information from all direct rdram* devices in the channel and determining the least common denominator value for refresh. 000 = refresh disabled 001 = 1.95 s 010 = 3.9 s 011 ? 111 = reserved 8:6 dram refresh rate rambus channel pair #2 (drr2). the dram refresh rate is adjusted according to the frequency selected by this field. note that refresh is also disabled via this field, and that disabling refresh results in the eventual loss of dram data. this field is programmed by bios after collecting configuration information from all direct rdram devices in the channel and determining the least common denominator value for refresh. 000 = refresh disabled 001 = 1.95 s 010 = 3.9 s 011 ? 111 = reserved 5:3 dram refresh rate rambus channel pair #1 (drr1). the dram refresh rate is adjusted according to the frequency selected by this field. note that refresh is also disabled via this field, and that disabling refresh results in the eventual loss of dram data. this field is programmed by bios after collecting config information from all direct rdram devices in the channel and determining the least common denominator value for refresh. 000 = refresh disabled 001 = 1.95 s 010 = 3.9 s 011 ? 111 = reserved 2:0 dram refresh rate rambus channel pair #0 (drr0). the dram refresh rate is adjusted according to the frequency selected by this field. note that refresh is also disabled via this field, and that disabling refresh results in the eventual loss of dram data. this field is programmed by bios after collecting configuration information from all direct rdram devices in the channel and determining the least common denominator value for refresh. 000 = refresh disabled 001 = 1.95 s 010 = 3.9 s 011 ? 111 = reserved
register description r 88 intel ? 82860 mch datasheet 3.4.39 skpd?scratchpad data (device 0) address offset: de?dfh default value: 0000h access: read/write size: 16 bits bit description 15:0 scratchpad [15:0]. these bits are r/w storage bits that have no effect on the mch functionality. 3.4.40 derrctl_sts?dram error control/status register (device 0) address offset: e2?e3h default value: 0000h access: read only size: 16 bits this register enables and reflects the status of various errors checking functions that the mch supports on the dram interface. bit description 15:8 reserved 7:0 dram ecc syndrome (deccsyn). after a dram ecc error, hardware loads this field with a syndrome that describes the set of bits found to be in error. note that this field is locked from the time that it is loaded up to the time when the error flag is cleared by software. if the first error was a single-bit, correctable error, then a subsequent multiple-bit error will overwrite this field. in all other cases, an error that occurs after the first error and before the error flag has been cleared by software will escape recording.
register description r intel ? 82860 mch datasheet 89 3.4.41 eap?error address pointer register (device 0) address offset: e4?e7h default value: 0000h access: read only size: 32 bits this register stores the dram address when an ecc error occurs. bit description 31:9 error address pointer (eap). this field is used to store address bits a[33:11] of the 4-kb block of main memory of which an error (single-bit or multiple-bit error) has occurred. note that the value of this bit field represents the address of the first single- or the first multiple-bit error occurrence after the error flag bits in the errsts register have been cleared by software. a multiple-bit error will overwrite a single-bit error. once the error flag bits are set as a result of an error, this bit field is locked and does not change as a result of a new error until the error flag is cleared by software. 8:1 reserved. 0 error address segment (eas). this bit indicates whether the reported error was found on rambus* channel a or on rambus channel b. once the error flag bits are set as a result of an error, this bit is locked and does not change as a result of a new error until the error flag is cleared by software. 1 = rambus channel b 0 = rambus channel a 3.4.42 misc_cntl?miscellaneous control register (device 0) address offset: f4?f7h default: 0000f874h default: r/w size 32 bits bit description 31:22 reserved. 21 write combining disable (pcibwcd). 1 = disable. write combining is disabled for host bus writes targeting agp (depends on configuration). 0 = enable (default). note: this bit must be set to 1 (disable) for normal operations. 20:0 reserved.
register description r 90 intel ? 82860 mch datasheet 3.5 agp bridge registers (device 1) table 9 describes the access attributes for the device 1 configuration space. table 9. mch configuration space (device 1) address offset symbol register name default value access 00?01h vid1 vendor identification 8086h ro 02?03h did1 device identification 2532h ro 04?05h pcicmd1 pci command register 0000h ro, r/w 06?07h pcists1 pci status register 00a0h ro, r/wc 08h rid1 revision identification 04h ro 09h ? reserved ? ? 0ah subc1 sub-class code 04h ro 0bh bcc1 base class code 06h ro 0ch ? reserved ? ? 0dh mlt1 master latency timer 00h ro, r/w 0eh hdr1 header type 01h ro 0f?17h ? reserved ? ? 18h pbusn1 primary bus number 00h ro 19h sbusn1 secondary bus number 00h r/w 1ah subusn1 subordinate bus number 00h r/w 1bh smlt1 secondary bus master latency timer 00h ro, r/w 1ch iobase1 i/o base address register f0h ro, r/w 1dh iolimit1 i/o limit address register 00h ro, r/w 1e?1fh ssts1 secondary status register 02a0h ro, r/wc 20?21h mbase1 memory base address register fff0h ro, r/w 22?23h mlimit1 memory limit address register 0000h ro, r/w 24?25h pmbase1 prefetchable memory base address register fff0h ro, r/w 26?27h pmlimit1 prefetchable memory limit address register 0000h ro, r/w 28?3dh ? reserved ? ? 3eh bctrl1 bridge control register 00h ro, r/w 3fh ? reserved ? ? 40h errcmd1 error command 00h ro, r/w 41?ffh ? reserved ? ?
register description r intel ? 82860 mch datasheet 91 3.5.1 vid1?vendor identification register (device 1) address offset: 00?01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number . this is a 16-bit value assigned to intel. intel vid = 8086h. 3.5.2 did1?device identification register (device 1) address offset: 02?03h default value: 2532h attribute: read only size: 16 bits this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number . this is a 16-bit value assigned to the mch device 1. mch device 1 did =2532h.
register description r 92 intel ? 82860 mch datasheet 3.5.3 pcicmd1?pci-pci command register (device 1) address offset: 04?05h default: 0000h access: read only, read/write size 16 bits bit descriptions 15:10 reserved 9 fast back-to-back?ro. not implemented; hardwired to 0. 8 serr message enable (serre1)?r/w. this bit is a global enable bit for device 1 serr messaging. the mch communicates the serr# condition by sending an serr message to the ich2. 1 = enable. mch is enabled to generate serr messages over the hub interface for specific device 1 error conditions that are individually enabled in the bctrl register. the error status is reported in the pcists1 register. 0 = disable. serr message is not generated by the mch for device 1. note: this bit only controls serr messaging for device 1. device 0 has its own serre bit to control error reporting for error conditions occurring on device 0. 7 address/data stepping?ro. not implemented; hardwired to 0. 6 parity error enable (perre1)?ro. not implemented; hardwired to 0. parity checking is not supported on the primary side of this device. 5 reserved 4 memory write and invalidate enable?ro. not implemented; hardwired to 0. 3 special cycle enable?ro. not implemented; hardwired to 0. 2 bus master enable (bme1)?r/w. this bit is not functional. it is a r/w bit for compatibility with compliance testing software. 1 memory access enable (mae1)?r/w. 1 = enable. this bit must be set to 1 to enable the memory and prefetchable memory address ranges defined in the mbase1, mlimit1, pmbase1, and pmlimit1 registers. 0 = disable. all of device 1?s memory space is disabled. 0 i/o access enable (ioae1)?r/w. 1 = enable. this bit must be set to1 to enable the i/o address range defined in the iobase1, and iolimit1 registers. 0 = disable. all of device 1?s i/o space is disabled.
register description r intel ? 82860 mch datasheet 93 3.5.4 pcists1?pci-pci status register (device 1) address offset: 06?07h default value: 00a0h access: read only, read/write clear size: 16 bits pcists1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the ?virtual? pci-pci bridge in the mch. since this device does not physically reside on pci_a, it reports the optimum operating conditions so that it does not restrict the capability of pci_a. bit descriptions 15 detected parity error (dpe1)?ro. not implemented; hardwired to 0. 14 signaled system error (sse1)?r/wc 1 = mch device 1 generates an serr message over the hub interface_a for any enabled device 1 error condition. device 1 error conditions are enabled in the errcmd, pcicmd1 and bctrl1 registers. device 1 error flags are read/reset from the errsts and ssts1 register. 0 = software clears this bit by writing a 1 to it. 13 received master abort status (rmas1)?ro. not implemented; hardwired to 0. 12 received target abort status (rtas1)?ro. not implemented; hardwired to 0. 11 signaled target abort status (stas1)?ro. not implemented; hardwired to 0. 10:9 devsel# timing (devt1): this bit field is hardwired to ?00b? to indicate that the device 1 uses the fastest possible decode. 8 data parity detected (dpd1)?ro. not implemented; hardwired to 0. 7 fast back-to-back (fb2b1)?ro. this bit is hardwired to 1 to indicate that the agp port always supports fast back-to-back transactions. 6 reserved 5 66 mhz capability?ro. this bit is hardwired to 1 to indicate that the agp port is 66 mhz capable. 4:0 reserved
register description r 94 intel ? 82860 mch datasheet 3.5.5 rid1?revision identification register (device 1) address offset: 08h default value: 04h access: read only size: 8 bits this register contains the revision number of the mch device 1. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number . this is an 8-bit value that indicates the revision identification number for the mch device 1. a-3 stepping = 04h 3.5.6 subc1?sub-class code register (device 1) address offset: 0ah default value: 04h access: read only size: 8 bits this register contains the sub-class code for the mch device 1. bit description 7:0 sub-class code (subc1) . this is an 8-bit value that indicates the category of bridge for the mch. 04h = host bridge. 3.5.7 bcc1?base class code register (device 1) address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the mch device 1. bit description 7:0 base class code (basec) . this is an 8-bit value that indicates the base class code for the mch device 1. 06h = bridge device.
register description r intel ? 82860 mch datasheet 95 3.5.8 mlt1?master latency timer register (device 1) address offset: 0dh default value: 00h access: read/write, read only size: 8 bits this functionality is not applicable. it is described here since these bits should be implemented as read/write to prevent standard pci-pci bridge configuration software from getting ?confused?. bit description 7:3 not applicable but support read/write operations. (reads return previously written data.) 2:0 reserved 3.5.9 hdr1?header type register (device 1) offset: 0eh default: 01h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit descriptions 7:0 this read only field always returns 01h when read. writes have no effect. 3.5.10 pbusn1?primary bus number register (device 1) offset: 18h default: 00h access: read only size: 8 bits this register identifies that ?virtual? pci-pci bridge is connected to bus #0. bit descriptions 7:0 bus number. hardwired to 0.
register description r 96 intel ? 82860 mch datasheet 3.5.11 sbusn1?secondary bus number register (device 1) offset: 19h default: 00h access: read /write size: 8 bits this register identifies the bus number assigned to the second bus side of the ?virtual? pci-pci bridge (i.e., to agp). this number is programmed by the pci configuration software to allow mapping of configuration cycles to agp. bit descriptions 7:0 bus number. programmable default = 00h. 3.5.12 subusn1?subordinate bus number register (device 1) offset: 1ah default: 00h access: read /write size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below agp. this number is programmed by the pci configuration software to allow mapping of configuration cycles to agp. bit descriptions 7:0 bus number. programmable default = 00h.
register description r intel ? 82860 mch datasheet 97 3.5.13 smlt1?secondary master latency timer register (device 1) address offset: 1bh default value: 00h access: read/write, read only size: 8 bits this register controls the bus tenure of the mch on agp. mlt is an 8-bit register that controls the amount of time the mch as an agp/pci bus master, can burst data on the agp bus. the count value is an 8-bit quantity; however, mlt[2:0] are reserved and assumed to be 0 when determining the count value. the mch?s mlt is used to guarantee to the agp master a minimum amount of the system resources. when the mch begins the first agp frame# cycle after being granted the bus, the counter is loaded and enabled to count from the assertion of frame#. if the count expires while the mch?s grant is removed (due to agp master request), then the mch will lose the use of the bus and the agp master agent may be granted the bus. if the mch?s bus grant is not removed, the mch will continue to own the agp bus, regardless of the mlt expiration or idle condition. note that the mch must always properly terminate an agp transaction, with frame# negation prior to the final data transfer. the number of clocks programmed in the mlt represents the guaranteed time slice (measured in 66 mhz agp clocks) allotted to the mch, after which it must complete the current data transfer phase and then surrender the bus as soon as its bus grant is removed. for example, if the mlt is programmed to 18h, the value is 24 agp clocks. the default value of mlt is 00h and disables this function. when the mlt is disabled, the burst time for the mch is unlimited (i.e., the mch can burst forever). bit description 7:3 secondary mlt counter value. default=0 (i.e., smlt disabled) 2:0 reserved
register description r 98 intel ? 82860 mch datasheet 3.5.14 iobase1?i/o base address register (device 1) address offset: 1ch default value: f0h access: read/write, read only size: 8 bits this register controls the host-to-agp i/o access routing based on the following formula: io_base address io_limit only upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4-kb boundary. note: bios must not set this register to 00h; otherwise, 0cf8h/0cfch accesses will be forwarded to agp. bit description 7:4 i/o address base. corresponds to a[15:12] of the i/o address. default=f0h 3:0 reserved 3.5.15 iolimit1?i/o limit address register (device 1) address offset: 1dh default value: 00h access: read/write, read only size: 8 bits this register controls the host-to-agp i/o access routing based on the following formula: io_base address io_limit only the upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are assumed to be fffh. thus, the top of the defined i/o address range will be at the top of a 4-kb aligned address block. bit description 7:4 i/o address limit. corresponds to a[15:12] of the i/o address. default=0 3:0 reserved. only 16-bit addressing is supported.
register description r intel ? 82860 mch datasheet 99 3.5.16 ssts1?secondary pci-pci status register (device 1) address offset: 1e?1fh default value: 02a0h access: read only, read/write clear size: 16 bits ssts1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., agp side) of the ?virtual? pci-pci bridge in the mch. bit descriptions 15 detected parity error (dpe1)?r/wc. 1 = mch detected a parity error in the address or data phase of agp bus transactions. 0 = software clears this bit by writing a 1 to it. 14 received system error (sse1)?r/wc. 1 = mch detects g_serr# assertion on the secondary side of this device. 0 = software clears this bit by writing a 1 to it. 13 received master abort status (rmas1)?r/wc. 1 = mch terminates a host-to-agp with an unexpected master abort. 0 = software clears this bit by writing a 1 to it. 12 received target abort status (rtas1)?r/wc. 1 = mch-initiated transaction on agp is terminated with a target abort. 0 = software clears this bit by writing a 1 to it. 11 signaled target abort status (stas1)?ro. hardwired to a 0; the mch does not generate target abort on agp. 10:9 devsel# timing (devt1)?ro. this 2-bit field indicates the timing of the g_devsel# signal when the mch responds as a target on agp, and is hardwired to the value 01b (medium) to indicate the time when a valid g_devsel# can be sampled by the initiator of the pci cycle. 8 master data parity error detected (dpd1)?ro. hardwired to 0. mch does not implement the g_perr# signal. 7 fast back-to-back (fb2b1)?ro. hardwired to 1; mch, as a target, supports fast back-to-back transactions on agp. 6 reserved 5 66 mhz capable (cap66)?ro. hardwired to 1; agp bus is capable of 66 mhz operation. 4:0 reserved .
register description r 100 intel ? 82860 mch datasheet 3.5.17 mbase1?memory base address register (device 1) address offset: 20?21h default value: fff0h access: read/write, read only size: 16 bits this register controls the host to agp non-prefetchable memory accesses routing based on the following formula: memory_base1 address memory_limit1 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom 4 bits of this register are read-only and return 0s when read. configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. bit description 15: 4 memory address base 1 (mem_base1). corresponds to a[31:20] of the memory address. 3:0 reserved
register description r intel ? 82860 mch datasheet 101 3.5.18 mlimit1?memory limit address register (device 1) address offset: 22?23h default value: 0000h access: read/write, read only size: 16 bits this register controls the host-to-agp non-prefetchable memory accesses routing based on the following formula: memory_base1 address memory_limit1 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom 4 bits of this register are read-only and return zeroes when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. bit description 15: 4 memory address limit 1(mem_limit1). corresponds to a[31:20] of the memory address. default=0 3:0 reserved note: memory range covered by the mbase1 and mlimit1 registers are used to map non-prefetchable agp address ranges (typically, where control/status memory-mapped i/o data structures of the graphics controller will reside) and pmbase 1and pmlimit1 are used to map prefetchable address ranges (typically, graphics local memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved host-agp memory access performance.
register description r 102 intel ? 82860 mch datasheet 3.5.19 pmbase1?prefetchable memory base address register (device 1) address offset: 24?25h default value: fff0h access: read/write, read only size: 16 bits this register controls the host-to-agp prefetchable memory access routing based on the following formula: prefetchable_memory_base1 address prefetchable_memory_limit1 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom 4 bits of this register are read-only and return zeroes when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. bit description 15:4 prefetchable memory address base 1(pmem_base1). corresponds to a[31:20] of the memory address. 3:0 reserved
register description r intel ? 82860 mch datasheet 103 3.5.20 pmlimit1?prefetchable memory limit address register (device 1) address offset: 26?27h default value: 0000h access: read/write, read only size: 16 bits this register controls the host-to-agp prefetchable memory access routing based on the following formula: prefetchable_memory_base1 address prefetchable_memory_limit1 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom 4 bits of this register are read-only and return zeroes when read. the configuration software must initialize this register. for the purpose of address decode, address, bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. bit description 15:4 prefetchable memory address limit 1(pmem_limit1). corresponds to a[31:20] of the memory address. default=0 3:0 reserved note: prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective .
register description r 104 intel ? 82860 mch datasheet 3.5.21 bctrl1?pci-pci bridge control register (device 1) address offset: 3eh default: 00h access: read only, read/write size 8 bits this register provides extensions to the pcicmd1 register that are specific to pci-pci bridges. the bctrl provides additional control for the secondary interface (i.e., agp) as well as some bits that affect the overall behavior of the ?virtual? pci-pci bridge in the mch (e.g., vga- compatible address ranges mapping). bit descriptions 7 fast back to back enable?ro. hardwired to 0. since there is only one target allowed on agp, this bit is meaningless. the mch will not generate fb2b cycles in 1x mode, but will generate fb2b cycles in 2x and 4x fast write modes. 6 secondary bus reset?ro. hardwired to 0. mch does not support generation of reset via this bit on the agp. note: that the only way to perform a hard reset of the agp is via the system reset either initiated by software or hardware via ich2. 5 master abort mode?ro. this bit is hardwired to 0. this means that when acting as a master on agp, the mch will discard data on writes and return all 1s during reads when a master abort occurs. 4 reserved 3 vga enable (vgaen1)?r/w. this bit controls the routing of host-initiated transactions targeting vga compatible i/o and memory address ranges. 1 = the mch will forward the following host accesses to the agp: - memory accesses in the range 0a0000h to 0bffffh - i/o addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases - a[15:10] are not decoded) when this bit is set, forwarding of these accesses issued by the host is independent of the i/o address and memory address ranges defined by the previously defined base and limit registers. forwarding of these accesses is also independent of the settings of bit 2 (isa enable) of this register if this bit is 1. 0 = vga compatible memory and i/o range accesses are not forwarded to agp; rather, they are mapped to primary pci, unless they are mapped to agp via i/o and memory range registers defined above (iobase1, iolimit1, mbase1, mlimit1, pmbase1, pmlimit1). (default) refer to the system address map chapter of this document for further information. note: this bit must be set to 1 if a video device sits behind this bridge (i.e., video device is on agp). if there is no video device behind this bridge, then this bit must be set to 0. one of the mch devices must set this bit. this must be enforced via software.
register description r intel ? 82860 mch datasheet 105 bit descriptions 2 isa enable?r/w. this bit modifies the response by the mch to an i/o access issued by the host that targets isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. 1 = enable. mch does not forward to agp any i/o transactions addressing the last 768 bytes in each 1-kb block, even if the addresses are within the range defined by the iobase and iolimit registers. instead of going to agp, these cycles are forwarded to pci0 where they can be subtractively or positively claimed by the isa bridge. 0 = disable. all addresses defined by the iobase and iolimit for host i/o transactions are mapped to agp. (default) note: this bit must be set to 1. 1 serr# enable?r/w. this bit controls the forwarding of serr# on the secondary interface to the primary interface. 1 = enable. mch generates serr messages to hub interface_a when the serr# pin on agp bus is asserted and when the messages are enabled by the serre bit in the pcicmd1 register. 0 = disable 0 parity error response enable?r/w. this bit controls the mch?s response to data phase parity errors on agp. 1 = g_perr# is not implemented by the mch. however, when this bit is set to 1, address and data parity errors detected on agp are reported via hub interface_a serr# messaging mechanism, if further enabled by serre1. 0 = address and data parity errors on agp are not reported via the mch hub interface_a serr# messaging mechanism. other types of error conditions can still be signaled via serr# messaging independent of this bit?s state. 3.5.22 errcmd1?error command register (device 1) address offset: 40h default value: 00h access: read/write, read only size: 8 bits bit description 7:1 reserved 0 serr on receiving target abort (serta). 1 = mch generates an serr message over hub interface_a upon receiving a target abort on agp. serr messaging for device 1 is globally enabled in the pcicmd1 register. 0 = mch does not assert an serr message upon receipt of a target abort on agp.
register description r 106 intel ? 82860 mch datasheet 3.6 hub interface_b bridge registers (device 2) table 10 provides an address map and describes the access attributes for the device 2 configuration space. table 10. mch configuration space (device 2) address offset symbol register name default value access 00?01h vid2 vendor identification 8086h ro 02?03h did2 device identification 2533h ro 04?05h pcicmd2 pci command register 0000h ro, r/w 06?07h pcists2 pci status register 00a0h ro, r/wc 08h rid2 revision identification 03h ro 09h ? reserved ? ? 0ah subc2 sub-class code 04h ro 0bh bcc2 base class code 06h ro 0ch ? reserved ? ? 0dh mlt2 master latency timer 00h ro, r/w 0eh hdr2 header type 01h ro 0f?17h ? reserved ? ? 18h pbusn2 primary bus number 00h ro 19h sbusn2 secondary bus number 00h r/w 1ah subusn2 subordinate bus number 00h r/w 1bh smlt2 secondary bus master latency timer 00h r/w 1ch iobase2 i/o base address register f0h ro, r/w 1dh iolimit2 i/o limit address register 00h ro, r/w 1e?1fh ssts2 secondary status register 02a0h ro, r/wc 20?21h mbase2 memory base address register fff0h ro, r/w 22?23h mlimit2 memory limit address register 0000h ro, r/w 24?25h pmbase2 prefetchable memory base address register fff0h ro, r/w 26?27h pmlimit2 prefetchable memory limit address register 0000h ro, r/w 28?3dh ? reserved ? ? 3eh bctrl2 bridge control register 00h ro, r/w 3fh ? reserved ? ? 40h errcmd2 error command 00h ro, r/w 41?ffh ? reserved ? ?
register description r intel ? 82860 mch datasheet 107 3.6.1 vid2?vendor identification register (device 2) address offset: 00?01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number. this is a 16-bit value assigned to intel. intel vid = 8086h. 3.6.2 did2?device identification register (device 2) address offset: 02?03h default value: 2533h attribute: read only size: 16 bits this 16-bit register, combined with the vendor identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number . this is a 16-bit value assigned to the mch device 2. mch device 2 did =2533h.
register description r 108 intel ? 82860 mch datasheet 3.6.3 pcicmd2?pci-pci command register (device 2) address offset: 04?05h default: 0000h access: read only, read/write size 16 bits bit descriptions 15:10 reserved. 9 fast back-to-back?ro. not implemented; hardwired to 0. 8 serr message enable (serre2)?r/w. this bit is a global enable bit for device 2 serr messaging. the mch does not have an serr# signal. the mch communicates the serr# condition by sending an serr message to the ich2. 1 = enable. mch is enabled to generate serr messages over the hub interface_a for specific device 2 error conditions. 0 = disable. serr message is not generated by the mch for device 2. note: this bit only controls serr messaging for the device 2. device 0?5 have their own serre bit to control error reporting for error conditions occurring on their device. 7 address/data stepping?ro. not implemented; hardwired to 0. 6 parity error enable (perre2)?ro. hardwired to 0. parity checking is not supported on the primary side of this device. 5 reserved. 4 memory write and invalidate enable?ro. not implemented; hardwired to 0. 3 special cycle enable?ro. not implemented; hardwired to 0. 2 bus master enable (bme2)?r/w. not applicable. however, supported as a read/write bit to avoid the problems with standard pci-pci bridge configuration software. 1 memory access enable (mae2)?r/w. 1 = enable. must be set to 1 to enable the memory and prefetchable memory address ranges defined in the mbase2, mlimit2, pmbase2, and pmlimit2 registers. 0 = disable. all of device 2?s memory space is disabled. 0 i/o access enable (ioae2)?r/w. 1 = enable. must be set to 1 to enable the i/o address range defined in the iobase2 and iolimit2 registers. 0 = disable. all of device 2?s i/o space is disabled.
register description r intel ? 82860 mch datasheet 109 3.6.4 pcists2?pci-pci status register (device 2) address offset: 06?07h default value: 00a0h access: read only, read/write clear size: 16 bits pcists2 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the ?virtual? pci-pci bridge in the mch. since this device does not physically reside on pci_a, it reports the optimum operating conditions so that it does not restrict the capability of pci_a. bit descriptions 15 detected parity error (dpe2)?ro. not implemented; hardwired to 0. 14 signaled system error (sse2)?r/wc. 1 = mch device 2 generates an serr message over the hub interface_a for any enabled device 2 error condition. 0 = software clears this bit by writing a 1 to it. 13 received master abort status (rmas2)?ro. hardwired to 0. the concept of master abort does not exist on primary side of this device. 12 received target abort status (rtas2)?ro. hardwired to 0. the concept of target abort does not exist on primary side of this device. 11 signaled target abort status (stas2)?ro. hardwired to 0. the concept of target abort does not exist on primary side of this device. 10:9 devsel# timing (devt2)?ro. hardwired to 00. device 2 uses the fastest possible decode. 8 master data parity error detected (dpd2)?ro. hardwired to 0. parity is not supported on the primary side of this device. 7 fast back-to-back (fb2b2)?ro. hardwired to 1. fast back-to-back writes are always supported on this interface. 6 reserved . 5 66 mhz capability?ro. hardwired to 1. device is capable of 66 mhz operation. 4:0 reserved .
register description r 110 intel ? 82860 mch datasheet 3.6.5 rid2?revision identification register (device 2) address offset: 08h default value: 03h access: read only size: 8 bits this register contains the revision number of the mch device 2. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number . this is an 8-bit value that indicates the revision identification number for the mch device 2. a-3 stepping = 03h. 3.6.6 subc2?sub-class code register (device 2) address offset: 0ah default value: 04h access: read only size: 8 bits this register contains the sub-class code for the mch device 2. bit description 7:0 sub-class code (subc2) . this is an 8-bit value that indicates the category of bridge for the mch. 04h = host bridge. 3.6.7 bcc2?base class code register (device 2) address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the mch device 2. bit description 7:0 base class code (basec2) . this is an 8-bit value that indicates the base class code for the mch device 2. 06h = bridge device.
register description r intel ? 82860 mch datasheet 111 3.6.8 mlt2?master latency timer register (device 2) address offset: 0dh default value: 00h access: read/write, read only size: 8 bits this functionality is not applicable. it is described here since these bits should be implemented as a read/write to prevent standard pci-pci bridge configuration software from getting ?confused?. bit description 7:3 not applicable but support read/write operations. reads return previously written data. 2:0 reserved 3.6.9 hdr2?header type register (device 2) offset: 0eh default: 01h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit descriptions 7:0 this read only field always returns 01h when read. writes have no effect. 3.6.10 pbusn2?primary bus number register (device 2) offset: 18h default: 00h access: read only size: 8 bits this register identifies that ?virtual? pci-pci bridge is connected to bus #0. bit descriptions 7:0 bus number. hardwired to 0.
register description r 112 intel ? 82860 mch datasheet 3.6.11 sbusn2?secondary bus number register (device 2) offset: 19h default: 00h access: read /write size: 8 bits this register identifies the bus number assigned to the second bus side of the ?virtual? pci-pci bridge (the hub interface_b connection). this number is programmed by the pci configuration software to allow mapping of configuration cycles to a second bridge device connected to hub interface_b. bit descriptions 7:0 bus number. programmable. default = 00h. 3.6.12 subusn2?subordinate bus number register (device 2) offset: 1ah default: 00h access: read /write size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below the secondary hub interface. this number is programmed by the pci configuration software to allow mapping of configuration cycles to devices subordinate to the secondary hub interface port. bit descriptions 7:0 bus number. programmable. default = 00. 3.6.13 smlt2?secondary master latency timer register (device 2) address offset: 1bh default value: 00h access: read only size: 8 bits bit description 7:0 reserved
register description r intel ? 82860 mch datasheet 113 3.6.14 iobase2?i/o base address register (device 2) address offset: 1ch default value: f0h access: read/write, read only size: 8 bits this register control the host-to-hub interface_b i/o accesses routing based on the following formula: io_base2 address io_limit2 only upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4-kb boundary. bit description 7:4 i/o address base 2. corresponds to a[15:12] of the i/o addresses passed by the device 2 bridge-to-hub interface_b. default=f0h 3:0 reserved 3.6.15 iolimit2?i/o limit address register (device 2) address offset: 1dh default value: 00h access: read/write, read only size: 8 bits this register control the host-to-hub interface_b i/o accesses routing based on the following formula: io_base2 address io_limit2 only upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are assumed to be fffh. thus, the top of the defined i/o address range will be at the top of a 4-kb aligned address block. bit description 7:4 i/o address limit. corresponds to a[15:12] of the i/o address limit of device 2. default = 0 3:0 reserved. only 16-bit addressing supported.
register description r 114 intel ? 82860 mch datasheet 3.6.16 ssts2?secondary pci-pci status register (device 2) address offset: 1e?1fh default value: 02a0h access: read only, read/write clear size: 16 bits ssts2 is a 16-bit status register that reports the occurrence of error conditions associated with the secondary side (i.e., hub interface_b side) of the ?virtual? pci-pci bridge in the mch. bit descriptions 15 detected parity error (dpe2)?r/wc. 1 = mch detected a parity error in the address or data phase of hub interface_b bus transactions. 0 = software clears this bit by writing a 1 to it. 14 received system error (sse2)?r/wc. 1 = mch receives an serr message across the hub interface_b. 0 = software clears this bit by writing a 1 to it. 13 received master abort status (rmas2)?r/wc. 1 = mch receives a master abort completion packet or master abort special cycle on hub interface_b. 0 = software clears this bit by writing a 1 to it. 12 received target abort status (rtas2)?r/wc. 1 = mch receives a target abort completion packet or target abort special cycle on hub interface_b this bit is set. 0 = software clears this bit by writing a 1 to it. 11 signaled target abort status (stas2)?ro. not implemented; hardwired to 1. 10:9 devsel# timing (devt2)?ro. not applicable. hardwired to 01b 8 master data parity error detected (dpd2)?ro. not implemented; hardwired to 1. 7 fast back-to-back (fb2b2)?ro. not implemented; hardwired to 1. 6 reserved 5 66 mhz capable (cap66)?ro. hardwired to 1. hub interface_b is capable of 66 mhz operation. 4:0 reserved
register description r intel ? 82860 mch datasheet 115 3.6.17 mbase2?memory base address register (device 2) address offset: 20?21h default value: fff0h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_b non-prefetchable memory access routing based on the following formula: memory_base2 address memory_limit2 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. bit description 15: 4 memory address base 2 (mem_base2). corresponds to a[31:20] of the lower limit memory address that will be passed by the device 2 to hub interface_b. 3:0 reserved
register description r 116 intel ? 82860 mch datasheet 3.6.18 mlimit2?memory limit address register (device 2) address offset: 22?23h default value: 0000h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_b non-prefetchable memory access routing based on the following formula: memory_base2 address memory_limit2 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. bit description 15:4 memory address limit 2(mem_limit2). corresponds to a[31:20] of the upper limit memory address that will be passed by the device 2 to hub interface_b. default=0 3:0 reserved note: the memory range covered by mbase2 and mlimit2 registers are used to map non- prefetchable hub interface_b address ranges (typically, where control/status memory-mapped i/o data structures of the graphics controller will reside) and pmbase2 and pmlimit2 are used to map prefetchable address ranges (typically, graphics local memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved host-hub interface memory access performance.
register description r intel ? 82860 mch datasheet 117 3.6.19 pmbase2?prefetchable memory base address register (device 2) address offset: 24?25h default value: fff0h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_b prefetchable memory access routing based on the following formula: prefetchable_memory_base2 address prefetchable_memory_limit2 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. bit description 15: 4 prefetchable memory address base 2 (pmem_base2). corresponds to a[31:20] of the memory address. 3:0 reserved
register description r 118 intel ? 82860 mch datasheet 3.6.20 pmlimit2?prefetchable memory limit address register (device 2) address offset: 26?27h default value: 0000h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_b prefetchable memory access routing based on the following formula: prefetchable_memory_base2 address prefetchable_memory_limit2 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return zeroes when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. bit description 15: 4 prefetchable memory address limit 2(pmem_limit2). corresponds to a[31:20] of the memory address. default=0 3:0 reserved note: the prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective .
register description r intel ? 82860 mch datasheet 119 3.6.21 bctrl2?pci-pci bridge control register (device 2) address offset: 3eh default: 00h access: read/write, read only size 8 bits this register provides extensions to the pcicmd2 register that are specific to pci-pci bridges. the bctrl2 provides additional control for the secondary interface (i.e., hub interface_b) as well as some bits that affect the overall behavior of the ?virtual? pci-pci bridge in the mch (e.g., vga-compatible address ranges mapping). bit descriptions 7 fast back to back enable?ro. hardwired to 0. the mch does not generate fast back-to- back cycles as a master on hub interface_b. 6 secondary bus reset?ro. hardwired to 0. mch does not support generation of reset via this bit on the hub interface_b. 5 master abort mode?ro. hardwired to 0. as a master on hub interface_b, the mch discards data on writes and returns all 1s during reads when a master abort occurs. 4 reserved 3 vga2 enable (vgaen2)?r/w. this bit controls the routing of host-initiated transactions targeting vga compatible i/o and memory address ranges. 1 = mch forwards the following host accesses to the hub interface_b: ? memory accesses in the range 0a0000h?0bffffh ? i/o addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases - a[15:10] are not decoded) when this bit is set, forwarding of these accesses issued by the processor is independent of the i/o address and memory address ranges defined by the previously defined base and limit registers. forwarding of these accesses is also independent of the settings of the bit 2 (isa enable) of this register if this bit is 1. 0 = vga compatible memory and i/o range accesses are not forwarded to hub interface_b; rather, they are subtractively mapped to primary pci unless they are mapped to hub interface_b via i/o and memory range registers defined above (iobase2, iolimit2, mbase2, mlimit2, pmbase2, pmlimit2). (default) refer to the system address map chapter of this document for further information. note: this bit must be set to 1 if a video device sits behind this bridge (i.e., video device is on agp). if there is no video device behind this bridge, this bit must be set to 0. one of the mch devices must set this bit. this must be enforced via software.
register description r 120 intel ? 82860 mch datasheet bit descriptions 2 isa enable?r/w. modifies the response by the mch to an i/o access issued by the processor that targets isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. 1 = enable. the mch does not forward to hub interface_b any i/o transactions addressing the last 768 bytes in each 1 kb block, even if the addresses are within the range defined by the iobase and iolimit registers. instead of going to hub interface_b, these cycles are forwarded to hub interface_a where they can be subtractively or positively claimed by the isa bridge. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions will be mapped to hub interface_b. (default) note: this bit must be set to 1. 1 serr# enable?r/w. this bit enables or disables forwarding of serr messages from hub interface_b-to-hub interface_a, where they can be converted into interrupts that are eventually delivered to the processor. 1 = enable 0 = disable 0 parity error response enable?r/w. this bit controls the mch?s response to data phase parity errors on hub interface_b. 1 = address and data parity errors on hub interface_b are reported via the hub interface_a serr# messaging mechanism, if further enabled by serre2. 0 = address and data parity errors on hub interface_b are not reported via the mch hub interface_a serr# messaging mechanism. other types of error conditions can still be signaled via serr# messaging independent of this bit?s state.
register description r intel ? 82860 mch datasheet 121 3.6.22 errcmd2?error command register (device 2) address offset: 40h default value: 00h access: read/write, read only size: 8 bits bit description 7:4 reserved 3 serr on detecting hub interface_b unimplemented special cycle (hiduscerr). 1 = mch generates an serr message over hub interface_a when an unimplemented special cycle is received on the hub interface. 0 = mch does not generate an serr message for this event. serr messaging for device 2 is globally enabled in the pcicmd2 register. 2 serr on generating hub interface_b master abort (hidmaerr). 1 = mch generates an serr message over hub interface_a when an invalid address is received on the hub interface. 0 = mch does not generate an serr message for this event. serr messaging for device 2 is globally enabled in the pcicmd2 register. 1 reserved. 0 serr on receiving target abort (hiserta). 1 = mch generates a serr message over hub interface_a upon receiving a target abort on hub interface_b. 0 = mch does not assert an serr message upon receipt of a target abort on hub interface_b. serr messaging for device 2 is globally enabled in the pcicmd2 register.
register description r 122 intel ? 82860 mch datasheet 3.7 hub interface_c bridge registers (device 3) table 11 provides the address map and describes the access attributes for device 3 configuration space. table 11. mch configuration space (device 3) address offset symbol register name default value access 00?01h vid3 vendor identification 8086h ro 02?03h did3 device identification 2534h ro 04?05h pcicmd3 pci command register 0000h ro, r/w 06?07h pcists3 pci status register 00a0h ro, r/wc 08 rid3 revision identification 03h ro 09 ? reserved ? ? 0ah subc3 sub-class code 04h ro 0bh bcc3 base class code 06h ro 0ch ? reserved ? ? 0dh mlt3 master latency timer 00h ro, r/w 0eh hdr3 header type 01h ro 0f?17h ? reserved ? ? 18h pbusn3 primary bus number 00h ro 19h sbusn3 secondary bus number 00h r/w 1ah subusn3 subordinate bus number 00h r/w 1bh smlt3 secondary bus master latency timer 00h ro, r/w 1ch iobase3 i/o base address register f0h ro, r/w 1dh iolimit3 i/o limit address register 00h ro, r/w 1e?1fh ssts3 secondary status register 02a0h ro, r/wc 20?21h mbase3 memory base address register fff0h ro, r/w 22?23h mlimit3 memory limit address register 0000h ro, r/w 24?25h pmbase3 prefetchable memory base address register fff0h ro, r/w 26?27h pmlimit3 prefetchable memory limit address register 0000h ro, r/w 28?3dh ? reserved ? ? 3eh bctrl3 bridge control register 00h ro, r/w 3fh ? reserved ? ? 40h errcmd3 error command 00h ro, r/w 41?ffh ? reserved ? ?
register description r intel ? 82860 mch datasheet 123 3.7.1 vid3?vendor identification register (device 3) address offset: 00?01h default value: 8086h attribute: read only size: 16 bits the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 vendor identification number . this is a 16-bit value assigned to intel. intel vid = 8086h. 3.7.2 did3?device identification register (device 3) address offset: 02?03h default value: 2534h attribute: read only size: 16 bits this 16-bit register, combined with the vendor identification register, uniquely identifies any pci device. writes to this register have no effect. bit description 15:0 device identification number . this is a 16-bit value assigned to the mch device 3. mch1 device 3 did =2534h.
register description r 124 intel ? 82860 mch datasheet 3.7.3 pcicmd3?pci-pci command register (device 3) address offset: 04?05h default: 0000h access: read only, read/write size 16 bits bit descriptions 15:10 reserved 9 fast back-to-back?ro. not implemented; hardwired to 0. 8 serr message enable (serre3)?rw. this bit is a global enable bit for device 3 serr messaging. the mch does not have an serr# signal. the mch communicates the serr# condition by sending an serr message to the ich2. 1 = enable. mch is enabled to generate serr messages over the hub interface_a for specific device 3 error conditions. 0 = disable. serr message is not generated by the mch for device 3. note: this bit only controls serr messaging for the device 3. device 0?5 have their own serre bit to control error reporting for error conditions occurring on their device. 7 address/data stepping?ro. not implemented; hardwired to 0. 6 parity error enable (perre3)?ro. hardwired to 0. parity checking is not supported on the primary side of this device. 5 reserved 4 memory write and invalidate enable?ro. not implemented; hardwired to 0. 3 special cycle enable?ro. not implemented; hardwired to 0. 2 bus master enable (bme3)?r/w. not applicable. however, supported as a read/write bit to avoid the problems with standard pci-pci bridge configuration software. 1 memory access enable (mae3)?r/w. 1 = enable. must be set to 1 to enable the memory and prefetchable memory address ranges defined in the mbase3, mlimit3, pmbase3, and pmlimit3 registers. 0 = disable. all of device 3?s memory space is disabled. 0 i/o access enable (ioae3)?r/w. 1 = enable. must be set to 1 to enable the i/o address range defined in the iobase3 and iolimit3 registers. 0 = disable. all of device 3?s i/o space is disabled.
register description r intel ? 82860 mch datasheet 125 3.7.4 pcists3?pci-pci status register (device 3) address offset: 06?07h default value: 00a0h access: read only, read/write clear size: 16 bits pcists3 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the ?virtual? pci-pci bridge in the mch. since this device does not physically reside on pci_a, it reports the optimum operating conditions so that it does not restrict the capability of pci_a. bit descriptions 15 detected parity error (dpe3)?ro. not applicable. hardwired to 0. 14 signaled system error (sse3)?r/wc. 1 = mch device 3 generates an serr message over the hub interface_a for any enabled device 3 error condition. 0 = software clears this bit by writing a 1 to it. 13 received master abort status (rmas3)?ro. hardwired to 0. the concept of master abort does not exist on primary side of this device. 12 received target abort status (rtas3)?ro. hardwired to 0. the concept of target abort does not exist on primary side of this device. 11 signaled target abort status (stas3)?ro. hardwired to 0. the concept of target abort does not exist on primary side of this device. 10:9 devsel# timing (devt3)?ro. hardwired to 00; device 3 uses the fastest possible decode. 8 master data parity error detected (dpd3)?ro. hardwired to 0. parity is not supported on the primary side of this device. 7 fast back-to-back (fb2b3)?ro. hardwired to 1; fast back-to-back writes are always supported on this interface. 6 reserved 5 66 mhz capability?ro. hardwired to a 1; device is capable of 66 mhz operation. 4:0 reserved
register description r 126 intel ? 82860 mch datasheet 3.7.5 rid3?revision identification register (device 3) address offset: 08h default value: 03h access: read only size: 8 bits this register contains the revision number of the mch device 3. these bits are read only and writes to this register have no effect. bit description 7:0 revision identification number . this is an 8-bit value that indicates the revision identification number for the mch device 3. a-3 stepping = 03h. 3.7.6 subc3?sub-class code register (device 3) address offset: 0ah default value: 04h access: read only size: 8 bits this register contains the sub-class code for the mch device 3. bit description 7:0 sub-class code (subc3) . this is an 8-bit value that indicates the category of bridge for the mch. 04h = host bridge 3.7.7 bcc3?base class code register (device 3) address offset: 0bh default value: 06h access: read only size: 8 bits this register contains the base class code of the mch device 3. bit description 7:0 base class code (basec3) . this is an 8-bit value that indicates the base class code for the mch device 3. 06h = bridge device
register description r intel ? 82860 mch datasheet 127 3.7.8 mlt3?master latency timer register (device 3) address offset: 0dh default value: 00h access: read/write, read only size: 8 bits this functionality is not applicable. it is described here since these bits should be implemented as a read/write to prevent standard pci-pci bridge configuration software from getting ?confused.? bit description 7:3 not applicable but supports read/write operations. reads return previously written data. 2:0 reserved 3.7.9 hdr3?header type register (device 3) offset: 0eh default: 01h access: read only size: 8 bits this register identifies the header layout of the configuration space. no physical register exists at this location. bit descriptions 7:0 this read only field always returns 01h when read. writes have no effect. 3.7.10 pbusn3?primary bus number register (device 3) offset: 18h default: 00h access: read only size: 8 bits this register identifies that ?virtual? pci-pci bridge is connected to bus #0. bit descriptions 7:0 bus number. hardwired to 0.
register description r 128 intel ? 82860 mch datasheet 3.7.11 sbusn3?secondary bus number register (device 3) offset: 19h default: 00h access: read /write size: 8 bits this register identifies the bus number assigned to the second bus side of the ?virtual? pci-pci bridge (the hub interface_c connection). this number is programmed by the pci configuration software to allow mapping of configuration cycles to a second bridge device connected to hub interface_c. bit descriptions 7:0 bus number. programmable. default = 00h. 3.7.12 subusn3?subordinate bus number register (device 3) offset: 1ah default: 00h access: read /write size: 8 bits this register identifies the subordinate bus (if any) that resides at the level below the secondary hub interface. this number is programmed by the pci configuration software to allow mapping of configuration cycles to devices subordinate to the secondary hub interface port. bit descriptions 7:0 bus number. programmable. default = 00. 3.7.13 smlt3?secondary master latency timer register (device 3) address offset: 1bh default value: 00h access: read only size: 8 bits bit description 7:0 reserved
register description r intel ? 82860 mch datasheet 129 3.7.14 iobase3?i/o base address register (device 3) address offset: 1ch default value: f0h access: read/write, read only size: 8 bits this register control the host-to-hub interface_c i/o access routing based on the following formula: io_base3 address io_limit3 only upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4-kb boundary. bit description 7:4 i/o address base 3. corresponds to a[15:12] of the i/o addresses passed by the device 3 bridge to hub interface_c. default=f0h 3:0 reserved 3.7.15 iolimit3?i/o limit address register (device 3) address offset: 1dh default value: 00h access: read/write, read only size: 8 bits this register controls the host-to-hub interface_c i/o access routing based on the following formula: io_base3 address io_limit3 only upper four bits are programmable. for the purpose of address decode, address bits a[11:0] are assumed to be fffh. thus, the top of the defined i/o address range will be at the top of a 4- kb aligned address block. bit description 7:4 i/o address limit. corresponds to a[15:12] of the i/o address limit of device 3. default = 0 3:0 reserved. only 16-bit addressing supported.
register description r 130 intel ? 82860 mch datasheet 3.7.16 ssts3?secondary pci-pci status register (device 3) address offset: 1e?1fh default value: 02a0h access: read only, read/write clear size: 16 bits ssts3 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., hub interface_c side) of the ?virtual? pci-pci bridge in the mch. bit descriptions 15 detected parity error (dpe3)?r/wc. 1 = mch detected of a parity error in the address or data phase of hub interface_c bus transactions. 0 = software clears this bit by writing a 1 to this bit. 14 received system error (sse3)?r/wc. 1 = mch receives a serr message across the hub interface_c. 0 = software clears this bit by writing a 1 to this bit. 13 received master abort status (rmas3)?r/wc. 1 = mch receives a master abort completion packet or master abort special cycle on hub interface_c this bit is set. 0 = software clears this bit by writing a 1 to this bit. 12 received target abort status (rtas3)?r/wc. 1 = mch receives a target abort completion packet or target abort special cycle on hub interface_c. 0 = software clears this bit by writing a 1 to this bit. 11 signaled target abort status (stas3)?ro. not applicable. hardwired to 0. 10:9 devsel# timing (devt3)?ro. not applicable. hardwired to 01b 8 master data parity error detected (dpd3)?ro. not applicable. hardwired to 0. 7 fast back-to-back (fb2b3)?ro. not applicable. hardwired to 1. 6 reserved 5 66 mhz capable (cap66)?ro. this bit is hardwired to 1 to indicate that hub interface_c is capable of 66 mhz operation. 4:0 reserved
register description r intel ? 82860 mch datasheet 131 3.7.17 mbase3?memory base address register (device 3) address offset: 20?21h default value: fff0h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_c non-prefetchable memory access routing based on the following formula: memory_base3 address memory_limit3 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. bit description 15: 4 memory address base 3 (mem_base3). corresponds to a[31:20] of the lower limit memory address that will be passed by the device 3 to hub interface_c. 3:0 reserved
register description r 132 intel ? 82860 mch datasheet 3.7.18 mlimit3?memory limit address register (device 3) address offset: 22?23h default value: 0000h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_c non-prefetchable memory access routing based on the following formula: memory_base3 address memory_limit3 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. bit description 15:4 memory address limit 3(mem_limit3). corresponds to a[31:20] of the upper limit memory address that will be passed by the device 3 to hub interface_c. default = 0 3:0 reserved note: memory range covered by mbase3 and mlimit3 registers are used to map non-prefetchable hub interface_c address ranges (typically, where control/status memory-mapped i/o data structures of the graphics controller will reside) and pmbase3 and pmlimit3 are used to map prefetchable address ranges (typically, graphics local memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved host-hub interface memory access performance.
register description r intel ? 82860 mch datasheet 133 3.7.19 pmbase3?prefetchable memory base address register (device 3) address offset: 24?25h default value: fff0h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_c prefetchable memory access routing based on the following formula: prefetchable_memory_base3 address prefetchable_memory_limit3 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. bit description 15: 4 prefetchable memory address base 3(pmem_base3). corresponds to a[31:20] of the memory address. 3:0 reserved
register description r 134 intel ? 82860 mch datasheet 3.7.20 pmlimit3?prefetchable memory limit address register (device 3) address offset: 26?27h default value: 0000h access: read/write, read only size: 16 bits this register controls the host-to-hub interface_c prefetchable memory access routing based on the following formula: prefetchable_memory_base3 address prefetchable_memory_limit3 the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. the configuration software must initialize this register. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. bit description 15: 4 prefetchable memory address limit 3(pmem_limit3). corresponds to a[31:20] of the memory address. default=0 3:0 reserved note: the prefetchable memory range is supported to allow segregation by the configuration software between the memory ranges that must be defined as uc and the ones that can be designated as a uswc (i.e., prefetchable) from the processor perspective .
register description r intel ? 82860 mch datasheet 135 3.7.21 bctrl3?pci-pci bridge control register (device 3) address offset: 3eh default: 00h access: read/write, read only size 8 bits this register provides extensions to the pcicmd3 register that are specific to pci-pci bridges. the bctrl3 provides additional control for the secondary interface (i.e., hub interface_c) as well as some bits that affect the overall behavior of the ?virtual? pci-pci bridge in the mch (e.g., vga-compatible address ranges mapping). bit descriptions 7 fast back to back enable?ro. hardwired to 0. the mch does not generate fast back-to- back cycles as a master on hub interface_c. 6 secondary bus reset?ro. hardwired to 0. mch does not support generation of reset via this bit on hub interface_c. 5 master abort mode?ro. hardwired to 0. as a master on hub interface_c the mch will discard data on writes and return all 1s during reads when a master abort occurs. 4 reserved 3 vga3 enable (vgaen3)?r/w. this bit controls the routing of host-initiated transactions targeting vga compatible i/o and memory address ranges. 1 = the mch forwards the following host accesses to hub interface_c: ? memory accesses in the range 0a0000h?0bffffh ? i/o addresses where a[9:0] are in the ranges 3b0h to 3bbh and 3c0h to 3dfh (inclusive of isa address aliases - a[15:10] are not decoded) when this bit is set, forwarding of these accesses issued by the processor is independent of the i/o address and memory address ranges defined by the previously defined base and limit registers. forwarding of these accesses is also independent of the settings of the bit 2 (isa enable) of this register, if this bit is 1. 0 = vga compatible memory and i/o range accesses are not forwarded to hub interface_c; rather, they are subtractively mapped to primary pci unless they are mapped to hub interface_c via i/o and memory range registers defined above (iobase3, iolimit3, mbase3, mlimit3, pmbase3, pmlimit3). (default) refer to the system address map chapter of this document for further information. note: this bit must be set to 1 if a video device sits behind this bridge (i.e., video device is on agp). if there is no video device behind this bridge, this bit must be set to 0. one of the mch devices must set this bit. this must be enforced via software.
register description r 136 intel ? 82860 mch datasheet bit descriptions 2 isa enable?r/w. this bit modifies the response by the mch to an i/o access issued by the processor that targets isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. 1 = enable. mch does not forward to hub interface_c any i/o transactions addressing the last 768 bytes in each 1 kb block even if the addresses are within the range defined by the iobase and iolimit registers. instead of going to hub interface_c these cycles will be forwarded to hub interface_a where they can be subtractively or positively claimed by the isa bridge. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions will be mapped to hub interface_c. (default) note: this bit must be set to 1. 1 serr# enable?r/w. this bit enables or disables forwarding of serr messages from hub interface_c-to-hub interface_a, where they can be converted into interrupts that are eventually delivered to the processor. 1 = enable 0 = disable 0 parity error response enable?r/w. this bit controls the mch?s response to data phase parity errors on hub interface_c. 1 = address and data parity errors on hub interface_c are reported via the hub interface_a serr# messaging mechanism, if further enabled by serre3. 0 = address and data parity errors on hub interface_c are not reported via the mch hub interface_a serr# messaging mechanism. other types of error conditions can still be signaled via serr# messaging independent of this bit?s state.
register description r intel ? 82860 mch datasheet 137 3.7.22 errcmd3?error command register (device 3) address offset: 40h default value: 00h access: read/write, read only size: 8 bits bit description 7:4 reserved 3 serr on detecting hub interface_c unimplemented special cycle (hiduscerr). 1 = mch generates an serr message over hub interface_a when an unimplemented special cycle is received on the hub interface. 0 = mch does not generate an serr message for this event. serr messaging for device 3 is globally enabled in the pcicmd3 register. 2 serr on generating hub interface_c master abort (hidmaerr). 1 = mch generates an serr message over hub interface_a when an invalid address is received on the hub interface. 0 = mch does not generate an serr message for this event. serr messaging for device 3 is globally enabled in the pcicmd3 register. 1 reserved. 0 serr on receiving target abort (hiserta). 1 = mch generates an serr message over hub interface_a upon receiving a target abort on hub interface_c. 0 = mch does not assert an serr message upon receipt of a target abort on hub interface_c. serr messaging for device 3 is globally enabled in the pcicmd3 register.
register description r 138 intel ? 82860 mch datasheet this page is intentionally left blank.
system address map r intel ? 82860 mch datasheet 139 4 system address map a system based on the intel 82860 mch supports 16 gb of addressable memory space and 64 kb+3 of addressable i/o space. the i/o and memory spaces are divided by system configuration software into regions. the memory ranges are useful either as system memory or as specialized memory, while the i/o regions are used solely to control the operation of devices in the system. when the mch receives a write request whose address targets an invalid space, the data is ignored. for reads, the mch responds by returning all zeros on the requesting interface. 4.1 memory address ranges the system memory map is divided into three categories: ? high memory range (above 4 gb) ? the first is dram only, and exists between 4 gb and 16 gb (bit 32 of the address is active) ? extended memory range (1 mb to 4 gb) - the second is extended memory, existing between 1 mb and 4 gb. it contains a 32-bit memory space, which is used for mapping pci, agp, apic, smram, and bios memory spaces. ? dos compatible area (below 1 mb) - the final range is a dos legacy space, which is used for bios and legacy devices on the lpc interface. figure 4 shows the major portions of the system address map. figure 5 and figure 6 provide detailed address maps for the dos memory address range and extended memory address range. figure 4. system address map dos legacy address range main memory address range pci memory address range top of low memory 1 mb 4 gb hub interface_a-c agp graphics aperture i/o aperture apics independently programmable non-overlapping w indows sys_addr_map_1 additional main memory address range 16 gb
system address map r 140 intel ? 82860 mch datasheet these address ranges are always mapped to system memory, regardless of the system configuration. memory may be taken out of the main memory segment for use by system management mode (smm) hardware and software. the top of low memory (tom) register defines the top of main memory. note that the address of the highest 16 mb quantity of valid memory in the system is placed into the gba15 register. for memory populations < 3 gb, this value will be the same as the one programmed into the tom register. for other memory configurations, the two are unlikely to be the same, since the pci configuration portion of the bios software will program the tom register to the maximum value that is less than the amount of memory in the system and that allows enough room for all populated pci devices. figure 5. detailed dos compatible area address map monochrome display adapter space upper, lower, expansion card bios and buffer area 1 mb sys_addr_map_2 640 kb 704 kb 736 kb 768 kb 0a0000h 0b0000h 0b8000h 0c0000h standard pci/isa video memory (smm memory) controlled by pam[6:0] controlled by vga enable and mda enable = optional agp = optional dram = main memory
system address map r intel ? 82860 mch datasheet 141 figure 6. detailed extended memory range address map = main memory region = optional main memory region 1_0000_0000 (4 gb) fef0_0000 fee0_0000 fed0_0000 top of low memory (tom) fec0_0000 fec8_0000 ff00_0000 100a_0000 100c_0000 00f0_0000 (15 mb) 0100_0000 (16 mb) 0010_0000 (1 mb) tem - tseg high bios, optional extended smram sys_addr_map_3 isa hole extended smram (translated to < 1 mb) extended smram space local apic space hub interface_b-c, i/o apic space hub interface_a, i/o apic space agp/pci, hub interface_b-c hub interface_a (always) hub interface_a (always)
system address map r 142 intel ? 82860 mch datasheet 4.1.1 vga and mda memory space video cards use these legacy address ranges to map a frame buffer or a character-based video buffer. the address ranges in this memory space are: ? vgaa 0_000a_0000h to 0_000a_ffffh ? mda 0_000b_0000h to 0_000b_7fffh ? vgab 0_000b_8000h to 0_000b_ffffh by default, accesses to these ranges are forwarded to hub interface_a. however, if the vga_en bit is set in the bctrl1?3 configuration registers, then transactions within the vga and mda spaces are sent to agp or hub interface_b?c, respectively. note that the vga_en bit may be set in one and only one of the bctrl registers. software must not set more than one of the vga_en bits. if the configuration bit mchcfg.mdap is set, accesses that fall within the mda range will be sent to hub interface_a without regard for the vgaen bits. if the configuration bit mchcfg.mdap is set, then accesses that fall within the mda range will be sent to hub interface_a without regard for the vgaen bits. legacy support requires the ability to have a second graphics controller (monochrome) in the system. in an intel 82860 mch system, accesses in the standard vga range are forwarded to the agp or hub interface_b?c (depending on configuration bits). since the monochrome adapter may be on hub interface_a (or isa bus) the mch must decode cycles in the mda range and forward them to hub interface_a. this capability is controlled by a configuration bit (mdap bit). in addition to the memory range b0000h to b7fffh, the mch decodes i/o cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah, and 3bfh and forwards them to hub interface_a. an optimization allows the system to reclaim the memory displaced by these regions. if smm memory space is enabled by smram.g_smrare and either the smram.d_open bit is set or the processor bus receives an smm-encoded request for code (not data), then the transaction is steered to system memory rather than hub interface_a. under these conditions, both of the vgaen bits and the mdap bit are ignored.
system address map r intel ? 82860 mch datasheet 143 4.1.2 pam memory spaces the address ranges in this memory space are: ? pamc0 0_000c_0000h to 0_000c_3fffh ? pamc4 0_000c_4000h to 0_000c_7fffh ? pamc8 0_000c_8000h to 0_000c_bfffh ? pamcc 0_000c_c000h to 0_000c_ffffh ? pamd0 0_000d_0000h to 0_000d_3fffh ? pamd4 0_000d_4000h to 0_000d_7fffh ? pamd8 0_000d_8000h to 0_000d_bfffh ? pamdc 0_000d_c000h to 0_000d_ffffh ? pame0 0_000e_0000h to 0_000e_3fffh ? pame4 0_000e_4000h to 0_000e_7fffh ? pame8 0_000e_8000h to 0_000e_bfffh ? pamec 0_000e_c000h to 0_000e_ffffh ? pamf0 0_000f_0000h to 0_000f_ffffh the 256-kb pam region is divided into three parts: ? isa expansion region , a 128-kb area between 0_000c_0000h ? 0_000d_ffffh ? extended bios region , a 64-kb area between 0_000e_0000h ? 0_000e_ffffh ? system bios region , a 64-kb area between 0_000f_0000h ? 0_000f_ffffh. the isa expansion region is divided into eight, 16-kb segments. each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled. typically, these blocks are mapped through mch and are subtractively decoded to isa space. the extended system bios region is divided into four 16 kb segments. each segment can be assigned independent read and write attributes so it can be mapped either to main dram or to hub interface_a. typically, this area is used for ram or rom. the system bios region is a single 64-kb segment. this segment can be assigned read and write attributes. it is by default (after reset) read/write disabled and cycles are forwarded to hub interface_a. by manipulating the read/write attributes, the mch can ?shadow? bios into the main dram. 4.1.3 isa hole memory space bios software may optionally open a ?window? between 15 mb and 16 mb (0_00f0_0000h to 0_00ff_ffffh) that relays transactions to hub interface_a instead of completing them with a system memory access. this window is opened with the fdhc.hen configuration field.
system address map r 144 intel ? 82860 mch datasheet 4.1.4 tseg smm memory space the tseg smm space (tom ? tseg to tom) allows system management software to partition a region of main memory just below the top of low memory (tom) that is accessible only by system management software. this region may be 128 kb, 256 kb, 512 kb, or 1 mb, depending on the esmramc.tseg_sz field. smm memory is globally enabled by smram.g_smrare. requests may access smm system memory when either smm space is open (smram.d_open) or the mch receives an smm code request on its processor bus. in order to access the tseg smm space, the tseg must be enabled by esmramc.t_en. when all of these conditions are met, a processor bus access to the tseg space (between tom-tseg and tom) is sent to system memory. if the high smram is not enabled or if the tseg is not enabled, all memory requests from all interfaces are forwarded to system memory. if the tseg smm space is enabled, and an agent attempts a non-smm access to tseg space, the transaction is specially terminated. hub interface and agp originated accesses are not allowed to smm space. 4.1.5 i/o apic memory space the i/oapic spaces are used to communicate with i/o apic interrupt controllers that may be populated on hub interface_a?c. since it is difficult to relocate an interrupt controller using plug- and-play software, fixed address decode regions have been allocated for them. the address ranges are: ? ioapic0 (hub interface_a) 0_fec0_0000h to 0_fec7_ffffh ? ioapic1 (hub interface_b) 0_fec8_0000h to 0_fec8_0fffh ? ioapic2 (hub interface_c) 0_fec8_1000h to 0_fec8_1fffh processor accesses to the ioapic0 region are always sent to hub interface_a. processor accesses to the ioapic1 region are always sent to hub interface_b and so on. 4.1.6 system bus interrupt memory space the system bus interrupt space (0_fee0_0000h to 0_feef_ffffh) is the address used to deliver interrupts to the system bus. any device on agp or hub interface_a?c may issue a memory write to 0feex_xxxxh. the mch will forward this memory write, along with the data, to the system bus as an interrupt message transaction. the mch terminates the system bus transaction by providing the response and asserting trdy#. this memory write cycle does not go to dram. 4.1.7 high smm memory space the highsmm space (0_feda_0000h to 0_fedb_ffffh) allows cacheable access to the compatible smm space by re-mapping valid smm accesses between 0_feda_0000 and 0_fedb_ffff to accesses between 0_000a_0000 and 0_000b_ffff. the accesses are remapped when smram space is enabled, an appropriate access is detected on the processor bus, and when esmramc.h_smrame allows access to high smram space. smm memory accesses from any hub interface or agp are specially terminated: reads are provided with the value from address 0 while writes are ignored entirely.
system address map r intel ? 82860 mch datasheet 145 4.1.8 agp aperture space (device 0 bar) processors and agp devices communicate through a special buffer called the ?graphics aperture? (located at apbase to apbase + apsize). this aperture acts as a window into main memory and is defined by the apbase and apsize configuration registers of the mch. note that the agp aperture must be above the tom and must not intersect with any other address space. 4.1.9 agp memory and prefetchable memory plug-and-play software configures the agp memory window to provide enough memory space for the devices behind this pci-to-pci bridge. accesses whose addresses fall within this window are decoded and forwarded to agp for completion. the address ranges are: ? m1 mbase1 to mlimit1 ? pm1 pmbase1 to pmlimit1 note that these registers must be programmed with values that place the agp memory space window between the value in the tom register and 4 gb. in addition, neither region should overlap with any other fixed or relocatable area of memory. 4.1.10 hub interface_b memory and prefetchable memory plug-and-play software configures the hub interface_b memory window to provide enough memory space for the devices behind this pci-to-pci bridge. accesses whose addresses fall within this window are decoded and forwarded to hub interface_b for completion. the address ranges are: ? m2 mbase2 to mlimit2 ? pm2 pmbase2 to pmlimit2 note that these registers must be programmed with values that place the hub interface_b memory space window between the value in the tom register and 4 gb. in addition, neither region should overlap with any other fixed or relocatable area of memory. 4.1.11 hub interface_c memory and prefetchable memory plug-and-play software configures the hub interface_c memory window to provide enough memory space for the devices behind this pci-to-pci bridge. accesses whose addresses fall within this window are decoded and forwarded to hub interface_c for completion. the address ranges are: ? m3 mbase3 to mlimit3 ? pm3 pmbase3 to pmlimit3 note that these registers must be programmed with values that place the hub interface_c memory space window between the value in the tom register and 4 gb. in addition, neither region should overlap with any other fixed or relocatable area of memory.
system address map r 146 intel ? 82860 mch datasheet 4.1.12 hub interface_a subtractive decode all accesses that fall between the values programmed into the tom register and 4 gb are subtractively decoded and forwarded to hub interface_a, if they do not decode to a space that corresponds to another device. 4.2 agp memory address ranges the mch can be programmed to direct memory accesses to the agp bus interface when addresses are within either of two ranges specified via registers in mch device 1 configuration space. the first range is controlled via the memory base (mbase1) register and memory limit (mlimit1) register. the second range is controlled via the prefetchable memory base (pmbase1) register and prefetchable memory limit (pmlimit1) register. the mch positively decodes memory accesses to agp memory address space as defined by the following equations: ? memory_base_address address memory_limit_address ? prefetchable_memory_base_address address prefetchable_memory_limit_address the plug-and-play configuration software programs the effective size of the range and it depends on the size of memory claimed by the agp device. note: that the mch device 1 memory range registers described above are used to allocate memory address space for any devices sitting on agp bus that require such a window. 4.2.1 agp dram graphics aperture memory-mapped, graphics data structures can reside in a graphics aperture to main dram memory . this aperture is an address range defined by the apbase and apsize configuration registers of the mch device 0. the apbase register follows the standard base address register template as defined by the pci 2.1 specification. the size of the range claimed by the apbase is programmed via ?back-end? register apsize (programmed by the chipset specific bios before plug-and-play session is performed). apsize allows the bios software to pre-configure the aperture size to be 4 mb, 8 mb, 16 mb, 32 mb, 64 mb, 128 mb or 256 mb. by programming apsize to specific size, the corresponding lower bits of apbase are forced to 0 (behave as hardwired). default value of apsize forces an aperture size of 256 mb. the aperture address range is naturally aligned. accesses within the aperture range are forwarded to the main dram subsystem. the mch will translate the originally issued addresses via a translation table maintained in main memory. the range should be programmed as non-cacheable in the processor caches. note: plug-and-play software configuration model does not allow overlap of different address ranges. therefore the agp graphics aperture and agp memory address range are independent address ranges that may abut, but cannot overlap one another.
system address map r intel ? 82860 mch datasheet 147 4.3 system management mode (smm) memory range the mch supports the use of main memory as system management ram (smram) enabling the use of smm. the mch supports two smram options: compatible smram (c_smram) and extended smram (e_smram). system management ram (smram) space provides a memory area that is available for the smi handler?s and code and data storage. this memory resource is normally hidden from the system os so that the processor has immediate access to this memory space upon entry to smm. the mch provides three smram options: ? below 1 mb option that supports compatible smi handlers. ? above 1 mb option that allows new smi handlers to execute with write-back cacheable smram. ? optional larger write-back cacheable t_seg area from 128 kb to 1 mb in size above 1 mb is reserved from the highest area in system dram memory. the above 1-mb solutions require changes to compatible smram handlers? code to properly execute above 1 mb. note: masters from the hub interface and agp are not allowed to access the smm space. 4.3.1 smm space definition the addressed smm space is defined as the range of bus addresses used by the processor to access smm space. dram smm space is defined as the range of physical dram memory locations containing the smm code. smm space can be accessed at one of three transaction address ranges: compatible, high and tseg. the compatible and tseg smm space is not remapped; therefore, the addressed and dram smm space is the same address range. since the high smm space is remapped, the addressed and dram smm space is a different address range. note that the high dram space is the same as the compatible transaction address space. therefore, table 12 describes three unique address ranges: ? compatible transaction address ? high transaction address ? tseg transaction address table 12. smm space address ranges smm space enabled transaction address space dram space (dram) compatible a0000h to bffffh a0000h to bffffh high 0feda0000h to 0fedbffffh a0000h to bffffh tseg (tom-tseg_sz) to tom (tom-tseg_sz) to tom notes: 1. high smm: this is different than in previous chip sets. in previous chip sets the high segment was the 384-kb region from a0000h to fffffh. however, c0000h to fffffh was not practically useful so it is deleted in mch. 2. tseg smm: this is different than in previous chipsets. in previous chipsets the tseg address space was offset by 256 mb to allow for simpler decoding and the tseg was remapped to just under the tom. in the mch 256 mb do not offset the tseg region and it is not remapped.
system address map r 148 intel ? 82860 mch datasheet 4.3.2 smm space restrictions if any of the following conditions are violated, the results of smm accesses are unpredictable and may cause the system to hang: ? the compatible smm space must not be setup as cacheable. ? high or tseg smm transaction address space must not overlap address space assigned to system dram, the agp aperture range, or to any ?pci? devices (including hub interface and agp devices). this is a bios responsibility. ? both d_open and d_close must not be set to 1 at the same time. ? when tseg smm space is enabled, the tseg space must not be reported to the os as available main memory. this is a bios responsibility. ? any address translated through the agp aperture gtlb must not target main memory from 000a0000h to 000fffffh. 4.4 i/o address space the mch does not support the existence of any other i/o devices beside itself on the system bus. the mch generates either hub interface_a?c or agp bus cycles for all processor i/o accesses. the mch contains two internal registers in the processor i/o space, configuration address (conf_addr) register and the configuration data (conf_data) register. these locations are used to the implement configuration space access mechanism as described in the register description chapter. the processor allows 64k+3 bytes to be addressed within the i/o space. the mch propagates the processor i/o address without any translation on to the destination bus and therefore provides addressability for 64k+3 byte locations. note that the upper 3 locations can be accessed only during i/o address wrap-around when system bus a16# address signal is asserted. a16# is asserted on the system bus whenever an i/o access is made to 4 bytes from address 0fffdh, 0fffeh, or 0ffffh. a16# is also asserted when an i/o access is made to 2 bytes from address 0ffffh. the i/o accesses (other than ones used for configuration space access) are forwarded normally to either the hub interface_a, hub interface_b, or hub interface_c unless they fall within the agp i/o address range as defined by the mechanisms explained below. the mch will not post i/o write cycles to ide. the mch never responds to i/o or configuration cycles initiated on agp or any of the hub interfaces. hub interface transactions requiring completion are terminated with ?master abort? completion packets on the hub interfaces. hub interface write transactions not requiring completion are dropped. agp/pci i/o reads are never acknowledged by the mch.
system address map r intel ? 82860 mch datasheet 149 4.5 mch decode rules and cross-bridge address mapping the address map described above applies globally to accesses arriving on any of the five interfaces (i.e., host bus, hub interface_a, hub interface_b, hub interface_c, or agp). 4.5.1 hub interface_a decode rules the mch accepts accesses from the hub interface_a with the following address ranges: ? all memory read and write accesses to main memory (except smm space). ? all memory write accesses from the hub interface_a-to-agp memory range defined by mbase1, mlimit1, pmbase1, and pmlimit1. ? all memory read/write accesses to the graphics aperture defined by apbase and apsize. ? memory writes to vga range on agp if enabled. all memory reads from the hub interface_a that are targeted > 4 gb memory range are terminated with master abort completion, and all memory writes (> 4 gb) from the hub interface_a are ignored. 4.5.2 hub interface_b decode rules the mch accepts accesses from the hub interface_b from the following address ranges: ? all memory read and write accesses to main dram (except smm space). ? all memory write accesses from the hub interface-to-agp memory range defined by mbase2, mlimit2, pmbase2, and pmlimit2. ? all memory read/write accesses to the graphics aperture defined by apbase and apsize. ? memory writes to vga range on agp if enabled. memory accesses from the hub interface_b that fall elsewhere within the memory range and i/o cycles will not be accepted. they are terminated with master abort completion. 4.5.3 hub interface_c decode rules the mch accepts accesses from the hub interface_c from the following address ranges: ? all memory read and write accesses to main memory (except smm space). ? all memory write accesses from the hub interface-to-agp memory range defined by mbase3, mlimit3, pmbase3, and pmlimit3. ? all memory read/write accesses to the graphics aperture defined by apbase and apsize. ? memory writes to vga range on agp if enabled. memory accesses from the hub interface_c that fall elsewhere within the memory range and i/o cycles will not be accepted. they are terminated with master abort completion.
system address map r 150 intel ? 82860 mch datasheet 4.5.4 agp interface decode rules cycles initiated using agp frame# protocol the mch does not support any agp frame# access targeting the hub interface_a. the mch will claim agp-initiated memory read and write transactions decoded to the main memory range or the graphics aperture range. all other memory read and write requests are master-aborted by the agp initiator as a consequence of mch not responding to a transaction. under certain conditions, the mch restricts access to the dos compatibility ranges governed by the pam registers by distinguishing access type and destination bus. the mch does not accept agp frame# write transactions to the compatibility ranges if the pam designates main memory as writeable. if accesses to a range are not write-enabled by the pam, the mch does not respond and the cycle results in a master-abort. the mch accepts agp frame# read transactions to the compatibility ranges if the pam designates main memory as readable. if accesses to a range are not read-enabled by the pam, the mch does not respond and the cycle results in a master-abort. if an agent on agp issues an i/o, pci configuration or pci special cycle transaction, the mch does not respond and the cycle results in a master-abort. cycles initiated using agp pipe# or sb protocol all cycles must reference main memory; that is, main memory address range (including pam) or graphics aperture range (also physically mapped within main memory but using a different address range). agp accesses to smm space are not allowed. agp-initiated cycles that target main memory are not snooped on the host bus, even if they fall outside of the agp aperture range. if a cycle is outside of the main memory range, it terminates as follows: ? reads: remap to memory address 0h, return data from address 0h, and set the iaaf error bit in errsts register in device 0 ? writes: dropped ?on the floor? (i.e., terminated internally without affecting any buffers or main memory) agp accesses to mch that cross device boundaries for agp frame# accesses, when an agp master gets disconnected, it resumes at the new address which allows the cycle to be routed to or claimed by the new target. therefore, the target on potential device boundaries should disconnect accesses. the mch disconnects agp frame# transactions on 4 kb boundaries. agp pipe# and sba accesses are limited to 256 bytes and must hit main memory. read accesses crossing a device boundary returns invalid data when the access crosses out of main memory. write accesses crossing out of main memory are discarded. iaaf error bit will be set.
memory interface r intel ? 82860 mch datasheet 151 5 memory interface the mch directly supports dual channels (interfaces) of rambus direct rdram devices operating in lock-step using rsl technology. the mch supports two different operation modes: ? single channel-pair mode. the mch is configured to directly support direct rdram devices on its dual rambus interfaces. there is no intel mrh-r used on the memory subsystem. a maximum of 64 direct rdram devices are supported on the paired channels without external logic. ? multiple channel-pair mode. the mch is configured to use the intel mrh-r on the memory subsystem. each rambus channel of the intel mrh-r on the mch direct rambus channel a is paired with one rambus channel of the intel mrh-r on the direct rambus channel b. the mch supports one intel mrh-r per interface, and each intel mrh-r can support up to two rambus channels. therefore, up to four rambus channels are supported by the mch. the interface between the mch and direct rdram devices is referred to either as a ?channel? or as an ?expansion channel.? the channel interface consists of 33 signals including clocks (30 signals are rsl and three signals are cmos). there are two additional rsl signals per channel when the intel mrh-r is used for channel expansion. figure 7 shows the interconnections between the mch and its dual rambus channels configured in single channel-pair mode.
memory interface r 152 intel ? 82860 mch datasheet figure 7. single channel-pair mode mch channel a rdram* device cfm_a, cfm_a# rq_a[7:0] dq_a[15:0], dqp_a[1:0] sfm, stm, scfm ctm, ctm# terminator cfm, cfm# rq[7:0] dq[15:0], dqp[1:0] sfm, stm, scfm gen clock channel b rdram device cfm, cfm# rq[7:0] dq[15:0], dqp[1:0] sfm, stm, scfm ctm, ctm# terminator cfm, cfm# rq[7:0] dq[15:0], dqp[1:0] sfm, stm, scfm gen clock single_pr-ch up to 32 devices up to 32 devices figure 8 shows the interconnections between mch and its dual rambus channels configured at multiple channel-pair mode.
memory interface r intel ? 82860 mch datasheet 153 figure 8. multiple channel-pair mode multi_pr-ch terminator rambus* channel b expansion mrh-r mch up to 32 rdram* devices terminator rambus* channel a expansion mrh-r the maximum system memory supported by the mch depends on the direct rdram device technology (section 1.4.2, memory interface lists the maximum memory supported). the row, column, and bank address bits required for the direct rdram device depends on the number of banks and page size of the device (see section 1.4.2, memory interface for further information). a brief overview of the registers that configure the direct rdram device interface is provided below: ? group boundary address register (gba). gba registers define the upper and lower addresses for a group of direct rdram device pairs in a channel-pair. each group requires a separate gba register. each group consists of four device-pairs in single-channel mode and eight device-pairs in multiple-channel mode. the mch contains 16 gba registers. ? group architecture register (gar). gar registers specify the architecture features of each group of device pairs in a channel pair. the architecture features specified are bank-type and device-core technology. each gar represents a group consisting of four device-pairs in single-channel mode and eight device-pairs in multiple-channel mode. there is a 1:1 correspondence between gba and gar registers. ? direct rdram device timing register (rdtr). the dtr defines the timing parameters for all devices in all channels. bios programs this register with ?least common denominator? values after reading the configuration registers of each device in the channels. ? direct rdram device pool sizing register (rpmr). this register provides bits to program the number of rdram device-pair in one of three rdram power management states. ? direct rdram device initialization control register (ricm). this register provides bits to program the mch to do initialization activities on direct rdram devices.
memory interface r 154 intel ? 82860 mch datasheet 5.1 direct rdram* device organization and configuration the mch supports 16-/18-bit direct rdram device configurations. the mch supports a maximum of 64 direct rdram devices (32 devices per channel) on its dual rambus channels. the rambus channel can be populated with a mix of 128-/144-mbit and 256-/288-mbit direct rdram devices. 5.1.1 rules for populating direct rdram* devices mch rambus channels can be fully or partially loaded with direct rdram devices; however, they must be populated in either single-device pair or multiple-device pair. ? single-device-pair. the mch is configured to directly support direct rdram devices on its dual rambus channel. each direct rdram device of the mch rambus channel a is paired with one direct rdram device of the rambus channel b. there is no intel mrh-r used on the memory subsystem. ? multiple device-pair. the mch is configured to use intel mrh-r on the memory subsystem. each direct rdram device on rambus channel a is paired with one direct rdram device on the rambus channel b. note: the mch supports a maximum of two rimms per channel. from the mch point of view, all device-pairs in the channels are grouped into logical groups. system initialization software partitions the direct rdram devices into groups of four device- pairs in single-channel mode operation and into groups of eight device-pairs in multiple channel mode operation. as a result, there can be a maximum of eight groups per channel-pair in single- channel pair operation and a maximum of four groups per channel pair in multiple channel-pair mode. all device-pairs populated in a group must be of the same architecture. in other words all device-pairs in a group must be the same core technology and have the same number of banks. following are the rules for populating the groups: ? a group can be partially populated. ? there is no requirement that group members have to be populated in contiguous physical slots. ? there can be a maximum of eight groups in single-channel pair mode or four groups per channel in multiple channel-pair mode. a member that does not belong to any of the groups in the channel will not be recognized.
memory interface r intel ? 82860 mch datasheet 155 table 13 provides the device ids for members in all groups. table 13. direct rdram* device grouping single-channel mode multiple channel mode device-pair ids for group members group name device pair ids for group members group name 0, 1, 2, 3 group#0 0, 1, 2, 3, 4, 5, 6, 7, ch#0 pair, group#0 4, 5, 6, 7 group#1 8, 9, 10, 11, 12, 13, 14, 15 ch#0 pair, group#1 8, 9, 10, 11 group#2 16, 17, 18, 19, 20, 21, 22, 23 ch#0 pair, group#2 12, 13, 14, 15 group#3 24, 25, 26, 27, 28, 28, 30, 31 ch#0 pair, group#3 16, 17, 18, 19 group#4 0, 1, 2, 3, 4, 5, 6, 7, ch#1 pair, group#0 20, 21, 22, 23 group#5 8, 9, 10, 11, 12, 13, 14, 15 ch#1 pair, group#1 24, 25, 26, 27 group#6 16, 17, 18, 19, 20, 21, 22, 23 ch#1 pair, group#2 28, 29, 30, 31 group#7 24, 25, 26, 27, 28, 28, 30, 31 ch#1 pair, group#3 0, 1, 2, 3, 4, 5, 6, 7, ch#2 pair, group#0 8, 9, 10, 11, 12, 13, 14, 15 ch#2 pair, group#1 16, 17, 18, 19, 20, 21, 22, 23 ch#2 pair, group#2 24, 25, 26, 27, 28, 28, 30, 31 ch#2 pair, group#3 0, 1, 2, 3, 4, 5, 6, 7, ch#3 pair, group#0 8, 9, 10, 11, 12, 13, 14, 15 ch#3 pair, group#1 16, 17, 18, 19, 20, 21, 22, 23 ch#3 pair, group#2 24, 25, 26, 27, 28, 28, 30, 31 ch#3 pair, group#3 all rsl signals must be terminated at the far end from the mch. the default device id for a direct rdram device after power up is 1fh.
memory interface r 156 intel ? 82860 mch datasheet 5.1.2 direct rdram* device cmos signals there are three cmos signal pins per channel on the mch to support direct rdram device configuration, sio reset, register accesses, and nap and powerdown exits. these signals are sck, cmd and sio. these signals are used to perform the following operations: ? sio pin initialization ? sio operations (includes register accesses and device reset) ? device selection for nap and powerdown exits note: the mch supports dual rambus channels figure 9. direct rdram* devices sideband cmos signal configuration on rambus* channel a rdram_cmos sio sio1 sio0 sio0 sck cmd sck cmd mch rambus* channel a note: mch supports dual rambus channels. rdram* device rdram device rdram device rdram device table 14. sideband cmos signal description signal description sck serial clock: this signal serves as the clock for sio and cmd signals. sck is a clock source used for reading from and writing to control register. ? for sio operations and pin initialization, sck 1 mhz ? for power mode operations, sck 100 mhz cmd command: cmd is a control signal used for power mode transitions, sio pin configuration during initialization, and framing of sio operations. cmd is active high. cmd is sampled at both edges of sck. cmd is a level sensitive signal. sio serial in out: this bi-directional signal is daisy chained through all direct rdram* devices (sio0 to sio1) in a channel. this pin carries data used for sio operations, which include register accesses, device reset, and device id initialization. it is also used for power mode control. sio is an active low signal and is sampled on the falling edge of sck.
memory interface r intel ? 82860 mch datasheet 157 table 15. cmd signal value decode sio = 0, cmd sample value on 4 sck edges command sio = 1, cmd sample value on 4 sck edges command cycle 0 cycle 1 cycle 0 cycle 1 0 1 x x nap exit 0 1 x x power-down exit 1 0 x x reserved 1 0 x x reserved 0 0 x x no-op 0 0 x x no-op 1 1 1 1 sio request frame 1 1 1 1 sio request frame 1 1 0 0 sio reset 1 1 0 0 sio reset 1 1 1 0 reserved 1 1 1 0 reserved 1 1 0 1 reserved 1 1 0 1 reserved sio pin initialization the sio0 and sio1 pins on the direct rdram devices are bi-directional and their direction needs to be initialized. the ?sio reset? initializes the sio0 and sio1 pins on all direct rdram devices as daisy chain configuration and is performed with the sck and cmd. once the sio daisy chain is fully configured, sio operations can occur. note: ?sio reset? does not reset the entire device. for a complete description of the operation and associated timing diagrams, refer to the direct rdram component data sheet from rambus. sio operations sio operations are also known as direct rdram device initialization operations. these operations include direct rdram device register accesses and device reset, and is performed using the cmos pins: sck, cmd, sio0, and sio1. for a complete description of operation and associated timing diagram, refer to direct rdram component data sheet from rambus. nap and powerdown exits the nap and powerdown exits are performed using cmd, sio and sck signals. for complete description and timing diagrams associated with nap and powerdown exits, refer to direct rdram component data sheet from rambus*.
memory interface r 158 intel ? 82860 mch datasheet 5.1.3 direct rdram* device core refresh all rows in a direct rdram device must be refreshed within 32 ms. the refresh rate depends on the device size and page size of a device. the mch supports two core refresh mechanisms: active refresh and self refresh ? active refresh: refresh and precharge after refresh commands are issued from the primary control packet. these commands provide refresh support in standby/active modes. ? self refresh: internal time-base and row/bank address counters in the core allow for a self refresh in powerdown modes without controller support. direct rdram* device current calibration all direct rdram devices must be current calibrated once every 100 ms. there are rsl commands to perform this function. the mch schedules periodic current calibration activity such that every device in the channel is current calibrated at least once every 100 ms. 5.2 direct rdram* device command encoding the operations on a rambus channel are performed using control packets. there are two types of command packets: row (rowa/rowr) packet and column (colc/colm/colx) packet. each command packet requires four direct rdram device clock durations and packet data is transferred on both (leading and falling) edges of the clock. the row packet contains 24 bits and the column packet contains 40 bits. 5.2.1 row packet (rowa/rowr) the row packet is defined using three rsl signals rq[7:5]/row[2:0]. it will generally be the first control packet issued to a device. major characteristics of row packet are: ? the only way to activate (sense) a row within a bank ? independent of direct rdram device active/standby state ? a non-broadcast row package causes an addressed direct rdram device to move to active state
memory interface r intel ? 82860 mch datasheet 159 the packet definition of row packet is given below. table 16. rowa packet for activating (sensing) a row (i.e., av = 1) row cycle 0 cycle 1 cycle 2 cycle 3 row 2 dr4t dr[2] br[0] br[3] r[10] r[8] r[5] r[2] row 1 dr4f d[r1] br[1] br[4] r[9] r[7] r[4] r[1] row 0 dr[3] dr[0] br[2] rev av = 1 r[6] r[3] r[0] table 17. rowr packet for other operations (i.e., av = 0) row cycle 0 cycle 1 cycle 2 cycle 3 row 2 dr4t dr[2] br[0] br[3] rop[10] rop[8] rop[5] rop[2] row 1 dr4f dr[1] br[1] br[4] rop[9] rop[7] rop[4] rop[1] row 0 dr[3] dr[0] br[2] rev av = 0 rop[6] rop[3] rop[0] dr4t dr4f device id 0 0 no row packet 0 1 dr[3:0], dr[4] = 0 1 0 dr[3:0], dr[4] = 1 1 1 broadcast notes: 1. dr[4]?dr[0] device address 2. br[5]?br[0] bank address 3. r[10]?r[0] row address 4. av select between rowa and rowr, active row 5. rop[10]?rop[0] opcode for primary control packet 6. rev reserved
memory interface r 160 intel ? 82860 mch datasheet table 18. row packet encodings opcode bits av 10 9 8 7 6 5 4 3 2: 0 operation description 1 x x x x x x x x xxx activate row 0 1 1 0 0 0 0 0 0 000 precharge 0 1 1 0 0 0 0 0 1 000 precharge and relax 0 0 0 0 1 1 0 0 0 000 refresh 0 1 0 1 0 1 0 0 0 000 precharge postrefresh 0 0 0 0 0 0 1 0 0 000 nap 0 0 0 0 0 0 1 1 0 000 conditional nap 0 0 0 0 0 0 0 1 0 000 power down 0 0 0 0 0 0 0 0 1 000 relax 0 0 0 0 0 0 0 0 0 010 temp calibration enable 0 0 0 0 0 0 0 0 0 001 temp calibration 0 0 0 0 0 0 0 0 0 000 no-op notes: 1. x = controller drives 0 or 1 2. 0 = controller drives 0 3. 1 = controller drives 1 5.2.2 column packet (colc/colx) the column packet is defined using five of the rsl signals rq[4:0]/col[4:0]. major characteristics of column are: ? the only way to dispatch column operation for read or write ? requires the target direct rdram device to be in active state note: when a direct rdram device is in the active state, it can receive both row and column packets. when a direct rdram device is in the standby state, it can only receive a row packet. thus, before sending a column packet, make sure the addressed direct rdram device is in the active state.
memory interface r intel ? 82860 mch datasheet 161 the packet definition of column packet is given below. table 19. colc packet column cycle 0 cycle 1 cycle 2 cycle 3 col4 dc[4] s = 1 c[6] c[4] col3 dc[3] c[5] c[3] col2 dc[2] cop[1] rev bc[2] c[2] col1 dc[1] cop[0] bc[4] bc[1] c[1] col0 dc[0] cop[2] cop[3] bc[3] bc[0] c[0] notes: 1. dc[4:0] device id for column operation 2. s start bit; for framing 3. m mask bit; asserted indicates mask format for packet 4. cop[3:0] column operation code 5. c[6:0] address for column operation 6. bc[4:0] bank address for column operation 7. rev reserved table 20. colc packet field encodings s cop[3] cop[2] cop[1] cop[0] command operation 0 x x x x no operation 1 x 0 0 0 nocop. retire write buffer of this device 1 x 0 0 1 write 1 x 0 1 1 read note: all other combination are reserved colx packet (m = 0) column cycle 0 cycle 1 cycle 2 cycle 3 col4 dx[4] xop[4] rev bx[1] col3 m = 0 dx[3] xop[3] bx[4] bx[0] col2 dx[2] xop[2] bx[3] col1 dx[1] xop[1] bx[2] col0 dx[0] xop[0] notes: 1. dx[4:0] device id for extra operation 2. bx[4:0] bank address for extra operation 3. ma[7:0] byte mask (low order) 4. mb[7:0] byte mask (high order) 5. xop[4:0] opcode for extra operation 6. rev reserved
memory interface r 162 intel ? 82860 mch datasheet table 21. colm packet and colx packet field encodings m xop bits operation description 4 3 2 1 0 1 x x x x x non existent xop 0 0 0 0 0 0 noxop 0 1 0 0 0 0 reserved 0 0 1 0 0 0 calibrate current 0 0 1 1 0 0 calibrate current and sample 0 0 0 0 0 1 reserved notes: 1. x = controller drives 0 or 1 2. 0 = controller drives 0 3. 1 = controller drives 1 5.2.3 data packet table 22. data packet data signals cycle 0 cycle 1 cycle 2 cycle 3 dqa[8:0] da0[8:0] da1[8:0] da2[8:0] da3[8:0] da4[8:0] da5[8:0] da6[8:0] da7[8:0] dqb[8:0] db0[8:0] db1[8:0] db2[8:0] db3[8:0] db4[8:0] db5[8:0] db6[8:0] db7[8:0] 5.3 direct rdram* device register programming software can read and write direct rdram device registers by programming the direct rdram device initialization control management register (ricm) in the mch. the register data returned by the device is available in the device register data register (drd). 5.4 direct rdram* device operating states the direct rdram devices support different operating and idle states to minimize the power consumption and thermal overload. table 23 provides an overview of the different operating/power states supported by direct rdram devices.
memory interface r intel ? 82860 mch datasheet 163 table 23. dram operating states direct rdram* device state functionality refresh scheme direct rdram device clock state inactive states powerdown no operation allowed except refresh. direct rdram* device awaits cmos signals to exit powerdown state self refresh stopped nap no operation allowed except refresh. direct rdram device awaits nap exit command to exit nap active refresh stopped active states standby device ready to receive row packet with fast clock active refresh full speed active device ready to receive any control packet active refresh full speed active-read device ready to receive any control packet. transmitting data on channel active refresh full speed active-write device ready to receive any control packet. receiving data from channel active refresh full speed active-read/write state a direct rdram device is in active-read/write state when it is transferring data. this state lasts as long as data transfer is occurring. once the data transfer is complete, the direct rdram device transitions into active or standby state based on the column command last executed. active state a direct rdram device enters into the active state immediately after the data transfer from/to that device is complete and the last colc command that caused the data transfer does not have its rc bit set to 1. when a device is in active state, it can accept both row and column packets. standby state a direct rdram device enters into standby state either from active-read/write or active state. transition from active-read/write to standby happens if the last column executed has its rc bit set to 1. transition from active-to-standby happens if colc or row specifies an operation with the relax command. when a device is in standby mode it can accept only row packets. once a device receives any row packet, it transitions into active state and then only it can accept a column packet. nap state a direct rdram device enters into nap state when it receives a row packet that specified an operation with nap. no operation except refresh is allowed during nap state. powerdown state a direct rdram device enters into powerdown state when it receives a row packet that specified an operation with powerdown. no operations except self-refresh is allowed during powerdown state.
memory interface r 164 intel ? 82860 mch datasheet 5.5 direct rdram* device operating pools to minimize the operating power, the direct rdram devices are grouped into three operating pools called pool ?a?, pool ?b?, and pool ?c?. pool ?a?, pool ?b?, and pool ?c? operation in the pool mode, three queues are used inside the mch. the ?a? pool contains references to device pairs that are currently in the active mode; the ?b? pool contains references to device pairs that are in the standby mode. all devices that are not found in pool ?a? or ?b? are said to be in pool ?c? and can be configured for either napping or standby. the ?a? pool may hold between 1 and 8 device pairs, while the ?b? pool may be configured to contain between 1 and 16 device pairs. 5.6 direct rdram* device power management systems based on the intel 82860 mch support acpi-based power management. the mch puts all direct rdram devices into powerdown (pd) state during s3 power management states. to enter the powerdown state all direct rdram devices in the channel must be in active or standby state. the mch then sends a broadcast powerdown command to that channel. during the powerdown state, direct rdram devices are put into self-refresh mode so that external (active) refreshes are not required. during the powerdown state, the clocks to direct rdram devices are shut off. exiting the power-down and nap states are done through cmos signals. table 24 shows the actions taken by the mch during different processor and system power states. table 24. direct rdram* device power management states processor state system state state of direct rdram* devices in pool ?a? state of direct rdram devices in pool ?b? state of direct rdram devices in pool ?c? refresh scheme direct rdram device clock state c0, c1, c2 (processor in working state) s0 active- read/write, active standby nap or standby active running (processor in inactive state) s1, s3( str) no devices in pool ?a? no devices in pool ?b? power- down self stopped
memory interface r intel ? 82860 mch datasheet 165 5.7 data integrity the mch supports an error correcting code (or error checking and correcting) on the main memory interface. the mch can optionally be configured to generate the ecc code for writes to memory and check the code for reads from memory. the mch generates an 8-bit code word for each 64-bit qword of memory. since the code word covers a full qword, writes of less than a qword require a read-merge-write operation. consider a dword write to memory. in this case, when in ecc mode, the mch will read the qword where the addressed dword will be written, merge in the new dword, generate a code covering the new qword and finally write the entire qword and code back to memory. any correctable (single) errors detected during the initial qword read are corrected before merging the new dword. single-bit and multiple-bit errors set separate flags in the errsts register. single-bit errors and multiple-bit errors can be independently enabled to generate hub interface serr, smi, or sci special cycles to the ich2. the address and syndrome of the first single-bit error are latched in the eap and derrctl registers. subsequent single-bit errors will not overwrite the eap and derrctl registers unless the single-bit error status bit is cleared. a multiple-bit error will overwrite the eap and derrctl registers. subsequent multiple-bit errors will not overwrite the eap and derrctl registers unless the multiple-bit error status bit is cleared. note: during a write to memory over hub interface_b/c, if a parity error occurs, the byte enables will be turned off. parity errors will be logged and can be recovered by system or device handlers. data with parity errors will not be merged into memory. some pci cards do not implement parity correctly. if a false parity error occurs, that transaction will not be placed in memory. note: when an intel 860 chipset platform is configured for ecc support, if a multi-bit uncorrectable memory error is detected during a memory read by a system device, an serr, sci, or smi will be generated. this typically results in an nmi; however, bad data can still reach the intended target before the nmi can be generated or before the nmi interrupt handler can service the problem. this can result in bad data being returned to the target and may be permanently stored, resulting in system data corruption. this chipset was not designed to ensure that targets are protected from this corrupted data in these situations.
memory interface r 166 intel ? 82860 mch datasheet 5.8 direct rdram* device array thermal management the direct rdram device thermal and power management of the mch has been optimized for workstation system designs. it is assumed that proper system design will always provide and ensure adequate cooling in a system based on the intel 860 chipset. the failsafe mechanism that protects the devices in the event of a catastrophic failure requires an external thermal sensor. when the thermal sensor is activated, the mch immediately exits the ?all devices on? mode and reverts to the pool mode that has been programmed by system software. in a system based on the intel 82860 mch, direct rdram devices operate in one of three modes: active, standby, or nap. the number of devices allowed in each state at any given time is dictated by the heat dissipation budget specified by the system designer. at any point, between 1 and 8 device-pairs may be in the ?a? pool and are configured to operate in the active mode. in addition, between 1 and 16 device-pairs may be in the ?b? pool and are configured to operate in the standby mode. the rest of the device-pairs are in the ?c? pool and may be configured to operate in either nap mode or standby mode. regardless of how many devices are configured into the ?a? and ?b? pools or whether the ?c? pool devices are in napping or standby mode, the system designer is responsible for providing adequate cooling for the number of direct rdram devices in the system. after bios loads the system?s ?target? values into the dps register and initializes the pools, it should load a ?safer? set of values into the dps register without setting the poolinit field. the poolinit bit instructs the mch to transition to the new pool sizes. there are two other conditions that cause the mch to resize and initialize the pools: ? the transition of the overt# pin from electrical 1 to electrical 0 ? the detection of an over-temperature condition on any direct rdram device the overt# method is intended to allow system designers to use external thermal sensors to monitor the system temperature and assert overt# when the system temperature exceeds system specifications. when the mch detects a falling edge on the overt# signal, it reinitializes and resizes the pools with the values that are in the dps register. also, the direct rdram devices report over-temperature conditions back to the mch via a special bit asserted during their current calibration operations. when the mch detects an over-temperature condition in any of the memory devices, the direct rdram device pools are reinitialized with ?safer? values. finally, the mch may be configured to send an serr, sci, or smi hub interface message to ich2. software may take action to cool the system or to log the condition
electrical characteristics r intel ? 82860 mch datasheet 167 6 electrical characteristics this chapter provides the absolute maximum ratings, thermal characteristics and dc characteristics for the intel 82860 mch. agtl+ (assisted gunning transceiver logic) signals are open-drain and require termination to a supply that provides the high signal level. termination resistors are provided on the mch and are terminated to vtt. this eliminates the need to terminate the bus on the system motherboard. for reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. unused agtl+ inputs should be left as no connects, as agtl+ termination is provided on the chip. unused active high inputs should be connected through a resistor to ground (vss). unused outputs can be left unconnected. the direct rdram device interface introduces a new type of interface called rsl (rambus signaling level) signaling. rsl signals are open-drain drivers and must be terminated to 1.8 v via a 28 ? termination resistor. 6.1 absolute maximum ratings table 25 lists the mch?s maximum environmental stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operating beyond the ?operating conditions? is not recommended and extended exposure beyond ?operating conditions? may affect reliability. table 25. absolute maximum ratings symbol parameter min max unit notes tdie die temperature under bias 0 110 c 1 tstorage storage temperature 0 105 c vcc 1.8 v supply voltage with respect to vss -0.3 2.5 v vtt agtl+ buffer dc input voltage with respect to vss 1.4 1.7 v vddq agp bus dc input voltage with respect to vss 1.4 1.8 v notes: 1. based on a no heatsink condition.
electrical characteristics r 168 intel ? 82860 mch datasheet 6.2 thermal characteristics the mch is designed for operation at die temperatures between 0 c and 110 c. the thermal resistance of the package is provided in table 26. table 26. intel ? 860 chipset package thermal resistance parameter air flow ( c/watt) no air flow 1 m/s psi jt 0.0 0.7 theta ja 20.0 16.0 note: typical value measured in accordance with eia/jesd 51-2 testing standard. 6.3 power characteristics table 27. dc characteristics functional operating range (vcc1_8 = 1.8v 5%; tdie = 110 c) symbol parameter min typ max unit notes p colusa thermal power dissipation for intel ? 860 chipset 7.2 9.5 w 1 i vtt intel 860 chipset vtt supply current 2.2 a i ddq power supply current for agp interface 370 ma i cc power supply current for intel 860 chipset 4.3 a notes: 1. this specification is the thermal design power and it is the estimated maximum possible expected power generated in a component by a realistic application. it is based on extrapolations in both hardware and software technology over the life of the component. it does not represent the expected power generated by a power virus. studies by intel indicate that no application will cause thermally significant power dissipation exceeding this specification, although it is possible to concoct higher power synthetic workloads that write but never read. under realistic read/write conditions, this higher power workload can only be transient, and is accounted in the icc (max) specification. for more information, refer to the intel ? 860 chipset thermal considerations application note (ap-721).
electrical characteristics r intel ? 82860 mch datasheet 169 6.4 i/o interface signal groupings the signal description includes the type of buffer used for the particular signal: agtl+ open drain agtl+ interface signal. refer to the agtl+ i/o specification for complete details. the mch integrates agtl+ termination resistors. agp agp interface signals. these signals are compatible with agp 2.0 1.v signaling environment dc and ac specifications. the buffers are not 3.3 v tolerant. cmos 1.8v cmos buffers. rsl rambus signaling level interface signal. refer to the rdram* direct specification for complete details. rcmos rcmos buffers are 1.8 v cmos buffers used for the cmos signals on the direct rdram device interface. table 28. signal groups signal group signal type signals notes (a) agtl+ i/o ads#, ap[1:0]#, bnr#, bro#,dbsy#, dp[3:0]#, dbi[3:0]#, drdy#, ha[35:3]#, hadstb[1:0] #, hd[63:0]#,hdstbp[3:0]#, hdstbn[3:0]#, hit#, hitm#, hreq[4:0]# (b) agtl+ output bpri#, cpurst#, defer#, htrdy#, rs[2:0]#, rsp# (c) agtl+ input hlock#, berr# (d) hub interface?s cmos i/o hl_a[11:0], hla_stb, hla_stb#, hl_b[19:0], hlb_stb[1:0], hlb_stb[1:0]#, hl_c[19:0], hlc_stb[1:0], hlc_stb[1:0]# (e) cmos output chx_hclk[a,b], chx_rclk[a,b] (f) cmos input testin#, overt#, buspark, hla_enh# (g) miscellaneous cmos input rstin#(3.3 v) (h) cmos clock input bclk[1:0], 66in 1 (i) rsl i/o dqa_a[8:0], dqb_a[8:0], dqa_b[8:0], dqb_b[8:0] (j) rsl output rq_a[7:5], rq_a[4:0], cfm_a, cfm_a#, exp_a[1:0], rq_b[7:5], rq_b[4:0], cfm_b, cfm_b#, exp_b[1:0] 2 (k) rsl input ctm_a, ctm_a#, ctm_b, ctm_b# 2 (l) rambus* cmos i/o sio_a, sio_b (m) rambus* cmos output cmd_a, sck_a, cmd_b, sck_b (n) agp input pipe#, sba[7:0], rbf#, wbf#, sb_stb, sb_stb#, g_req#, g_serr# (o) agp output st[2:0], g_gnt#
electrical characteristics r 170 intel ? 82860 mch datasheet signal group signal type signals notes (p) agp i/o ad_stb0, ad_stb0#, ad_stb1, ad_stb1#, g_frame#, g_irdy#, g_trdy#, g_stop#, g_devsel#, g_ad[31:0], g_c/be[3:0]#, g_par (q) rsl reference cha_ref[1:0], chb_ref[1:0] (r) agtl+ reference havref[1:0], hdvref[3:0], ccvref (s) hub interface?s and agp reference gref_0, gref_1, hlref_a, hlref_b, hlref_c (t) host compensation reference voltage hswng[1:0] (u) agp / hub interface compensation reference voltage hlswng_b, hlswng_c,g_swng (v) agp i/o voltage vddq (w) agtl+ termination voltage vtt (x) 1.8v vcc1_8 notes: 1. 66in is a 3.3 v signal coming from the system clock generator. a voltage translation occurs internally before the clocks are utilized in the 1.8 v mch. 2. ctm_a, ctm_a#, ctm_b, ctm_b#, cfm_a, cfm_a#, cfm_b, cfm_b# rambus* channel differential clocks are also operating at a different dc value. for further details, refer to the drcg data sheet at www.rambus.com
electrical characteristics r intel ? 82860 mch datasheet 171 6.5 dc characteristics table 29. dc characteristics at vcc1_8 = 1.8v 5% symbol signal group parameter min nom max unit notes i/o buffer supply voltage vcc1_8 (x) cmos i/o supply voltage 1.71 1.8 1.89 v vddq (v) agp i/o supply voltage 1.425 1.5 1.575 v vtt (w) host agtl+ termination voltage 1.44 1.6 1.7 v reference voltage ccvref (r) host common clock reference voltage 0.64 x vtt 2/3 x vtt 0.70 x vtt v chx_ref (q) rambus* channel rsl reference voltage 1.32 1.40 1.48 v gref/ hlref (s) hub interface reference voltage when configured for enhanced buffer mode 0.64 x vcc1_8 2/3 x vcc1_8 0.70 x vcc1_8 v hub interface reference voltage when configured for standard buffer mode 0.48 x vcc1_8 1/2 x vcc1_8 0.52 x vcc1_8 v agp reference voltage 0.48 x vddq 1/2 x vddq 0.52 x vddq v hxvref (r) host address and data reference voltage 0.64 x vtt 2/3 x vtt 0.70 x vtt v hswing (t) host compensation reference voltage 0.32 x vtt 1/3 x vtt 0.35 x vtt v (u) hub interface compensation reference voltage 0.32 x vcc1_8 1/3 x vcc1_8 0.35 x vcc1_8 v agp compensation reference voltage 0.48 x vddq 1/2 x vddq 0.52 x vddq v
electrical characteristics r 172 intel ? 82860 mch datasheet symbol signal group parameter min nom max unit notes host interface v il_h (a), (c) host agtl+ input low voltage ? ? (2/3 x vtt) - 0.1 v v ih_h (a), (c) host agtl+ input high voltage (2/3 x vtt) + 0.1 ? ? v v ol_h (a), (b) host agtl+ output low voltage ? ? (1/3 x vtt) + 0.1 v vtt =1.7 v v oh_h (a), (b) host agtl+ output high voltage vtt - 0.1 ? ? v i ol_h (a), (b) host agtl+ output low leakage 19 26.65 34 ma v ol max i l_h (a), (c) host agtl+ input leakage current ? ? 10 a v ol electrical characteristics r intel ? 82860 mch datasheet 173 symbol signal group parameter min nom max unit notes i oh_rc (l), (m) direct rdram device cmos output high current 35.5 ? ? ma v oh = (vcc 1.8/ 2) + 0.4 and vcc 1.8 (max) i l_rc (l) direct rdram device cmos input leakage current ? ? 10 a 0 < vin < vcc1_8 c in_r (i) rsl input capacitance 4 ? 6 pf f c =1 mhz c in_rc (l) direct rdram device cmos input (sck, cmd) capacitance 7 ? 9 pf f c =1 mhz (l) direct rdram device cmos input (sio) capacitance 4 ? 6 pf f c =1 mhz agp interface v il_a (n), (p) agp input low voltage -0.5 ? 0.4 x vddq v v ih_a (n), (p) agp input high voltage 0.6 x vddq ? vddq + 0.5 v v ol_a (o), (p) agp output low voltage ? ? 0.15 x vddq v v oh_a (o), (p) agp output high voltage 0.85 x vddq ? ? v i ol_a (o), (p) agp output low current ? ? 1 ma v ol =0.15 vddq i oh_a (o), (p) agp output high current -0.2 ? ? ma v oh =0.85 vddq i l_a (n), (p) agp input leakage current ? ? 10 a 0 electrical characteristics r 174 intel ? 82860 mch datasheet symbol signal group parameter min nom max unit notes i oh_hl (d) hub interface output high current -1 ? ? ma v oh =0.9 x vcc1_8 i l_hl (d) hub interface input leakage current ? ? 10 a 0 electrical characteristics r intel ? 82860 mch datasheet 175 symbol signal group parameter min nom max unit notes i oh_hl (d) hub interface output high current ? ? 1 ma i l_hl (d) hub interface input leakage current ? ? 10 a 0 electrical characteristics r 176 intel ? 82860 mch datasheet this page is intentionally left blank.
ballout and package information r intel ? 82860 mch datasheet 177 7 ballout and package information 7.1.1 ballout information this section lists the mch ballout assignment. figure 10 and figure 11 show the footprint ballout assignment from a top view of he package. table 30 lists the ballout assignment. if hub interface_b or hub interface_c is not used, only the corresponding hlswng and hlref should be connected to vcc1_8 and the hub interface vref circuit respectively. the rest of the unused hub interface pins may be left as no connect.
ballout and package information r 178 intel ? 82860 mch datasheet figure 10. mch ballout with agp and hub interface ball names (top view ? left side) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 am g_ad8 vddq g_ad15 g_c/be1# vss g_ad18 g_ad22 vddq g_ad24 g_ad28 vss sb_stb wbf# g_gnt# al g_ad6 g_c/be0# g_ad11 vss rsvd g_c/be2# vddq rsvd g_c/be3# vss ad_stb1 sba7 vddq sba0 st0 ak g_ad2 g_ad5 vss ad_stb0 rsvd vddq g_irdy# rsvd vss g_ad21 ad_stb1# vddq g_ad31 sb_stb# vss st1 aj vddq g_ad4 ad_stb0# vddq g_ad14 g_stop# vss g_ad17 g_ad20 vddq rsvd g_ad27 vss sba4 sba1 st2 ah g_ad1 vss rsvd g_ad9 vss g_trdy# g_devsel# vddq g_ad19 rsvd vss g_ad26 g_ad30 vddq sba2 rbf# ag g_ad0 rsvd vddq g_ad10 g_ad13 g_serr# g_frame# g_ad16 vss 66in g_ad23 vddq g_ad29 sba5 sba3 pipe# af g_ad3 vss g_ad7 vss g_ad12 g_par gref_0 h l1_8 rsvd vss vcc 1_8 g_ad25 g_swng sba6 gref_1 grcomp ae vss dqa_a6 vss dqa_a8 vss dqa_a7 vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 ad vss vss dqa_a4 vss dqa_a5 vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 ac vss dqa_a2 vss dqa_a0 vss dqa_a1 vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 ab vss vss vcc 1_8 vss dqa_a3 vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 aa ctm_a ctm_a# vss cha_ref1 vss vcc 1_8 vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss y cfm_a# cfm_a vss cha_ref0 vss vcc 1_8 vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss w vss vss vcc 1_8 vss rq_a7 vss vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss v vss rq_a6 vss exp_a1 vss rq_a5 vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss u rq_a4 vss exp_a0 vss rq_a3 vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 t vss rq_a2 vss rq_a1 vss dqb_a0 vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 r rq_a0 vss vcc 1_8 vss vss vcc 1_8 vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss p vss dqb_a1 vss dqb_a2 vss dqb_a4 vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss n vss vss dqb_a6 vss dqb_a8 vss vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss m vss dqb_a5 vss dqb_a3 vss dqb_a7 vss vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss l cmd_a vss sio_a vcc 1_8 vss vcc 1_8 vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 k sck_a cha_hclkout cha_rclkout vss hlref_b hlrcomp_b hlswng_b vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 j hl_b14 hl_b8 vcc1_8 hl_b15 hl_b11 vcc1_8 vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 h hlb_stb1 vss hl_b12 hl_b13 vss hl_b18 vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vcc 1_8 g vcc1_8 hlb_stb1# hl_b16 vcc1_8 hl_b19 hl_b17 vss vss vss vss vss vss vss vss vss vss f hl_b6 hl_b5 vss hl_b10 hl_b9 hlref_a hl_a10 vcc 1_8 vss dqa_b1 vss vcc 1_8 vcc1_8 vss rq_b5 vss e hlb_stb0 vcc1_8 hl_b7 hlrcomp_a vss hl_a9 hl_a8 vss dqa_b5 vss dqa_b3 vss vss rq_b7 vss rq_b3 d vss hlb_stb0# hl_b1 hl_a0 hla_stb vcc 1_8 vcc1_8 dqa_b7 vss dqa_b0 vss chb_ref1 chb_ref0 vss exp_b1 vss c hl_b4 hl_b3 vss hl_a1 vss hla_stb# hl_a11 vss dqa_b6 vss vcc 1_8 vss vss vcc 1_8 vss exp_b0 b vcc1_8 hl_b0 vcc1_8 hl_a3 hl_a5 vss dqa_b8 vss dqa_b2 vss ctm_b# cfm_b vss rq_b6 vss a hl_b2 hl_a2 hl_a4 hl_a6 hl_a7 vss dqa_b4 vss vss ctm_b cfm_b# vss vss rq_b4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
ballout and package information r intel ? 82860 mch datasheet 179 figure 11. mch ballout with agp and hub interface ball names (top view ? right side) 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 rstin# bro# htrdy# drdy# bnr# rs0# rs2# vtt ha 27# ha26# vtt ha20# ha13# vtt am g_req# reservd vtt hit# vss cpurst# rs1# ha 32# vss ha 35# ha34# vss ha 14# ha10# ha16# al testin# rsvd rsp# hitm# bpri# ap0# vss ha 31# ha33# vtt ha22# ha30# vtt ha12# ha15# vtt ak overt# rsvd berr# vss dbsy# vtt ha 21# vtt ha23# hadstb1# vss ha 25# ha11# vss hadstb0# ha9# aj buspark hla_enh# vss hlock# defer# ap1# ha 29# ha19# vss ha 24# ha28# vtt ha8# ha6# vtt ha5# ah vss vss vtt ccvref vtt ads# vtt ha 18# vss bclk1 bclk0 vcc 1_8 vss hreq0# ha7# vss ag vss vss vss hrcomp0 hswng0 vtt vss vtt havref0 ha 17# vtt hreq3# ha4# vtt hreq1# hreq2# af vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss ha3# vss hreq4# hd 59# vss hd 63# ae vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vtt havref1 hd60# vtt hd58# hd57# vtt ad vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss hd 56# hd61# vss hd 62# dbi3# ac vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vtt hd51# vtt hd55# hd53# vtt hd54# ab vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vss hd 49# hd50# vss hdstbn3# hdstbp3# vss aa vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vtt vtt hd 46# hd47# vtt hd48# hd52# y vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vss hdvref3 vss hd 44# hd45# vss hd 42# w vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vtt hd 43# hd40# vtt hd41# dbi2# vtt v vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss hd 37# hd39# vss hd 35# hd38# u vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vtt hdvref2 vtt hd32# hdstbn2# vtt hdstbp2# t vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vss hd 36# hd34# vss hd 33# dp3# vss r vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss hrcomp1 vtt dp2# dp1# vtt hd 31# dp0# p vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss hswng1 hd 30# vss hdstbn1# hdstbp1# vss hd 24# n vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss vss vss vtt hdvref1 hd 27# vtt hd25# hd28# vtt m vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vss hd 23# hd22# vss hd 26# hd29# l vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vtt hd16# vtt hd18# hd20# vtt dbi1# k vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss hdvref0 hd 17# vss hd 19# hd21# vss j vcc1_8 vss vss vss vss vcc 1_8 vcc1_8 vcc1_8 vcc1_8 vss vtt hd 15# hd14# vtt hd12# hdstbp0# h vss vss vss vss vss vcc 1_8 vss vcc 1_8 hlswng_c vcc1_8 hd13# vss hd 10# hdstbn0# vss hd 11# g dqb_b0 vcc1_8 dqb_b4 vss dqb_b7 vss hl_c11 hl_c13 hl_c9 hlrcomp_c hlref_c hl_c0 vtt hd9# hd5# vtt f vss vss vss dqb_b8 vss vss vcc 1_8 hl_c8 hl_c14 vcc1_8 hl_c2 hl_c1 hd3# vss hd6# hd2# e rq_b1 vss dqb_b2 vss dqb_b3 vcc 1_8 hl_c15 vss hlc_stb1# hl_c17 vss hlc_stb0# hd7# hd0# vtt hd8# d vss vcc 1_8 vss dqb_b6 vss sio_b chb_rclkout hlc_stb1 vcc 1_8 hl_c19 hlc_stb0 vcc1_8 hl_c3 vss hd4# vss c rq_b2 vss dqb_b1 vss dqb_b5 vss chb_hclkout hl_c12 hl_c10 vss hl_c6 hl_c7 vss vtt hd1# b vss rq_b0 vss vss vss cmd_b sck_b vcc 1_8 hl_c16 hl_c18 vcc1_8 hl_c4 hl_c5 dbi0# a 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
ballout and package information r 180 intel ? 82860 mch datasheet figure 12. mch ballout topside view (looking through the top of the package) am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 14 15 16
ballout and package information r intel ? 82860 mch datasheet 181 table 30. mch alphabetical ballout list signal ball # 66in ag23 ad_stb0 ak29 ad_stb0# aj30 ad_stb1 al21 ad_stb1# ak22 ads# ag11 ap0# ak11 ap1# ah11 bclk0 ag6 bclk1 ag7 berr# aj14 bnr# am12 bpri# ak12 bro# am15 buspark ah16 ccvref ag13 cfm_a y31 cfm_a# y32 cfm_b b20 cfm_b# a20 cha_hclkout k31 cha_rclkout k30 cha_ref0 y29 cha_ref1 aa29 chb_hclkout b10 chb_rclkout c10 chb_ref0 d20 chb_ref1 d21 cmd_a l32 cmd_b a11 cpurst# al11 ctm_a aa32 ctm_a# aa31 ctm_b a21 signal ball # ctm_b# b21 dbi0# a3 dbi1# k1 dbi2# v2 dbi3# ac1 dbsy# aj12 defer# ah12 dp0# p1 dp1# p4 dp2# p5 dp3# r2 dqa_a0 ac29 dqa_a1 ac27 dqa_a2 ac31 dqa_a3 ab28 dqa_a4 ad30 dqa_a5 ad28 dqa_a6 ae31 dqa_a7 ae27 dqa_a8 ae29 dqa_b0 d23 dqa_b1 f23 dqa_b2 b23 dqa_b3 e22 dqa_b4 a24 dqa_b5 e24 dqa_b6 c24 dqa_b7 d25 dqa_b8 b25 dqb_a0 t27 dqb_a1 p31 dqb_a2 p29 dqb_a3 m29 dqb_a4 p27 signal ball # dqb_a5 m31 dqb_a6 n30 dqb_a7 m27 dqb_a8 n28 dqb_b0 f16 dqb_b1 b14 dqb_b2 d14 dqb_b3 d12 dqb_b4 f14 dqb_b5 b12 dqb_b6 c13 dqb_b7 f12 dqb_b8 e13 drdy# am13 exp_a0 u30 exp_a1 v29 exp_b0 c17 exp_b1 d18 g_ad0 ag32 g_ad1 ah32 g_ad2 ak32 g_ad3 af32 g_ad4 aj31 g_ad5 ak31 g_ad6 al31 g_ad7 af30 g_ad8 am30 g_ad9 ah29 g_ad10 ag29 g_ad11 al29 g_ad12 af28 g_ad13 ag28 g_ad14 aj28 g_ad15 am28
ballout and package information r 182 intel ? 82860 mch datasheet signal ball # g_ad16 ag25 g_ad17 aj25 g_ad18 am25 g_ad19 ah24 g_ad20 aj24 g_ad21 ak23 g_ad22 am24 g_ad23 ag22 g_ad24 am22 g_ad25 af21 g_ad26 ah21 g_ad27 aj21 g_ad28 am21 g_ad29 ag20 g_ad30 ah20 g_ad31 ak20 g_c/be0# al30 g_c/be1# am27 g_c/be2# al26 g_c/be3# al23 g_devsel# ah26 g_frame# ag26 g_gnt# am17 g_irdy# ak26 g_par af27 g_req# al16 g_serr# ag27 g_stop# aj27 g_swng af20 g_trdy# ah27 grcomp af17 gref_0 af26 gref_1 af18 ha3# ae6 ha4# af4 signal ball # ha5# ah1 ha6# ah3 ha7# ag2 ha8# ah4 ha9# aj1 ha10# al3 ha11# aj4 ha12# ak3 ha13# am4 ha14# al4 ha15# ak2 ha16# al2 ha17# af7 ha18# ag9 ha19# ah9 ha20# am5 ha21# aj10 ha22# ak6 ha23# aj8 ha24# ah7 ha25# aj5 ha26# am7 ha27# am8 ha28# ah6 ha29# ah10 ha30# ak5 ha31# ak9 ha32# al9 ha33# ak8 ha34# al6 ha35# al7 hadstb0# aj2 hadstb1# aj7 havref0 af8 havref1 ad6 signal ball # hd0# d3 hd1# b2 hd2# e1 hd3# e4 hd4# c2 hd5# f2 hd6# e2 hd7# d4 hd8# d1 hd9# f3 hd10# g4 hd11# g1 hd12# h2 hd13# g6 hd14# h4 hd15# h5 hd16# k6 hd17# j5 hd18# k4 hd19# j3 hd20# k3 hd21# j2 hd22# l4 hd23# l5 hd24# n1 hd25# m3 hd26# l2 hd27# m5 hd28# m2 hd29# l1 hd30# n6 hd31# p2 hd32# t4 hd33# r3 hd34# r5
ballout and package information r intel ? 82860 mch datasheet 183 signal ball # hd35# u2 hd36# r6 hd37# u5 hd38# u1 hd39# u4 hd40# v5 hd41# v3 hd42# w1 hd43# v6 hd44# w4 hd45# w3 hd46# y5 hd47# y4 hd48# y2 hd49# aa6 hd50# aa5 hd51# ab6 hd52# y1 hd53# ab3 hd54# ab1 hd55# ab4 hd56# ac5 hd57# ad2 hd58# ad3 hd59# ae3 hd60# ad5 hd61# ac4 hd62# ac2 hd63# ae1 hdstbn0# g3 hdstbn1# n4 hdstbn2# t3 hdstbn3# aa3 hdstbp0# h1 hdstbp1# n3 signal ball # hdstbp2# t1 hdstbp3# aa2 hdvref0 j6 hdvref1 m6 hdvref2 t6 hdvref3 w6 hit# al13 hitm# ak13 hl_a0 d29 hl_a1 c29 hl_a2 a29 hl_a3 b28 hl_a4 a28 hl_a5 b27 hl_a6 a27 hl_a7 a26 hl_a8 e26 hl_a9 e27 hl_a10 f26 hl_a11 c26 hl_b0 b30 hl_b1 d30 hl_b2 a30 hl_b3 c31 hl_b4 c32 hl_b5 f31 hl_b6 f32 hl_b7 e30 hl_b8 j31 hl_b9 f28 hl_b10 f29 hl_b11 j28 hl_b12 h30 hl_b13 h29 hl_b14 j32 signal ball # hl_b15 j29 hl_b16 g30 hl_b17 g27 hl_b18 h27 hl_b19 g28 hl_c0 f5 hl_c1 e5 hl_c2 e6 hl_c3 c4 hl_c4 a5 hl_c5 a4 hl_c6 b6 hl_c7 b5 hl_c8 e9 hl_c9 f8 hl_c10 b8 hl_c11 f10 hl_c12 b9 hl_c13 f9 hl_c14 e8 hl_c15 d10 hl_c16 a8 hl_c17 d7 hl_c18 a7 hl_c19 c7 hl1_8 af25 hla_enh# ah15 hla_stb d28 hla_stb# c27 hlb_stb0 e32 hlb_stb0# d31 hlb_stb1 h32 hlb_stb1# g31 hlc_stb0 c6 hlc_stb0# d5
ballout and package information r 184 intel ? 82860 mch datasheet signal ball # hlc_stb1 c9 hlc_stb1# d8 hlock# ah13 hlrcomp_a e29 hlrcomp_b k27 hlrcomp_c f7 hlref_a f27 hlref_b k28 hlref_c f6 hlswng_b k26 hlswng_c g8 hrcomp0 af13 hrcomp1 p7 hreq0# ag3 hreq1# af2 hreq2# af1 hreq3# af5 hreq4# ae4 hswng0 af12 hswng1 n7 htrdy# am14 overt# aj16 pipe# ag17 rbf# ah17 rq_a0 r32 rq_a1 t29 rq_a2 t31 rq_a3 u28 rq_a4 u32 rq_a5 v27 rq_a6 v31 rq_a7 w28 rq_b0 a15 rq_b1 d16 rq_b2 b16 signal ball # rq_b3 e17 rq_b4 a17 rq_b5 f18 rq_b6 b18 rq_b7 e19 rs0# am11 rs1# al10 rs2# am10 rsp# ak14 rstin# am16 rsvd al15 rsvd ak15 rsvd aj15 rsvd ah30 rsvd ag31 rsvd al27 rsvd ak28 rsvd al24 rsvd ak25 rsvd aj22 rsvd ah23 rsvd af24 sb_stb am19 sb_stb# ak19 sba0 al18 sba1 aj18 sba2 ah18 sba3 ag18 sba4 aj19 sba5 ag19 sba6 af19 sba7 al20 sck_a k32 sck_b a10 sio_a l30 signal ball # sio_b c11 st0 al17 st1 ak17 st2 aj17 testin# ak16 vcc1_8 ab25 vcc1_8 u25 vcc1_8 t25 vcc1_8 l25 vcc1_8 k25 vcc1_8 j25 vcc1_8 h25 vcc1_8 ae24 vcc1_8 ad24 vcc1_8 ac24 vcc1_8 ab24 vcc1_8 u24 vcc1_8 t24 vcc1_8 l24 vcc1_8 k24 vcc1_8 j24 vcc1_8 h24 vcc1_8 ae23 vcc1_8 ad23 vcc1_8 ac23 vcc1_8 ab23 vcc1_8 u23 vcc1_8 t23 vcc1_8 l23 vcc1_8 k23 vcc1_8 j23 vcc1_8 h23 vcc1_8 af22 vcc1_8 ae22 vcc1_8 ad22
ballout and package information r intel ? 82860 mch datasheet 185 signal ball # vcc1_8 ac22 vcc1_8 ab22 vcc1_8 u22 vcc1_8 t22 vcc1_8 l22 vcc1_8 k22 vcc1_8 j22 vcc1_8 h22 vcc1_8 y21 vcc1_8 w21 vcc1_8 v21 vcc1_8 r21 vcc1_8 p21 vcc1_8 n21 vcc1_8 m21 vcc1_8 aa20 vcc1_8 y20 vcc1_8 t16 vcc1_8 l16 vcc1_8 w20 vcc1_8 v20 vcc1_8 r20 vcc1_8 p20 vcc1_8 n20 vcc1_8 m20 vcc1_8 aa19 vcc1_8 y19 vcc1_8 w19 vcc1_8 v19 vcc1_8 r19 vcc1_8 p19 vcc1_8 n19 vcc1_8 m19 vcc1_8 aa18 vcc1_8 y18 signal ball # vcc1_8 w18 vcc1_8 v18 vcc1_8 r18 vcc1_8 p18 vcc1_8 n18 vcc1_8 m18 vcc1_8 ae17 vcc1_8 ad17 vcc1_8 ac17 vcc1_8 ab17 vcc1_8 u17 vcc1_8 t17 vcc1_8 l17 vcc1_8 k17 vcc1_8 j17 vcc1_8 h17 vcc1_8 ae16 vcc1_8 ad16 vcc1_8 ac16 vcc1_8 ab16 vcc1_8 u16 vcc1_8 k16 vcc1_8 j16 vcc1_8 h16 vcc1_8 aa15 vcc1_8 y15 vcc1_8 w15 vcc1_8 v15 vcc1_8 r15 vcc1_8 p15 vcc1_8 n15 vcc1_8 ae10 vcc1_8 ad10 vcc1_8 m15 vcc1_8 f15 signal ball # vcc1_8 c15 vcc1_8 aa14 vcc1_8 y14 vcc1_8 w14 vcc1_8 v14 vcc1_8 r14 vcc1_8 p14 vcc1_8 n14 vcc1_8 m14 vcc1_8 aa13 vcc1_8 y13 vcc1_8 w13 vcc1_8 v13 vcc1_8 r13 vcc1_8 p13 vcc1_8 n13 vcc1_8 m13 vcc1_8 aa12 vcc1_8 y12 vcc1_8 w12 vcc1_8 v12 vcc1_8 r12 vcc1_8 p12 vcc1_8 n12 vcc1_8 m12 vcc1_8 ae11 vcc1_8 ad11 vcc1_8 ac11 vcc1_8 ab11 vcc1_8 u11 vcc1_8 t11 vcc1_8 l11 vcc1_8 k11 vcc1_8 j11 vcc1_8 h11
ballout and package information r 186 intel ? 82860 mch datasheet signal ball # vcc1_8 g11 vcc1_8 d11 vcc1_8 ac10 vcc1_8 ab10 vcc1_8 u10 vcc1_8 t10 vcc1_8 l10 vcc1_8 k10 vcc1_8 j10 vcc1_8 h10 vcc1_8 e10 vcc1_8 ae9 vcc1_8 g32 vcc1_8 e31 vcc1_8 b31 vcc1_8 j30 vcc1_8 l29 vcc1_8 g29 vcc1_8 b29 vcc1_8 l27 vcc1_8 j27 vcc1_8 d27 vcc1_8 h26 vcc1_8 d26 vcc1_8 ae25 vcc1_8 ad25 vcc1_8 ac25 vcc1_8 ad9 vcc1_8 ac9 vcc1_8 ab9 vcc1_8 u9 vcc1_8 t9 vcc1_8 l9 vcc1_8 k9 vcc1_8 j9 signal ball # vcc1_8 h9 vcc1_8 g9 vcc1_8 a9 vcc1_8 ae8 vcc1_8 ad8 vcc1_8 ac8 vcc1_8 ab8 vcc1_8 u8 vcc1_8 t8 vcc1_8 l8 vcc1_8 k8 vcc1_8 j8 vcc1_8 h8 vcc1_8 c8 vcc1_8 ag5 vcc1_8 g7 vcc1_8 e7 vcc1_8 a6 vcc1_8 c5 vcc1_8 aa21 vcc1_8rac f25 vcc1_8rac f21 vcc1_8rac f20 vcc1_8rac c19 vcc1_8rac ab30 vcc1_8rac w30 vcc1_8rac r30 vcc1_8rac aa27 vcc1_8rac y27 vcc1_8rac r27 vcc1_8rac c22 vddq ag21 vddq al19 vddq aj32 vddq ag30 signal ball # vddq am29 vddq aj29 vddq ak27 vddq al25 vddq ah25 vddq am23 vddq aj23 vddq ak21 vddq ah19 vss m32 vss d32 vss ah31 vss af31 vss ad31 vss ab31 vss w31 vss u31 vss r31 vss n31 vss l31 vss h31 vss ak30 vss ae30 vss ac30 vss aa30 vss y30 vss v30 vss t30 vss p30 vss m30 vss f30 vss c30 vss af29 vss ad29 vss ab29
ballout and package information r intel ? 82860 mch datasheet 187 signal ball # vss w29 vss u29 vss r29 vss n29 vss k29 vss al28 vss ah28 vss ae28 vss ac28 vss aa28 vss y28 vss v28 vss t28 vss r28 vss p28 vss m28 vss l28 vss h28 vss e28 vss c28 vss ad27 vss ab27 vss w27 vss u27 vss n27 vss m16 vss g16 vss e16 vss c16 vss a16 vss ag15 vss af15 vss ae15 vss ad15 vss ac15 signal ball # vss ab15 vss u15 vss t15 vss l15 vss k15 vss j15 vss h15 vss g15 vss e15 vss d15 vss b15 vss ah14 vss af14 vss ae14 vss ad14 vss ac14 vss ab14 vss u14 vss t14 vss l14 vss k14 vss j14 vss h14 vss g14 vss e14 vss c14 vss a14 vss aj13 vss ae13 vss ad13 vss ac13 vss ab13 vss u13 vss t13 vss l13 signal ball # vss k13 vss j13 vss h13 vss g13 vss f13 vss d13 vss am26 vss aj26 vss ae26 vss ad26 vss ac26 vss ab26 vss aa26 vss y26 vss w26 vss v26 vss u26 vss t26 vss r26 vss p26 vss n26 vss m26 vss l26 vss j26 vss g26 vss b26 vss aa25 vss y25 vss w25 vss v25 vss r25 vss p25 vss n25 vss m25 vss g25
ballout and package information r 188 intel ? 82860 mch datasheet signal ball # vss e25 vss c25 vss a25 vss ak24 vss ag24 vss aa24 vss y24 vss w24 vss v24 vss r24 vss p24 vss n24 vss m24 vss g24 vss f24 vss d24 vss b24 vss af23 vss aa23 vss y23 vss w23 vss v23 vss b13 vss a13 vss al12 vss ae12 vss ad12 vss ac12 vss ab12 vss u12 vss t12 vss l12 vss k12 vss j12 vss h12 signal ball # vss g12 vss e12 vss c12 vss a12 vss aa11 vss y11 vss w11 vss v11 vss r11 vss p11 vss n11 vss m11 vss f11 vss e11 vss b11 vss ak10 vss af10 vss aa10 vss y10 vss w10 vss v10 vss r10 vss p10 vss n10 vss m10 vss g10 vss aa9 vss y9 vss w9 vss v9 vss r9 vss p9 vss n9 vss m9 vss d9 signal ball # vss al8 vss ah8 vss ag8 vss r23 vss p23 vss n23 vss m23 vss g23 vss e23 vss c23 vss a23 vss al22 vss ah22 vss aa22 vss y22 vss w22 vss v22 vss r22 vss p22 vss n22 vss m22 vss g22 vss f22 vss d22 vss b22 vss a22 vss ae21 vss ad21 vss ac21 vss ab21 vss u21 vss t21 vss l21 vss k21 vss j21
ballout and package information r intel ? 82860 mch datasheet 189 signal ball # vss h21 vss g21 vss e21 vss c21 vss am20 vss aj20 vss ae20 vss ad20 vss ac20 vss ab20 vss u20 vss t20 vss l20 vss k20 vss j20 vss h20 vss g20 vss e20 vss c20 vss aa8 vss y8 vss w8 vss v8 vss r8 vss p8 vss n8 vss m8 vss ae7 vss ac7 vss aa7 vss w7 vss u7 vss r7 vss l7 vss j7 signal ball # vss h7 vss b7 vss aj6 vss ac6 vss u6 vss l6 vss d6 vss al5 vss ae5 vss w5 vss n5 vss g5 vss ag4 vss aa4 vss r4 vss j4 vss b4 vss u3 vss l3 vss e3 vss c3 vss ae2 vss n2 vss g2 vss ag1 vss aa1 vss r1 vss j1 vss c1 vss w2 vss ae32 vss ad32 vss ac32 vss ab32 vss w32 signal ball # vss v32 vss t32 vss p32 vss n32 vss aj3 vss ac3 vss ae19 vss ad19 vss ac19 vss ab19 vss u19 vss t19 vss l19 vss k19 vss j19 vss h19 vss g19 vss f19 vss d19 vss b19 vss a19 vss ak18 vss ae18 vss ad18 vss ac18 vss ab18 vss u18 vss t18 vss l18 vss k18 vss j18 vss h18 vss g18 vss e18 vss c18
ballout and package information r 190 intel ? 82860 mch datasheet signal ball # vss a18 vss aa17 vss y17 vss w17 vss v17 vss r17 vss p17 vss n17 vss m17 vss g17 vss f17 vss d17 vss b17 vss ag16 vss af16 vss aa16 vss y16 vss w16 vss v16 vss r16 vss p16 vss n16 vtt h6 vtt k5 signal ball # vtt al14 vtt ag14 vtt ag12 vtt aj11 vtt af11 vtt ag10 vtt am9 vtt aj9 vtt af9 vtt ak7 vtt ad7 vtt ab7 vtt y7 vtt v7 vtt t7 vtt m7 vtt am6 vtt af6 vtt y6 vtt p6 vtt ah5 vtt k7 vtt ab5 vtt t5 signal ball # vtt ak4 vtt ad4 vtt v4 vtt m4 vtt f4 vtt am3 vtt af3 vtt y3 vtt p3 vtt h3 vtt b3 vtt ah2 vtt ab2 vtt t2 vtt k2 vtt d2 vtt ak1 vtt ad1 vtt v1 vtt m1 vtt f1 wbf# am18
ballout and package information r intel ? 82860 mch datasheet 191 7.2 intel ? 82860 mch package information figure 13 shows the package dimensions for the mch. figure 13. mch package dimensions back (land) view notes: 1. substrate thicknes and package overall height are thicker than standard 492-l pbga 2. dimension is measured at the maximum solder ball diameter, parallel to primary dataum -c- 3. primary dataum -c- and seating plane are determined by the spherical crowns of the solder balls 4. all dimensions are in millimeters, unless otherwise specified 5. all dimensions and tolerances conform to ansi y14.5m; 1982 b 0.200 a pkg_olga_1012 10 16 20 3579 11 13 15 17 19 46 18 81214 22 21 24 23 d e g h k l p r u v y n w m aa ab ac ad ae af j f a 26 25 28 27 30 29 31 ah ag aj ak al am 0.90 0.60 b 0.30 c s s a s 2x 42.500 0.100 1 2 1.270 2x 1.465 min. 19.685 39.370 b c 1.270 t 0.635 21.250 1.940 0.150 0.60 0.10 1.10 0.10 seating plane die 0.20 -c- side view (note 2) (note 3) 32
ballout and package information r 192 intel ? 82860 mch datasheet 7.3 chipset interface trace length compensation in this section, detailed information about the internal component package trace length is provided to enable trace length compensation. trace length compensation is very important to maximize design flexibility. these lengths must be considered when matching trace lengths as described in the intel ? 860 chipset platform design guide . note that these lengths are normalized to 0 with the longest trace on the package. they do not represent the actual lengths from pad to ball. the data given can be renormalized to start routing from a different ball. if a different signal (other than longest trace) is used for nominalization, use the following equation: new ? l pkg ? = ? l pkg - ? l ref ? ? l ref is the reference signal used for nominalization table 31 shows an example where signal memory1 trace length is used for nominalization. table 31. example nominalization table ? ? ? ? l pkg (mils) new ? ? ? ? l pkg (mils) memory1 102.756 0.000 memory2 118.897 16.141 memory3 130.315 27.559 memory4 152.364 49.608 memoryn 175.984 73.228
ballout and package information r intel ? 82860 mch datasheet 193 7.3.1 mch rsl trace length compensation depending on the memory configuration, different trace length compensation equations are used to determine the ? l pcb for rsl signals. the following equations are for a rimm only solution and intel mrh-r for the expansion channel. to calculate the ? l pcb for rsl signals from the mch to rimms, use the following formula. ? l pcb = ( ? l pkg_mch *v pkg_mch ) / v pcb ? ? lpcb is the nominal ? pcb trace length to be added on the pcb ? ? lpkg_mch is the nominal ? package trace length of the mch ? vpkg_mch is the package trace velocity of the mch, and its the nominal value is 167.64 ps/in (6.6 ps/mm) ? vpcb is the pcb trace velocity to calculate the ? l pcb for rsl signals from the mch to intel mrh-r, first normalize the rsl signals to one signal. then, use the following formula to calculate ? l pcb . ? l pcb = ( ? l pkg_mch *v pkg_mch + ? l pkg_mrh-r *v pkg_mrh-r ) / v pcb ? ? lpcb is the nominal ? pcb trace length to be added on the pcb ? ? lpkg_mch is the nominal ? package trace length of the ? vpkg_mch is the package trace velocity of the mch, and its the nominal value is 167.64 ps/in (6.6 ps/mm) ? ? lpkg_mrh_r is the nominal ? package trace length of the intel mrh-r ? vpkg_mrh-r is the package trace velocity, and its the nominal value is 180 ps/in (7.09 ps/mm) ? vpcb is the pcb trace velocity
ballout and package information r 194 intel ? 82860 mch datasheet 7.3.1.1 mch rsl normalized trace length data the mch package trace length information for rambus channel a and rambus channel b is listed in table 32. table 32. mch ? ? ? ? l pkg data for rambus* channel a and rambus channel b channel a ? ? ? ? l pkg normalized to dqa_a7 channel b ? ? ? ? l pkg normalized to dqa_b4 signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) cfm_a y31 76.535 cfm_b b20 104.291 cfm_a# y32 5.394 cfm_b# a20 32.874 ctm_a aa32 13.307 ctm_b a21 41.024 ctm_a# aa31 69.567 ctm_b# b21 98.031 dqa_a0 ac29 118.189 dqa_b0 d23 146.654 dqa_a1 ac27 135.512 dqa_b1 f23 156.417 dqa_a2 ac31 12.874 dqa_b2 b23 41.417 dqa_a3 ab28 162.244 dqa_b3 e22 213.898 dqa_a4 ad30 31.496 dqa_b4 a24 0.000 dqa_a5 ad28 158.346 dqa_b5 e24 195.157 dqa_a6 ae31 6.575 dqa_b6 c24 105.236 dqa_a7 ae27 0.000 dqa_b7 d25 90.906 dqa_a8 ae29 46.732 dqa_b8 b25 21.890 dqb_a0 t27 316.102 dqb_b0 f16 331.417 dqb_a1 p31 69.331 dqb_b1 b14 105.197 dqb_a2 p29 208.386 dqb_b2 d14 212.677 dqb_a3 m29 129.882 dqb_b3 d12 137.677 dqb_a4 p27 330.276 dqb_b4 f14 337.047 dqb_a5 m31 20.866 dqb_b5 b12 60.276 dqb_a6 n30 154.331 dqb_b6 c13 155.669 dqb_a7 m27 243.346 dqb_b7 f12 258.661 dqb_a8 n28 218.780 dqb_b8 e13 228.268 exp_a0 u30 157.638 exp_b0 c17 186.102 exp_a1 v29 208.780 exp_b1 d18 237.283 rq_a0 r32 51.890 rq_b0 a15 79.409 rq_a1 t29 196.811 rq_b1 d16 231.024 rq_a2 t31 105.039 rq_b2 b16 139.016 rq_a3 u28 249.213 rq_b3 e17 281.693 rq_a4 u32 58.937 rq_b4 a17 82.362 rq_a5 v27 295.433 rq_b5 f18 324.055 rq_a6 v31 89.370 rq_b6 b18 120.394 rq_a7 w28 230.079 rq_b7 e19 258.504
ballout and package information r intel ? 82860 mch datasheet 195 7.3.2 mch system bus signal normalized trace length data to calculate the ? l pcb for the system bus, first normal the processor and mch to the same signal within a group. then follow the trace length equations documented in the intel ? xeon? processor and intel ? 860 chipset platform design guide . the mch system bus interface normalized data per group is provided in the following tables. table 33. mch system bus signal normalized trace length data per group hadstb0# group normalized to ha9# hadstb1# group normalized to ha32# hdstbx3# group normalized to hd62# signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) hadstb0# aj2 38.031 hadstb1# aj7 263.031 hdstbp3# aa2 269.764 ap0# ak11 254.803 ap1# ah11 402.874 hdstbn3# aa3 353.228 ha3# ae6 364.252 ha17# af7 395.157 hd48# y2 309.921 ha4# af4 223.583 ha18# ag9 437.283 hd49# aa6 408.071 ha5# ah1 38.780 ha19# ah9 306.693 hd50# aa5 436.654 ha6# ah3 115.827 ha20# am5 71.693 hd51# ab6 518.031 ha7# ag2 136.220 ha21# aj10 349.961 hd52# y1 228.228 ha8# ah4 191.417 ha22# ak6 200.039 hd53# ab3 122.441 ha9# aj1 0.000 ha23# aj8 324.567 hd54# ab1 194.646 ha10# al3 36.772 ha24# ah7 349.252 hd55# ab4 388.228 ha11# aj4 138.189 ha25# aj5 235.276 hd56# ac5 439.370 ha12# ak3 94.331 ha26# am7 40.906 hd57# ad2 190.669 ha13# am4 19.606 ha27# am8 100.709 hd58# ad3 235.079 ha14# al4 50.551 ha28# ah6 303.543 hd59# ae3 224.843 ha15# ak2 42.717 ha29# ah10 380.984 hd60# ad5 332.953 ha16# al2 1.850 ha30# ak5 149.016 hd61# ac4 359.882 hreq0# ag3 123.307 ha31# ak9 265.157 hd62# ac2 0.000 hreq1# af2 139.055 ha32# al9 0.000 hd63# ae1 160.157 hreq2# af1 72.087 ha33# ak8 249.094 dbi3# ac1 104.724 hreq3# af5 291.260 ha34# al6 103.189 hreq4# ae4 273.701 ha35# al7 163.701
ballout and package information r 196 intel ? 82860 mch datasheet table 34. mch system bus signal normalized trace length data per group (continued) hdstbx2# group normalized to hd42# hdstbx1# group normalized to hdstbn1# hdstbx0# group normalized to hd2# signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) hdstbp2# t1 15.354 hdstbp1# n3 26.024 hdstbp0# h1 10.236 hdstbn2# t3 151.181 hdstbn1# n4 0.000 hdstbn0# g3 244.055 hd32# t4 215.630 hd16# k6 596.378 hd0# d3 169.803 hd33# r3 151.142 hd17# j5 476.575 hd1# b2 66.496 hd34# r5 246.417 hd18# k4 499.843 hd2# e1 0.000 hd35# u2 81.181 hd19# j3 406.575 hd3# e4 228.346 hd36# r6 281.850 hd20# k3 425.669 hd4# c2 96.181 hd37# u5 242.205 hd21# j2 388.701 hd5# f2 179.370 hd38# u1 14.291 hd22# l4 515.276 hd6# e2 132.126 hd39# u4 227.283 hd23# l5 540.906 hd7# d4 200.512 hd40# v5 261.772 hd24# n1 367.953 hd8# d1 86.850 hd41# v3 115.709 hd25# m3 475.591 hd9# f3 224.449 hd42# w1 0.000 hd26# l2 390.157 hd10# g4 278.701 hd43# v6 292.559 hd27# m5 580.748 hd11# g1 90.315 hd44# w4 196.339 hd28# m2 378.543 hd12# h2 173.543 hd45# w3 128.937 hd29# l1 325.433 hd13# g6 394.843 hd46# y5 203.701 hd30# n6 621.339 hd14# h4 324.843 hd47# y4 139.449 hd31# p2 453.110 hd15# h5 358.622 dbi2# v2 79.213 dbi1# k1 351.260 dbi0# a3 31.024
ballout and package information r intel ? 82860 mch datasheet 197 7.3.3 mch 16-bit hub interface normalized trace length to calculate the ? l pcb for 16-bit hub interfaces to the intel p64h, use the following formula. ? l pcb = ( ? l pkg_mch *v pkg_mch ) / v pcb ? ? lpcb is the nominal ? pcb trace length to be added on the pcb ? ? lpkg_mch is the nominal ? package trace length of the mch ? vpkg_mch is the package trace velocity of the mch, and its the nominal value is 167.64 ps/in (6.6 ps/mm) ? vpcb is the pcb trace velocity ? reference the intel ? xeon? processor and intel ? 860 chipset platform design guide for information regarding how and when to use this data contained in the following sections for the 16-bit hub interface_b?c. 7.3.3.1 mch 16-bit hub interface_b normalized trace length data below is the mch package trace length information for the 16-bit hub interface_b. table 35. mch 16-bit hub interface_b signal normalized trace length data hub interface_b normalized to hl_b6 signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) hl_b0 b30 264.094 hl_b2 a30 229.567 hl_b1 d30 326.457 hl_b3 c31 270.433 hl_b10 f29 283.543 hl_b4 c32 199.685 hl_b11 j28 559.882 hl_b5 f31 190.157 hl_b12 h30 424.528 hl_b6 f32 0.000 hl_b13 h29 479.567 hl_b7 e30 301.772 hl_b14 j32 347.362 hl_b8 j31 419.488 hl_b15 j29 540.709 hl_b9 f28 449.803 hl_b16 g30 428.189 hlb_stb0 e32 239.567 hl_b17 g27 588.189 hlb_stb0# d31 312.165 hl_b18 h27 486.732 hlb_stb1 h32 302.205 hl_b19 g28 509.449 hlb_stb1# g31 372.244
ballout and package information r 198 intel ? 82860 mch datasheet 7.3.3.2 mch 16-bit hub interface_c normalized trace length data below is the mch package trace length information for the 16-bit hub interface_c. table 36. mch 16-bit hub interface_c signal normalized trace length data hub interface_c normalized to hlc_stb0# signal ball no. ? ? ? ? l pkg (mils) signal ball no. ? ? ? ? l pkg (mils) hl_c0 f5 440.906 hl_c2 e6 431.575 hl_c1 e5 359.331 hl_c3 c4 167.205 hl_c10 b8 291.260 hl_c4 a5 152.795 hl_c11 f10 552.244 hl_c5 a4 138.858 hl_c12 b9 323.543 hl_c6 b6 229.331 hl_c13 f9 527.953 hl_c7 b5 154.173 hl_c14 e8 446.890 hl_c8 e9 464.567 hl_c15 d10 472.283 hl_c9 f8 519.764 hl_c16 a8 251.535 hlc_stb0 c6 246.654 hl_c17 d7 222.992 hlc_stb0# d5 0.000 hl_c18 a7 220.827 hlc_stb1 c9 385.748 hl_c19 c7 282.362 hlc_stb1# d8 426.654
testability r intel ? 82860 mch datasheet 199 8 testability in the mch, the testability for automated test equipment (ate) board level testing has been implemented as an xor chain. an xor-tree is a chain of xor gates, each with one input pin connected to it. figure 14. xor-tree chain (high level view) input xor out xor.vsd input input input input vcc1_8 the algorithm used for in-circuit test is as follows: ? drive all input pins to their initial logic level as indicated in the tables below. observe the output. ? toggle pins one at a time starting from the first pin continuing to the last pin from its initial logic level to its opposite level. observe that the output changes with each pin toggle. certain pin pairs must be toggled together. these pin pairs are: ad_stb0 and ad_stb0#, ad_stb1 and ad_stb1#, and sb_stb and sb_stb#. for example ad_stb0 has an initial state of 1 and ad_stb0# has an initial state of 0 when reaching ad_stb0, both ad_stb0 and ad_stb0# should be toggled together (ad_stb0: 1 -> 0 and ad_stb0#: 0 -> 1). when these pins are toggled together, the output will not change. it is important to use the initial input states found in the following tables. the following pins must be connected to their proper circuit in order for the xor chain to work: ? hlref_a ? hlref_b ? hlref_c ? hlswng_b ? hlswng_c ? hl1_8 ? all inputs must be driven to cmos voltage levels (0-1.8 v) regardless of signal type.
testability r 200 intel ? 82860 mch datasheet 8.1 xor test mode initialization the mch uses a single pin (testin#) to activate the xor test mode. ? 32,771 clocks (66in) after the deassertion of pci reset (rstin#), drive testin# from 1 to 0. ? start to serially load the bits: 8010 0000 1000 0000 0000 3f0c 003c 0001h into the testin# pin. ? once in the xor test mode, any high-to-low transition on testin# will cause the serial test mode entry state machine to be activated. care should be taken to keep testin# stable after activating the xor test mode. 8.2 xor chains table 37. xor chain 1 chain 1 ball element # note initial logic level ha13# am4 1 input 1 ha14# al4 2 input 1 ha10# al3 3 input 1 ha11# aj4 4 input 1 ha12# ak3 5 input 1 ha16# al2 6 input 1 ha8# ah4 7 input 1 ha3# ae6 8 input 1 ha15# ak2 9 input 1 hreq3# af5 10 input 1 hadstb0# aj2 11 input 1 ha4# af4 12 input 1 ha9# aj1 13 input 1 ha6# ah3 14 input 1 hreq4# ae4 15 input 1 hreq0# ag3 16 input 1 ha7# ag2 17 input 1 ha5# ah1 18 input 1 hreq1# af2 19 input 1 hreq2# af1 20 input 1 hd56# ac5 21 input 1 hd59# ae3 22 input 1
testability r intel ? 82860 mch datasheet 201 chain 1 ball element # note initial logic level hd60# ad5 23 input 1 hd61# ac4 24 input 1 hd51# ab6 25 input 1 hd49# aa6 26 input 1 hd63# ae1 27 input 1 hd57# ad2 28 input 1 hd55# ab4 29 input 1 hd58# ad3 30 input 1 hdstbn3# aa3 31 input 1 hdstbp3# aa2 32 input 1 hd53# ab3 33 input 1 dbi3# ac1 34 input 1 hd50# aa5 35 input 1 hd54# ab1 36 input 1 hd62# ac2 37 input 1 hd48# y2 38 input 1 hd52# y1 39 input 1 hd46# y5 40 input 1 hd47# y4 41 input 1 hd44# w4 42 input 1 hd45# w3 43 input 1 hd43# v6 44 input 1 hd42# w1 45 input 1 hd40# v5 46 input 1 dbi_2# v2 47 input 1 hd37# u5 48 input 1 hd41# v3 49 input 1 hd39# u4 50 input 1 hd35# u2 51 input 1 hd38# u1 52 input 1 hdstbn2# t3 53 input 1 hdstbp2# t1 54 input 1 sba0 al18 55 output n/a
testability r 202 intel ? 82860 mch datasheet table 38. xor chain 2 chain 2 ball element # note initial logic level hd32# t4 1 input 1 hd33# r3 2 input 1 hd34# r5 3 input 1 hd36# r6 4 input 1 hd31# p2 5 input 1 hd24# n1 6 input 1 hrcomp1 p7 7 input 1 hd28# m2 8 input 1 hd29# l1 9 input 1 hd25# m3 10 input 1 hd26# l2 11 input 1 dbi1# k1 12 input 1 hd30# n6 13 input 1 hd27# m5 14 input 1 hdstbn1# n4 15 input 1 hdstbp1# n3 16 input 1 hd22# l4 17 input 1 hd20# k3 18 input 1 hd21# j2 19 input 1 hd23# l5 20 input 1 hd18# k4 21 input 1 hd19# j3 22 input 1 hd16# k6 23 input 1 hd17# j5 24 input 1 hd2# e1 25 input 1 hd11# g1 26 input 1 hd14# h4 27 input 1 hd12# h2 28 input 1 hd5# f2 29 input 1 hd15# h5 30 input 1 hd10# g4 31 input 1 hdstbn0# g3 32 input 1 hdstbp0# h1 33 input 1 hd9# f3 34 input 1
testability r intel ? 82860 mch datasheet 203 chain 2 ball element # note initial logic level hd6# e2 35 input 1 hd8# d1 36 input 1 hd4# c2 37 input 1 hd0# d3 38 input 1 hd3# e4 39 input 1 hd1# b2 40 input 1 hd13# g6 41 input 1 hd7# d4 42 input 1 dbi0# a3 43 input 1 cmd_b a11 44 input 1 sio_b c11 45 input 1 sck_b a10 46 input 1 chb_hclkout b10 47 input 1 chb_rclkout c10 48 input 1 hl_a7 a26 49 input 1 hl_a8 e26 50 input 1 hl_a5 b27 51 input 1 hl_a6 a27 52 input 1 hl_a4 a28 53 input 1 hl_a3 b28 54 input 1 sba1 aj18 55 output n/a
testability r 204 intel ? 82860 mch datasheet table 39. xor chain 3 chain 3 ball element # note initial logic level dp3# r2 1 input 1 dp0# p1 2 input 1 dp2# p5 3 input 1 dp1# p4 4 input 1 hl_c0 f5 5 input 1 hl_c17 d7 6 input 1 hl_c1 e5 7 input 1 hl_c2 e6 8 input 1 hl_c3 c4 9 input 1 hl_c7 b5 10 input 1 hlc_stb0# d5 11 input 1 hlc_stb0 c6 12 input 1 hlrcomp_c f7 13 input 1 hl_c5 a4 14 input 1 hl_c4 a5 15 input 1 hl_c6 b6 16 input 1 hl_c19 c7 17 input 1 hl_c9 f8 18 input 1 hl_c13 f9 19 input 1 hl_c14 e8 20 input 1 hl_c8 e9 21 input 1 hlc_stb1# d8 22 input 1 hlc_stb1 c9 23 input 1 hl_c18 a7 24 input 1 hl_c11 f10 25 input 1 hl_c16 a8 26 input 1 hl_c15 d10 27 input 1 hl_c10 b8 28 input 1 hl_c12 b9 29 input 1 hl_a11 c26 30 input 1 hl_b2 a30 31 input 1 hl_b0 b30 32 input 1 hl_b1 d30 33 input 1
testability r intel ? 82860 mch datasheet 205 chain 3 ball element # note initial logic level hl_b6 f32 34 input 1 hl_b3 c31 35 input 1 hl_b17 g27 36 input 1 hl_b4 c32 37 input 1 hlb_stb0# d31 38 input 1 hlb_stb0 e32 39 input 1 sba2 ah18 40 output n/a table 40. xor chain 4 chain 4 ball element # note initial logic level hl_a2 a29 1 input 1 hla_stb# c27 2 input 1 hla_stb d28 3 input 0 hlrcomp_a e29 4 input 1 hl_a9 e27 5 input 1 hl_a0 d29 6 input 1 hl_a1 c29 7 input 1 hl_a10 f26 8 input 1 cmd_a l32 9 input 1 sio_a l30 10 input 1 sck_a k32 11 input 1 cha_rclkout k30 12 input 1 cha_hclkout k31 13 input 1 g_ad1 ah32 14 input 1 g_ad5 ak31 15 input 1 g_ad0 ag32 16 input 1 g_ad3 af32 17 input 1 g_ad10 ag29 18 input 1 g_ad9 ah29 19 input 1 g_ad14 aj28 20 input 1 g_ad2 ak32 21 input 1 g_ad15 am28 22 input 1 ad_stb0 ak29 23 input 1 ad_stb0# aj30 24 input 0 g_ad4 aj31 25 input 1
testability r 206 intel ? 82860 mch datasheet chain 4 ball element # note initial logic level g_c/be0# al30 26 input 1 g_ad11 al29 27 input 1 g_ad7 af30 28 input 1 g_ad6 al31 29 input 1 g_ad8 am30 30 input 1 g_ad12 af28 31 input 1 g_c/be1# am27 32 input 1 g_ad13 ag28 33 input 1 g_devsel# ah26 34 input 1 g_frame# ag26 35 input 1 g_irdy# ak26 36 input 1 g_trdy# ah27 37 input 1 g_stop# aj27 38 input 1 g_par af27 39 input 1 g_c/be2# al26 40 input 1 g_ad20 aj24 41 input 1 g_ad16 ag25 42 input 1 g_ad21 ak23 43 input 1 g_ad17 aj25 44 input 1 g_ad18 am25 45 input 1 g_ad19 ah24 46 input 1 g_ad23 ag22 47 input 1 g_ad22 am24 48 input 1 ad_stb1 al21 49 input 1 ad_stb1# ak22 50 input 0 grcomp af17 51 input 1 g_c/be3# al23 52 input 1 g_ad24 am22 53 input 1 g_ad25 af21 54 input 1 sba3 ag18 55 output n/a
testability r intel ? 82860 mch datasheet 207 table 41. xor chain 5 chain 5 ball element # note initial logic level g_ad27 aj21 1 input 1 g_ad26 ah21 2 input 1 g_ad30 ah20 3 input 1 g_ad29 ag20 4 input 1 g_ad28 am21 5 input 1 g_ad31 ak20 6 input 1 sb_stb am19 7 input 1 sb_stb# ak19 8 input 0 st0 al17 9 input 1 st1 ak17 10 input 1 st2 aj17 11 input 1 rbf# ah17 12 input 1 g_gnt# am17 13 input 1 pipe# ag17 14 input 1 wbf# am18 15 input 1 g_req# al16 16 input 1 hla_enh# ah15 17 input 1 bro# am15 18 input 1 htrdy# am14 19 input 1 drdy# am13 20 input 1 hit# al13 21 input 1 hitm# ak13 22 input 1 bnr# am12 23 input 1 hlock# ah13 24 input 1 bpri# ak12 25 input 1 rs0# am11 26 input 1 cpurst# al11 27 input 1 dbsy# aj12 28 input 1 rs2# am10 29 input 1 hrcomp0 af13 30 input 1 rs1# al10 31 input 1 defer# ah12 32 input 1 ads# ag11 33 input 1 ha21# aj10 34 input 1
testability r 208 intel ? 82860 mch datasheet chain 5 ball element # note initial logic level ha31# ak9 35 input 1 ha29# ah10 36 input 1 ha19# ah9 37 input 1 ha27# am8 38 input 1 ha26# am7 39 input 1 ha23# aj8 40 input 1 hadstb1# aj7 41 input 1 ha20# am5 42 input 1 ha18# ag9 43 input 1 ha22# ak6 44 input 1 ha30# ak5 45 input 1 ha24# ah7 46 input 1 ha25# aj5 47 input 1 ha28# ah6 48 input 1 ha17# af7 49 input 1 sba4 aj19 50 output n/a table 42. xor chain 6 chain 6 ball element # note initial logic level hlrcomp_b k27 1 input 1 hl_b19 g28 2 input 1 hl_b18 h27 3 input 1 hl_b5 f31 4 input 1 hl_b7 e30 5 input 1 hl_b9 f28 6 input 1 hl_b16 g30 7 input 1 hl_b10 f29 8 input 1 hl_b11 j28 9 input 1 hlb_stb1# g31 10 input 1 hlb_stb1 h32 11 input 1 hl_b13 h29 12 input 1 hl_b12 h30 13 input 1 hl_b15 j29 14 input 1 hl_b8 j31 15 input 1 hl_b14 j32 16 input 1
testability r intel ? 82860 mch datasheet 209 chain 6 ball element # note initial logic level rsvd ag31 17 input 1 rsvd ah30 18 input 1 rsvd af24 19 input 1 rsvd ak28 20 input 1 rsvd al27 21 input 1 g_serr# ag27 22 input 1 rsvd ak25 23 input 1 rsvd al24 24 input 1 rsvd ah23 25 input 1 rsvd aj22 26 input 1 overt# aj16 27 input 1 buspark ah16 28 input 1 rsvd al15 29 input 1 rsvd ak15 30 input 1 rsvd aj15 31 input 1 rsp# ak14 32 input 1 berr# aj14 33 input 1 ap0# ak11 34 input 1 ap1# ah11 35 input 1 ha33# ak8 36 input 1 ha35# al7 37 input 1 ha32# al9 38 input 1 ha34# al6 39 input 1 sba5 ag19 40 output n/a
testability r 210 intel ? 82860 mch datasheet table 43. xor chain 7 chain 7 ball element # note initial logic level dqa_a5 ad28 1 input 1 dqa_a3 ab28 2 input 1 dqa_a7 ae27 3 input 1 dqa_a6 ae31 4 input 1 dqa_a8 ae29 5 input 1 dqa_a0 ac29 6 input 1 dqa_a4 ad30 7 input 1 dqa_a1 ac27 8 input 1 dqa_a2 ac31 9 input 1 ctm_a aa32 10 input 1 ctm_a# aa31 11 input 1 rq_a7 w28 12 input 1 exp_a1 v29 13 input 1 rq_a6 v31 14 input 1 rq_a5 v27 15 input 1 rq_a4 u32 16 input 1 exp_a0 u30 17 input 1 rq_a3 u28 18 input 1 rq_a0 r32 19 input 1 rq_a2 t31 20 input 1 rq_a1 t29 21 input 1 dqa_b5 e24 22 input 1 dqa_b1 f23 23 input 1 dqa_b0 d23 24 input 1 dqa_b6 c24 25 input 1 dqa_b2 b23 26 input 1 dqa_b3 e22 27 input 1 dqa_b4 a24 28 input 1 dqa_b8 b25 29 input 1 dqa_b7 d25 30 input 1 sba6 af19 31 output n/a
testability r intel ? 82860 mch datasheet 211 table 44. xor chain 8 chain 8 ball element # note initial logic level dqb_a5 m31 1 input 1 dqb_a3 m29 2 input 1 dqb_a7 m27 3 input 1 dqb_a6 n30 4 input 1 dqb_a8 n28 5 input 1 dqb_a0 t27 6 input 1 dqb_a4 p27 7 input 1 dqb_a1 p31 8 input 1 dqb_a2 p29 9 input 1 ctm_b a21 10 input 1 ctm_b# b21 11 input 1 rq_b7 e19 12 input 1 exp_b1 d18 13 input 1 rq_b6 b18 14 input 1 rq_b5 f18 15 input 1 rq_b4 a17 16 input 1 exp_b0 c17 17 input 1 rq_b3 e17 18 input 1 rq_b0 a15 19 input 1 rq_b2 b16 20 input 1 rq_b1 b14 21 input 1 dqb_b5 b12 22 input 1 dqb_b1 b14 23 input 1 dqb_b0 f16 24 input 1 dqb_b6 c13 25 input 1 dqb_b2 d14 26 input 1 dqb_b3 d12 27 input 1 dqb_b4 f14 28 input 1 dqb_b8 e13 29 input 1 dqb_b7 f12 30 input 1 sba7 al20 31 output n/a rstin#, testin#, cfm_a, cfm_a#, cha_ref[0:1], cfm_b, cfm_b#, chb_ref[0:1] are not part of any xor chain. this is in addition to sba[0:7].

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