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53 features compatible with: british telecom (bt) sin227 & sin242 u.k.s cable communications association (cca) speci?ation tw/p&e/312 bellcore gr-30-core (formerly known as tr-nwt-000030) & sr-tsv-002476 bellcore ?pe alerting signal (cas) and bt ?dle state tone alert signal detection ring and line reversal detection 1200 baud bell 202 and ccitt v.23 frequency shift keying (fsk) demodulation 3 or 5v 10% supply voltage high input sensitivity (-40dbv tone and fsk detection) selectable 3-wire fsk data interface (microcontroller or MT88E43B initiated) low power cmos with powerdown mode input gain adjustable ampli?r carrier detect status output uses 3.58 mhz crystal applications bt calling line identity presentation (clip), cca clip, and bellcore calling identity delivery (cid) systems feature phones, including analog display services interface (adsi) phones phone set adjunct boxes fax and answering machines database query and computer telephony integration (cti) systems description the MT88E43B calling number identi?ation circuit 2 is a low power cmos integrated circuit intended for receiving physical layer signals transmitted according to bt (british telecom) sin227 & sin242, the u.k.s cca (cable communications association) tw/p&e/312 and bellcore gr-30-core & sr-tsv-002476 speci?ations. the MT88E43B is suitable for applications using a ?ed voltage power source between 3 and 5v 10%. the MT88E43B contains a fsk demodulator and a cas/tone alert signal detector. the 1200 baud fsk demodulator is compatible with both bell 202 and ccitt v.23 formats. to facilitate fsk data extraction, a dual mode 3-wire serial data interface is provided. in one mode data transfer is initiated by the device. in the second mode, the microcontroller initiates the 8-bit data word extraction from the device. the MT88E43B also offers line reversal detection capability for bts clip, ring burst detection for the u.k.s ccas clip, and ring detection for bellcores cid. figure 1- functional block diagram + - anti-alias filter fsk bandpass filter fsk demodulator data timing recovery carrier detector alert signal high tone filter alert signal low tone filter tone detection algorithm bias generator oscillator guard time std st/gt est trigout trigrc trigin data dr dclk mode fsken cd cap oscin oscout in+ in- gs vref int pwdn vdd vss to internal to internal cct. cct. interrupt generator ds5157 issue 1 april 1999 ordering information MT88E43Be 24 pin plastic dip (0.6 inch package only) MT88E43Bs 24 pin soic -40 c to +85 c MT88E43B extended voltage calling number identi?ation circuit 2 cmos preliminary information
MT88E43B preliminary information 54 figure 2 - pin connections pin description pin # name description 1 in+ non-inverting input of the internal opamp. 2 in- inverting input of the internal opamp. 3gs gain select (output) of internal opamp. the opamps gain should be set according to the nominal vdd of the application using the information in figure 10. 4v ref reference voltage (output) . nominally v dd /2 . it is used to bias the input opamp. 5 cap capacitor . a 0.1 f decoupling capacitor should be connected across this pin and v ss . 6 trigin trigger input . schmitt trigger buffer input. used for line reversal and ring detection. 7 trigrc trigger rc (open drain output/schmitt input) . used to set the (rc) time interval from trigin going low to trigout going high. an external resistor connected to v dd and capacitor connected to v ss determine the duration of the (rc) time interval. 8 trigout trigger out (cmos output). schmitt trigger buffer output. used to indicate detection of line reversal and/or ringing. 9 mode 3-wire interface: mode select (cmos input) . when low, selects fsk data interface mode 0. when high, selects fsk data interface mode 1. see pin 16 (dclk) description to understand how mode affects the dclk pin. 10 oscin oscillator input . a 3.579545mhz crystal should be connected between this pin and oscout. it may also be driven directly from an external clock source. 11 oscout oscillator output . a 3.579545mhz crystal should be connected between this pin and oscin. when oscin is driven by an external clock, this pin should be left open. 12 v ss power supply ground . 13 ic internal connection . must be connected to v ss for normal operation. 14 pwdn power down (schmitt input) . active high. when high, the device consumes minimal power by disabling all functionality except trigin, trigrc and trigout . must be pulled low for device operation. 15 fsken fsk enable (cmos input) . must be high for fsk demodulation. this pin should be set low to prevent the fsk demodulator from reacting to extraneous signals (such as speech, alert signal and dtmf which are all in the same frequency band as fsk). 16 dclk 3-wire interface: data clock (cmos input/output) . in mode 0 (mode pin low), this pin is an output. in mode 1 (mode pin high), this pin is an input. 1 7 data 3-wire interface: data (cmos output) . in mode 0 the fsk data appears at the pin once demodulated. in mode 1 the fsk data is shifted out on the rising edge of the microcontroller supplied dclk. vdd st/gt est std int dr data dclk fsken pwdn ic cd in+ in- gs vref cap trigin trigrc trigout oscin oscout vss mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17
preliminary information MT88E43B 55 18 dr 3-wire interface: data ready (cmos output) . active low. in mode 0 this output goes low after the last dclk pulse of each data word. this identi?s the 8-bit word boundary on the serial output stream. typically, dr is used to latch 8-bit words from a serial-to-parallel converter into a microcontroller. in mode 1 this pin will signal the availability of data. 19 cd carrier detect (cmos output) . active low. a logic low indicates the presence of in-band signal at the output of the fsk bandpass ?ter. 20 int interrupt (open drain output) . active low. it is active when trigout or dr is low, or std is high. this output stays low until all three signals have become inactive. 21 std dual tone alert signal delayed steering output (cmos output) . when high, it indicates that a guard time quali?d alert signal has been detected. 22 est dual tone alert signal early steering output (cmos output) . alert signal detection output. used in conjunction with st/gt and external circuitry to implement the detect and non-detect guard times. 23 st/gt dual tone alert signal steering input/guard time (analog input/cmos output) . a voltage greater than v tgt (see ?ure 4) at the st/gt pin causes the device to indicate that a dual tone has been detected by asserting std high. a voltage less than v tgt frees the device to accept a new dual tone. 24 v dd positive power supply . pin description pin # name description functional overview the MT88E43B is compatible with the caller id speci?ations of bt, the u.k.s cca and bellcore. as shown in figure 1, the MT88E43B provides an fsk demodulator and a cas/bt tone alert signal detector. a 3-wire fsk data interface provides two modes of operation - a mode whereby data transfer is initiated by the device and a mode whereby data transfer is initiated by an external microcontroller. the MT88E43B also provides line reversal detection and ring detection. bt speci?ations sin227 and sin242 describe the signalling mechanism between the network and the terminal equipment (te) for the caller display service (cds). cds provides calling line identity presentation (clip), which delivers to an on hook (idle state) te the identity of an incoming caller before the ?st ring. an incoming cds call is indicated by a polarity reversal on the a and b wires (see figure 3), followed by an idle state tone alert signal. caller id information is then transmitted in ccitt v.23 format fsk. the MT88E43B can detect the line reversal, tone alert signal, and demodulate the incoming fsk signal. the u.k.s cca speci?ation tw/p&e/312 proposes an alternate cds te interface. according to tw/ p&e/312, data is transmitted after a single burst of ringing rather than before the ?st ringing cycle (as speci?d in the bt standards). the idle state tone alert signal is not required as it is replaced by a single ring burst. the MT88E43B has the capability to detect the ring burst. it can also demodulate the bell 202 or ccitt v.23 fsk following the ring burst. the u.k.s cca speci?s that data can be transmitted in either format. bellcore speci?ation gr-30-core is the generic requirement for transmitting asynchronous voiceband data to customer premises equipment (cpe). another bellcore speci?ation sr-tsv-002476 describes the same requirements from the cpes perspective. the data transmission technique speci?d in both documents is applicable in a variety of services like calling number delivery (cnd), calling name delivery (cnam) and calling identity delivery on call waiting (cidcw) - services promoted by bellcore. in cnd/cnam service, information about a calling party is embedded in the silent interval between the ?st and second ring burst. the MT88E43B detects the ?st ring burst and can then be setup to receive and demodulate the incoming bell 202 fsk data. the device will output the demodulated data onto a 3-wire serial interface.
MT88E43B preliminary information 56 in cidcw service, information about an incoming caller is sent to the subscriber, while he/she is already engaged in another call. a cpe alerting signal (cas) indicates the arrival of cidcw information. the MT88E43B can detect the cas and then be setup to demodulate the incoming fsk containing the cidcw information. functional description detection of clip/cid call arrival indicators the circuit in figure 3 illustrates the relationship between the trigin, trigrc and trigout signals. typically, the three pin combination is used to detect an event indicated by an increase of the trigin voltage from v ss to above the schmitt trigger high going threshold v t+ (see dc electrical characteristics). figure 3 shows a circuit to detect any one of three clip/cid call arrival indicators: line reversal, ring burst and ringing. line re v ersal detection line reversal, or polarity reversal on the a and b wires indicates the arrival of an incoming cds call, as speci?d in sin227. when the event (line reversal) occurs, trigin rises past the high going schmitt threshold v t+ and trigout , which is normally high, is pulled low. when the event is over, trigin falls back to below the low going schmitt threshold v t- and trigout returns high. the components r5 and c3 (see figure 3) at trigrc ensure a minimum trigout low interval. in a te designed for clip, the trigout high to low transition may be used to interrupt or wake-up the microcontroller. the controller can thus be put into power-down mode to conserve power in a battery operated te. ring burst detection cca does not support the dual tone alert signal (refer to dual tone alert signal detection section). instead, cca requires that the te be able to detect a single burst of ringing (duration 200-450ms) that precedes clip fsk data. the ring burst may vary from 30 to 75vrms and is approximately 25hz. again in a te designed for cca clip, the trigout high to low transition may be used to interrupt or wake-up the microcontroller. the controller can thus be put into power-down mode to conserve power in a battery operated te. ring detection in bellcores cnd/cnam scheme, the cid fsk data is transmitted between the ?st and second ringing cycles. the circuit in figure 3 will generate a ring envelope signal (active low) at trigout for a ring voltage of at least 40vrms. r5 and c3 ?ter the ring signal to provide an envelope output. the diode bridge shown in figure 3 works for both single ended and balanced ringing. a fraction of the figure 3 - circuit to detect line reversal, ring burst and ringing tip/a c1=100nf r1=499k ring/b c2=100nf r2=499k MT88E43B trigout to microcontroller r3=200k r4=301k r5=150k c3=220nf trigrc trigin v dd v1 v2 v3 v4 max v t+ = 0.68 v dd min v t+ = 0.48 v dd the application circuit must ensure that, v trigin >max v t+ where max v t+ =3.74v @v dd =5.5v. tolerance to noise between a/b and v ss is: max v noise = (min v t+ )/0.30+0.7 = 5.6vrms @4.5v v dd where min v t+ = 2.16v @v dd =4.5v. suggested r 5 c 3 component values: r5 from 10k ? to 500k ? c3 from 47nf to 0.68 f an example is c3=220nf, r5=150k ? ; trigout low from 21.6ms to 37.6ms after the trigin signal stops triggering the circuit. notes: to determine values for c3 and r5: r5c3 = -t / ln(1-v trigrc /v dd )
preliminary information MT88E43B 57 ring voltage is applied to the trigin input. when the voltage at trigin is above the schmitt trigger high going threshold v t+ , trigrc is pulled low as c3 discharges. trigout stays low as long as the c3 voltage stays below the minimum v t+ . in a cpe designed for cnd/cnam, the trigout high to low transition may be used to interrupt or wake up the microcontroller. the controller can thus be put into power down mode to conserve power. if precise ring duration determination is critical, capacitor c3 in figure 3 may be removed. the microcontroller will now be able to time the ring duration directly. the result will be that trigout will be low only as long as the ringing signal is present. previously the rc time constant would cause only one interrupt. dual tone alert signal detection the bt on hook (idle state) caller id scheme uses a dual tone alert signal whose characteristics are shown in table 1. table 1 also shows the bellcore speci?ations for a similar dual tone signal called cpe alerting signal (cas) for use in off-hook data transmission. for the cidcw service, the cas must be detected in the presence of near end speech. the cas detector must also be immune to imitation from near and far end speech. in the MT88E43B the dual tone signal is separated into a high and a low tone by two bandpass ?ters. a detection algorithm examines the two ?ter outputs to determine the presence of a dual tone alert signal. the est pin goes high when both tones are present. note that est is only a preliminary indication. the indication must be sustained over the tone present guard time to be considered valid. tone present and tone absent guard times can be implemented with external rc components. the tone present guard time rejects signals of insuf?ient duration. the tone absent guard time masks momentary detection dropout once the tone present guard time has been satis?d. std is the guard time quali?d detector output. dual tone detection guard time when the dual tone signal is detected by the MT88E43B, est goes high. when the signal ceases to be detected, est goes low. the est pin indicates raw detection of the dual tone signal. since the bt application requires a minimum signal duration and the bellcore application requires protection from imitation by speech, est detection must be guard time quali?d. the std pin provides guard time quali?d signal detection. when the MT88E43B is used in a caller identity system, std indicates correct cas/tone alert signal detection. figure 4 shows the relationship between the st/gt, est and std pins. it also shows the operation of the guard time circuit. the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to timing between est, st/ gt and std in figures 17 and 20). item bt bellcore low tone frequency 2130hz 1.1% 2130hz 0.5% high tone frequency 2750hz 1.1% 2750hz 0.5% received signal level -2 to -40dbv per tone on-hook (0.22 to -37.78dbm) -14 to -32dbm a per tone off-hook a. the signal power is expressed in dbm referenced to 600 ohm at the cpe a/b (tip/ring) interface. signal reject level -46dbv (-43.78dbm) -45dbm signal level differential (twist) up to 7db up to 6db unwanted signals <= -20db (300-3400hz) <= -7dbm asl b near end speech b. asl = active speech level expressed in dbm referenced to 600 ohm at the cpe tip/ring interface. the level is measured according to method b of recommendation p.56 "objective measurement of active speech level" published in the ccitt blue book, volume v "telephone transmission quality" 1989. epl (equivalent peak level) = asl+11.7db duration 88ms to 110ms c c. sin227 suggests that the recognition time should be not less than 20ms if both tones are detected. 75ms to 85ms speech present no yes table 1 - dual tone alert signal characteristics
MT88E43B preliminary information 58 the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to timing between est, st/ gt and std in figures 17 and 20). bellcore states that it is desirable to be able to turn off cas detection for an off-hook capable cpe. the disable switch allows the subscriber who disconnects a service that relies on cas detection (e.g., cidcw) but retains the cpe, to turn off the detector and not be bothered by false detection. when sw1 in figure 4 is in the b position the guard time circuit is disabled. the detector will still process cas/alerting tones but the MT88E43B will not signal their presence by ensuring that std is low. bt speci?s that the idle state tone alert signal recognition time should not be less than 20ms when both tones are used for detection. that is, both tones must be detected together for at least 20ms before the signal can be declared valid. this requirement can be met by setting the t gp (refer to figure 5) to at least 20ms. bt also speci?s that the te is required to apply a dc wetting pulse and an ac load 15-25ms after the end of the alerting signal. if t abs =t da +t ga is 15 to 25ms, the dc current wetting pulse and the ac load can both be applied at the falling edge of std. the maximum t da is 8ms so t ga should be 15-17ms. therefore, t gp must be greater than t ga . figure 5(a) shows a possible implementation. the values in figures 9 and 11 (r2=r3=422k, c=0.1 f) will meet the bt timing requirements. figure 4 - guard time circuit operation figure 5 - guard time circuits with unequal times input con?uration the MT88E43B provides an input arrangement comprised of an operational ampli?r, and a bias source (v ref ) which is used to bias the opamp inputs at v dd /2 . the feedback resistor at the opamp output (gs) can be used to adjust the gain. in a single-ended con?uration, the opamp is connected as shown in figure 6. for a differential input con?uration, figure 7 shows the necessary connections. figure 6 - single-ended input con?uration + - v tgt est st/gt v dd std = v ss both tones detected from c r q1 q2 MT88E43B comparator p n v ss sw1 b a detector (b) t gp < t ga t gp = r p c ln [(v dd -v d (r p /r2))/(v dd -v tgt -v d (r p /r2))] t ga = r1c ln (v dd /v tgt ) r p = r1r2/(r1+r2) (a) t gp > t ga t gp = r1c ln [v dd /(v dd -v tgt )] t ga = r p c ln [(v dd -v d (r p /r2))/(v tgt -v d (r p /r2))] r p = r1r2/(r1+r2) MT88E43B v dd st/gt est r1 r2 c v dd st/gt est r1 r2 c MT88E43B v d =diode forward voltage v d =diode forward voltage c r in in+ in- gs v ref voltage gain (a v ) = r f / r in r f
preliminary information MT88E43B 59 figure 7 - differential input con?uration fsk demodulation the MT88E43B ?st bandpass ?ters and then demodulates the fsk signal. the carrier detector provides an indication of the presence of signal at the bandpass ?ter output. the MT88E43Bs dual mode 3-wire interface allows convenient extraction of the 8-bit data words in the demodulated fsk bit stream. note that signals such as cas/tone alert signal, speech and dtmf tones lie in the same frequency band as fsk. they will, therefore, be demodulated and as a result, false data will be generated. to avoid demodulation of false data, an fsken pin is provided so that the fsk demodulator may be disabled when fsk signal is not expected. there are two events that if either is true, should be used to disable fsken. the events are the carrier detector output cd returning high or receiving all the data indicated by the message length word. table 2 shows the bt and bellcore fsk signal characteristics. the bt frequencies correspond to ccitt v.23 format. the bellcore frequencies correspond to bell 202. the u.k.s cca requires that the te be able to receive both ccitt v.23 and bell 202 formats. the MT88E43B is compatible with both formats without any adjustment. 3-wire fsk data interface the MT88E43B provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated fsk bit stream can be extracted without the need either for an external uart or for the te/cpes microcontroller to perform the uart function in software. the interface is speci?ally designed for the 1200 baud rate and is comprised of the data, dclk (data clock) and dr (data ready) pins. two modes (modes 0 and 1) are selectable via control of the devices mode pin: in mode 0, data transfer is initiated by the MT88E43B; in mode 1, data transfer is initiated by the external microcontroller. mode 0 this mode is selected when the mode pin is low. in this mode, data transfer is initiated by the device. the MT88E43B receives the fsk signal, demodulates it, and outputs the data directly to the data pin (refer to figure 14). for each received stop and start bit sequence, the MT88E43B outputs a c1 r1 c2 r4 r3 r2 r5 in+ in- gs v ref differential input amplifier c1 = c2 r1 = r4 (for unity gain r5= r4) r3 = (r2r5) / (r2 + r5) voltage gain (a v diff) = r5/r1 (see figure 9,10,11) input impedance (z in diff) = 2 r1 2 + (1/ c) 2 item bt bellcore mark frequency (logic 1) 1300hz 1.5% 1200hz 1% space frequency (logic 0) 2100hz 1.5% 2200hz 1% received signal level -8 to -40dbv (-5.78 to -37.78dbm) -12 to -36dbm a a. the signal power is expressed in dbm referenced to 600 ohm at the cpe tip/ring (a/b) interface. signal level differential (twist) up to 6db up to 10db b b. sr-3004, issue 2, january 1995. unwanted signals <= -20db (300-3400hz) <= -25db (0-4khz) c c. the frequency range is speci?d in gr-30-core. transmission rate 1200 baud ?1% 1200 baud ?1% word format 1 start bit (logic 0), 8 bit word (lsb ?st), 1 to 10 stop bits (logic 1) 1 start bit (logic 0), 8 bit word (lsb ?st), 1 stop bit (logic 1) d d. up to 20 marks may be inserted in speci? places in a single or multiple data message. table 2 - fsk characteristics
MT88E43B preliminary information 60 ?ed frequency clock string of 8 pulses at the dclk pin. each clock rising edge occurs in the centre of each data bit cell. dclk is not generated for the stop and start bits. consequently, dclk will clock only valid data into a peripheral device such as a serial to parallel shift register or a micro-controller. the MT88E43B also outputs an end of word pulse (data ready) on the dr pin. the data ready signal indicates the reception of every 10-bit word (including start and stop bits) sent from the network to the te/cpe. this dr signal can be used to interrupt a micro-controller. dr can also cause a serial to parallel converter to parallel load its data into a microcontroller. the mode 0 data pin can also be connected to a personal computers serial communication port after converting from cmos to rs-232 voltage levels. mode 1 this mode is selected when the mode pin is high. in this mode, the microcontroller supplies read pulses (dclk) to shift the 8-bit data words out onto the MT88E43B data pin. the MT88E43B asserts dr to denote the word boundary and indicate to the microprocessor that a new word has become available (refer to figure 16). internal to the MT88E43B, the demodulated data bits are sampled and stored. after the 8th bit, the word is parallel loaded into an 8 bit shift register and dr goes low. the shift registers contents are shifted out to the data pin on the supplied dclks rising edge in the order they were received. if dclk begins while dr is low, dr will return to high upon the first dclk. this feature allows the associated interrupt (see section on "interrupt") to be cleared by the first read pulse. otherwise dr is low for half a nominal bit time (1/2400 sec). after the last bit has been read, additional dclks are ignored. carrier detector the carrier detector provides an indication of the presence of a signal in the fsk frequency band. it detects the presence of a signal of suf?ient amplitude at the output of the fsk bandpass ?ter. the signal is quali?d by a digital algorithm before the cd output is set low to indicate carrier detection. an 8ms hysteresis is provided to allow for momentary signal drop out once cd has been activated. cd is released when there is no activity at the fsk bandpass ?ter output for 8 ms. when cd is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (refer to figure 1). in mode 0, the data pin is forced high. no dclk or dr signal is generated. in mode 1, the internal shift register is not updated. no dr is generated. if the mode 1 dclk is clocked, data is unde?ed. note that signals such as cas/tone alert signal, speech and dtmf tones also lie in the fsk frequency band and the carrier detector may be activated by these signals. the signals will be demodulated and presented as data. to avoid false data detection, the fsken pin should be used to disable the fsk demodulator when no fsk signal is expected. ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector. interrupt to facilitate interfacing with microcontrollers running interrupt driven ?mware, an open drain interrupt output int is provided. int is asserted when trigout is low, std is high, or dr is low. when int is asserted, these signals should be read (into an input port of the microcontroller) to determine the cause of the interrupt (trigout , std or dr ) so that the appropriate response can be made. when system power is ?st applied, trigout will be low because capacitor c3 at trigrc (see figure 3) has no initial charge. this will result in an interrupt upon power up. also when system power is ?st applied and the pwdn pin is low, an interrupt will occur due to std. since there is no charge across the capacitor at the st/gt pin in figure 4, std will be high triggering an interrupt. the interrupts will not clear until both capacitors are charged. the microcontroller should ignore interrupt from these sources on initial power up until there is suf?ient time to charge the capacitors. it is possible to clear std and its interrupt by asserting pwdn immediately after system power up. when pwdn is high, std is low. pwdn will also force both est and the comparator output low, q2 will turn on so that the capacitor at the st/gt pin charges up quickly (refer to figure 4). power down for applications requiring reduced power consumption, the MT88E43B can be powered up only when it is required, that is, upon detection of one of three clip/cid call arrival indicators: line reversal, ring burst and ringing.
preliminary information MT88E43B 61 the MT88E43B is powered down by setting the pwdn pin to logic high. in power down mode, the oscillator, input opamp and all internal circuitry are disabled except for trigin, trigrc and trigout pins. these three pins are not affected by power down, such that, the MT88E43B can still react to call arrival indicators. the MT88E43B can be powered up by setting the pwdn pin to logic low. crystal oscillator the MT88E43B requires a 3.579545mhz crystal oscillator as the master timing source. figure 8 - common crystal connection the crystal speci?ation is as follows (e.g. cts mp036s) : frequency: 3.579545 mhz frequency tolerance: 0.1%(-40 o c+85 o c) resonance mode : parallel load capacitance: 18 pf maximum series resistance : 150 ohms maximum drive level (mw): 2 mw any number of MT88E43B devices can be connected as shown in figure 8 such that only one crystal is required. the connection between osc2 and osc1 can be dc coupled as shown, or the osc1 input on all devices can be driven from a cmos buffer (dc coupled) with the osc2 outputs left unconnected. to meet bt and bellcore requirements for proper tone detection the crystal must have a frequency tolerance of 0.1%. vref and cap inputs v ref is the output of a low impedance voltage source equal to v dd /2 and is used to bias the input opamp. a 0.1 f capacitor is required between cap and v ss to eliminate noise on v ref. osc1 osc2 osc1 osc2 osc1 osc2 3.579545 mhz MT88E43B MT88E43B MT88E43B to the next MT88E43B
MT88E43B preliminary information 62 figure 9 - application circuit in+ in- gs v ref trigin trigrc trigout mode oscin oscout v ss v dd st/gt est std int dr data dclk fsken pwdn ic MT88E43B cap cd (fsk interface mode 0 selected) vdd = to microcontroller = from microcontroller 100nf tip / a ring / b vdd vdd vdd 53k6 60k4 464k 499k, 5% 499k, 5% 200k 301k 150k 100nf 100nf 22nf 22nf 100nf 220nf c tisp4180, tpa150a12 or tpb150b12 tisp5180, vdd 100k note: resistors must have 1% tolerance and capacitors have 20% tolerance unless otherwise specified. 5% 5% 5% 5% 5% 5% 5% 1n4003 1n4003 1n4003 1n4003 vdd 20% 1n914 : crystal is 3.579545mhz, 0.1% frequency tolerance. 1n914 1n914 1n914 1n914 r 3 r 2 : for bt application c=0.1 f 5%, r 3 =422k ? 1%, r 2 =422k ? 1% : for applications where cas speech immunity is required (e.g. cidcw) r 1 r 1 : r 1 = 430k, r 4 = 34k for v dd = 5v 10% (see figure 10) : r 1 = 620k, r 4 = 63k4 for v dd = 3v 10% (see figure 10) c=0.1 f 5%, r 3 =825k ? 1%, r 2 =226k ? 1% r 4 r 4 application circuits the circuits shown in figures 9 and 11 are application circuits for the MT88E43B. as supply voltage (v dd ) is decreased, the threshold of the devices tone and fsk detectors will be reduced. therefore, to meet the bt or bellcore tone reject level requirements the gain of the input opamp should be reduced according to the graph in figure 10. for example when v dd =5v (+/- 10%), r 1 should equal 430k ? and r 4 should equal 34k ? ; and if v dd =3v (+/- 10%) r 1 should equal 620k ? and r 4 should equal 63.4k ? . resistors r 1 and r 4 are shown in figures 9 and 11. the circuit shown in figure 9 illustrates the use of the MT88E43B in a proprietary system that doesn? need to meet fcc, doc, and ul approvals. it should be noted that if glitches on the tip/ring interface are of sufficient amplitude, the circuit will falsely detect these signals as ringing or line reversal. the circuit shown in figure 11 will provide common mode rejection of signals received by the ringing circuit. this circuit should pass safety related tests specified by fcc part 68, doc cs-03, ul 1459, and csa c22.2. these safety tests will simulate high voltage faults that may occur on the line. the circuit provides isolation from these high voltage faults via r1 and the 12.1k ? resistors as well as the 22nf & 330nf capacitors. irc manufactures a resistor (part number gs3) that should be used for r1. this resistor is a 3w, 5%, 1kv power resistor. the 12k1 resistor is manufactured by irc (part number fa8425f). this resistor is a 1.5w, 5%, fuseable type resistor. the 22nf and 330nf capacitors have a 400v rating. see the application note "msan-164: applications of the mt8843 calling number identi?ation circuit 2" for information on designing the MT88E43B into cid and cidcw systems.
preliminary information MT88E43B 63 figure 10: gain ratio as a function of nominal vdd note: in the application circuits shown in figures 9 and 11, the gain ratio of MT88E43B opamp is 2 2.5 3 3.5 4 4.5 5 5.5 6 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 nominal vdd ( volts ) gain ratio 0.678 gainratio 464 k ? r 1 r 4 + ------------------ =
MT88E43B preliminary information 64 a pprovals fcc part 68, doc cs-03, ul 1459, and can/ csa-22.2 no. 225-m90 are all system (i.e. connectors, power supply, cabinet, etc.) requirements. since the MT88E43B is a component and not a system, the application circuit (figure 11) has been designed to meet the co trunk interface requirements of fcc, doc, ul, and csa; thus enabling the complete system to be approved by these standards bodies. products are designed in accordance with meeting the above requirements; however, full conformance to these standards is dependent upon the application in which the MT88E43B is being used, and therefore, approvals are the responsibility of the customer and zarlink will not have tested the product to meet the above standards. figure 11 - application circuit with improved common mode noise immunity and isolation in line interface in+ in- gs v ref trigin trigrc trigout mode oscin oscout v ss v dd st/gt est std int dr data dclk fsken pwdn ic MT88E43B cap cd (fsk interface mode 0 selected) vdd = to microcontroller = from microcontroller 100nf tip / a ring / b vdd vdd 53k6 60k4 464k 12k1 464k 200k 150k 330nf 100nf 22nf 22nf 100nf 220nf vdd 100k vdd 10nf vdd note: resistors must have 1% tolerance, capacitors have 20% tolerance unless specified otherwise. motorola 4n25 1n4003 1n4003 1n4003 1n4003 5% 5% 10% 5% 5% 5% 5% 20% 1n914 1n5231b : bridge rectifier diodes are 1n914. 10% c r 3 r 2 r 1 r 1 : r 1 = 430k, r 4 = 34k for v dd = 5v 10% (see figure 10) : r 1 = 620k, r 4 = 63k4 for v dd = 3v 10% (see figure 10) r 4 r 4 : for bt application c=0.1 f 5%, r 3 =422k ? 1%, r 2 =422k ? 1% : for applications where cas speech immunity is required (e.g. cidcw) c=0.1 f 5%, r 3 =825k ? 1%, r 2 =226k ? 1%
preliminary information MT88E43B 65 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ** under normal operating conditions voltage on any pin except supplies can be minimum v ss -1v to maximum v dd +1v for an input current limited to less than 200 a. . typical ?ures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ss unless otherwise stated. parameter symbol min max units 1 supply voltage with respect to v ss v dd -0.3 6 v 2 voltage on any pin other than supplies ** v pin v ss -0.3 v dd +0.3 v 3 current at any pin other than supplies i pin -10ma 4 storage temperature t st -65 150 o c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ max units 1 power supplies v dd 2.7 - 5.5 v 2 clock frequency f osc - 3.579545 - mhz 3 tolerance on clock frequency ? fc -0.1 - +0.1 % 4 operating temperature t op -40 - 85 o c dc electrical characteristics ? characteristics sym min typ max units test conditions 1 s u p p l y standby supply current i ddq - 0.5 15 a ali inputs are v dd / v ss except for oscillator pins. no analog input. outputs unloaded. pwdn=v dd 2 operating supply current v dd = 5v 10% v dd = 3v 10% i dd - - 3.0 2.1 8 4.5 ma ma all inputs are v dd / v ss except for oscillator pins. no analog input. outputs unloaded. pwdn=v ss fsken=v dd 3 power consumption po - - 44 mw 4 trigin trigrc pwdn schmitt input high threshold v t+ 0.48*v dd - 0.68*v dd v schmitt input low threshold v t- 0.28*v dd - 0.48*v dd v 5 schmitt hysteresis v hys 0.2 - - v 6 dclk mode fsken cmos input high voltage v ih 0.7*v dd -v dd v cmos input low voltage v il v ss - 0.3*v dd v
MT88E43B preliminary information 66 ? dc electrical characteristics are over recommended operating conditions unless otherwise stated. typical ?ures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. 7 trigout dclk data dr , cd std, est st/gt output high sourcing current i oh 0.8 - - ma v oh =0.9*v dd 8 trigout dclk data dr , cd std, est st/gt trigrc int output low sinking current i ol 2--mav ol =0.1*v dd 9 in+, in- trigin input current iin1 - - 1 av in =v dd to v ss pwdn dclk mode fsken iin2 - - 10 av in =v dd to v ss 10 trigrc output high-impedance current ioz1 - - 1 av out =v dd to v ss 11 int ioz2 - - 10 a 12 st/gt ioz3 - - 5 ? 13 v ref output voltage v ref 0.5v dd - 0.05 - 0.5v dd + 0.05 v no load 14 output resistance r ref --2k ? 15 st/gt comparator threshold voltage v tgt 0.5v dd - 0.05 - 0.5v dd + 0.05 v dc electrical characteristics ? (continued) characteristics sym min typ max units test conditions
preliminary information MT88E43B 67 ac electrical characteristics - timing parameter measurement voltage levels ac electrical characteristics ? - dual tone alert signal detection characteristic sym min typ max unit notes* 1 low tone frequency f l - 2130 - hz 2 high tone frequency f h - 2750 - hz 3 frequency deviation accept 1.1% - - range within which tones are accepted 4 frequency deviation reject 3.5% - - ranges outside of which tones are rejected 5 accept signal level per tone -40 -37.78 --2 0.22 dbv a dbm b a. dbv = decibels above or below a reference voltage of 1vrms. signal level is per tone. b. dbm = decibels above or below a reference power of 1mw into 600 ohms. 0dbm = 0.7746vrms. signal level is per tone. 3 6 reject signal level per tone (vdd = 5v 10% only) - - -46 -43.78 dbv dbm 7 reject signal level per tone (vdd = 3 to 5v 10%) - - -47.22 -45 dbv dbm 3 8 positive and negative twist c accept c. twist = 20 log (f h amplitude / f l amplitude). *notes: 1. both tones have the same amplitude. 2. band limited random noise 300-3400hz. measurement valid only when tone is present. 3. tip/ring signal level. input opamp con?ured to 0db gain at v dd =5v+/-10%, -3.38db gain at v dd =3v+/-10%. (see figure 10) ac electrical characteristics are over recommended operating conditions, unless otherwise stated. typical ?ures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. 7--db 9 signal to noise ratio snr tone 20 - - db 1, 2 characteristics sym level units notes 1 cmos threshold voltage v ct 0.5*v dd v 2 rise/fall threshold voltage high v hm 0.7*v dd v 3 rise/fall threshold voltage low v lm 0.3*v dd v
MT88E43B preliminary information 68 ? electrical characteristics are over recommended operating conditions, unless otherwise stated. *notes 1. both mark and space have the same amplitude. 2. band limited random noise (200-3400hz). present when fsk signal is present. note that the bt band is 300-3400hz, the bellcore band is 0-4khz. 3. tip/ring signal level. input opamp con?ured to 0db gain at v dd =5v+/-10%, -3.38db gain at v dd =3v+/-10%. (see figure 10) ? ac electrical characteristics are over recommended operating conditions, unless otherwise stated. typical ?ures are nominal values and are for design aid only: not guaranteed and not subject to production testing. *notes 1. refer to figures 17 and 20 electrical characteristics ? - gain setting ampli?r characteristics sym min max units test conditions 1 input leakage current i in -1 av ss v in v dd 2 input resistance r in 10 - m ? 3 input offset voltage v os -25mv 4 power supply rejection ratio psrr 40 - db 1khz ripple on v dd 5 common mode rejection cmrr 40 - db v cmmin v in v cmmax 6 dc open loop voltage gain a vol 30 - db 7 unity gain bandwidth f c 0.3 - mhz 8 output voltage swing v o 0.5 v dd -0.7 v load 100k ? 9 capacitive load (gs) c l -50pf 10 resistive load (gs) r l 100 - k ? 11 common mode range voltage v cm 1.0 v dd -1.0 v ac electrical characteristics ? - fsk demodulation characteristics sym min typ max units notes* 1 input level -40 -37.78 10.0 --8 -5.78 398.1 dbv a dbm b mvrms a. dbv = decibels above or below a reference voltage of 1vrms. b. dbm = decibels above or below a reference power of 1mw into 600 ohms. 0dbm = 0.7746vrms. 1, 3 2 transmission rate 1188 1200 1212 baud 3 input frequency bell 202 mark (1) bell 202 space (0) ccitt v.23 mark (1) ccitt v.23 space (0) 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 hz hz hz hz 4 signal to noise ratio snr fsk 20 - - db 1, 2 ac electrical characteristics ? - dual tone alert signal timing characteristics sym min max units notes* 1 alert signal present detect time t dp 0.5 10 ms 1 2 alert signal absent detect time t da 0.1 8 ms 1
preliminary information MT88E43B 69 ? ac electrical characteristics are over recommended operating conditions unless otherwise stated. ? ac electrical characteristics are over recommended operating conditions unless otherwise stated. typical ?ures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. *notes: 1. fsk input data at 1200 12 baud. 2. osc1 at 3.579545 mhz 0.1%. 3. function of signal condition. ? ac electrical characteristics are over recommended operating conditions unless otherwise stated. ac electrical characteristics ? - carrier detect and power down timing characteristics sym min max units notes 1 pwdn osc1 power-up time t pu -50ms 2 power-down time t pd -1ms 3 cd input fsk to cd low delay t cp -25ms 4 input fsk to cd high delay t ca 8-ms 5 hysteresis 8 - ms ac electrical characteristics ? - 3-wire interface timing (mode 0) characteristics sym min typ max units notes* 1 dr rise time t rr - - 200 ns into 50pf load 2 fall time t rf - - 200 ns into 50pf load 3 low time t rl 415 416 417 s2 4 data rate 1188 1200 1212 baud 1 5 input fsk to data delay t idd -15ms 6 data dclk rise time t r - - 200 ns into 50pf load 7 fall time t f - - 200 ns into 50pf load 8 data to dclk delay t dcd 6 416 - s 1, 2, 3 9 dclk to data delay t cdd 6 416 - s 1, 2, 3 10 dclk frequency f dclk0 1201.6 1202.8 1204 hz 2 11 high time t ch 415 416 417 s2 12 low time t cl 415 416 417 s2 13 dclk dr dclk to dr delay t crd 415 416 417 s2 ac electrical characteristics ? - 3-wire interface timing (mode 1) characteristics sym min max units notes 1 dclk frequency f dclk1 - 1 mhz 2 duty cycle 30 70 % 3 rise time t r1 -20ns 4 dclk dr dclk low set up to dr t dds 500 - ns 5 dclk low hold time after dr t ddh 500 - ns
MT88E43B preliminary information 70 figure 12 - data and dclk mode 0 output timing figure 13 - dr output timing figure 14 - serial data interface timing (mode 0) data dclk t r t dcd t cdd t r t f t cl t ch t f v hm v lm v ct v hm v lm v ct t rf t rr t rl d r v hm v lm v ct (a/b) data dclk dr stop start stop start stop start stop start b0 b1 b2 b3 b4 b5 b6 b7 b7 10 b0 b1 b2 b3 b4 b5 b6 b7 10 b0 b1 b2 10 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 stop start stop start t idd t crd 1/f dclk0 t rl tip/ring wires
preliminary information MT88E43B 71 figure 15 - dclk mode 1 input timing figure 16 - serial data interface timing (mode 1) dclk t r1 v hm v lm stop start stop 0 1 234 5 67 7 word n word n+1 0 1 2 3 4 5 67 word n 0 word n-1 7 1/f dclk1 t rl t ddh 6 t dds demodulated dr dclk data internal bit stream ? ? ? dclk clears dr ? dclk does not clear dr , so dr is low for maximum time (1/2 bit width)
MT88E43B preliminary information 72 figure 17 - input and output timing for bt caller display service (cds), e.g., clip notes: 1) the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to section ?ual tone detection guard time on page 57 for details). v tgt is the comparator threshold (refer to figure 4). 2) the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to section ?ual tone detection guard time on page 57 for details). v tgt is the comparator threshold (refer to figure 4). 3) by choosing t ga =15ms, t abs will be 15-25ms so that the current wetting pulse and ac load can be applied right after the std falling edge. 4) sin227 speci?s that the ac and dc loads should be removed between 50-150ms after the end of the fsk signal, indicated by cd returning to high. the MT88E43B may also be powered down at this time. 5) fsken should be set low when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such a s speech, tone alert signal and dtmf tones. 6) trigout is the ring envelope during ringing. line reversal alerting signal ch. seizure mark data packet ring ..101010.. data t dp t da t gp t ga t rec t abs note 3 t cp t ca ab c d e f g zss (refer to sin227) < 0.5ma (optional) <120 a note 4 v tgt note 6 note 5 a/b wires trigout pwdn est st/gt std te dc load te ac load fsken cd dr dclk data oscout a 100ms b = 88-110ms c 45ms (up to 5sec) d = 80-262ms e = 45-75ms f 2.5sec (typ. 500ms) g > 200ms note: all values obtained from sin227 issue 1 note 1 note 2 50-150ms current wetting pulse (see sin227) t pu t pd 15 1ms 20 5ms
preliminary information MT88E43B 73 figure 18 - input and output timing for cca caller display service (cds), e.g., clip notes: 1) tw/p&e/312 speci?s that the ac and dc loads should be removed between 50 to 150ms after the end of the fsk signal, indicated by cd returning to high. the MT88E43B may also be powered down at this time. 2) fsken should be set low when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such a s speech, and dtmf tones. 3) trigout represents the ring envelope during ringing. line reversal ring burst ch. seizure mark data packet first ring cycle ..101010.. data 250-400ms t cp t ca a bc d e f note 1 note 2 a/b wires trigout pwdn te dc load te ac load fsken cd dr dclk data oscout 50-150ms note 3 a = 200-450ms b 500ms c = 80-262ms d = 45-262ms e 2.5s (typ. 500ms) f >200ms note: parameter f from "cca exceptions document issue 3" note 3 t pu t pd
MT88E43B preliminary information 74 figure 19 - input and output timing for bellcore on-hook data transmission associated with ringing, e.g., cid notes: this on-hook case application is included because a cidcw (off-hook) cpe must be also capable of receiving on-hook data transmission (with ringing) from the end of?e. tr-nwt-000575 speci?s that cidcw will be offered only to lines which subscribe to cid. 1) the cpe designer may choose to enable the MT88E43B only after the end of ringing to conserve power in a battery operated cpe. cd is not activated by ringing. 2) the cpe designer may choose to set fsken always high while the cpe is on-hook. setting fsken low prevents the fsk demodulator from reacting to other in-band signals such as speech, cas or dtmf tones. 3) the microcontroller in the cpe powers down the MT88E43B after cd has become inactive. 4) the microcontroller times out if cd is not activated. 1st ring 2nd ring ch. seizure mark data packet a cdef .101010.. data note 1 note 2 note 3 note 1 note 4 t ca t cp b tip/ring trigout pwdn oscout fsken cd dr dclk data a = 2sec typical b = 250-500ms c = 250ms d = 150ms e = feature specific max c+d+e = 2.9 to 3.7sec f 200ms t pd t pu
preliminary information MT88E43B 75 figure 20 - input and output timing for bellcore off-hook data transmission, e.g., cidcw notes : 1) in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes off-hook and use battery power while on-hook. the cpe must be also cid (on-hook) capable because tr-nwt-000575 speci?s that cidcw will be offered only to lines which subscribe to cid. 2) non-fsk signals such as cas, speech and dtmf tones are in the same frequency band as fsk. they will be demodulated and give false data. the fsken pin should be set low to disable the fsk demodulator when fsk is not expected. 3) fsken may be set high as soon as the cpe has ?ished sending the acknowledgment signal ack. tr-nwt-000575 speci?s that ack = dtmf d for non-adsi cpe, a for adsi cpe. 4) fsken should be set low when cd has become inactive. 5) in an unsuccessful attempt where the end of?e does not send the fsk signal, the cpe should unmute the handset and enable the keypad after this interval. 6) sr-tsv-002476 states that it is desirable that the cpe have an on/off switch for the cas detector. see sw1 in figure 4. 7) the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time (refer to section ?ual tone detection guard time on page 57 for details). v tgt is the comparator threshold (refer to figure 4). 8) the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time (refer to section ?ual tone detection guard time on page 57 for details). v tgt is the comparator threshold (refer to figure 4). cpe goes off-hook cas ack cpe sends cpe mutes handset & disables keypad mark data cpe unmutes handset and enables keypad t dp t da t gp t ga t rec t abs t cp t ca data v tgt ac e f g bd note 1 note 2 note 3 note 4 note 5 tip/ring pwdn fsken oscout est st/gt std (note 6) cd dr dclk data packet a = 75-85ms b = 0-100ms c = 55-65ms d = 0-500ms e = 58-75ms f = feature specific g 50ms note 7 note 8 t pu

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