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mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 1 description m2v64s20btp is organized as 4-bank x4,194,304-word x 4-bit,and m2v64s30btp is organized as 4-bank x 2097152-word x 8-bit , and m2v64S40Btp is organized as 4-bank x 1048576-word x 16-bit synchronous dram with lvttl interface. all inputs and outputs are referenced to the rising edge of clk. m2v64s20btp,m2v64s30btp,m2v64S40Btp achieves very high speed data rates up to 133mhz, and is suitable for main memory or graphic memory in computer systems. features - single 3.3v 0.3v power supply - max. clock frequency -6 : 133mhz [pc133<3-3-3> ] - fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by ba0,ba1(bank address) - /cas latency- 2/3 (programmable) - burst length- 1/2/4/8/fp (programmable) - burst type- sequential and interleave burst (programmable) - random column access - auto precharge / all bank precharge controlled by a10 - auto and self refresh - 4096 refresh cycles /64ms - lvttl interface - package 400-mil, 54-pin thin small outline (tsop ii) with 0.8mm lead pitch preliminary some of contents are described for general products and are subject to change without notice. item tclk m2v64s20tp tras trcd tac trc icc1 icc6 clock cycle time (min.) active to precharge command period (min.) row to column delay (min.) access time from clk (max.) (cl=3) ref/active command period (min.) operation current (max.) [single bank] self refresh current (max.) -6 7.5 ns 45 ns 20.0ns 5.4 ns 67.5ns 1 ma 120ma m2v64s30tp m2v64s40tp
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 2 clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dq0-3(x4), dq0-7(x8), dq0-15(x16) : data i/o dqm (x4, x8) ,dqml/u (x16) : output disable/ write mask a0-11 : address input ba0,1 : bank address vdd : power supply vddq : power supply for output vss : ground vssq : ground for output pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 vdd dq0 vddq dq2 vssq dq4 vddq dq6 vssq vdd dqml /we /cas /ras /cs ba0(a13) ba1(a12) a10 vss dq15 vssq dq13 vddq dq11 vssq dq9 vddq vss nc dqmu clk cke nc a11 a8 a7 23 32 24 31 25 30 26 29 27 28 a2 a3 vdd a0 a1 a6 a5 a4 vss a9 dq1 dq3 dq5 dq7 dq8 dq10 dq12 dq14 vddq dq0 vssq vddq dq1 vssq /cas /ras ba0(a13) ba1(a12) vdd nc nc nc nc vdd nc /we /cs a10 a2 a3 vdd a0 a1 nc nc vss vssq nc dq3 vddq nc vssq nc dq2 vddq nc vss nc dqm clk cke nc a11 a8 a7 a6 a5 a4 vss a9 nc nc vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke nc a11 a8 a7 a6 a5 a4 vss a9 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc /we /cas /ras /cs ba0(a13) ba1(a12) a10 a2 a3 vdd a0 a1 m2v64S40Btp m2v64s30btp m2v64s20btp
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 3 block diagram address buffer a0-11 ba0,1 control signal buffer /cs /ras /cas /we dqm clk cke clock buffer memory array bank #0 control circuitry i/o buffer dq0-3 (x4) dq0-7 (x8) dq0-15 (x16) mode register memory array bank #1 memory array bank #2 memory array bank #3 type designation code m2 v 64 s 2 0 b tp - 7 access item package type tp: tsop(ii) process generation function 0: random column organization 2n 2: x4, 3: x8, 4: x16 synchronous dram density 64:64m bits interface s: sstl, v:lvttl mitsubishi semiconductor memory this rule is applied only to synchronous dram families beyond 64m b-version.
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 4 pin function clk input master clock: all other inputs are referenced to the rising edge of clk. cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-11 input a0-11 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-11. the column address is specified by a0-a9(x4), a0-a8(x8), a0-7(x16) . a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. dq0-3(x4), dq0-7(x8), dq0-15(x16) input / output data in and data out are referenced to the rising edge of clk. dqm(x4,x8), dqmu/l(x16) input din mask / output disable: when dqmu/l is high in burst write, din for the current cycle is masked. when dqmu/l is high in burst read, dout is disabled at the next but one cycle. vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only.
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 5 basic functions the m2v64s20(30,40)btp provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto-precharge, reada ). write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto-precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, both banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated inter-nally. after this command, the banks are precharged automatically.
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 6 command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number note: 1. a7-a9 =0, a0-a6 =mode address command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a11 a10 a0-9 deselect desel h x h x x x x x x x no operation nop h x l h h h x x x x row address entry & bank activate act h x l l h h v v v v single bank precharge pre h x l l h l v x l x precharge all banks prea h x l l h l x h x column address entry & write write h x l h l l v x l v column address entry & write with auto- precharge writea h x l h l l v x h v column address entry & read read h x l h l h v x l v column address entry & read with auto- precharge reada h x l h l h v x h v auto-refresh refa h h l l l h x x x x self-refresh entry refs h l l l l h x x x x self-refresh exit refsx l h h x x x x x x x l h l h h h x x x x burst terminate tbst h x l h h l x mode register set mrs h x l l l l l l l v*1 x x x x
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 7 function truth table current state /cs /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l ba tbst nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 8 function truth table (continued) current state /cs /ras /cas /we address command action write h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge*3 l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 9 function truth table (continued) current state /cs /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea nop*4 (idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 10 function truth table (continued) current state /cs /ras /cas /we address command action re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l ba tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed.
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 11 current state cke n-1 cke n /cs /ras /cas /we add action self- refresh*1 h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) all banks idle*2 h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle*3 l h x x x x x exit clk suspend at next cycle*3 l l x x x x x maintain clk suspend function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command.
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 12 row active idle pre charge auto refresh self refresh mode register set power down read reada write writea read suspend reada suspend write suspend writea suspend power on clk suspend ckel ckeh ckel ckeh ckel ckeh ckel ckeh act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada write read pre reada writea reada pre pre pre power applied automatic sequence command sequence simplified state diagram tbst (for full page) tbst (for full page)
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 13 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1.clock will be applied at power up along with power. attempt to maintain cke high, dqm (x4,x8), dqmu/l (x16) high and nop condition at the inputs along with power. 2. maintain stable power, stable clock, and nop input conditions for a minimum of 200us. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when both banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. r: reserved for future use bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 1 2 4 8 r r r fp 1 2 4 8 r r r r 0 1 burst type sequential interleave a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 wm 0 0 ltmode bt bl 0 0 cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 latency mode /cas latency 2 3 r r r r r r /cs /ras /cas /we ba0,1 a11-a0 clk v fp: full page 0 1 write mode burst single bit
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 14 [ /cas latency ] /cas latency, cl, is used to synchronize the first output data with the clk frequency, i.e., the speed of clk determines which cl should be used. first output data is available after cl cycles from read command. /cas latency timing(bl=4) clk command address x act read y trcd dq q0 q1 q2 q3 dq q0 q1 q2 q3 cl=2 cl=3 cl=2 cl=3 [ burst length ] the burst length, bl, determines the number of consecutive writes or reads that will be automatically performed after the initial write or read command. for bl=1,2,4,8, full page the output data is tristated (hi-z) after the last read. for bl=fp (full page), the tbst (burst terminate) command should be issued to stop the output of data. burst length timing( cl=2 ) clk command address trcd dq q0 bl=1 dq q0 q1 bl=2 dq q0 q1 q2 q3 bl=4 dq q0 q1 q2 q3 bl=8 q4 q5 q6 q7 act read x y dq q0 q1 q2 q3 q4 q5 q6 q7 q8 qm q0 q1 m2v64s20b : m=1023 m2v64s30b : m=511 m2v64S40B : m=255 full page counter rolls over and continues to count. bl=fp
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 15 command address clk read y q0 q1 q2 q3 write y d0 d1 d2 d3 /cas latency burst length burst length dq burst type cl= 3 bl= 4 a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 16 operational description bank activate the sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row addresses a11-0. the minimum activation interval between one bank and the other bank is trrd.the number of banks which are active concurrently is not limited. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea, pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a9-0(x4), a8-0(x8), a7-0(x16), and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto- precharge (reada) is performed. any command (read, write, pre, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl after reada. the next act command can be issued after (bl + trp) from the previous reada. command bank activation and precharge all (bl=4, cl=3) clk a0-9 a10 ba0,1 dq act xa xa 00 read y 0 00 qa0 qa1 qa2 qa3 act xb xb 01 pre trrd trcd 1 act xb xb 01 precharge all tras trp trcmin a11 xa xb xb
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 17 multi bank interleaving read (bl=4, cl=3) clk command a0-9 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 qa0 qa1 qa2 qa3 qb0 qb1 qb2 act xb xb 10 pre 0 00 trcd /cas latency burst length a11 xa xb read with auto-precharge (bl=4, cl=3) clk command a0-9 a10 ba0,1 dq act xa xa 00 read y 1 00 qa0 qa1 qa2 qa3 act xa xa 00 internal precharge start trcd trp a11 xa xa bl bl + trp read auto-precharge timing (bl=4) clk command act read internal precharge start timing dq dq cl=3 cl=2 qa1 qa2 qa3 qa0 bl qa1 qa2 qa3 qa0
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 18 write after trcd from the bank activation, a write command can be issued. 1st input data is set at the same cycle as the write. following (bl -1) data are written into the ram, when the burst length is bl. the start address is specified by a9-0 (x 4), a8-0 (x 8) and a7-0 (x 16), and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is h igh at a write command, the auto-precharge (writea) is performed. any command (read, write, pre, act) to the same bank is inhib-ited till the internal precharge is complete. the internal precharge begins at twr after the last input data cycle. the next act command can be issued after trp from the internal precharge timing. the mode register can be programmed for burst read and single write. in this mode the write data is only clocked in when the write command is issued and the remaining burst length is ignored. the read data burst length os unaffected while in this mode multi bank interleaving write (bl=4) clk command a0-9 a10 ba0,1 dq act xa xa 00 write y 00 write y 0 0 10 da0 act xb xb 10 0 10 trcd trcd pre xa a11 xa xb 0 xa 0 00 pre 0 da1 da2 da3 db0 db1 db2 db3 write with auto-precharge (bl=4) twr clk command a0-9 a10 ba0,1 dq act xa xa 00 write y 1 00 da0 da1 da2 da3 act xa xa 00 internal precharge starts trcd trp a11 xa xa
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 19 [ burst write ] a burst write operation is enabled by setting a9=0 at mrs. a burst write starts in the same cycle as a write command set. (the latency of data input is 0.) the burst length can be set to 1,2,4,8, and full-page, like burst read operations. clk command address trcd dq d 0 bl=1 dq d 0 d 1 bl=2 dq d 0 d 1 d 2 d 3 bl=4 dq d 0 d 1 d 2 d 3 bl=8 d 4 d 5 d 6 d 7 act write dq d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d m d 0 d 1 m2v64s20b : m=1023 m2v64s30b : m=511 m2v64S40B : m=255 full page counter rolls over and continues to count. d 9 d 10 bl=fp a single write operation is enabled by setting a9=1 at mrs. in a single write operation, data is written only to the column address specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0.) [ single write ] clk command address x act write y trcd dq d 0
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 20 burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1 clk. [ read interrupted by write ] burst read operation can be interrupted by write of any bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 1 cycle after write assertion. read interrupted by read (bl=4, cl=3) clk command a0-9 a10 ba0,1 dq yi qai0 qaj1 qbk0 qbk1 qaj0 qbk2 qal0 qal1 qal2 qal3 read read read read yj yk yl 0 0 0 0 00 10 00 01 a11 dqm control write control read interrupted by write (bl=4, cl=3) clk command a0-9 a10 ba0,1 q read yi 0 00 qai0 write yj 0 00 d daj0 daj1 daj2 daj3 dqm(x4,x8) dqmu/l(x16) a11
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 21 [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same bank . read to pre interval is mini-mum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=4. read interrupted by precharge (bl=4) clk cl=3 command dq read pre q0 q1 q2 command dq read pre q0 cl=2 command dq read pre q0 q1 q2 command dq read pre q0 command dq read pre q0 q1 command dq read pre q0 q1
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 22 [ read interrupted by burst terminate ] similar to a precharge, the burst terminate command, tbst, can interrupt the burst read operation and disable the data output. the read to tbst interval is a minimum of one clk. tbst is mainly used to interrupt fp bursts. the figures below show examples, of how the output data is terminated with tbst. read interrupted by burst terminate(bl=4) clk command read tbst dq q0 q1 q2 command read tbst dq q0 q1 q2 q3 command read tbst dq q0 command read tbst dq q0 q1 q2 command read tbst dq q0 q1 q2 q3 command read tbst dq q0 cl=3 cl=2
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 23 [ write interrupted by write ] burst write operation can be interrupted by new write of any bank. random column access is allowed. write to write interval is minimum 1 clk. [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". write interrupted by write (bl=4) clk command a0-9 a10 ba0,1 dq write yi 0 00 write yk 0 10 dai0 daj0 daj1 dbk0 write yj 0 00 dbk1 dbk2 write yl 0 00 dal0 dal1 dal2 dal3 a11 write interrupted by read (bl=4, cl=3) clk command a0-9 a10 ba0,1 dq write yi 0 00 qaj0 read yj 0 00 qaj1 dai0 dbk0 dbk1 write yk 0 10 read yl 0 00 qal0 a11 dqm(x4,x8) dqmu/l(x16)
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 24 [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank . random column access is allowed. write recovery time (twr) is required from the last data to pre command. write interrupted by precharge (bl=4) clk command a0-9 a10 ba0,1 dq write yi 0 00 pre 0 00 act xb xb 00 twr trp a11 xb dai0 dai1 dai2 [ write interrupted by burst terminate ] a burst terminate command tbst can be used to terminate a burst write operation. in this case, the write recovery time is not required and the bank remains active (please see the waveforms below). the write to tbst minimum interval is one clk. write interrupted by burst terminate(bl=4) clk command a0-9 a10 ba dq write yi 0 0 dai0 dqm(x4,x8) dqmu/l(x16) tbst dai1 dai2 dqm(x4,x8) dqmu/l(x16)
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 25 auto refresh single cycle of auto-refresh is initiated with a refa (/cs= /ras= /cas= l, /we= /cke= h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 64mbit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trc. any command must not be supplied to the device before trc from the refa command. auto-refresh clk /cs /ras /cas /we cke a0-11 ba0,1 auto refresh on all banks minimum trc nop or deselect auto refresh on all banks
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 26 self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input ,all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke (refsx) for longer than tsrx. after trc from refsx all banks are in the idle state and a new command can be issued, but desel or nop commands must be asserted till then. self-refresh clk /cs /ras /cas /we cke a0-11 ba0,1 self refresh entry self refresh exit x 00 stable clk nop new command tsrx minimum trc +1 clock for recovery
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 27 clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self- refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. power down by cke clk command pre cke command cke act nop nop nop nop nop nop nop nop nop nop nop nop standby power down active power down nop nop ext.clk cke int.clk dq suspend by cke clk command dq write d0 cke read q0 q1 q2 q3 d1 d2 d3
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 28 dqm control for x16, dqmu/l are dual function signals defined as the data mask for writes and the output disable for reads. during writes, dqmu/l mask input data word by word. dqmu/l to write mask latency is 0. during reads, dqmu/l force outputs to hi-z word by word. dqmu/l to output hi-z latency is 2. dqml and dqmu control lower byte (dq0-7), and upper byte (dq8-15), respectively. dqm function clk command dq0-7 write d0 d2 d3 dqml read q0 q1 q3 masked by dqml=h disabled by dqmu=h dq8-15 d0 d2 d3 q0 q1 q3 dqmu d1 q2 for x4/x8, dqm is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqm masks input data word by word. dqm to write mask latency is 0. during reads, dqm forces output to hi-z word by word. dqm to output hi-z latency is 2. dqm function clk command dq write d0 d2 d3 dqm read q0 q1 q3 masked by dqm=h disabled by dqm=h
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 29 absolute maximum ratings recommended operating conditions capacitance notes) 1. vih(max)= vdd+2.0v ac for pulse width less than 3ns acceptable. 2. vil(min) = -2.0v ac for pulse width less than 3ns acceptable. symbol parameter limits unit min. typ. max. vdd supply voltage 3.0 3.3 3.6 v vss supply voltage 0 0 0 v vddq supply voltage for output 3.0 3.3 3.6 v vssq supply voltage for output 0 0 0 v vih*1 high-level input voltage all inputs 2.0 vddq +0.3 v vil*2 low-level input voltage all inputs -0.3 0.8 v symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 - 4.6 v vddq supply voltage for output -0.5 - 4.6 v vi input voltage -0.5 - 4.6 v vo output voltage -0.5 - 4.6 v io output current 50 ma pd power dissipation ta = 25o c 1000 mw topr operating temperature 0 - 70 tstg storage temperature -65 - 150 o c with respect to vssq with respect to vss with respect to vssq o c symbol parameter test condition limits (max.) unit ci(a) input capacitance, address pin 3.8 pf ci(c) input capacitance, contorl pin 1mhz, 1.4v bias 200mv swing 3.8 pf ci(k) input capacitance, clk pin 3.5 pf ci/o input capacitance, i/o pin 6.5 pf (ta=0 ? 70 o c, unless otherwise noted ) limits (min.) 2.5 2.5 2.5 4.0 (ta=0 ? 70 o c, vdd= vddq= 3.3 0.3v, vss= vssq= 0v, unless otherwise noted )
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 30 average supply current from vdd ac operating conditions and characteristics note) 1. icc(max) is specified at the output open condition. 2.input signal are changed one time during 30ns symbol parameter test conditions limits unit min. max. voh (dc) high-level output voltage (dc) ioh=-2ma 2.4 v vol (dc) low-level output voltage (dc) iol= 2ma 0.4 v ioz off-state output current q floating vo=0 -- vddq -10 10 a input current vih = 0 -- vddq +0.3v -10 10 a i i (ta=0 ? 70 o c, vdd= vddq= 3.3 0.3v, vss= vssq= 0v, unless otherwise noted ) (ta=0 ? 70 o c, vdd= vddq= 3.3 0.3v, vss= vssq= 0v, unless otherwise noted ) symbol item limits (max.) unit icc1 operating current ma icc2n tclk = 15ns cke = vihmin icc2p ma icc4 all bank active,tclk = min bl=4, cl=3,i ol =0ma organi- zation note x4/x8 single bank operation *1 tclk = 15ns cke = vilmax *1,2 *1,2 *1,2 *1 ma ma ma -6 145 120 25 2 trc=min, tclk =min, bl=1 , cl=3,iol=0ma precharge standby current in non power down mode active standby current in non power down mode burst current icc5 trfc=min, tclk=min *1 ma auto-refresh current icc2ns c lk = vilmax cke = vihmin *1 ma 20 icc2ps clk = cke =vilmax(fixed) *1 ma 1 icc6 self-refresh current *1 ma 1 cke < 0.2v 150 icc3ns 40 icc3n cke = /cs=vihmin, tclk=15ns 55 precharge standby current in power down mode x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8 x4/x8/x16 x4/x8/x16 (fixed) ma *1 active standby current in power down mode cke = /cs=vihmin, clk=vilmax (fixed) icc3p tclk = 15ns cke = vilmax *1,2 ma 2 icc3ps clk = cke =vilmax(fixed) *1 ma 1 x4/x8/x16 x4/x8/x16 x16 130 160 x16
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 31 ac timing requirements any ac timing is referenced to the input signal passing through 1.4v. (ta=0 ? 70 o c, vdd= vddq= 3.3 0.3v, vss= vssq= 0v, unless otherwise noted ) input pulse levels: 0.8v ? 2.0v input timing measurement level: 1.4v clk dq 1.4v 1.4v symbol parameter limits unit tclk clk cycle time cl=3 ns cl=2 ns tch clk high pulse width ns tcl clk low pulse width ns tt transition time of clk ns tis input setup time (all inputs) ns tih input hold time (all inputs) ns trc row cycle time ns trcd row to column delay ns tras row active time ns trp row precharge time ns twr write recovery time ns trrd act to act delay time ns trsc mode register set cycle time ns tsrx self-refresh exit time ns tref refresh interval time ms tpde power down exit time ns min. max. 7.5 2.5 1 10 1.5 0.8 67.5 20 45 1 00k 20 15 15 15 7.5 64 7.5 -6 10 2.5 trfc row refresh cycle time ns 75
mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 32 switching characteristics output load condition (ta=0 ? 70 o c, vdd= vddq= 3.3 0.3v, vss= vssq= 0v, unless otherwise noted ) note) 1. if clock rising time is longer than 1ns, (tr /2 ? 0.5ns) should be added to the parameter. v out ext.cl=50pf output timing measurement reference point clk 1.4v 1.4v dq symbol parameter limits unit tac access time from clk cl=3 ns cl=2 ns toh output hold time from clk ns tolz delay time, output low- impedance from clk ns tohz delay time, output high- impedance from clk 2.7 ns note *1 -6 min. max. 5.4 2.7 0 5.4 6.0 tohz tac clk dq 1.4v 1.4v toh tolz cl=3 cl=2 3.0 ns
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 33 burst write (single bank) @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd twr trp trc trcd clk italic parameter indicates minimum case tras
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 34 burst write (multi bank) @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras twr trp trc trcd d1 d1 d1 d1 x x x 1 trrd y twr 0 x 1 x x x 2 trrd act#1 write#1 pre#1 act#2 clk italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 35 burst read (single bank) @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 read to pre 3bl allows full data out dqm read latency =2 clk italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 36 burst read (multiple bank) @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 dqm read latency =2 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 x x x 2 1 cl=3 read#1 pre#1 act#2 clk italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 37 burst write (multi bank) with auto-precharge @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 with autoprecharge act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd d1 d1 d1 d1 x x x 1 trrd y x 1 x x x trrd act#1 write#1 with autoprecharge bl-1+ twr + trp y 1 d1 trcd act#1 write#1 clk bl-1+ twr + trp italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 38 burst read (multiple bank) with auto-precharge @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 with auto-precharge act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd cl=3 dqm read latency =2 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 cl=3 read#1 with auto-precharge act#1 bl+ trp bl+ trp x x x 1 y 1 clk q0 cl=3 trcd italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 39 page mode burst write (multi bank) @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 act#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd d1 d1 d1 d1 y y 0 write#1 clk x x x 1 trrd 1 y d0 d0 d0 d0 d0 d0 d0 act#1 write#0 italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 40 page mode burst read (multi bank) @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q1 q1 q1 q1 y y 0 read#1 clk x x x 1 trrd 1 y q0 q0 q0 q0 act#1 read#0 q0 cl=3 cl=3 cl=3 dqm read latency=2 italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 41 write interrupted by write / read @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 write#1 clk x x x 1 trrd 1 y d0 d0 d1 d1 q0 q0 q0 act#1 write#0 y y 0 0 0 y tccd cl=3 write#0 read#0 burst write can be interrupted by write or read of any active bank. italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 42 read interrupted by read / write @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 d0 d0 y y 0 read#1 clk x x x 1 trrd 0 y q0 q0 q1 q1 act#1 read#0 q0 dqm read latency=2 0 y 1 y burst read can be interrupted by read or write of any active bank. read#0 read#0 blank to prevent bus contention italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 43 write interrupted by precharge @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd write#1 clk x x x 1 trrd 1 d1 d1 d1 d1 d1 act#1 y 1 1 y burst write is not interrupted by precharge of the other bank. 0 x x x 1 pre#1 pre#0 act#1 write#1 burst write is interrupted by precharge of the same bank. italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 44 read interrupted by precharge @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd y 1 pre#1 clk x x x 1 trrd q1 q1 act#1 pre#0 q0 dqm read latency=2 1 y 1 burst read is not interrupted by precharge of the other bank. 0 x x x 1 trcd trp read#1 act#1 read#1 burst read is interrupted by precharge of the same bank. italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 45 mode register setting /cs /ras /cas /we cke ba0,1 dq auto-ref (last of 8 cycles) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 y 0 clk trc d0 mode register setting m 0 x x x 0 trcd trsc act#0 write#0 d0 d0 d0 italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 46 auto-refresh @bl=4 /cs /ras /cas /we cke ba0,1 dq auto-refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk trc before auto-refresh, all banks must be idle state. y 0 d0 x x x 0 trcd act#0 write#0 d0 d0 d0 after trc from auto-refresh, all banks are idle state. italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 47 self-refresh /cs /ras /cas /we cke ba0,1 dq self-refresh entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk before self-refresh entry, all banks must be idle state. x x x 0 self-refresh exit act#0 after trc from self-refresh exit, all banks are idle state. trc+1 tsrx clk can be stopped cke must be low to maintain self-refresh italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 48 dqm write mask @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 y 0 d0 d0 d0 act#0 write#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 49 dqm read mask @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 y 0 q0 q0 q0 act#0 read#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked dqm read latency=2 italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 50 power down /cs /ras /cas /we cke ba0,1 dq 0 precharge all act#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk x x x standby power down active power down cke latency=1 italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 51 clk suspend @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 act#0 write#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y d0 d0 d0 d0 clk suspended clk suspended cke latency=1 cke latency=1 italic parameter indicates minimum case
a 0-9 * a 10 dqm(u/l) a 11 * a9 (x8) and a8,a9 (x16) for column address of read/write are don't care mitsubishi electric oct . '99 mitsubishi lsis pc133 sdram (rev.0.5) m2v64s20btp-6 (4-bank x 4194304-word x 4-bit) m2v64s30btp-6 (4-bank x 2097152-word x 8-bit) m2v64S40Btp-6 (4-bank x 1048576-word x 16-bit) 64m bit synchronous dram 52 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1.these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to mitsubishi electric corporation or a third party. 2.mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or ci rcuit application examples contained in these materials. 3.all information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. 4.mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular, medical,aerospace,nuclear,or undersea repeater use. 5.the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. 6.if these products or technologies are subject the japanese export control restrictions,they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 7.please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.

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