skyworks solutions, inc. [781] 376-3000 ? fax [781] 376-3100 ? email sales@skyworksinc.com ? www.skyworksinc.com 1 specifications subject to change without notice. 10/02a suggested pcb land pattern designs for leaded and leadless packages and detailed surface mount guidelines for leadless packages below are sample printed circuit board land pattern dimensions. these are based on the ipc (institute for interconnecting and packaging electronic circuits) surface mount design and land pattern standard: ipc-sm-782. these drawings are for reference only. it is recommended that you consult with the company doing the component mounting and soldering to the printed circuit board. these companies have more information on options (various possible dimensions) of actual land patterns. sc-70 0.087 (2.20 mm) 0.055 (1.40 mm) 0.051 (1.30 mm) 0.026 (0.65 mm) 0.020 (0.50 mm) sot-23 3 lead 0.087 (2.20 mm) 0.075 (1.90 mm) 0.037 (0.95 mm) 0.039 (1.00 mm) 0.055 (1.40 mm) sod-323 0.095 (2.40 mm) 0.035 (0.90 mm) 0.030 (0.80 mm) sc-79 0.014 (0.35 mm) nom. 0.014 (0.35 mm) nom. 0.053 (1.35 mm) nom. sot-143 0.075 (1.90 mm) 0.039 (1.00 mm) 0.031 (0.80 mm) 0.057 (1.44 mm) 0.039 (1.00 mm) min. 0.047 (1.20 mm) max. 0.067 (1.70 mm) 0.087 (2.20 mm) chip scale 375 m 600 m 250 m
suggested pcb land pattern designs for leaded and leadless packages and detailed surface mount guidelines for leadless packages 2 skyworks solutions, inc. [781] 376-3000 ? fax [781] 376-3100 ? email sales@skyworksinc.com ? www.skyworksinc.com specifications subject to change without notice. 10/02a 16 lead soic wide body 9.2 mm 1.27 mm 0.6 mm 2.2 mm 14 lead soic narrow body 2.200 mm 0.600 mm 1.270 mm 5.200 mm 28 lead soic wide body 9.2 mm 1.27 mm 0.6 mm 2.2 mm 0.70 mm ref. 3.4 mm ref. 0.95 mm ref. 0.95 mm ref. 1.0 mm ref. 2.4 mm ref. sot-5, sot-6 msop-8 0.4 mm 1.7 mm 2.4 mm 4.1 mm 5.8 mm 0.65 mm 8 lead ssop (5.3 mm) 5.0 mm 7.2 mm 9.4 mm 2.2 mm 0.40 mm 0.65 mm
suggested pcb land pattern designs for leaded and leadless packages and detailed surface mount guidelines for leadless packages skyworks solutions, inc. [781] 376-3000 ? fax [781] 376-3100 ? email sales@skyworksinc.com ? www.skyworksinc.com 3 specifications subject to change without notice. 10/02a 5.200 mm 1.270 mm 0.600 mm 2.200 mm 8 lead soic narrow body 16 lead soic narrow body 2.200 mm 5.200 mm 1.270 mm 0.600 mm lpcc-16 lead 4 x 4 mm (-307) surface mount land pattern outside of package footprint of pcb land = lead length +0.1 mm lead width lead length of lpcc 0.013 (0.33 mm) typ. gnd via 0.063 (1.60 mm) typ. 0.165 (4.20 mm) 0.126 (3.20 mm) 0.008 (0.20 mm) 0.010 (0.25 mm) 0.026 (0.65 mm) 0.020 (0.50 mm) 0.110 (2.79 mm) sq. 5.200 mm 1.270 mm 0.600 mm 2.200 mm soic-8 qfn-32 lead 5 x 5 mm (-310) surface mount land pattern 0.013 (0.33 mm) typ. gnd via 0.063 (1.60 mm) typ. 0.020 (0.50 mm) 0.020 (0.50 mm) 0.122 (3.10 mm) sq. 0.020 (0.50 mm) 0.020 (0.50 mm) 0.013 (0.33 mm) 0.65 mm ref. 0.65 mm ref. 0.40 mm ref. 0.75 mm ref. 1.65 mm ref. sc-88 (6 lead sc-70)
suggested pcb land pattern designs for leaded and leadless packages and detailed surface mount guidelines for leadless packages 4 skyworks solutions, inc. [781] 376-3000 ? fax [781] 376-3100 ? email sales@skyworksinc.com ? www.skyworksinc.com specifications subject to change without notice. 10/02a skyworks? plastic encapsulated leadless style packages are being offered on several products to reduce size and weight and to improve application performance. these packages are gaining acceptance in the industry and are often referred to by such names as ?qfn,? ?lpcc,? ?mlf? and others, and conform to jedec outline mo-220. these packages use perimeter lands on the bottom of the package to provide contact to the pcb. these packages also have an exposed paddle on the bottom to provide a stable ground for optimum electrical performance of switches and attenuators, and an efficient heat path for thermal performance for amplifier products. the ground pad on the pcb should match the size of the exposed paddle of the package and should be solder mask defined (smd). the solder mask opening should overlap the edges of the pcb ground pad by 0.065 mm (0.0025") on all four sides. the recommended design gap between the pcb ground pad and land pad is 0.15 mm minimum to avoid solder bridging and shorting. when space is available, a gap of 0.25 mm or more is preferred. plated thru via holes in the pcb ground pad should be 0.33 (0.013") in diameter and plugged. if via holes cannot be plugged, it is recommended to cap the vias on the backside of the board using solder mask material. this should allow the vias to be filled with solder during reflow. gold wire lead mold compound down bond exposed die paddle die figure 1. package cross section 0.65 (0.026) 4.20 (0.165) 3.20 (0.126) 2.79 (0.110) 1.60 (0.063) typ. 0.50 (0.020) 0.25 (0.010) 0.33 (0.013) typ. 0.20 (0.008) dimensions in mm (in.) lead length of lpcc lead width outside of package footprint of pcb land = lead length + 0.1 mm figure 2. surface mount land pattern, 4 x 4 mm 16 lead lpcc within are the suggested guidelines for layout of a pcb and stencil for skyworks? 4 x 4 mm lpcc-16. pcb design guidelines for the lead/terminal solder pad design, it is recommended to use a non solder mask defined (nsmd) approach, but a small amount of solder mask should remain between the pads to avoid solder bridging between terminals. the pcb land width should match package pad width. the pcb land length should be 0.1 mm greater than the package pad length, with the extra area on the outside of the package. see figure 2. detailed surface mount guidelines for leadless packages
suggested pcb land pattern designs for leaded and leadless packages and detailed surface mount guidelines for leadless packages skyworks solutions, inc. [781] 376-3000 ? fax [781] 376-3100 ? email sales@skyworksinc.com ? www.skyworksinc.com 5 specifications subject to change without notice. 10/02a solder mask design two types of stencil designs are used for surface mount packages: 1. solder mask defined (smd): solder mask openings smaller than metal pads. 2. non-solder mask defined (nsmd): solder mask openings larger than metal pads. nsmd is recommended for the perimeter i/o lands, as this allows the solder to wrap around the sides of the metal pads on the board for a reliable solder joint. because the spacing between the ground pad and the land pads can be small, smd is recommended for the ground pad to prevent solder bridging. a stainless steel stencil, 0.125?0.150 mm (0.005?0.006") thick, is recommended for solder paste application. for better paste release, the aperture walls should be trapezoidal and the corners rounded. for the terminal lands, the stencil opening should be 0.05 mm larger than the pcb land (0.025 mm in each direction). for the ground pad area, it is recommended to screen the solder paste in an array of small openings rather than one large opening. the total (cumulative) area of all the openings should be approximately equal to 50% of the total ground pad area. this will ensure good solder coverage with fewer voids. see figure 3. solder paste and reflow profile because leadless packages have a low stand-off height and small terminal pitch, a no clean, type 3 solder paste, and a convection/ir reflow is recommended. sn63 (63% sn, 37% pb) solder is preferred because it is a eutectic compound with a melting point of 183c. the reflow temperature in this case would be above 183c for 30?60 seconds, with a peak temperature of 205?210c. if a lead-free alloy is used, such as tin/silver or tin/silver/copper, the melting point is 221c and 217c respectively. in this case, the profile would be above 221/217c for 30?60 seconds, with a peak temperature of 230?240c. maximum temperature should not exceed 240c. a typical reflow profile is presented in figure 4, which could be used as a starting point. the actual profile used will depend on the thermal mass of the entire populated board and the solder compound used. multiple small stencil openings (total area approximately 50% of total pcb ground pad) pcb ground pad boundary terminal land stencil opening figure 3. recommended stencil design temperature (?c) 250 200 150 100 50 0 0 60 120 180 240 300 time (seconds) preheat flux activation/ thermal equalization reflow cool down 2?4 minutes max. 3 minutes min. <2.5?c sec. 30?60 sec. <0.5??0.6?c/sec. <1.3??1.6?c/sec. figure 4. typical solder reflow profile
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