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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. 12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 19-5192; rev 0; 6/10 general description the MAX11068 is a programmable, highly integrated, high-voltage, 12-channel, battery-monitoring smart data- acquisition interface. it is optimized for use with batter - ies used in automotive systems, hybrid electric battery packs, electric cars, and any system that stacks long series strings of secondary metal batteries. this highly integrated battery sensor incorporates a simple state machine and a high-speed i 2 c bus for smbus k -laddered serial communication. the MAX11068 analog front-end combines a 12-channel voltage measurement data-acquisition system with a high- voltage switch bank input. all measurements are done differentially across each cell. the full-scale measurement range is from 0 to 5.0v, with full stated accuracy guaran - teed from 0.5v to 4.7v. the input mux/switch bank allows for differential measurement of each cell in a series stack. a high-speed, 12-bit successive approximation (sar) a/d converter is used to digitize the cell voltages. all 12 cells can be measured in less than 107 f s. the MAX11068 uses a two-scan approach for collecting cell measurements and correcting them for errors. the first phase of the scan is the acquisition phase where the voltages of all 12 cells are acquired. the second phase is the error-cancellation phase where the adc input is chopped to remove errors. this two-phase approach yields excellent accuracy over temperature and in the face of extreme noise in the sys - tem. the MAX11068 incorporates an internal oscillator that generates a 6.0mhz system clock with q 3.0% accuracy. the MAX11068 consumes less than 2.0ma from the power supply while in data-acquisition modes. this current is reduced to 75 f a in standby mode and less than 1 f a in shutdown mode. the device is packaged in a 38-pin, 9.7mm x 4.4mm x 1.0mm tssop package that is lead free and rohs compliant and is designed to operate over the aec-q100 grade 2, -40 n c to +105 n c temperature range. applications high-voltage, multicell series-stacked-battery systems electric and hybrid electric vehicle (hev) battery packs electric bikes high-power battery backup systems supercap backup systems power tools features s 12-cell battery voltage measurement with temperature monitoring up to 12 lithium-ion (li+), nimh, or super-cap cells two auxiliary analog inputs for temperature measurement s high-accuracy i/os excellent 0.25 % voltage-measurement accuracy 5mv offset voltage s integrated 12-channel data-acquisition system 12-channel high-voltage mux to adc differential cell-voltage measurement 12-bit precision, high-speed sar adc 12 cell voltages measured within 107s s battery-fault detection overvoltage and undervoltage digital threshold detection cell sense line open-circuit detection high/low temperature digital threshold detection s 12 integrated cell-equalization switches support up to 200ma s integrated 6v to 70v input linear regulator s integrated 25ppm/ n c, 2.5v precision reference s integrated level-shifted, i 2 c-compliant smbus ladder interface supports multiple devices, up to 31 smbus- ladder-connected ics communications protocol with autoaddressing fault-tolerant hardware handshake and data crc checking s three general-purpose digital i/o lines s ultra-low power dissipation standby mode quiescent current drain 75 a shutdown mode leakage current 1a s operating temperature range from -40 n c to +105 n c (aec-q100 grade 2) s 38-pin, lead -free/ rohs-compliant tssop package (9.7mm x 4.4mm) ordering information + denotes a lead(pb)-free/rohs-compliant package. /v denotes an automotive qualified part. smbus is a trademark of intel corp. evaluation kit available part temp range pin-package MAX11068guu+ -40 n c to +105 n c 38 tssop MAX11068guu/v+ -40 n c to +105 n c 38 tssop
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 2 stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hv, vdd u , gnd u , dcin to agnd ...................... -0.3v to +80v hv to c12 ................................................................ -0.3v to +6v c1Cc12 to agnd ...................................... -0.3v to (v hv + 0.3v) c(n+1) to c(n) ..................................................... -0.3v to +9.0v c0 to agnd ......................................................... -0.3v to +4.0v shdn to agnd ..................................................... -0.3v to +60v vaa to agnd ....................................................... -0.3v to +4.0v vdd l to gnd l ..................................................... -0.3v to +4.0v vdd u to gnd u .................................................... -0.3v to +6.0v gnd u to gnd l ..................................................... -0.3v to +80v agnd to gnd l .................................................... -0.3v to +0.3v auxin1, auxin2, thrm to agnd ...................... -0.3v to +6.0v ref to agnd ........................................... -0.3v to (vaa + 0.3v) scl l , sda l , alrm l to gnd l ............... -0.3v to (vdd l + 0.3v) scl u , sda u , alrm u to gnd u ............. -0.3v to (vdd u + 0.3v) cp+ to agnd ......................... (gnd u - 1.0v) to (vdd u + 1.0v) cp- to agnd ......................................... -0.3v to (gnd u + 0.3v) gpio0, gpio1, gpio2 ........................... -0.3v to (vdd l + 0.3v) esd rating (hbm, note 1) .................................................. q 2kv c0Cc12, auxin1, auxin2, ref, vaa, vdd u , gnd u , vdd l , gnd l , dcin, shdn , cp+, cp-, hv, scl u , sda u , alrm u , scl l , sda l , alrm l , gpio0, gpio1, gpio2 maximum continuous current into any pin ....................... 20ma esd diode maximum average power dissipation for hot plug (note 2) ... ..................14.4 / w continuous power: multilayer board .......................... 1269.8mw continuous power: single-layer board (derating 15.9mw/ n c above +70 n c) ....................... 1095.9mw operating temperature range ....................... .-40 n c to +105 n c storage temperature range ............................ -55 n c to +150 n c junction temperature (continuous) ................................ +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c electrical characteristics ( t a = t min to t max , unless otherwise noted. v gndu = v dcin = 18v to +60v, typical values are at t a = +25 n c, unless otherwise specified from -40 n c to +105 n c per the application circuit in figure 4.) absolute maximum ratings note 1: human body model to specification mil-std-883 method 3015.7. note 2: maximum average power dissipation for time period . peak current must never exceed 2a. is one time constant (in s) of hot-plug current waveform through a given diode. for example, if is 330s, the maximum average diode power dissipation is 0.793w. actual average power dissipation must be calculated from current waveform for the application circuit. parameter symbol conditions min typ max units c0Cc12 inputs differential cell input-voltage range vcell xin any 2 inputs cn+1 to cn for c12Cc0 (note 2) 0.5 4.7 v cell input common-mode voltage range ( note 5) vc xin input c1 referred to agnd 0.7 7.0 v inputs c2 through c[top] referred to agnd 0.7 c[top] referred to agnd gnd u c0 referred to agnd -0.05 +0.05 input-leakage current i cx in adc off; c n to c n+1 = 5v -1.0 +1.0 f a adc on; c n to c n+1 = 3v q 10.0 adc resolution adc bits lsb size is +1.22mv 12 bits channel- conversion time t s highest enabled input 11.34 f s/ channel enabled inputs except highest 7.66 channel accuracy t a = +25 n c (note 4); v cell = 3.0v -5 +5 mv -10 n c < t a < +50 n c; v cell = 3.0v (note 3) -10 +10 -40 n c < t a < +85 n c; v cell = 3.0v (note 3) -15 +15 -40 n c < t a < +105 n c; v cell = 3.0v -20 +20
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 3 electrical characteristics (continued) ( t a = t min to t max , unless otherwise noted. v gndu = v dcin = 18v to +60v, typical values are at t a = +25 n c, unless otherwise specified from -40 n c to +105 n c per the application circuit in figure 4.) parameter symbol conditions min typ max units differential nonlinearity dnl no missing codes at 12 bits q 1.0 lsb channel offset error cellv os cells 1 through 12 -5 +5 mv channel gain error cella v cells 1 through 12 -1.0 +1.0 % cell-balancing switch resistance r switch from cn to cn+1 when enabled 1.5 6 20 i auxin1, auxin2 inputs absolute differential input range vauxinxin auxin1, auxin2 to agnd; adc ref = thrm 0 v thrm v common-mode input-voltage range inputs auxin1/2 referred to agnd 0 v thrm v input-leakage current i auxin adc off; input voltage = 3.3v -1.0 +1.0 f a adc resolution 12 bits conversion time t s 10 f s/ aux_ input accuracy t a = +25 n c -0.5 +0.5 % -40 n c < t a < +105 n c -1.0 +1.0 differential nonlinearity dnl no missing codes at 12 bits q 1.0 lsb offset error auxv os auxin1, auxin2 -8 +8 mv gain error auxa v auxin1, auxin2 -1.0 +1.0 % thrm switch resistance r thrm thrm to vaa (note 3) 5 18 28 i voltage reference output ref voltage refv out t a = +25 n c 2.45 2.50 2.55 v ref output short-circuit current i ref-sc q 12.5 ma temperature coefficient d ref/ d temp q 25 ppm/ n c initial drift change after 1000hr burn-in 120 ppm logic inputs and outputs (gpio and shdn) shdn voltage high 1.8 v shdn voltage low 0.5 v shdn input leakage current v shdn = 3.4v 1 f a v shdn = 30v 5.15 18 v shdn = 56v 12.6 45 gpio input voltage low 0.8 v gpio input voltage high 2.4 v i/o leakage current i/o pins programmed to high impedance -1 +2 +6.2 f a gpio output voltage low i sink = 3ma 0.4 v gpio output voltage high i source = 3ma vdd l - 0.5 v
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 4 electrical characteristics (continued) ( t a = t min to t max , unless otherwise noted. v gndu = v dcin = 18v to +60v, typical values are at t a = +25 n c, unless otherwise specified from -40 n c to +105 n c per the application circuit in figure 4.) parameter symbol conditions min typ max units linear regulator +3.4v (vaa) input voltage range v dcin 0 < i load < 8ma 6.0 70 v output voltage v vaa 0 < i load < 8ma; 6v < v dcin < 70v 3.25 3.4 3.55 v short-circuit current vaa = 0v, 6v < v dcin < 30v 60 ma power-on reset threshold (note 3) falling vaa 2.85 2.95 3.05 v rising vaa 2.9 3.0 3.1 por threshold hysteresis 0.01 40 80 mv thermal shutdown rising temperature +145 n c thermal-shutdown hysteresis 15 n c charge pump +3.4v output voltage v vddu - v gndu i load = 0 at 0.1 f f cp+ to cp- 3.2 3.4 3.55 v 1ma = i load at 0.1 f f cp+ to cp- 3.2 2.5 3.55 charge-pump efficiency i vddu /i gndu - i vddu at 2.7v, vdd u - gnd u 60 89 99 % charge-pump undervoltage threshold v cpuv 2.0 2.7 3.2 v internal oscillators (32.768khz, 6.0mhz) internal 32.768khz oscillator frequency f wd-osc 32.113 32.768 33.423 khz internal 6.0mhz oscillator frequency f hf-osc 5.82 6.0 6.18 mhz i 2 c lower port scl l , sda l , alrm l (relative to gnd l, vdd l = nominal 3.4v) sda l , scl l input voltage low 0.3 x v vddl v sda l , scl l input voltage high 0.7 x v vddl v sda l , scl l input hysteresis 0.2 0.1 x v vddl 0.5 v sda l , alrm l output voltage low at sink = 3ma 0.4 v sda l , scl l leakage current v sdal = v scll = 1.5v 1.0 f a sda l , managed resistance r active_edge active edge 0.5 1 3 k i managed passive state 35 50 75 off passive state 1 m i t one_shot t one_shot (active edge pulse) 150 250 380 ns sda l 1-tau capacitance c 1_tau sda l rises to 70% within active edge time when loaded with this capacitance 120 280 550 pf alrm l output high voltage at source = 3ma vdd l - 0.4 v alrm l heartbeat frequency osc = 32.768khz q 2.0% 16,000 16,384 16,711 khz lower port input capacitance scl l , sda l , alrm l 15 pf
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 5 electrical characteristics (continued) ( t a = t min to t max , unless otherwise noted. v gndu = v dcin = 18v to +60v, typical values are at t a = +25 n c, unless otherwise specified from -40 n c to +105 n c per the application circuit in figure 4.) parameter symbol conditions min typ max units i 2 c upper port scl u , sda u , alrm u (relative to gnd u, vdd u ) sda u , alrm u input voltage low 0.3 x v vddu v sda u , alrm u input voltage high 0.7 x v vddu v sda u , alrm u input hysteresis 0.05 0.1 x v vddu 0.4 v sda u , scl u output voltage low at sink = 3ma 0.4 v sda u , scl u leakage current v sdau = v sclu = 1.5v -1 q 1.0 +1 f a sda u , managed resistance active edge 0.5 1 3 k i managed passive state 30 50 75 k i off passive state 1 m i t one_shot t one_shot (active edge pulse) 150 250 480 ns sda u 1-tau capacitance sda u rises to 70% within active edge time when loaded with this capaci tance, i.e., choose 100pf to guarantee 3 h rising edge 120 280 550 pf alrm u clamp current v alrmu = vdd u + 0.15v 1 f a v alrmu = gnd u - 0.15v 1 alrm u clamp voltage 250 f a current pulling below gnd u gnd u -0.49 v 250 f a current pulling above vdd u vdd u + 0.49 v upper port input capacitance scl u , sda u , alrm u 8 pf port-to-port level delay 1 f s interface startup from shdn or from por 3 ms i 2 c timing characteristics i 2 c clock frequency f i2c 10 200 khz bus timeout period t timeout timeout for maximum clock low/high time 27.4 ms bus free time t buf master to slave delay from a stop to the next start command 500 f s bus hold time t hd-sta master hold time after a start command 350 f s bus start command setup time t su-sta repeated start setup time 1 f s bus stop command setup time t su-stop stop condition setup time 100 ns sda data hold time slave port t hd-dat transmit 500 ns receive -30 master port t hd-dat transmit 400 receive (note 7) 400
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 6 electrical characteristics (continued) ( t a = t min to t max , unless otherwise noted. v gndu = v dcin = 18v to +60v, typical values are at t a = +25 n c otherwise specified from -40 n c to +105 n c per the application circuit in figure 4.) note 3: guaranteed by design and not production tested. note 4: differential input voltage range for which channel gain and offset error applies. note 5: common-mode level at each pin required for specified operation of the high-voltage mux. note 6: offset and gain error are calibrated at +25 n c and 3.0v per cell at the factory, assuming that vc xin is met. note 7: this is a derived specification. no characterization required. these specifications involve the clock low time and clock high time used. parameter symbol conditions min typ max units sda data setup time slave port t su-dat transmit (note 7) 250 ns receive 250 master port t su-dat transmit (note 7) 250 receive 1000 scl l low time t low 1.25 f s scl l high time t high 1.25 f s remastered clock minimum high time t mcl-min 1 us level-shift timing level shift delay (sda l to sda u or sda u to sda l ) t ls-dat rising or falling edge at 1.5v threshold; pin-to-pin delay with 100pf loading 400 1100 ns level shift delay (scl l to scl u ) t ls-clk rising or falling edge at 1.5v threshold; pin-to-pin delay with 100pf loading 600 800 ns power-supply requirements dcin current consumption ( note: idd q testing is done in production test with a coverage of 71%) i dcin acquisition mode high-voltage mux enabled, adc converting 12 channels; v dcin = 30v 3.0 6 ma i hv acquisition mode 4.1 9.6 i dcin cell-balancing mode cell balancing enabled for four switches, ldo, ref, and osc running; v dcin = v gndu = 6v 70 f a i gndu cell-balancing mode 63 i dcin standy mode no conversions or cell balancing; ldo, ref, and osc running, shdn = 1 55 150 i gndu standby mode 20 130 i dcin shutdown mode shdn = 0 0.25 2 i gndu shutdown mode 0.3 2
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 7 pin configuration pin description top view tssop 9.7mm x 4.4mm MAX11068 35 4 c10 vdd u 36 3 c11 cp- 37 2 c12 cp+ 38 1 + hv dcin 32 7 c7 sda u 33 6 c8 scl u 31 8 c6 alrm u 30 9 c5 n.c. 29 10 c4 gpio2 28 11 c3 gpio1 27 12 c2 gpio0 34 5 c9 gnd u 25 14 co gnd l 24 vaa 15 scl l 23 agnd 16 sda l 22 ref 17 alrm l 21 auxin1 18 20 thrm 19 auxin2 26 13 c1 vdd l shdn pin name function 1 dcin dc power-supply input. dcin supplies the internal 3.4v regulator, which provides low-voltage power to the device. bypass dcin to gnd with a 1 f f capacitor. 2 cp+ charge-pump capacitor plus input for the internal charge pump. connect a 0.1 f f high-voltage capacitor between cp+ and cp-. 3 cp- charge-pump capacitor minus input for the internal charge pump. connect a 0.1 f f high-voltage capacitor between cp+ and cp-. 4 vdd u level-shifted upper i 2 c port digital supply for use in communicating with an upper, neighboring battery module. this is a regulated output voltage from the internal charge pump that is level shifted above the dcin pin voltage level. 5 gnd u level-shifted upper i 2 c port ground. this pin is the reference level and ground return for vdd u and also the supply input for the charge pump. it should be tied to the dcin takeoff point on the battery stack as shown in the application diagrams. 6 scl u level-shifted upper port i 2 c clock line. scl u is the i 2 c clock line communicating with the upper neighboring battery module. this pin swings between vdd u and gnd u . 7 sda u level-shifted upper port i 2 c bidirectional serial data line. sda u is the i 2 c data line communicating with the upper neighboring battery module. this pin swings between vdd u and gnd u .
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 8 pin description (continued) pin name function 8 alrm u upper port alarm input. overvoltage, undervoltage, over/undertemperature, cell mismatch, and communication fault. the alarm signal is laddered. this signal is referenced to vdd u and gnd u . connect this signal to vdd u through a pullup resistor. 9 n.c. not internally connected/test i/o. leave open; do not connect any external circuit to this pin. 10 gpio2 general-purpose i/o 2. this pin swings between vdd l and gnd l . 11 gpio1 general-purpose i/o 1. this pin swings between vdd l and gnd l . 12 gpio0 general-purpose i/o 0. this pin swings between vdd l and gnd l . 13 vdd l lower port i 2 c + 3.4v digital supply input. connect to vaa and decouple to gnd l with a 0.47 f f capacitor. 14 gnd l lower port i 2 c common or ground. a star ground connection to agnd is recommended. 15 scl l lower port i 2 c clock. scl l is the i 2 c clock line communicating with the lower neighboring battery module. this pin swings between vdd l and gnd l . 16 sda l lower port i 2 c data i/o. sda l is the i 2 c serial data line communicating with the lower neighboring battery module. this pin swings between vdd l and gnd l . 17 alrm l lower port alarm output. overvoltage, undervoltage, over/undertemperature, cell mismatch, and communication faults. the alarm signal is laddered and driven from the highest module down to the lowest. the alarm output is nominally a clocked heartbeat signal that provides a 16khz clock when no alarm is present and is held at logic-high during an alarm. this signal swings between vdd l and gnd l . 18 shdn active-low shutdown/input. this pin completely shuts down the MAX11068 internal regulators and oscillators when the pin is less than +0.6v as referenced to agnd. the i 2 c bus is nonresponsive when shutdown is asserted. shdn for the first pack should be driven by the host controller through the recommended interface circuit. shdn for laddered modules should be tied to the lower neighboring battery module through the recommended interface circuit. the shutdown pin is 60v tolerant for connection directly to the top of the battery stack. 19 auxin2 auxiliary analog input 2. a low-voltage analog input pin with a full-scale range of agnd to vaa that can be used for monitoring an external ntc or general-purpose measurements. this channel uses the vaa voltage as the reference voltage for the adc conversion. when used with the thrm pin and a resistor-divider, ratiometric measurements can be made. 20 thrm external thermistor bias output. this is a switched connection for supplying a bias voltage from the internal +3.4v regulator (vaa) to an external ntc device for measuring the temperature of the battery module. this pin can supply up to 2ma from the vaa regulator. 21 auxin1 auxiliary analog input 1. a low-voltage analog input pin with a full-scale range of agnd to vaa that can be used for monitoring an external ntc or general-purpose measurements. this channel uses the vaa voltage as the reference voltage for the adc conversion. when used with the thrm pin, ratiometric measurements can be made. 22 ref +2.5v voltage reference. bypass ref to agnd with a 1 f f capacitor placed close to the device. 23 agnd analog ground. should be tied to the negative terminal of cell 1. 24 vaa +3.4v analog supply output. connect to vdd l and bypass with a 1.0 f f capacitor to agnd. 25 c0 cell 1 minus connection. bypass to agnd with a 1.0 f f capacitor. 26 c1 cell 2 minus connection and cell 1 plus connection 27 c2 cell 3 minus connection and cell 2 plus connection 28 c3 cell 4 minus connection and cell 3 plus connection 29 c4 cell 5 minus connection and cell 4 plus connection
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 9 pin description (continued) figure 1. functional diagram pin name function 30 c5 cell 6 minus connection and cell 5 plus connection 31 c6 cell 7 minus connection and cell 6 plus connection 32 c7 cell 8 minus connection and cell 7 plus connection 33 c8 cell 9 minus connection and cell 8 plus connection 34 c9 cell 10 minus connection and cell 9 plus connection 35 c10 cell 11 minus connection and cell 10 plus connection 36 c11 cell 12 minus connection and cell 11 plus connection 37 c12 cell 12 plus connection. top of battery module stack. 38 hv high-voltage bias pin. hv is biased through a diode connection to the charge pump. it is used internally to supply the high-voltage mux. connect to dcin through a 3.3 f f capacitor. switch bank sw_sel(26:0) agnd dis_sel(11:0) hv dcin vaa +3.4v por +6v to 72v c10 c11 c12 thrm auxin2 auxin1 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 agnd 27 linear regulator gnd l vdd l gnd u gnd u gnd u ref vdd u vdd u gpio0 gpio1 gpio2 precision +2.5v reference 6.0mhz osc 32khz osc control and status i 2 c upper port i 2 c lower port level shift instr am p com +3.4v 12-bit adc alrm l scl l sda l alrm u scl u cp+ cp- sda u shdn +3.4v 12 cell equalization MAX11068
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 10 figure 2. analog front-end block diagram c10 c12 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 auxin2 auxin1 agnd cell- balancing switches high- voltage mu x self- diagnostic 12-bit adc adc in + ref thrm adc in - lv mu x instr am p ref c11
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 11 figure 3. MAX11068 esd diode diagram hv dcin c12 c11 c2 c1 c0 agnd vdd u cp+ alrm u /sda u /scl u esd diodes gnd u cp- vaa ref/thrm shdn vdd l ain0/1 gpio0/1/2 gnd l alrm l /sda l /scl l 4v 4v 4v 80v 9v 9v 9v 9v 4v 80v 80v 6v 80v note: all diodes are rated for esd clamping conditions. they are not intended to accurately clamp dc voltage. all diodes shown have a parasitic pn diode from their cathode to agnd that is omitted for clarity. this parasitic diode has it s anode at agnd. c3 to c10 match other inputs MAX11068
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 12 figure 4. operating circuit diagram for a 12-cell system typical operating circuit diagrams module n-1 cell stack module- (n) module n+1 bus bar module + (n) c10 r11 r10 gnd u gnd u gnd u gnd u c hv 3.3 f, 6v hv c10 c11 c12 dcin vdd u alrm u scl u c dd 1.0 f, 6v 5.6v bat46 r3 dc 150ki r1 dc 150ki c p 0.1 f 100v c ref 1 f r p3 150ki 150i 5.6v 100nf r p2 150ki to shdn hv d hv s1b c3 dc 3.3nf, 630v isolator and control interface scl l alrm l r12 r13 c11 c12 c9 c8 c7 c0 1 f ct3 100pf rt2 10ki 1% rt1 10ki 1% 200ki 1ki 68nf 5.6v d 12 c2 dc 3.3nf, 630v sda l sda u cp+ cp- vaa gpio0 scl l sda l alrm l shdn vdd l gnd l c l 0.47 f 6v c a 1 f 6v gnd u c1 dc 3.3nf, 630v c8 c9 r9 c7 r8 r7 c6 c5 c4 c5 c6 r6 c4 r5 r4 c3 c2 c1 c0 thrm auxin2 auxin1 agnd ref c2 c3 r3 c1 r2 r1 gpio1 gpio2 MAX11068 smbus-laddered to upper modules local ground ct2 100pf ct1 100pf t t thermistors 10ki at +25nc cell #10 cell #11 cell #12 cell #9 cell #8 cell #7 cell #6 cell #5 cell #4 cell #3 cell #2 cell #1 module n+1 cell stack module- (n+1) bus bar fuse a kelvin connection is optional for the dcin takeoff in high-current applications. see the noise tolerance section for details. gnd u module n+1 gnd reference c dcin 1.0 f 80v smcj70 22i 22i 100ki d dcin
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 13 figure 5. simplified operating circuit diagram for an 8-cell system module- (n) module + (n) hv c10 c11 c12 dcin vdd u alrm u scl u c9 c8 c7 c0 1 f cp+ cp- vaa gnd l scl l sda l sda u alrm l vdd l gnd u c8 r9 c7 r8 r7 c6 c5 c4 c5 c6 r6 c4 r5 r4 c3 c2 c1 c0 thrm auxin2 auxin1 agnd ref c2 c3 r3 c1 r2 r1 MAX11068 cell 7 cell 6 cell 5 cell 4 cell 3 cell 2 cell 1 d hv gpio0 gpio1 gpio2 shdn cell 8
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 14 detailed description the MAX11068 has two auxiliary analog inputs that can be used to measure external resistance temperature detector (rtd) components. a negative temperature coefficient (ntc) rtd can be configured with the auxin1 or auxin2 analog inputs to accurately monitor module or battery-cell temperature. an internal tem - perature monitor on the die is used to detect thermal overload and disables the MAX11068 cell-balancing switches and linear regulator should the +145 n c thermal limit be exceeded. the MAX11068 has 12 built-in cell-balancing/discharge switches that can support up to 200ma cell discharge currents. the MAX11068 package can support up to 1.2w of power dissipation, which limits the number of balancing/discharge switches that can be enabled when using a 200ma set current to three nonconsecutive cells at no more than +75 n c ambient temperature. with a 110ma cell set current, all 12 internal cell switches can be enabled at the same time. the balancing switches can also be used to detect an open circuit on any of the cell sense wire connections. the MAX11068 contains a 25ppm/ n c precision band - gap reference and an internal regulator that creates the supply for the analog front end and the interchip, level- shifted, communication bus. the regulator can operate from a 6.0v to 72v supply input. the external shutdown pin can be used to reset the MAX11068. the MAX11068 incorporates an i 2 c physical interface for interchip communication and control. the i 2 c bus system is designed to allow smbus laddering of up to 31 devices without the need for any interchip isolation. these bidirectional serial buses can withstand large differences in interchip grounds and system noise. the built-in level-shifting and predefined command protocol provide a low-cost, flexible, and reliable communication bus. command-up forwarding relays communication along the bus from chip to chip for fast response. a 1 f s delay is incurred in relaying command messages, bounding the maximum delay in response to a com - mand to 1 f s multiplied by the number of chips used in the stack minus 1. for a 31-chip stack, a maximum 30 f s delay is incurred before the top module responds. this means that up to 372 cells can be measured with an elapsed measurement time from start to finish of 137 f s. for a 16-chip stack, a 15 f s delay is incurred. this allows measurement of up to 192 cells with an elapsed mea - surement time from start to finish of 122 f s. the MAX11068 incorporates an internal oscillator that generates a 6.0mhz system clock with q 3.0% accuracy. architectural overview the MAX11068 is a complete data-acquisition system on a chip designed for rugged, high-voltage measurement applications. it can measure up to 12 channels of volt - ages from batteries or supercaps with a high-accuracy, high-speed sar adc. two auxiliary input channels may be configured for general-purpose measurements or as specialized temperature conversion inputs when used with rtd devices. simple, yet fast and powerful digital command and control is implemented through unique, high-performance, level-shifted i 2 c communica - tion ports. this allows smbus laddering the communica - tion and control bus on up to 31 battery modules using the MAX11068.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 15 battery pack architectures battery packs are designed in a modular fashion to allow for multiple configurations, and fast and flexible assem - bly. this reduces cost by streamlining the build or repair process. the definition of a battery pack is a system comprising one or more battery modules connected in either a series or matrix configuration to create a high- voltage power source. transportation or high-power battery-backup-system applications typically use many series-connected battery modules to generate voltages of up to several hundred volts. this voltage can then be inverted and transformed to levels sui t able for the given load. a battery module is a series of cells configured as a subsystem that can be combined with other modules to build a high-voltage pack. for the MAX11068, the minimum cell count per module is limited by the 6.0v input requirement of the regulator, while the maximum cell count is 12. the 6.0v minimum requirement usually limits configurations to at least two lithium-ion (li+), six nimh, or six supercap cells per module. figure 6 is the module system with redundant fault-detection applica - tion schematic. battery packs used in transportation applications may be composed of various battery technologies (nimh, li+, supercap, or lead acid) and typically include an electronic battery-management system (bms), envi - ronment control, and several safety features. figure 7 shows the electric vehicle system (evs). in hybrid electric vehicles (hevs), plug-in hybrid electric vehicles (phevs), electric vehicles (evs), or fuel-cell vehicles (fcvs), cell counts can range from 36 cells to 200 cells using li+ batteries and up to as high as 200 to 500 cells using nimh batteries. supercaps are typically used in fast-charge holding applications such as regen - erative braking energy storage. there are two fundamental battery-pack management architectures that can be realized with the MAX11068: u distributed module communication u smbus-laddered module communication a distributed module system deploys a point-to-point connection from each battery module back to a master microcontroller in the bms. because the battery mod - ules operate from the high-voltage battery stack, galvan - ic isolation must be used when communicating with the master microcontroller. figure 8 shows the distributed communication battery pack. an smbus-laddered module system deploys a serial communication bus that travels through each battery module and is then accessed at one entry point in the system by the master microcontroller in the bms. the smbus ladder method reduces cost and requires at most a single galvanic isolator between the high-voltage batteries and the main power net. galvanic isolation may not be required in certain low-voltage applications. see figure 9.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 16 figure 6. battery module system with redundant fault-detection application schematic module n+1 cell stack module - (n+1) module + (n) module- (n) cell 12 cell 11 cell 10 cell 9 cell 8 cell 7 cell 6 cell 5 cell 4 cell 3 cell 2 cell 1 bus bar bus bar module n+1 gnd referecnce cd vaa hv c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 thrm auxin2 auxin1 agnd dcin vdd u alrm u scl u sda u gnd u cp+ cp- vaa vdd l scl l sda l alrm l gnd l gpio0 gpio1 gpio2 ref agnd c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 dcin hv c24 r26 r25 r24 r23 r22 r21 r20 r19 r18 r17 r16 r15 c23 c22 c21 c20 c19 c18 c17 c16 c15 c14 c13 shdn MAX11068 max11080/max11081 c12 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 local ground battery connector module n-1 cell stack note: refer to each device?s application reference circuits for components and values not shown on this simplified system-level schematic . isolator and control interface for first module shdn alrm l 11068 alrm l 11068 scl l sda l gpio alrm u vdd u gnd u cp+ cp- 3 2 1 0 ovsel 2 1 0 uvsel topsel alrm l shdn
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 17 figure 8. distributed communication battery pack figure 7. electric vehicle system inverter+ inverter+ battery module slave monitor and control isolator temp battery module slave monitor and control isolator temp battery module slave monitor and control isolator battery module slave monitor and control isolator pack switches inverter- pack switches master controller vehicle 12v pwr vehicle gnd comm bus fault check current sense temp temp vehicle control system (vcs) inverter main switch conn conn battery pack motor drive+ motor drive- vehicle 12v pwr vehicle gnd comm bus comm bus comm bus battery management system (bms) cell pack (li 40?90 cells) (nimh 100?300 cells)
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 18 figure 9. smbus-laddered battery module communication inverter+ inverter+ battery module slave monitor and control stub battery module slave monitor and control battery module slave monitor and control i shunt pack v/i measurement pack switches inverter- pack switches master controller vehicle 12v pwr vehicle gnd r pack1 r pack2 comm bus fault check iso temp temp temp
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 19 battery-management system (bms) the bms in an electric vehicle monitors cell voltage, pack current, and temperature. the bms is composed of two components. the first is the master controller of the system that handles all communication with the vcs. it also handles state of charge, state of health, and fault- management features of the battery pack. the second component is the data-monitoring function, which gath - ers information on the conditions of the battery cells, takes voltage/current/temperature measurements, and signals safety faults. the slave monitor controller (slc) is directly connected to the series stack battery cells. the slc measures cell voltages and module temperature, as well as controls the cell-charge equalization feature that keeps all cells balanced to equal states of charge. the slcs are also designed to report alarm conditions such as cell over - voltage or undervoltage, sense wire-open circuits, and in the case of li+ battery chemistries, overtemperature situations. the slcs are managed by the master control - ler. the master controller orchestrates all data acquisi - tion and cell-balancing tasks in the slaves. the master also measures the pack current coincident to voltage measurements so that state of health of the battery pack can be determined. measurement of the current through the pack is made across a low-value shunt resistor or hall sensor. cell inputs c0Cc12 the MAX11068 contains 13 analog inputs that are used for the differential measurement of as many as 12 bat - tery cells. each differential cell input can withstand up to 9.0v and can be included in the measurement cycle through the cell-channel scan-enable bits of the cellen register (address 0x09). cell inputs are measured differ - entially and level shifted down to the internal adc by a high-voltage mux and adc preamp. the common-mode range of the cell inputs from c2 to c12 is 0.5v to v hv - 2.9v. common-mode range for c1 is limited to 7.0v and for c0 it is limited to voltages within 50mv of agnd for proper measurements. the absolute maximum differen - tial input between two inputs must always be observed, which is 9.0v. the application circuit shows rc filtering for each cell input. the values of the resistors are chosen in large part depending on the cell-balancing functionality that is desired. the capacitor value chosen complements the resistor values to provide lowpass filtering of the adc measurement. capacitor values should be in the 100nf to 1 f f range. the first cell position between c1 and c0 must be popu - lated for all applications with a voltage of at least 500mv. this ensures accurate measurements for all other cell positions as defined by the adc specifications. when implementing a module configuration with fewer than 12 cells, the first cell position should always be used, and then other cell positions may be used in any configura - tion. any unused cell positions should have their inputs shorted together. random connection of cells or the high-voltage supplies during module configuration does not cause adverse effects. measurement scanning when a cell is enabled for acquisition by setting the associated scan-enable bits in the cellen register (address 0x09), the appropriate cell differential input is scheduled for conversion. the auxiliary input channels along with the self-diagnostic channel may be similarly enabled using their enable bits in the adccfg register (address 0x08). conversion begins with the setting of the scan bit in the scanctrl register. the setting of the scan bit may be accomplished using either the writeall command or the writedevice command, depending on whether all devices are expected to perform the conversion. if the adc is still busy from a previous acquisition scan, the scan command is ignored. each module in a sys - tem begins the measurement scan cycle as soon as it receives the scan signal. the measurement order of the inputs during a cycle is as follows: 1) all enabled cell inputs phase 1, descending order (12C1) 2) all enabled cell inputs phase 2, descending order (12C1) 3) self-diagnostic measurement phase 1, if enabled 4) self-diagnostic measurement phase 2, if enabled 5) all enabled auxiliary inputs phase 1, ascending order (auxin1, auxin2) the complete acquisition of the cell voltages takes place in two phases, which is shown in figure 10. the first phase is the raw cell-voltage acquisition. in this stage, the adc scans through all the enabled cell input chan - nels, starting with the highest cell.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 20 figure 10. cell-scanning timing the second stage in the channel-scanning process is the correction phase, where the front-end amplifier chops out any offset and reference-induced errors. this provides a high-accuracy cell voltage result. in this stage, the channels are converted in the same highest to lowest order as the initial measurement. the module- to-module sampling points differ by the communication forwarding delay from the i 2 c command. with the mea - surements from the two scan phases complete, the adc data is then offset corrected, averaged, and updated in the cell data registers. after the cell-measurement cycle is complete, the self- diagnostic channel is acquired when enabled. it is a two-phase measurement as described for the cell-volt - age inputs, with each phase measured one immediately after the other. finally, the enabled auxiliary inputs are measured. they are measured in a single conversion, with results reported in the ain1 and ain2 registers. the auxiliary channels have a configurable option to increase settling time that is set in the lower byte of the acqcfg register (address 0x0c). the configured extra settling time is implemented just before the conversion for each auxin channel that is enabled for measure - ment. so, when both auxiliary channels are measured, the extra settling time occurs twice. extra settling time is not needed by the MAX11068 adc; it is only for the benefit of the external application circuit. calculating measurement time the first requirement for performing a measurement conversion is setting the scan bit. this can be done by using the writeall or writedevice commands. the write commands require 5 full bytes of data, plus 5 acknowledge bits and the start and stop bits. this totals 47 bits of data sent by the host, which would require 235 f s at a 200khz i 2 c clock rate. the timing of the cell measurements is shown in figure 10. at the start of the measurement cycle, there is a measurement setup time prior to the measurement of the highest cell totaling 11.3 f s. the highest cell measured requires a sampling time of 5.67 f s, while the rest of the inputs are sampled at 3.83 f s per channel. when all 12 channels are enabled, the 12-cell voltages for one phase are acquired in 47.8 f s, not including the measurement setup time. the total acquisition time for 12 cells is 106.9 f s cell sample time t 0 + 16.97s t 0 + 59.1s t 0 + 106.9s t 0 - strobe point top cell sampling time = 5.67s other cells sampling time = 3.83s mux powerup - 6.3s top cell setup - 5s b9+ b10+ b11+ b12+ b11- b12- b8+ b7+ b6+ b5+ b4+ b3+ b2+ b1+ b9- b10- b8- b7- b6- b5- b4- b3- b2- b1- top cell measure - 5.67s
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 21 for every module in the battery pack, a 1 f s communi - cation delay is incurred while the scan command is for - warded up the smbus ladder. therefore, the difference in the scan completion time from the first module to the last module in a chain is no more than 1 f s x (no. of mod - ules in the chain - 1) as shown in figure 11. taking the module conversion time and combining it with the communication delay, the overall sampling window of the system can be calculated: sampling window = 11.3 f s + (5.67 f s + (no. of cells enabled per module -1) x 3.83 f s) x 2 phases + ((no. of modules per pack - 1) x 1 f s per module) so, for a battery pack that uses 12 cells per module and a system with four modules (total cell count = 48), the sampling window would be: sampling window = 11.3 + (5.67 + 11 x 3.83 f s) x 2 + ((4 modules -1) x 1 f s) sampling window = (106.9 f s) + (3 f s) = 109.9 f s thus, from the time the first device receives the scan command until the last device completes its measure - ment conversion, 109.9 f s elapse. the final aspect of the measurement conversion is the retrieval of data from all devices. a readall command is the only way to transfer data from each device. since up to 12 cells are measured, the readall command must be performed for each cell whose data must be transferred. for each readall command, there are 5 total bytes of overhead. these include the broadcast address byte, the command code byte (register address to be read), the i 2 c address byte, the data check byte, and the packet-error check (pec) byte. each of these bytes has an acknowledge bit associated with it. the register data from each device consists of 2 more bytes plus 2 acknowledge bits. finally, the overall data stream consists of 3 more bits, start, stop, and repeated start. thus, for a read of a single register from all modules, the total bit count is: readall bit count = 3 + 5 x 8 + 5 + no. of modules x (2 x 8 + 2) = 120 figure 11. measurement scan timing for a multimodule system scan at t 0 command forwarding delay = 1s module n t all modules = (no. of modules x 1s) + 107s module 5 t all modules module 1 module 2 module 3 module 4
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 22 figure 12. programmable overvoltage and undervoltage thresholds diagram for the example with four modules and 12 cells per mod - ule, the total readall bit count would be 120 bits per cell or 1440 bits for all 12 cells. at a 200khz i 2 c clock rate, the total time for this command would be 7.2ms. the overall time from the host issuing the scan command to the last data being received by the host includes the write time for the scan command, the measurement con - version time, and the time for the readall command. for this 12-cell, four-module, 200khz i 2 c example the total is: 235 f s + 106.9 f s + 7200 f s = 7.542ms effectively, the number of complete 12-cell measure - ments that can be acquired and transferred back to the host is no more than 132 per second. if the data from every measurement is not transferred back to the host, then significantly more measurements may be taken per second. enabling the auxiliary or self-diagnostic chan - nels would decrease the effective sampling rate. cell overvoltage and undervoltage the MAX11068 incorporates cell-voltage monitoring with alert and alarm capability for diagnosing system status. after each adc voltage conversion, cell-voltage data is stored in the cell-data registers. only data registers for cell positions that were enabled for the previous mea - surement scan are updated. cells that were not in the measurement scan retain their previous value. the data is also analyzed for the minimum, maximum, and total cell-voltage values, as well as for overvoltage and under - voltage conditions. the maximum and minimum cell voltage readings are stored in the upper 12 bits of the maxcell and mincell registers (addresses 0x11 and 0x12). also stored in the lowest 4 bits of those registers is the cell number corre - sponding to the data reading. where multiple cells had the same minimum or maximum reading, the highest cell position having that reading is reported. the sum total value of cell data whose measurements were enabled in the last scan is stored in the total register (address 0x10) as a 16-bit value. where a conversion is initiated with no enabled cell inputs, the mincell, maxcell, and total registers retain their current value. cell-voltage data is also compared against programma - ble cell overvoltage and undervoltage thresholds. these thresholds are configured through the overvoltage and undervoltage set and clear threshold registers (address - es 0x18 to 0x1b). alerts, when enabled, are triggered as cell voltage data passes through the set threshold level. conversely, alerts are cleared when the cell volt - age data passes through the clear threshold level. if the voltage data is equal to a relevant cell threshold limit, no action occurs. therefore, if the set threshold level is placed at full scale for the overvoltage alert or at zero scale for the undervoltage alert, the alert cannot trigger and is effectively disabled. the two thresholds, set and clear, for each condition allow for digital hysteresis to be configured in the alarm trigger. figure 12 is a diagram of the programmable overvoltage and undervoltage thresholds. overvoltage set and clear threshold s por default value (+5.0v) overvoltage set threshold (ovthrset ) undervoltage set and clear threshold s por default value (+0.0v) overvoltage clear threshold (ovthrclr) undervoltage clear threshold (uvthrclr) undervoltage set threshold (uvthrset) overvoltage alert set v t undervoltage alert cleared overvoltage alert cleared undervoltage alert set cell n voltag e
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 23 alerts may be enabled on a per-cell basis. local enable bits oven and uven are found in each cells data reg - ister (addresses 0x20 to 0x2b). these bits are mapped to the equivalent bits of the ovalrten and uvalrten registers (address 0x06 and 0x07). if these bits are enabled for a given cell, the cell reports its overvolt - age or undervoltage alert status to the appropriate alert status register (addresses 0x04 and 0x05). the alert status is updated whenever new cell measurement data is available. if either of these two alerts are active for a cell, that cells corresponding alrtcell register bit (address 0x03) is also set. all voltage alert status regis - ter bits are zero when no alert is present and cannot be manually cleared. to clear an active voltage alert, the alert condition must be removed and a new measure - ment must be taken or the alert must be disabled. the global alrtov and alrtuv bits in the status reg - ister (address 0x02) are set when any cell has an active alert as indicated in the alrtovcell or alrtuvcell registers. all alerts are automatically cleared following the next conversion cycle when the alert conditions no longer exist. using this tiered approach to alert report - ing, the system host may quickly establish whether any voltage alerts are active and, if necessary, determine exactly which cells and conditions are affected. the mismatch alert is another status condition flag that can be enabled to signal when the minimum and max - imum cell voltages are mismatched by more than a programmed amount. the alert is enabled by setting the alrmmmtchen bit of the adccfg register. the msmtch register (address 0x1c) sets the 12-bit thresh - old for the mismatch alert, alrtmsmtch. whenever maxcell - mincell > msmtch, the alrtmsmtch bit in the status register is set. the alert bit is cleared when new conversion data does not violate the threshold condition. cell balancing the basic cell-balancing circuit for the MAX11068 incor - porates the use of internal 6 i switches and external resistors to set an equalization discharge current that is dependent on cell voltage. figure 13 shows the basic circuit used with the internal cell-balancing switches. the following limitations must be taken into account when using the basic circuit: u maximum power dissipation allowed in the package u measurement during cell balancing u current variation due to enabled adjacent cell switches u protection from open-circuit faults in the battery stack destroying the MAX11068 managing power the MAX11068 contains 12 independently controlled switches that have a typical on-resistance (r sw ) of 6 i with q 50% variation due to process and tempera - ture. the package used for the MAX11068 is a 38-pin tssop package with a maximum power limit (p max ) of 1.2698w and a junction-to-ambient thermal resistance of +63 n c/w for a multilayer board. these parameters are the fundamental limits for the package-power dissipa - tion and require careful consideration when using the internal cell-balancing switches since the switches are the dominant power consumers in the device. for oper - ating margin, it is recommended targeting a maximum power level that is 70% of the absolute maximum rating. the maximum die junction temperature that is allowed is +150 n c. a built-in overtemperature protection circuit protects the die at a junction temperature of +145 n c, however. when the overtemperature limit is reached, the internal cell-balancing switches are disabled. the asso - ciated cell-balancing switch enable bits in the balancing switch control register (balcfg at address 0x0b) are not directly affected, but the resulting power down of the linear regulator may cause a power-on reset (por) condition, which would reset the balcfg register and deassert all switch-enable bits. the maximum number of cell-balancing switches that can be enabled at any one time is calculated as shown below: maximum number of enabled switches = (0.7 x p max )/ ((i balance ) 2 x r sw ) where: i balance = v cell /((2 x r eq ) + r sw ) p max = 1.2698w r sw = 6 i , typical table 1 lists example results obtained based on the formula above. figure 13. cell-balancing switch network f1 f2 r eq r eq cell balancing c f c n+1 r sw c n MAX11068
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 24 based on the calculations, up to two nonadjacent inter - nal cell-balancing enabled switches are supported for a discharge current of 250ma per cell. at least a 0.5w rated r eq is required to handle the 250ma nominal cur - rent and its worst-case range of 210ma to 308ma. measurements during cell balancing when using the internal cell-balancing switches, the measured voltage on the c n to c n+1 input is reduced by the external r eq resistors. for accurate cell-voltage measurements, disabling the internal cell-balancing switch is required. these switches are not disabled automatically during a conversion. after the internal cell- balancing switch is disabled, allow the input voltage to settle for a time period (t settle ), which is determined by external components c f and r eq , before performing a cell-measurement sequence: t settle = 10 x r eq x c f current variation due to enabled adjacent cell switches if adjacent internal cell-balancing switches are enabled, the discharge current would be much higher than the desired value. figure 14 shows the adjacent enabled bal - ancing switches and the resulting discharge current (i dis ): i dis = (v cell5 + v cell4 )/(2 x r eq + (2 x r sw )) from the i dis equation, it is apparent that the discharge current grows with the number of adjacent active internal cell-balancing switches. this is because the cell voltages across the active switches and the r sw values are grow - ing proportionally, but r eq remains fixed no matter how many adjacent switches are active. consequently, the numerator of the discharge current equation grows faster than the denominator with increasing active switch count and discharge current increases. unless this is accounted for by the host controller, the package power-dissipation limit could be reached unexpectedly and damage to the device could occur. to avoid this possibility, it is recom - mended to use an odd or even switch-enable control scheme for the internal cell-balancing switches. table 1. cell-balancing circuit parameter variation note 1: t settle is five time constants after the cell-balancing switch is disabled. note 2: nonadjacent cell switches. figure 14. discharge current path for adjacent enabled balancing switches cell name min typ max units high-side accuracy (%) low-side accuracy (%) r eq 5.1 5.2 5.3 i 1 -1 c f 9 10 11 f f 10 -10 r sw 3 6 9 i 50 -50 v cell 4.1 4.1 4.1 v na na i balance 308 250 210 ma 16 -23 filter 3db 3435 3061 2755 hz t settle at c n+1 (note 1) 0.6 0.8 1.1 ms max no. of switches on (note 2) 3 2 2 switches f1 r eq r eq r eq f2 f3 c f c 5 c 4 c 3 r sw v cell5 c f v cell4 i dis r sw
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 25 protection from open-cell faults there are two methods of protecting the MAX11068 from damage due to an open circuit occurring in a series bat - tery stack: u an external fuse placed in series with the internal or external cell-balancing circuit protects against high- voltage damage. if an external mosfet is used, as in the circuits described below, the high-value resistors protect the MAX11068 inputs from damage during an open-cell condition. u detection of any cell dropping below ground or vio - lating the undervoltage condition indicates an open- cell condition and that the electric motor is supplying voltage to the battery pack. to prevent damage, the switches connecting the battery stack to the load should be opened immediately after the undervolt - age flag asserts. external cell-balancing circuit the MAX11068 allows external cell balancing to be implemented by using the internal switch to control the bias network of an external transistor. when the internal switch is closed, the external resistors r bias1 and r bias2 form the bias network used to turn on the external bipolar or mosfet transistor. the discharge current of the battery is set with resistor r eq . the follow - ing sections describe different external cell-balancing circuits in more detail. figure 15 is a simplified external cell-balancing circuit. external cell balancing with a bipolar transistor when using an external bipolar transistor, it is recom - mended to select one with current gain (h fe ) greater than 100 and a v ce voltage that is rated to the overall pack voltage to avoid damage should an open circuit occur in the cell stack. if a bipolar transistor with a lower voltage rating is chosen, then series fuses are recom - mended to protect the circuit. typical component values for a 500ma cell discharge current are (see figure 16): r bias = 80 i r eq = 8 i bipolar transistor = mjd50 (for high-voltage tolerance) or mmbta05 (for low cost and low volt - age) external cell balancing with a mosfet when using an external mosfet, it is recommended to select one with low v gs (typically around 1.2v) and a v ds voltage that is rated to the overall pack voltage to avoid damage should an open circuit occur in the cell stack. if a mosfet with lower voltage rating is chosen, series fuses are recommended to protect the circuit. see figure 17. typical component values for a 500ma cell discharge current are: r bias1 = 10k i r gate = 470 r eq = 8 i mosfet = ntk3134n (for low cost, low voltage) external cell balancing with a mosfet switch results in little to no cell-to-cell interaction. the r bias resistor value combined with the input bias current requirements does add a small measurement error of less than 1mv worst case for a 10k r bias value. the recommended ntk3134n fets have built-in gate- protection diodes. during hot-plug conditions, inrush current flows through r bias and internal esd diodes to charge the hv to dcin capacitor. this current creates a negative v gs voltage that can turn on the gate-protec - tion diodes and possibly damage the transistor devices. a series resistor of no less than 470 should be placed in series with the transistor gate to make the circuit robust under cell hot-plug conditions. for other transis - tors, the negative v gs condition must be controlled so that it is tolerated by the devices. figure 15. simplified external cell-balancing circuit figure 16. external cell-balancing circuit with a bipolar transistor r eq r bias1 r bias2 r sw f1 f2 r bias1 r bias2 r eq c f c n+1 c n r gate d clamp
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 26 cell-balancing watchdog timeout the MAX11068 implements a watchdog-style timeout feature for the cell-balancing switch enables. a count - down timer is clocked at a rate specified by a predivider. the full range of possible timeout values is 0 to 240s. in the event of unexepected communication loss, the cell- balancing switches are safely disabled after the timer reaches zero. the timeout disables the cell switches with a signal separate from those of the balcfg register. thus, the balcfg register value is not affected by the cell-balancing timeout condition. figure 18 shows the timeout circuit block diagram. the cell-balancing timeout feature consists of a 4-bit countdown timer and a predivider with 2 control bits for range selection. both the timer and predivider are programmed through the msb of the acqcfg register (address 0x0c). the predivider sets the effective lsb time period of the timer. the user-selectable choices are shown in table 2. the cell-balancing timer counts down at the rate speci - fied by the predivider, cbpdiv[1:0]. the timer starts when the cbpdiv control bits are written to one of the three enabled settings. the cbtimer[3:0] bits are read - able and writeable and return the value of the timer as sampled during the acknowledge bit time of the register address bit of the readall command. the host appli - cation should periodically rewrite the acqcff register value to ensure that this value does not unintentionally go to zero. the timeout can be set to any value within the timer range specified by the cbpdiv setting by choos - ing the appropriate value to write to the cbtimer byte. if the value of the cbtimer does reach zero, the cell- balancing switches are disabled until the timer is either disabled or is refreshed by writing a nonzero value. if the timer is enabled by writing the cbpdiv bits while the cbtimer value is at 00h, the cell-balancing switches are not disabled. the first transition of cbtimer to the 00h value when the timer is enabled disables the bal - ancing switches. internal regulator and charge pump the MAX11068 incorporates a linear regulator for gen - erating the internal supply from dcin. the regulator can accept a supply voltage on the dcin pin from 6.0v to +70v, which it regulates to 3.3v to run the voltage- measurement system, control logic, and low-side com - munication interface. the regulator is designed to sup - ply up to 10ma of current. when the shdn pin and die temperature protection are not active and a sufficient voltage is applied to dcin, the output of the regulator becomes active. the regulator is paired with a power- on por circuit that senses its output voltage and holds the MAX11068 in a reset state until the internal supply has reached a sustainable threshold of +3.0v ( q 5%). the internal comparator has built-in hysteresis that can handle noise on the supply line, as well as slow sup - ply ramps of 1v/s. since secondary metal batteries are never fully discharged to 0v, the MAX11068 is designed figure 17. external cell-balancing circuit with a mosfet transistor figure 18. cell-balancing timer block diagram table 2. cell-balancing predivider settings f1 f2 r bias1 r bias2 r eq c f c n+1 c n r gate d clamp cbtimer zero flag cell- balancing switch [n] enable cbtimer enable balcfg [bit n] cbpdiv 32.768khz bit 3 cbpdiv1 cbpdiv0 bit 2 bit 1 bit 0 cbpdiv[1:0] setting timer lsb period (s) timer range (min to max) (s) 00 timer disabled timer disabled 01 1 1 to 15 10 4 4 to 60 11 16 16 to 240
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 27 for a hot-swap insertion of the battery cells. once the por threshold is reached, the internal reset signal disables. a status bit, rststat in the status register (address 0x02), is set when power is restored to the digital logic following a reset event to denote that a reset has occurred. it should be checked and cleared by the system controller so that any future reset condition can be resolved. figure 19 is the internal low-dropout regula - tor block diagram. the MAX11068 power-up sequence is shown in figure 20. starting with no dc power applied, the device waits for a power source and then waits until the shdn signal is deactivated. if the internal die temperature limit is not exceeded, the regulator is enabled. the regulator begins to regulate the dcin input voltage down to 3.3v. after vaa has reached the rising por threshold, the internal por signal is deasserted and the various sec - tions of the device begin to initialize, starting with the 32khz oscillator. an additional 280 f s after the oscillator becomes active, the digital logic becomes active and the charge pump begins operating. the charge pump reaches full regulation in approximately 3ms depending on the external circuit components used, at which time the MAX11068 is ready for operation. when the charge pump achieves regulation of 3.4v between vdd u and gnd u , it switches to a standby mode until the voltage drops by 20mv to minimize operation during light load - ing. the specification accuracies and full operation of the MAX11068 are not guaranteed until a minimum of 6.0v is applied to the dcin pin. the regulator has built-in short-circuit protection in case of a fault condition. figure 21 shows asynchronous regulator disable events and figure 22 shows the por event sequence. the regulator incorporates a thermal-shutdown feature. if the MAX11068 die temperature rises above +145 n c, the device shuts down by disabling the internal regula - tor. the cell-balancing switches are also independently disabled in case an external power source maintains power to the digital logic through vdd l . the settings of the balcfg register are not directly altered by the overtemperature condition, but unless vdd l is supplied from a source other than vaa, the por event caused by the regulator shutting down resets all registers to their default values. after a thermal shutdown event, the die temperature must cool 15 n c below the shutdown temperature before the device reenables the regulator. figure 23 shows a more detailed view of the charge pump and the supply and ground references for the regulator and charge pump. the charge pump is driven by a 4ma current source, i pump . figure 19. internal low-dropout regulator block diagram linear regulator regulator enable +6.0v to +72v internal +3.4v power-on reset comparator vaa dcin shdn gnd u vdd u por threshold +3.0v 5% +3.4v to gnd u - + - + die overtemp detect bandgap reference charge pump charge-pump enable 20mv hysteresis internal por
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 28 figure 20. power-up sequence figure 21. asynchronous regulator disable events regulator disabled por cleared 32khz oscillator enabled 280fs delay charge pump an d digital logi c enabled rststat bit set 3ms delay charge pump settled MAX11068 fully functiona l voltage applied to dcin check die temperature die temp > +145c shdn active regulator enabled check vaa vaa < v por_rising check shdn die temp > +145nc shdn active regulator disabled
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 29 figure 22. power-on-reset event sequence figure 23. detailed view of supply and ground connections 32khz i pump n p high-voltage mux ldo charge- pump control hv vdd u cp+ gnd u cp- dcin vaa vdd l scl l sda l alrm l gnd l agnd upper i 2 c interface analog adc lower i 2 c interface c12 alrm u sda u scl u c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c0 c1 shdn control MAX11068 por inactive por active oscillator, charge pump, digital logic disabled check vaa vaa > v por_rising vaa < v por_falling
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 30 figure 24. dcin overvoltage protection and decoupling circuit dcin pin application circuit the dcin pin is the input to the linear regulator. for maximum performance, it should be protected from any overvoltage conditions and also properly decoupled for peak transient current demands of the linear regulator. figure 24 shows a recommended protection and decou - pling circuit. since the linear regulator must supply load peaks to the adc and other low-voltage circuitry, the dcin pin must be properly decoupled to ensure proper performance. a 1 f f high-voltage, high-quality ceramic capacitor should be used at the pin. the series diode, d1, prevents dis - charge of the dcin decoupling capacitor during nega - tive transients. during regenerative braking conditions, a surge voltage is produced by the electric motor. the MAX11068 is designed to tolerate an absolute maximum of 80v under this condition. the MAX11068 should be protected against higher voltages with an external voltage sup - pressor such as the smcj70a. this protection circuit also helps to reduce power spikes that can occur during the insertion of the battery cells. precision internal- voltage reference the MAX11068 incorporates a precision, low-temper - ature coefficient, internal-voltage reference. the refer - ence is used in the MAX11068 to set the full-scale range of the adc. the ref pin is not designed to drive any external loads, and should be configured with an exter - nal 1 f f capacitor to agnd only. this capacitor should be mounted as close as possible to the ref pin. auxiliary analog inputs and external thermistor supply pin the auxiliary analog inputs (1 and 2) can be used to monitor analog voltages with a full-scale range of 0 to thrm (3.4v). the full-scale range of the adc for the auxiliary channel measurements is the thrm pin voltage referenced to agnd. the auxin1/2 pins are single-end - ed inputs that are measured against the agnd pin. a scan of the auxin inputs is first configured by enabling conversion of one or both inputs through the ain1en and ain2en bits of the adccfg register (address 0x08). after enabling the channels for measurement, a scan is initiated by setting the scan bit of the scanctrl register to 1. conversions on the enabled auxiliary channels commence after the conversions for the cell input channels are complete. conversion results are available in the ain1 and ain2 registers (addresses 0x40 and 0x41). the auxin1/auxin2 pins can also be used in con - junction with the thermal supply pin (thrm) to monitor external rtd devices. the thrm pin has an internal switch connected to the internal-voltage regulator of the MAX11068. the purpose of the switch is to save power when a measurement of an external temperature-sens - ing device is not needed. during normal operation, the thrm pin is disabled. when the ain1en or ain2en bits of the adccfg register (address 0x08) are enabled and a measurement scan is initiated, a voltage source taken from the internal regulator is connected to the thrm pin. this occurs as soon as the scan signal is received and before any cell or auxiliary channel measurements have taken place. the thrm pin biases the rtd network so that the effect of temperature on the rtd component can be measured as a voltage by the adc. figure 25 is the external temperature-sensor configuration. since the thrm pin is not driving the ain pin application circuit at all times, in some cases it may be necessary to adjust the settling time seen by the ain pins before the measurement is started. a customized delay can be pro - grammed through the acqcfg register (address 0x0c) aincfg bits to allow the application circuit extra time to settle before taking the adc measurement for the ain pins. the aincfg bits have a resolution of 5.3 f s, which is also the minimum delay value. the maximum delay is 339.2 f s. the programmed delay from the acqcfg register is implemented just before the measurement is taken on an ain channel. if both channels are enabled for measurement, the delay is implemented twice, once just before each channels measurement. top of cell stack r limit 22i note: see the application circuit diagram for the proper kelvin-connection location. to dcin input to gnd u input 100ki smcj70 c dcin 1ff 80v 22i
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 31 care must be taken when selecting the aincfg settling time value if the load on vdd u is more than that speci - fied by the typical application circuit diagrams. during the entire measurement cycle, the charge pump is dis - abled and the vdd u voltage is supported only by the decoupling capacitor stored charge. if an extra load is placed on vdd u and the aincfg value is set too high, the vdd u voltage may decay below levels that support error-free communication. the recommended rtd network is a 10k i resistor in series with a 10k i ntc thermistor. for an ntc thermistor, the resistance increases as the temperature decreases. they are typically specified by a resistance at +25 n c (r 0 ) and also by a factor called beta. to first order, the resistance at a temperature t in kelvin can be found from: 0 ( (1/t 1/t )) 0 r r e ? = a typical value of beta for an ntc thermistor might be approximately 3400. by determining the resistance of the thermistor at the desired temperature thresholds, the voltage at the auxiliary inputs can be calculated. this voltage can then be converted to a digital threshold value using the adc step size of 0.83mv/lsb, whose derivation follows below. once the adc power-up delay and any cell measurements and the self-diagnostic measurement have completed, the auxiliary channel-acquisition cycle begins. first, auxin1 is measured, if enabled, followed by auxin2, if enabled. each individual voltage reading from the completed acqui - sition is stored in the appropriate ain1 (address 0x40) or ain2 (address 0x41) register. since the adc is 12 bits with a full-scale voltage of 3.4v, each lsb is approxi - mately 0.83mv. overall, a conversion on the auxin1 and/ or auxin2 input completes in 10 f s when only one of the auxiliary inputs are enabled and in 17 f s when both are enabled. when the result is stored, it is compared against the under- and overtemperature thresholds saved in reg - isters 0x1e and 0x1f, respectively. separate alert bits alrtthot and alrttcold in the status register (address 0x02) may be enabled to indi - cate when one of these temperature thresholds has been violated. individual over- and undertemperature enables (hoten and colden) for each of the two auxiliary ana - log channels are found in the ain1 and ain2 data reg - isters. the alert bits are automatically cleared if the alert condition is cleared on subsequent conversions. the overtemperature and undertemperature alarm enable bits alrmoten and alrmuten found in the adccfg register (address 0x08) determine whether alerts result in an alarm. when 1 of these bits is enabled, the respective alert causes an alarm signal to occur on the alrm l pin. figure 25. external temperature-sensor configuration mux adc c aa 1ff vaa thrm conversions in progress from regulator +3.4v internal reference auxin2 auxin1 ct1 100pf rt1 rt2 10ki 1% 10ki 1% ct2 100pf ct3 100pf thermistor 10ki at +25c adc ref t t
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 32 self-diagnostics the MAX11068 incorporates the capability to check the health of its internal voltage reference and regula - tor output. the results are stored in the diag register. conversions are enabled by setting the diagen bit of the adccfg register (address 0x08). they are initiated immediately following the cell conversions. for the self- diagnostic measurement, the adc reference is taken from the internal thrm pin connection. this makes the full-scale range of the self-diagnostic measurement 3.4v. the reference voltage is measured differentially against the internal voltage on c0 through an instrumen - tation amp, the low-voltage mux, and finally the internal adc. the instrumentation amp has a gain of 1/2 that must be taken into account when calculating the expect - ed diagnostic result. the complete block diagram for the self-diagnostic measurement is shown in figure 26. the expected value of the self-diagnostic measurement varies depending on the regulator output voltage, the reference voltage itself, and the accuracy of the adc. when discussing the diag measurement values, the least significant nibble of the diag register is ignored since only the three most significant nibbles contain real data. to first order, the expected value of the self- diagnostic measurement is: ( ) ( ) diag ref c0 0.5 vaa 4096 = ? since the specified regulator voltage can vary by approximately q 10%, the expected result of the self- diagnostic varies proportionally. for typical values of ref = 2.5v and vaa = 3.4v, the nominal diag value for normal operation is 5e1h with a tolerance of q 150 lsbs ( q 0x96). typical devices may vary from this value due to trim differences. table 3 shows typical values and ranges for the diag value for various fault and no-fault conditions. in a typical application, the self-diagnostic measurement should be performed and stored when the system is operated for the first time. by periodically performing a new measurement, the results can be compared against the original value to verify that the system is operating at the expected performance level. as shown in table 2, a change on the order of p 4 lsbs can be expected across the full temperature range. the ref pin also has a special failure-mode effects analysis (fmea) detector to alert when an open-circuit may exist. the alert is the alrtref bit of the fmea register. it detects when the ref pin has an oscillating voltage condition, which is a symptom of an open circuit on the pin. figure 26. block diagram of self-diagnostic mode connections table 3. diag typical values and ranges instr amp g = 1/2 ref lv mux self - diagnostic c0 adc in + 12-bit adc thrm adc in - fault condition diag value (typical) diag value range (typical) variation from initial value (lsb) none 0x5e1 0x54b to 0x677 +4 to -4 c0 is open 0x1da to 0x1dc 0x1da to 0x1dc ref is shorted to agnd 0x292 to 0x293 0x292 to 0x293 ref pin is open or floating 0x3c1 to 0x7ae use alrtref in the fmea register
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 33 noise tolerance high-power batteries are often used in noisy environ - ments subject to high dv/dt supply noise and emi noise. for example, the supply noise of a power inverter driving a high-horsepower motor produces a large square wave at the battery terminals, even though the battery is also a high-power battery. typically, the battery dominates the task of absorbing this noise, since it is impractical to put hundreds of farads at the inverter. supply noise between two modules occurs due to the very large current transients that are often present in high-power battery systems. even very-low-impedance connections of only a few milliohms between the various battery modules and the load can produce substantial voltage noise that would not allow an ac-coupled ground-referenced i 2 c communication system to work reliably. voltage noise is also induced through the batteries impedance, which cannot be easily reduced. a unique level-shifting smbus ladder communication architecture solves these prob - lems by referencing the communication signals from one module to the next from a common voltage that is shared by both modules. the supply noise seen by the communication interface is thus greatly reduced and is then able to be rejected completely in most cases. in a typical application of up to approximately 200a to 400a, the gnd u supply may be connected to the top of the battery stack without the communication path experiencing adverse affects from bus-bar-induced noise. in some high-current applications where the load current is greater than 400a, or the module inter - connect impedance is more than a couple milliohms, further precautions may be necessary to ensure optimal performance. in these cases, the extreme current levels across even tiny interconnect impedances can result in significant noise due to the gnd u reference connection. applications with one or more of the following conditions may benefit from connecting gnd u with a kelvin style: u the bus bar impedance is greater than 1m i to 2m i . u battery pack current steps are greater than 400a in less than 100 f s. u the rc time constant at cell 12 does not match the time constant at dcin. in applications that meet these conditions, a kelvin con - nection should be made from gnd u to agnd of the next-higher module. for applications that do not have these conditions, the kelvin-style connection is optional. this connection can reject noise induced across the bus bar to further improve noise immunity for the i 2 c interface. figure 27 demonstrates how to properly kelvin-connect modules for maximum noise immunity. this method requires careful attention to the mechanical design of the module, since an extra module terminal connection is required. dcin and c12 should not share a common terminal of a module for kelvin-connected modules. figure 27. module-to-module dcin kelvin connection c12 c11 c2 c1 c0 pck+ module n+1 to ground reference of next module dcin gnd u dcin gnd u agnd agnd c12 c11 c2 c1 c0 pck+ module n
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 34 table 4. i 2 c register map register map register address register name r/w description por state management functions 0x00 version r contains coded information corresponding to the device model number and die version, where n is the least significant byte denot - ing the die revision code. 0x068 0x01 address r/w a read of this register returns the i 2 c address of the device and the device address of the last device in the smbus ladder. perform a rollcall command (special case of readall) to this address to determine the number of devices in the stack. 0x1fa0 0x02 status r/w read for status flags; write 0s to clear status flags. 0x8000 0x03 alrtcell r/w read for cell-alert status flags. 0x0000 0x04 alrtovcell r/w read for overvoltage cell-alert status flags. 0x0000 0x05 alrtuvcell r/w read for undervoltage cell-alert status flags. 0x0000 0x06 alrtoven r/w overvoltage cell-alert enables for cells 1C12. 0x0000 0x07 alrtuven r/w undervoltage cell-alert enables for cells 1C12. 0x0000 0x08 adccfg r/w aux channel enable, alarm enable, and scan control. 0x0000 0x09 cellen r/w cell measurement enable. 0x0000 0x0a gpio r/w gpio2 to gpio0 configuration. 0x0000 0x0b balcfg r/w cell-balancing switch control. 0x0000 0x0c acqcfg r/w acquisition time control configuration register for the auxiliary analog inputs. 0x0000 0x0d scanctrl r/w measurement scan control. 0x0000 0x0e fmea r/w failure-mode effects analysis status and control. 0x0000 0x0f broadcast address r/w broadcast address. 0x0040
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 35 table 4. i 2 c register map (continued) register address register name r/w description por state summary and alert functions 0x10 total r result for a sum total of all cell n measurements in the scan. 0x0000 0x11 maxcell r result for the highest/maximum cell voltage measured during the scan. 0x000f 0x12 mincell r result for the lowest/minimum cell voltage measured during the scan. 0x000f 0x18 ovthrclr r/w overvoltage clear threshold when any adc cell conversion is completed, the value is compared with ovthrset, ovthrclr, uvthrset, and uvthrclr. the difference between uvthrset and uvthrclr or ovthrset and ovthrclr is effectively a digital hysteresis for the alert threshold. if: cell n > ovthrset or cell n < uvthrset the corresponding alert bits are set. the over - voltage alert bit is cleared when: cell n < ovthrclr the undervoltage alert bits are cleared when: cell n > uvthrclr 0xfff0 0x19 ovthrset r/w overvoltage set threshold 0xfff0 0x1a uvthrset r/w undervoltage set threshold 0x0000 0x1b uvthrclr r/w undervoltage clear threshold 0x0000 0x1c msmtch r/w cell mismatch threshold when a scan of conversions is completed, a mismatch alert is generated if the result of: maxcell - mincell > msmtch set msmtch = 0xffff to disable mismatch alerts. 0xfff0 0x1e ainot r/w auxiliary input overtemperature threshold. 0x0000 0x1f ainut r/w auxiliary input undertemperature threshold. 0xfff0 measurements 0x20 cell1 r/w result for adc conversion of c1. 0x0000 0x21 cell2 r/w result for adc conversion of c2. 0x0000 0x22 cell3 r/w result for adc conversion of c3. 0x0000 0x23 cell4 r/w result for adc conversion of c4. 0x0000 0x24 cell5 r/w result for adc conversion of c5. 0x0000 0x25 cell6 r/w result for adc conversion of c6. 0x0000 0x26 cell7 r/w result for adc conversion of c7. 0x0000 0x27 cell8 r/w result for adc conversion of c8. 0x0000 0x28 cell9 r/w result for adc conversion of c9. 0x0000 0x29 cell10 r/w result for adc conversion of c10. 0x0000 0x2a cell11 r/w result for adc conversion of c11. 0x0000 0x2b cell12 r/w result for adc conversion of c12. 0x0000 0x40 ain1 r/w result for adc conversion of auxin1. 0x0000 0x41 ain2 r/w result for adc conversion of auxin2. 0x0000 0x44 diag r result for adc conversion for the diagnostic front-end test (used for self-test). 0x0000
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 36 register descriptions table 5. versionic version register description (address 0x00) table 6. address register description (address 0x01) the MAX11068 contains 38 registers that control and report the operational status of the device (see tables 5 through 34). bit name function d15 0 MAX11068 model number designator, 0x068 d14 0 d13 0 d12 0 d11 0 d10 1 d9 1 d8 0 d7 1 d6 0 d5 0 d4 0 d3 ver3 MAX11068 mask revision version number; revision 3.0 = 0x7h d2 ver2 d1 ver1 d0 ver0 bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 la4 the last address bits are used to support the smbus ladder alarm feature and the error- checking bytes of the readall command. these bits are set by the setlastaddress command and correspond to the a[4:0] device address bits of the last device in the chain. once properly set in all nodes, the alarm heartbeat function begins. d11 la3 d10 la2 d9 la1 d8 la0 d7 1 write ignored; read back 1. d6 0 write ignored; read back 0. d5 a0 i 2 c device address. a0 is the lsb. the first a[0:4] device address in the smbus ladder is set with the helloall command. the helloall command is then propagated up the smbus ladder and automatically incremented for each device, up to a maximum of 31 nodes. this gives each device a unique a[0:4] address. d4 a1 d3 a2 d2 a3 d1 a4 d0 0 write ignored; read back 0.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 37 table 7. status register description (address 0x02) bit name function d15 rststat reset status: rststat = 1 after a power-reset event. clear rststat to 0 after power-up and after a suc - cessful helloall command to detect any future resets. writing a 1 to this bit has no effect. pec errors should be ignored until this bit is cleared. d14 alrtov cell overvoltage alert: alrtov = 1 when a corresponding overvoltage has occurred. check the alrtovcell reg - ister to determine which cell is responsible. this is a read-only bit. all voltage alerts are auto - matically cleared when the next conversion occurs and the alert condition disappears. d13 alrtuv cell undervoltage alert: alrtuv = 1 when a corresponding undervoltage has occurred. check the alrtuvcell reg - ister to determine which cell is responsible. this is a read-only bit. all voltage alerts are auto - matically cleared when the next conversion occurs and the alert condition disappears. d12 alrtmsmtch mismatch alert: alrtmsmtch = 1 when maxcell - mincell > msmtch threshold: this is a read-only bit. all voltage alerts are automatically cleared when the next conversion occurs and the alert con - dition disappears. d11 alrttcold undertemperature alert: set when ain1 > ainut or ain0 > ainut. this is a read-only bit. all temperature alerts are automatically cleared when the next conversion occurs and the alert condition disappears. the comparison with ainut assumes an ntc thermistor is used as part of the suggested applica - tion circuit. d10 alrtthot overtemperature alert: set when ain1 < ainot or ain0 < ainot. this is a read-only bit. all temperature alerts are automatically cleared when the next conversion occurs and the alert condition disappears. the comparison with ainot assumes an ntc thermistor is used as part of the suggested applica - tion circuit. d9 alrtpec packet error check alert: indicates a communication failure occurred due to a slave or master pec error. the pec is a crc-8 error check byte, calculated on all message bytes except the ack, nack, start, and stop bits. the alrtpec bit must be cleared by writing a 0 to this bit location to detect future pec failures. writing a 1 to this bit has no effect. d8 alrtack acknowledge communication alert: indicates a communication fault due to an unexpected slave or master nack in the ack/ nack bit position. alrtack must be cleared by writing this bit to 0 to detect future nack events. writing a 1 to this bit has no effect. d7 alrtfmea fmea status alert: indicates that there is an fmea alert. this bit is the logical or of the alert bits in the fmea reg - ister. check the fmea register to determine which alerts are active.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 38 table 7. status register description (address 0x02) (continued) table 8. alrtcellper-cell alert status register description (address 0x03) bit name function d6 0 write ignored; read back 0. d5 0 d4 0 d3 0 d2 0 d1 alrtain2 ain1 fault: indicates a fault condition (over- or undertemperature) was detected on the ain1 analog input. a fault occurs when the ain1 input exceeds the set levels in the ainot and ainut registers. this bit is cleared automatically when the alert condition disappears following a new measure - ment. writing a 1 to this bit has no effect. d0 alrtain1 ain0 fault: indicates a fault condition (over- or undertemperature) was detected on the ain0 analog input. a fault occurs when the ain0 input exceeds the set levels in the ainot and ainut registers. this bit is cleared automatically when the alert condition disappears following a new measure - ment. writing a 1 to this bit has no effect. bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 alrtcell12 alert cell fault: alrtcell n is set when the corresponding cell is overvoltage or undervoltage. the register bits are the logical or of the corresponding alrtovcell and alrtuvcell register bits. all voltage alerts are automatically cleared when the alert condition dis - appears. d10 alrtcell11 d9 alrtcell10 d8 alrtcell9 d7 alrtcell8 d6 alrtcell7 d5 alrtcell6 d4 alrtcell5 d3 alrtcell4 d2 alrtcell3 d1 alrtcell2 d0 alrtcell1
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 39 table 9. alrtovcellper-cell overvoltage alert register description (address 0x04) table 10. alrtuvcellper-cell undervoltage alert register description (address 0x05) bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 alrtov12 alert cell overvoltage fault: alrtov[n] bits are set when the corresponding cell is overvoltage. all voltage alerts are automatically cleared when the alert condition disappears. d10 alrtov11 d9 alrtov10 d8 alrtov9 d7 alrtov8 d6 alrtov7 d5 alrtov6 d4 alrtov5 d3 alrtov4 d2 alrtov3 d1 alrtov2 d0 alrtov1 bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 alrtuv12 alert cell undervoltage fault: alrtuv[n] bits are set when the corresponding cell is undervoltage. all voltage alerts are automatically cleared when the alert condition disappears. d10 alrtuv11 d9 alrtuv10 d8 alrtuv9 d7 alrtuv8 d6 alrtuv7 d5 alrtuv6 d4 alrtuv5 d3 alrtuv4 d2 alrtuv3 d1 alrtuv2 d0 alrtuv1
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 40 table 11. alrtovenper-cell overvoltage alert enable register description (address 0x06) table 12. alrtuvenper-cell undervoltage alert enable register description (address 0x07) bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 ovalrten12 overvoltage cell-alert enable: overvoltage alert enable bits for cells 1C12. set the corresponding bit to enable alert notification for overvoltage events on that cell input. set to 0 to disable alarm notification for a cell or to clear the associated cell alarm. alert notification is not affected by the status of the alarm enable bits. this alert enable bit for each cell is also accessible through bit 1 of the cellen register. d10 ovalrten11 d9 ovalrten10 d8 ovalrten9 d7 ovalrten8 d6 ovalrten7 d5 ovalrten6 d4 ovalrten5 d3 ovalrten4 d2 ovalrten3 d1 ovalrten2 d0 ovalrten1 bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 uvalrten12 undervoltage cell alert enable: undervoltage alert enable bits for cells 1C12. set the corresponding bit to enable alarm notification for undervoltage alerts on that cell input. set to 0 to disable alarm notification for a cell or to clear the associated cell alarm. alert notification is not affected by the status of the alarm enable bits. this alert enable bit for each cell is also accessible through bit 0 of the cellen register. d10 uvalrten11 d9 uvalrten10 d8 uvalrten9 d7 uvalrten8 d6 uvalrten7 d5 uvalrten6 d4 uvalrten5 d3 uvalrten4 d2 uvalrten3 d1 uvalrten2 d0 uvalrten1
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 41 table 13. adccfg adc configuration register description (address 0x08) bit name function d15 scan start conversions scan set with 1 to initiate an adc scan of the enabled cell channels. a new measurement scan is initiated as long as the adc is not busy with a previous scan. otherwise, the scan start is ignored. this bit always reads back 0. the scan bit of the scanctrl register has the same function and is the recommended register control for initiating a scan. d14 alrmmmtchen voltage mismatch alarm enable mask: set alrmmmtchen = 1 to force a mismatch alert, alrtmsmtch, to generate an alarm. set alrmmmtchen = 0 to prevent a mismatch alert from generating an alarm. d13 alrmoven overvoltage alarm enable mask: set alrmoven = 1 to force an overvoltage alert, alrtov, to generate an alarm. set alrmoven = 0 to prevent an overvoltage alert from generating an alarm. d12 alrmuven undervoltage alarm enable mask: set alrmuven = 1 to force an undervoltage alert, alrtuv, to generate an alarm. set alrmuven = 0 to prevent an undervoltage alert from generating an alarm. d11 alrmuten undertemperature alarm enable mask: set alrmuten = 1 to force an undertemperature alert, alrttcold, to generate an alarm. set alrmuten = 0 to prevent an undertemperature alert from generating an alarm. d10 alrmoten overtemperature alarm enable mask: set alrmoten = 1 to force an overtemperature alert, alrtthot, to generate an alarm. set alrmoten = 0 to prevent an overtemperature alert from generating an alarm. d9 alrmpec packet-error check (pec) alarm enable mask: set alrmpec = 1 to force a packet-error check alert, alrtpec, to generate an alarm. set alrmpec = 0 to prevent a packet-error check alert from generating an alarm. d8 alrmack acknowledge communication fault alarm enable: set alrmack = 1 to force an acknowledge communication fault alert, alrtack, to generate an alarm. set alrmack = 0 to prevent an acknowledge communication check alert from generating an alarm. d7 unused unused bit: reads back written value. d6 unused d5 unused d4 diagen self-test diagnostic enable: enable reference channel diagnostic conversion. used for internal diagnostic self-test. set to 1 to enable the measurement to occur during the measurement cycle. d3 unused unused bit: reads back written value. d2 unused d1 ain2en auxin2 channel conversion enable: enables a conversion on the auxin2 input. after a conversion is completed, the results are compared to the over- and undertemperature thresholds. d0 ain1en auxin1 channel conversion enable: enables a conversion on the auxin1 input. after a conversion is completed, the results are compared to the over- and undertemperature thresholds.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 42 table 14. cellencell-scan enable register description (address 0x09) table 15. gpiogeneral-purpose i/o register description (address 0x0a) bit name d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 cell12en cell channel scan enable: set the cell enable bit to 1 to enable the corresponding channel in the measurement cycle. set to 0 to disable a cell measurement for a scan. disabled channels do not have their measurement values changed by a scan. d10 cell11en d9 cell10en d8 cell9en d7 cell8en d6 cell7en d5 cell6en d4 cell5en d3 cell4en d2 cell3en d1 cell2en d0 cell1en bit name function d15 unused unused bit: reads back written value. d14 dir2 input/output direction: write the dir bits to 1 to set the gpio pin drivers to output. write the dir bits to 0 to set the drivers as a high-impedance input. the bits default to a 0 and the high-impedance input state. d13 dir1 d12 dir0 d11 unused unused bit: reads back written value. d10 gpio2 gpio pin logic state: when reading this byte, the gpio[n] bits always return the logic state of each gpio pin. d9 gpio1 d8 gpio0 d7 0 write ignored; reads 0. d6 0 d5 0 d4 0 d3 unused unused bit: reads back written value. d2 gpio2out the gpio[n]out bits configure the gpio pin output driver-logic level. these bits only determine the driver state when the driver is set to be an output by the dir bits and have no affect on the gpio pins if the dir bits are set to the input state. d1 gpio1out d0 gpio0out
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 43 table 16. balcfgcell-balancing configuration register description (address 0x0b) table 17. acqcfgacquisition configuration register description (address 0x0c) bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 bal12 cell-balancing/discharge switch enable: select cell-balancing/discharge switches to activate. set bal[n] to 1 to enable the cell- balancing switch between c n-1 and c n. clearing to 0 disables the balancing/discharge switch. the switches are separately disabled by signals from the die overtemperature detection circuit and the cell-balancing watchdog timer. d10 bal11 d9 bal10 d8 bal9 d7 bal8 d6 bal7 d5 bal6 d4 bal5 d3 bal4 d2 bal3 d1 bal2 d0 bal1 bit name function d15 0 write ignored; read back 0. d14 0 d13 cbpdiv1 cell-balancing timer predivider: sets the step size of the cell-balancing timer lsb. 00 = disabled, no timeout for the cell-balancing switch on-time. 01 = 1s; timer range is then 1s to15s. 10 = 4s; timer range is then 4s to 60s. 11 = 16s; timer range is then 16s to 240s. d12 cbpdiv0 d11 cbtimer3 cell-balancing timer: acts as a safety watchdog timeout for the cell-balancing switches. the timer counts down at a rate set by the cbpdiv bits. when the timer reaches 0, all cell-balancing switches are disabled. the timer should be periodically rewritten with a timeout value to keep the cell- balancing switches enabled. when the timer value is read, the value reported is latched during the 9th bit time following the acqcfg register address of the readall command. d10 cbtimer2 d9 cbtimer1 d8 cbtimer0 d7 0 write ignored; read back 0. d6 0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 44 table 17. acqcfgacquisition configuration register description (address 0x0c) (continued) table 18. scanctrlmeasurement scan control register description (address 0x0d) bit name function d5 aincfg5 auxiliary analog input-acquisition time configuration: custom acquisition settling time for auxin1/auxin2. the auxiliary analog channels acquisition settling time can be set from 5.3 f s up to 339.2 f s with a count increment of 5.3 f s/ count. this is to allow extra settling time if the application circuit requires it since the thrm pin becomes active only during the measurement sequence. aincfg default is 0x000, which equals an acquisition time of 5.3 f s. the full settling time is added prior to the measurement for each enabled auxiliary channel. d4 aincfg4 d3 aincfg3 d2 aincfg2 d1 aincfg1 d0 aincfg0 bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 0 d10 0 d9 0 d8 0 d7 0 d6 0 d5 0 d4 0 d3 0 d2 0 d1 0 d0 scan start conversions scan: set to 1 to initiate an adc scan of the enabled cell channels. a new measurement scan is initiated as long as the adc is not busy with a previous scan. otherwise, the scan signal is ignored. this bit always reads back 0.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 45 table 19. fmeafailure-mode effects analysis status and control register description (address 0x0e) bit name function d15 alrmcpuv charge-pump undervoltage alarm enable mask: set alrmcpuv = 1 to force a charge-pump alert, alrtcpuv, to generate an alarm. set alrmcpuv = 0 to prevent a charge-pump alert from generating an alarm. d14 alrmhbeat heartbeat frequency alarm enable mask: set alrmhbeat = 1 to force a heartbeat frequency alert, alrthbeat, to generate an alarm. set alrmhbeat = 0 to prevent a heartbeat frequency alert from generating an alarm. d13 unused unused bit: reads back written value. d12 alrmref ref pin open-circuit alarm enable mask: set alrmref = 1 to force a ref pin open-circuit alert, alrtref, to generate an alarm. set alrmref = 0 to prevent a ref pin open-circuit alert from generating an alarm. d11 unused unused bit: reads back written value. d10 unused unused bit: reads back written value. d9 alrmvddl vddl open-circuit alarm enable mask: set alrmvddl = 1 to force a vdd l open-circuit alert, alrtvddl, to generate an alarm. set alrmvddl = 0 to prevent a vdd l open-circuit alert from generating an alarm. d8 alrmgndl gnd l open-circuit alarm enable mask: set alrmgndl = 1 to force a gnd l open-circuit alert, alrtgndl, to generate an alarm. set alrmgndl = 0 to prevent a gnd l open-circuit alert from generating an alarm. d7 alrtcpuv charge-pump undervoltage alert: indicates that the charge-pump output voltage has fallen below the undervoltage threshold v cpuv . this bit is not set before the rststat bit is cleared. writing a 1 to this bit has no effect. this bit must be written to 0 to clear the alert condition. d6 alrthbeat heartbeat frequency alert: indicates that the alarm heartbeat signal has a frequency error of more than 12.5% relative to the 32.768khz oscillator divided by 2. this bit is not set before the rststat bit is cleared. writing a 1 to this bit has no effect. this bit must be written to 0 to clear the alert condition. d5 unused unused bit: reads back written value. d4 alrtref ref pin open-circuit alert: indicates that the ref pin is oscillating, most likely due to a missing decoupling capacitor or open- circuit condition. the detection test occurs just after a valid measurement scan is initiated. after each adc strobe, there is a time of 4/32khz where logic transitions are counted. alrtref is set for four positive transitions. if there are no strobes, alrtref cannot be set. d3, d2 unused unused bit: reads back written value. d1 alrtvddl vdd l pin open-circuit alert: indicates that an open circuit is detected on the vdd l pin. this bit is not set before the rststat bit is cleared. writing a 1 to this bit has no effect. this bit must be written to 0 to clear the alert condition. d0 alrtgndl gnd l pin open-circuit alert: indicates that an open circuit is detected on the gnd l pin. this bit is not set before the rststat bit is cleared. writing a 1 to this bit has no effect. this bit must be written to 0 to clear the alert condition.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 46 table 20. broadcast addressbroadcast address register description (address 0x0f) table 21. totaltotal cell voltages data register description (address 0x10) bit name function d15 0 write ignored; read back 0. d14 0 d13 0 d12 0 d11 0 d10 0 d9 0 d8 0 d7 brdcst7 broadcast address: this byte contains the communication bus broadcast address. the lsb, brdcst0, is not used and can be considered a dont care. the default is 0040h. d6 brdcst6 d5 brdcst5 d4 brdcst4 d3 brdcst3 d2 brdcst2 d1 brdcst1 d0 brdcst0 bit name function d15 sum15 16-bit sum total value of all cells enabled in the measurement scan. d14 sum14 d13 sum13 d12 sum12 d11 sum11 d10 sum10 d9 sum9 d8 sum8 d7 sum7 d6 sum6 d5 sum5 d4 sum4 d3 sum3 d2 sum2 d1 sum1 d0 sum0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 47 table 22. maxcellmaximum cell reading register description (address 0x11) table 23. mincellminimum cell reading register description (address 0x12) bit name function d15 d11 12-bit adc conversion result of the highest cell-voltage reading. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 ch3 cell number of the maximum cell voltage acquired. if multiple cells have the same maximum value, this field contains the highest cell number with that measurement. d2 ch2 d1 ch1 d0 ch0 bit name function d15 d11 12-bit adc conversion result of the lowest cell-voltage reading. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 ch3 cell number of the minimum cell voltage acquired. if multiple cells have the same minimum value, this field contains the highest cell number with that measurement. d2 ch2 d1 ch1 d0 ch0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 48 table 24. ovthclrovervoltage clear threshold register description (address 0x18) table 25. ovthrsetovervoltage set threshold register description (address 0x19) bit name function d15 d11 12-bit limit for the reset threshold of overvoltage-alert detection. an alert that is issued when the overvoltage set threshold is exceeded by a cell voltage is not cleared until the voltage falls below this lower threshold. the overvoltage alert is updated on each new measurement scan of the cell voltages by comparing against the threshold values. this alert-clearing threshold builds in digital hysteresis to the overvoltage detection. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0 bit name function d15 d11 12-bit limit for the triggering threshold of overvoltage-alert detection. an alert for a given cell is issued when this set threshold is exceeded by the cell voltage and the alert is not cleared until the cell voltage falls below the clear threshold. the overvoltage alert is updated on each new measurement scan of the cell voltages by comparing against the overvoltage threshold values. this alert setting threshold is a critical maximum cell-voltage level. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 49 table 26. uvthrsetundervoltage set threshold register description (address 0x1a) table 27. uvthrclrundervoltage clear threshold register description (address 0x1b) bit name function d15 d11 12-bit limit for the triggering threshold of undervoltage-alert detection. an alert for a given cell is issued when the cell voltage falls below this set threshold and the alert is not cleared until the cell voltage rises above the clear threshold. the undervoltage alert is updated on each new measurement scan of the cell voltages by comparing against the undervoltage threshold values. this alert-setting threshold is a critical minimum cell-voltage level. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0 bit name function d15 d11 12-bit limit for the reset threshold of undervoltage-alert detection. an alert that is issued when the undervoltage set threshold is tripped by a cell voltage is not cleared until the voltage rises above this clearing threshold. the undervoltage alert is updated on each new measure - ment scan of the cell voltages by comparing against the threshold values. this alert-clearing threshold builds in digital hysteresis to the undervoltage detection. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 50 table 28. msmtchcell mismatch threshold register description (address 0x1c) table 29. ainotauxiliary analog input overtemperature threshold register description (address 0x1e) bit name function d15 d11 12-bit threshold limit for mismatch alert. if: maxcell - mincell > msmtch then the alrtmsmtch alert bit in the status register is set. if the msmtch threshold is set to 0xfff0, no alert is possible; this immediately clears the alert status. for all other msmtch threshold value changes, the alert status does not change until after the next measurement scan. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0 pin name function d15 d11 12-bit threshold limit for an undervoltage alert on the auxin1 and auxin2 inputs. when the auxiliary analog inputs are used with an ntc thermistor as part of the recommended circuit, this register can be used to store the overtemperature threshold. this threshold may also be used as a general undervoltage trip point for the auxiliary inputs. the alrtthot bit in the status register is set if: ain1 or ain0 < ainot the polarity of this comparison assumes that an ntc thermistor is used in the application circuit. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 51 table 30. ainutauxiliary analog input undertemperature threshold register description (address 0x1f) table 31. cell n data register description (addresses 0x20 to 0x2b ) pin name function d15 d11 12-bit threshold limit for an overvoltage alert on the ain0 and ain1 inputs. when the auxiliary analog inputs are used with an ntc thermistor as part of the recommended circuit, this register can be used to store the undertemperature threshold. this threshold may also be used as a general overvoltage trip point for the auxiliary inputs. the alrttcold bit in the status register is set if: ain1 or ain2 > ainut the polarity of this comparison assumes that an ntc thermistor is used in the application circuit. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0 pin name function d15 d11 12-bit adc conversion result from cell n . d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 write ignored; read back 0. d1 oven enable overvoltage alerts for this cell channel: maps to the alrtov(n-1) bit. d0 uven enable undervoltage alerts for this cell channel: maps to the alrtuv(n-1) bit.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 52 table 32. ain1auxiliary analog input 1 data register description (address 0x40) table 33. ain2auxiliary analog input 2 data register description (address 0x41) pin name function d15 d11 12-bit adc conversion result on the auxin1 channel. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 write ignored; read back 0. d1 colden enable undertemperature or overvoltage alerts for this channel. d0 hoten enable overtemperature or undervoltage alerts for this channel. pin name function d15 d11 12-bit adc conversion result on the auxin2 channel. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 write ignored; read back 0. d1 colden enable undertemperature or overvoltage alerts for this channel. d0 hoten enable overtemperature or undervoltage alerts for this channel.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 53 table 34. diag diagnostic data register description (address 0x44) i 2 c interface overview the MAX11068 uses an smbus ladder i 2 c physical interface with customized i 2 c command protocol to communicate with the host system and from module to module. each device contains two i 2 c ports, one master and one slave. the slave port is the lower port, referenced to the chip ground, and communicates with the host master or the master from a device lower on the smbus ladder. the upper port is a master port that is level shifted and referenced to gnd u . it drives commu - nication with devices higher on the smbus ladder and gathers information to be passed back toward the host. the two ports act together with the help of a digital con - troller to bridge two separate links of the smbus ladder. each link between master and slave of interconnected MAX11068 devices can be thought of as its own bus under the control of the master side device. a standard i 2 c hardware master found in many microcontrollers or a master implemented with firmware and general-purpose i/o pins is all that is required to successfully implement the physical communication bus. this level-shifted dual- port scheme allows modules to be easily stacked without the need for costly and complex galvanic isolation of the communication lines while providing very-high-noise rejection. i 2 c physical interface operation the physical i 2 c interface for each MAX11068 device consists of a master block and a slave block. the master block is level shifted and referenced to the gnd u sup - ply voltage. a digital controller manages each block and coordinates the passing of commands and data between the two as needed. the two standard i 2 c interface pins for all ports are scl for the serial data clock and sda for the serial data line. additional status pins used to com - plement the i 2 c communication in the MAX11068 are the ground-referenced alrm l output and the level-shifted alrm u input. these pins act as an smbus-laddered interrupt signal that the host can use to determine the health of the bus. to support the level-shifted i/o pins, a level-shifted supply, vdd u , is generated by an internal charge pump and referenced to gnd u. this supply provides a pullup voltage to the level-shifted bus com - munication signals. figure 28 shows the simplified view of the i 2 c physical interface from the perspective of the first device in an smbus ladder. pin name function d15 d11 12-bit adc conversion result on the diagnostic data value. this diagnostic tests the toler - ance of the reference, the stability of the internal regulator, and the open/short status of cell input c0. the converter delivers the data value based on the following formula: diag = ((ref - c0) x 0.5)/vaa x 4096 the nominal value for normal operation is 5e1h with a tolerance of q 150 lsbs. the ref open case also has a special fmea detector that has a separate alert, alrtref, in the fmea register. d14 d10 d13 d9 d12 d8 d11 d7 d10 d6 d9 d5 d8 d4 d7 d3 d6 d2 d5 d1 d4 d0 d3 0 write ignored; read back 0. d2 0 d1 0 d0 0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 54 figure 28. i 2 c physical interface block diagram i 2 c master block alrm u internal clamp vdd u vdd u vdd u alrm u scl u scl l internal sda u vaa vdd l alrm l scl l sda l p sda u internal sda u drive control level shifter gnd u one shot pullup management n glitch filter 50ki 1ki 1ki 250ns i 2 c slave block scl internal vdd l p p p alrm l internal sda l internal sda l drive control one shot pullup management n glitch filter glitch filter 50ki 1ki 250ns gnd l agnd gnd l gnd l gnd u gnd u cp- cp+ vdd u to top of stack or bottom of upper neighbor stack gnd u dcin MAX11068 p gnd u n
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 55 each port contains a bidirectional sda pin with managed internal pullup drivers. the scl pin for the lower slave port is an input only, while the upper port master scl pin has a 1k pullup driver. glitch filters and schmitt trig - ger buffers are present on the input signals to minimize communication errors. the alarm signal input is schmitt trigger with a current and voltage-clamping circuit while the lower port alarm output is a push-pull driver. each port is designed to operate in an ac- or dc-coupled bus configuration. all signal pins have a weak 150k i pullup to their respective vdd supply to establish the customary idle state of the i 2 c bus. the following operat - ing description assumes the ac-coupled circuit shown in figure 28. since the sda signal path must be bidirectional, manag - ing the handoff of roles between transmitting nodes and receiving nodes is critical to data integrity. at the same time, the bus must be able to drive a certain capacitive load size to maintain specified timing performance. to meet these requirements, a managed resistance pullup system with a strong pulldown driver is implemented in both the master and slave blocks. when the sda pin for a given block is the driver of a signal edge on the line, it first connects both a 1k i resistor and a 50k i resistor from its vdd supply to sda to initiate the active edge. this strong pullup provides extra drive strength initially to speed the charging of the parasitic capacitances connected to the sda pin and is active for the time period t one-shot , which is typically 250ns. a param - eter, c 1_tau, specifies the maximum capacitance that may be present on the sda pin so that the sda voltage level transitions to within 70% of its nominal value within the time period of the one-shot active edge. when the one-shot period is over, the 1k i resistor is disconnected and the 50k i pullup remains to complete the active edge transition. this weaker pullup continues to actively drive the line until the particular sda pin is no longer in a transmitting state. during the acknowledge bit time, the sda pin that had been receiving data is able to use its pulldown driver to overcome the 50k i pullup driven by the transmitting device and successfully acknowledge the transmission. internal circuitry prevents the coupling capacitors from accumulating charge and causing a dc drift on the signals. when the host or a device master drives the ac-coupled scl line with a signal edge, the high-frequency edge passes to the slave side of the coupling capacitor where it is received at the scl input pin. since the 150k i pas - sive pullup resistor value is large, the time constant of the pullups effect during communication when paired with the typical 3.3nf ac-coupling capacitor is large compared to the specified range of the i 2 c clock period. using resistor values lower than 150k i or changing the coupling-capacitor value could affect the margin of the bus timing specifications at some communication frequencies. since the scl signal is unidirectional, no internal pullup resistor manipulation for the driver circuit is necessary. as with the sda pins, internal circuitry pre - vents the coupling capacitors from accumulating charge. i 2 c command summary the MAX11068 supports seven different commands. there are two main cycle formats, one for readall and the other for the rest of the commands. several com - mands require the host to send a pec byte or for the chain to send a pec byte to the host. this is an imple - mentation of the smbus pec algorithm, which is a crc-8 process where all bits in the packet are cycled through the crc engine. table 35 is the i 2 c command list.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 56 table 35. i 2 c command list write word format readall format, single device i 2 c communication cycle formats the following cycle formats are used for the MAX11068 command set. function description pec byte helloall this command sets the device address of the first part in the chain. all other parts in the chain are then assigned an automatically incremented address as this command is forwarded from module to module. the helloall command should be issued after any power cycle or shut - down event. none rollcall reads 2 bytes from each device in the chain, which includes the address byte. when 0xff is returned, the host has the addresses of all devices. the rollcall command should be issued after the helloall command. none setlastaddress the host informs all devices of the device count determined by the rollcall command so that each device can know when to expect and generate pec bytes. the setlastaddress command should be issued after the rollcall command. required from host writeall broadcasts a common command to all enabled devices in the chain. required from host readall reads the available data from the device register specified by the com - mand code byte for each device in the chain. sent to host writedevice writes data only to a specified target device. required from host start device or global address wr ack command code/ register address ack data low [7:0] ack data high [15:8] ack stop 7 bits 8 bits 8 bits 8 bits start device or global address wr ack command code/ register address ack sr address rd ack data low [7:0] ack data high [15:8] nack stop 7 bits 8 bits 7 bits 8 bits 8 bits
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 57 i 2 c command protocol descriptions conventions the following conventions are used in the description of the i 2 c command protocols. binary values are prefixed with the notation 0b, e.g., 0b11101000. hexadecimal values are prefixed by the notation 0x, e.g., 0xe8. in the timing diagrams, standard i 2 c notations have been used: u s represents a start condition (pulls sda low while scl is high). u p represents a stop condition (pulls sda high while scl is high). u sr represents a repeated start condition. this is identical to a start condition except that it has not followed a stop condition. u a represents a positive acknowledge (ack). the data receiver drives the sda line low. u n represents a negative acknowledge (nack). the data receiver drives the sda line high. u w represents the r/wb bit set low for a write transac - tion. u r represents the r/wb bit set high for a read transac - tion. u x represents a dont-care value for a data bit. u n.c. represents an i 2 c link that is a no connect. the diagrams also represent the direction of sda by shading the data when the slave is the data source. for example, when the i 2 c master performs a write, it sends the data bits and receives the acknowledge bit. so, the data bits have a clear background and the acknowledge bit is shaded. when the i 2 c master performs a read, it receives the data bits and sends the acknowledge bit. so, the data bits have a shaded background and the acknowledge bit is clear. address byte encoding all commands begin with an i 2 c address byte immedi - ately following a start or repeated start condition. each MAX11068 responds to the following bytes after a start condition: u broadcast address u writedevice command containing the device address u helloall command the format for these bytes is shown in table 36. the broadcast address is an address value to which all enabled devices respond. this address is used for rollcall, writeall, and readall commands. the broadcast address b[7:0] is programmable through the brdcst bits of the broadcast address register (address 0x0f), but b[0] is not used since it falls in the position of the i 2 c r/wb bit. the default broadcast address is 0x40. the i 2 c general-call address 0x00 is not supported and the MAX11068 does not respond to messages sent to that address unless the brdcst bits are set to this value. the device address is unique to each part within the chain of devices. this address is used during helloall and writedevice commands, and is essential in deter - mining which device is the last in the smbus ladder. the helloall command sets the address of all de-vices by initializing the address of the first device in the chain and autoincrementing the addresses of remaining devices up the chain. when the MAX11068 is not used on a dedicated i 2 c bus, the other devices on the bus should not be configured to use addresses with a 1 as the msb. the broadcast address must also be chosen to avoid conflicts with the helloall and writedevice com - mands, as well as any other devices on the bus. table 36. i 2 c address byte encoding i 2 c address bit 7 6 5 4 3 2 1 r/wb broadcast address (default value) b7 0 b6 1 b5 0 b4 0 b3 0 b2 0 b1 0 1/0 1/0 helloall 1 1 a0 a1 a2 a3 a4 0 writedevice 1 0 a0 a1 a2 a3 a4 0
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 58 figure 29. i 2 c address byte for the helloall command figure 30. helloall command smbus ladder sequences with four modules helloall command the purpose of the helloall command is to initialize the device stack and assign a unique device address to each MAX11068 in the smbus ladder. it should be issued after any power cycle or shutdown event to recon figure all addresses. the helloall command is a standard i 2 c address byte where the first 2 bits must be 1s, the next 5 bits specify the desired address of the first MAX11068 device in the smbus ladder, and the last bit is the standard i 2 c r/wb bit. this bit should always be 0 for this command. the starting address a[0:4] is specified least significant bit first. since the device address consists of 5 bits, it has a maximum value of 32, while the maximum number of smbus-laddered devices is 31. the device address a[0:4] wraps to 0 if it exceeds the maximum value of 0x1f during a helloall com - mand. the writedevice command, which uses the device address, however, does not properly commu - nicate with devices whose address is less than that of device 1. therefore, the starting address used by the helloall command should always be set such that the last devices address a[0:4] is no greater than 0x1f. when using the maximum number of devices, the address a[0:4] of the first device must be initialized to 0x00 or 0x01 to meet this requirement. when the helloall command is first issued by the host, the address specified is stored to the a[0:4] bits of the address register (address 0x01) in the first smbus ladder device. the command is then forwarded to the next device in the chain with the a[0:4] bits of the address byte incremented by 1 lsb. this continues for each active device in the smbus ladder. a typical start - ing address is 0x01, which in this example would make the helloall address byte value 0b1110000 = 0xe0. figure 29 is the i 2 c address byte for the helloall command and figure 30 shows the helloall com - mand smbus ladder sequences with four modules. in the case of a four-module smbus ladder, the fourth MAX11068 upper i 2 c port is not connected to anything. therefore, it receives a nack when it transmits the helloall command. this sets the alrtack status bit, which should be cleared by the host. rollcall command the rollcall command is used to determine the num - ber of devices in the stack. it should be issued after the helloall command following any power cycle or shut - down event. the format for this command is similar to the readall command except that 0xff is returned in place of the pec and data check bytes. the rollcall command is always a read of the address register (address 0x01). this register cannot be read in any other way. figure 31 shows the i 2 c communication sequence for the rollcall command as viewed by the host con - troller and figure 32 is the rollcall command smbus ladder sequences with two modules. scl sda 1 1 a0 a1 a2 a3 a4 w a s p 11100000 i 2 c bus forwarding data stream a s p 11010000 a 11110000 a 11001000 a 11101000 n i 2 c bus link host to ic1 ic1 to ic2 ic2 to ic3 ic3 to ic4 ic4 to n.c. s s s s p p p p note: shown is the 1fs fowarding delay from one bus link level to the next. not drawn to scale. starting address of a[4:0] = 0x01.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 59 figure 32. rollcall command smbus ladder sequences with two modules figure 31. i 2 c communication sequence for the rollcall command as seen by the host i 2 c bus link host to ic1 s ic1 to ic2 ic2 to n.c. i 2 c bus forwarding data strea m a a a a a n p a a a sr b[7:1]+w 00000001 b[7:1]+r address 1 l address 2 l address 2 h 0xff 0xff a p 0xff a 0xff a a 0xff 0xff address 1 h s a a a a sr b[7:1]+w s n p b[7:1]+w 00000001 b[7:1]+r address 2 l address 2 h note: shown is the 1fs fowarding delay from one bus link level to the next. not drawn to scale. a note: the ic master port continues to output a clock on scl until it receives a stop from the lower module. b7 scl sda sda sda sda scl scl scl sda scl b6 b5 b4 b3 b2 b1 w a a a c7 c6 c7 c4 c3 c2 c1 c0 a a a b7 b6 b5 b4 b3 b2 b1 r a high byte device 1 low byte device 1 low byte device 2 sequence repeats. two bytes are returned for every device in the stack. high byte device 2 a a low byte device n high byte device n a n data check byte pec note: the i 2 c master knows the number of devices in the stack from a previous rollcall command. it therefore knows when to expect the data check and pec bytes, and when to nack and issue a stop condition. s sr p
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 60 figure 33. i 2 c communication sequence for the setlastaddress command the rollcall command is formatted like the readall cycle format. first, the broadcast address is sent on the bus as an i 2 c address byte with the r/wb bit configured as a write. next, the command 0x01 for the address register is sent. this address is always the target of the rollcall command. following the broadcast address and command byte, a repeated start is performed. next, the host sends another broadcast address byte with the last bit set to 1 for an i 2 c read. all command bytes are forwarded up the smbus ladder. after receiving the broadcast address byte for the read, each device in the chain starting with the first device responds by sending both bytes of their address registers. when each device is done sending its own data, it passes the data of the device above it in the chain. the scl signal provides a clock to all devices in the chain until the host issues a stop event. therefore, when devices no longer have valid register data to forward, they will continue to forward bytes consisting of 0xff since the sda lines are pulled to a logic-high level. when the host receives 2 bytes of 0xff, it should recognize that no more devices are present and send the nack/stop sequence. the stop propagates up the smbus ladder to halt the transfer of data. the host is then able to examine all the bytes received and determine the number of valid devices that are connected, in addition to the address of the last device. if a device is connected to the chain but not powered, its data is 0x0000 since the sda line is not pulled up by the vdd supplies. this allows the host processor to determine that a device is present, but not communicating properly or is faulty. because of the way in which data is shifted from the last device in the chain back to the first device and then to the host, the bus forwarding delay of the rollcall command is masked and no delay is perceived by the host once it begins receiving data from device 1. as an example, if a helloall command was issued previously with a starting address of 0x01, the first device returns in response to the rollcall command the device address 0x01 encoded as 0b10100000 = 0xa0. the second device returns a device address of 0x02, which is encoded 0b10010000 = 0x90 and so on. the last address byte is indeterminate during readback with this command, and should not be relied upon. setlastaddress command this command is used to tell each MAX11068 in an smbus ladder which device address is the last one. each device must know this information to properly place the pec byte in the data stream during relevant com - munication operations. the i 2 c master establishes the last device identity by using the rollcall command, which should always precede setlastaddress. once the last device address is known, the host initiates the setlastaddress command to write this information to the la[4:0] bits of the address register (address 0x01). as with all data bytes in the i 2 c stream, the last address byte is encoded msb first. figure 33 shows the i 2 c communication sequence for the setlastaddress command. figure 34 shows the setlastaddress command smbus ladder sequences with four modules. data a data a pec a scl sda scl sda 1 0 a0 a1 a2 a3 a4 w a c7 c6 c5 c4 c3 c2 c1 c0 a s p
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 61 figure 34. setlastaddress command smbus ladder sequences with four modules the communication sequence for setlastaddress follows the write word format. first, the broadcast address is sent on the bus as an i 2 c address byte with the r/wb bit configured as a write. next, the com - mand code byte 0x01 for the address register loca - tion is sent. this address is always the target of the setlastaddress command. next, the 2 data bytes to be written to each device are sent on the bus. only the second byte containing the la[4:0] bit information is written into each devices address register for the setlastaddress command. therefore, the first data byte may have any value. after the second data byte is sent, the pec byte, which is calculated from the first 4 bytes, is transmitted and then a stop event from the host should end the communication sequence. for example, if the host determined by use of the rollcall command that the device address byte (d[7:0] of the address register) for the last device in the chain was 0x84 = 0b10000100, then the device address bits (packed lsb first) a[0:4] are 0b00010. this value, noting proper orientation of the lsb and msb, is what must be written to the la[4:0] bits of the address regis - ter in all connected devices. to construct the last address byte, which consists of bits d[15:8] in the address register, start with 3 zeros, and append the a[4:0] data (oriented with the msb first), which results in 0b00001000 = 0x08. this is the byte value for this example that would be written to d[15:8] of the address register using the setlastaddress command. once the last device has been configured with the last address bit data, that device acts as the source of the alarm heartbeat. all other devices relay that heartbeat, or any alarm conditions that may be present, down the chain to the host using the alrm l and alrm u pins. writeall command the writeall command allows a given value to be written to a certain register in all active MAX11068 devices at the same time (neglecting communication delays). since most configuration information is common to all the devices, this command allows faster setup than writing to each device individually. first, the broadcast address is sent on the bus as an i 2 c address byte with the r/wb bit configured as a write. next, the command byte is sent with an msb first value corresponding to the register address to which the data byte is written. the i 2 c bus forwarding data stream i 2 c bus link host to ic1 ic1 to ic2 ic2 to ic3 ic3 to ic4 ic4 to n.c. b[7:1]+w a s a data register pec a data lsb data msb a a p p b[7:1]+w n s b[7:1]+w a s a data register pec a data lsb data msb a a p b[7:1]+w a s a data register pec a data lsb data msb a a p b[7:1]+w a s a data register pec a data lsb data msb a a p note: shown is the 1fs fowarding delay from one bus link level to the next. not drawn to scale.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 62 figure 35. i 2 c communication sequence for the writeall command figure 36. writeall command smbus ladder sequences with four modules low data byte and then the upper data byte follow the command byte. finally, the pec is sent and a stop event ends the communication sequence. figure 35 shows the i 2 c communication sequence for the writeall com - mand. figure 36 shows the writeall command smbus ladder sequences with four modules. the pec byte must be supplied with the writeall command. it is calculated from the first 4 bytes of the command. if any MAX11068 device does not receive a packet with a consistent pec, it will not perform the command or the register writes. it will also generate a pec alert in the status register, and this may (option - ally) cause the suspension of the alarm heartbeat. due to bus noise, it is possible for some devices to receive a consistent pec while others may not. in this case, an enabled pec alarm can signal the overall problem while a readall command can check the status registers to reveal which specific devices failed to correctly receive the command. when using the writeall command to change the broadcast register, it is important to verify that the command was executed by all known devices. this can be accomplished by enabling the pec alarm and verifying that the writeall was successful, or by performing a readall after the writeall and making sure a response was received from all expected devices. if a response was not received from all devices, steps should be taken to rewrite the new broadcast address or determine if a device has been removed from the stack. scl sda scl b7 b6 b5 b4 b3 b2 b1 w a c7 c6 c7 c4 c3 c2 c1 c0 a low data byte a high data byte a pec a sda s p i 2 c bus forwarding data stream i 2 c bus link host to ic1 ic1 to ic2 ic2 to ic3 ic3 to ic4 ic4 to n.c. b[7:1]+w a s a 00000001 pec a xxxxxxxx address msb a a p b[7:1]+w a s a 00000001 pec a xxxxxxxx address msb a a p b[7:1]+w a s a 00000001 pec a xxxxxxxx address msb a a p b[7:1]+w a s a 00000001 pec a xxxxxxxx address msb a a p p b[7:1]+w n s note: shown is the 1fs fowarding delay from one bus link level to the next. not drawn to scale.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 63 writedevice command this command allows a register in a specific device within the smbus ladder to be written. it is similar to the writeall command except that the i 2 c address byte contains the fixed msbs 0b10, followed by the device address a[0:4] encoded lsb first instead of the broad - cast address. once again, a consistent pec must be received for the command to be executed by the device. the pec alert is set if the command was aborted. the command sequence is forwarded up the smbus ladder until the device address sent with the command match - es or exceeds the receiving devices address. if the addresses match, the device executes the command. if the command address exceeds the devices address, the command forwarding stops. this can happen if the device addresses assigned during the helloall command exceeded 0x1f, or if the device addressed by the writedevice command is no longer active. figure 37 shows the i 2 c communication sequence for the writedevice command and figure 38 shows the writedevice command smbus-laddered sequences where the device address matches ic3. figure 37. i 2 c communication sequence for the writedevice command figure 38. writedevice command smbus ladder sequences where the device address matches ic3 i 2 c bus forwarding data stream i 2 c bus link host to ic1 ic1 to ic2 ic2 to ic3 10+a[0:4]+w a s a data register pec a data lsb data msb a a p 10+a[0:4]+w a s a data register pec a data lsb data msb a a p 10+a[0:4]+w a s a data register pec a data lsb data msb a a p note: shown is the 1fs fowarding delay from one bus- link level to the next. not drawn to scale. scl sda scl b7 b6 b5 b4 b3 b2 b1 w a 0 0 0 0 0 0 0 1 a don?t care a last address a pec a sda s p
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 64 figure 39. i 2 c communication sequence for the rollcall command as viewed by the host controller readall command this command is used to retrieve register information from the stack of devices and it is the only way to read register values (except for the address register, which is handled by the rollcall command). after sending the i 2 c address byte containing the broadcast address with the r/wb bit low and then the command byte, the readall format requires a repeated start to change the direction of data flow. following the repeated start, another broadcast address byte is sent with the r/wb bit, this time set for a read. this starts the flow of device data back to the host. the data stream as viewed at the lower port interface of the first device in the stack appears as shown in figure 39. after the first device receives the readall command, it begins to send the requested register data, low byte first, on the bus toward the host. approximately 1 f s later, the next device in the smbus ladder receives the readall command and sends its data to the upper port of the first device. the first device holds these bits until it is done sending its own data and receives an acknowledge bit, at which time it forwards the data from the second device. this process continues for each MAX11068 in the smbus ladder. because of the way the data is shifted from each device back toward the host, the module-to- module communication delays are effectively masked and the host sees a continuous stream of data once the first device receives the readall command. after the last device sends its data, it creates a data check byte and pec byte since it knows it is the last device in the chain. the pec byte generated by the MAX11068 uses a crc-8 algorithm, which is what the host should use on the sent data. each link of the smbus ladder contains a unique data sequence. therefore, each readall communication between modules has a different pec byte. the data check byte informs the host whether the entire communication succeeded by passing a flag containing the pec error status of the entire readall command down the chain. this makes it easier for the host controller to determine if the readall command was successful without hav - ing to check the alrtpec status of each module in the b7 scl sda sda sda sda scl scl scl sda scl b6 b5 b4 b3 b2 b1 w a a a 0 0 0 0 0 0 0 1 a a a b7 b6 b5 b4 b3 b2 b1 r a last address device address 1 device address 2 sequence repeats. two bytes are returned for every device in the stack. last address a a device address n last address a a 0xff 0xff note: the i 2 c master keeps reading 2 bytes at a time until the terminating sequence 0xff 0xff is seen. it then nacks and issues a stop condition. s sr p
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 65 smbus ladder. host processor efficiency is improved as a result. in addition, an alrtpec condition can be con - figured to generate an alarm on the alarm bus by setting the alrmpec bit. this alarm can be monitored by the host and provides the same information as the alrm bit of the data check byte. the benefit of the pecerr bit is that it provides a specific alrtpec flag to the host as part of each readall transaction. the data included in the calculation is the first address byte, the command byte, the address byte following the repeated start, all data sent on the bus by the device calculating the pec, and the data check byte. for the last device, the pec is calculated from the 3 bytes of the readall command, the 2 data bytes that it sent, and the data check byte. the data check byte is defined in table 37. the msb, alrm, is a flag indicating whether the device sending the data check byte or a device above it in the smbus ladder is in any alarm condition with the alrm pin pulled high. for the data check byte sent by the last device in the chain, the alrm bit is set according to the alarm status of the device while the pecerr bit is a 0, since this is the last device. when the next-to- last device receives the data check byte from the last device, it logically ors this byte with its own alarm status and whether its upper port received a valid pec byte from the last device. it sends out the data check byte after the last data byte (high byte from the last device) is sent. the lsb, pecerr, is a flag indicating whether the device sending the data check byte, or a device in a module above it, has an active alrtpec flag. when a device receives an invalid pec byte at its upper i 2 c port, it sets pecerr, as well as alrtpec to 1 before sending the data check byte down the smbus ladder. the next-to-last device recalculates the pec byte based on the same readall command bytes as the last device, plus all 4 data bytes belonging to the last two devices and the updated data check byte. the processing of the data check and pec bytes continues as all information is passed from the last device in the chain to the first device. when the first device has sent all data bits, it appends the processed data check byte as each of the devices before it has done. the pec byte is then appended having been calculated using all bytes shown in figure 40. any error in the process that causes an invalid pec does not terminate the transaction. since each intermediate device recalculates the pec, the host may receive a valid pec byte for invalid data, but the data check byte shows that a pec error has occurred along the way. in that case, the host should determine where the error occurred and take appropriate actions. as mentioned, the overall data stream appears to the host as it is shown in figure 40. in the transactions between intermediate modules, the data stream is simi - lar except that it contains only the data bytes from itself and the modules above it. since the module-to-module communication delay is much less than one i 2 c clock, and the clock itself is also delayed, there is no apparent module-to-module delay observed by the host controller as the real delay is masked in the process of shifting the data back to the host. a combination of the pec and data check byte approaches can ensure a very high probability of transactional integrity for the readall command. figure 40. readall command smbus ladder sequences with two modules i 2 c bus link host to ic1 s ic1 to ic2 ic2 to n.c. i 2 c bus forwarding datastrea m a a a a a n p a a sr b[7:1]+w data register b[7:1]+r data 1 lsb data 2 lsb data 2 msb data check pec a n p data check pec data 1 msb s a a a a sr b[7:1]+w s n p b[7:1]+w data register b[7:1]+r data 2 lsb data 2 msb note: shown is the 1fs fowarding delay from one bus link level to the next. not drawn to scale. a a
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 66 figure 41. i 2 c lower and upper port timing diagrams i 2 c port timing diagrams figure 41 shows the i 2 c lower and upper port timing diagrams. i 2 c functional description autoaddressing the helloall command automatically assigns each device a unique address. this address can be used during a writedevice command to write to only one selected device in the smbus ladder, and is also read during the rollcall command to identify all the unique active devices present on the bus. when all the device addresses are known, the last device in the chain can be identified and made known to all ports. it is important for each node and the host to know the relationship of devices that make up the smbus ladder so that the pec byte used in some command protocols can be properly located and calculated. the device address of the first device in the smbus lad - der stack is specified with the helloall command. this address is incremented by 1 before being sent to each successive downstream device. the maximum device address is 0x1fh and the address counter wraps to 0 if the starting address was set too high for the num - ber of devices in the chain. the smbus-laddered devic - es only forward writedevice commands that have a higher device address than their own. so, some devices are not addressable if the addresses a[0:4] written by helloall are allowed to wrap past 0x1fh. pack insertion and removal when a pack is removed or inserted, the smbus lad - der must be reconfigured. the helloall, rollcall, and setlastaddress sequence should be used to reinitialize the device addresses and the address of the last device. communication timeout if the scl u input remains high or low for longer than 28ms, then any transaction is aborted and the device behaves as if it observed a stop condition. the host can ensure that all devices are in a ready-to-communi - cate state by remaining idle for longer than 28ms. interface speed for optimal data transfer, the host microcontroller should make extensive use of the writeall and readall commands. one readall or rollcall command consumes the following amount of time based on the number of bits in the command protocol and the number of devices in the smbus ladder: ( ) ( ) readall scl modules scl t 5 8 bits 5 bits 3 bits t n 16 bits 2 bits t = + + + + t mcl-min t ls-clk t ls-dat t hd-sta t buf t low p scl l sda u scl u sda l s data data data data data data t hd-dat t su-dat t high t hd-dat
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 67 table 37. data check byte definition for 20 modules with a 200kbps i 2 c master data rate, it takes approximately 2.0ms to perform a readall or rollcall command for one register. since there are 16 frequently read registers, it would take 32ms to per - form a complete read of all devices for those registers. if an additional nine configuration registers are included, then 50ms are required. a 100kbps i 2 c master would be fast enough to perform this task in a reasonable amount of time. writeall consumes the following amount of time based on the number of bits in the command protocol, and the number of modules in the smbus ladder: ( ) ( ) writeall scl modules level shift delay t 5 8 bits 5 bits 2 bits t n 1 t ? ? = + + + ? for 20 modules with a 200kbps i 2 c master data rate, this is approximately 250 f s to perform a writeall com - mand for one register. packet-error checking (pec) the MAX11068 uses the smbus pec mechanism for maintaining data integrity. pec verifies stage-to-stage communication both in the write and read directions. during any write transaction, a device does not execute the write command internally unless the pec is received successfully by the lower port. the host can easily ignore the pec byte from a readall command if the host does not intend to support pec for read transac - tions. the only verification of a successful write trans - action that the host receives is through the ack bit following the pec byte returned from the first device in the smbus ladder. this bit indicates whether the first device received a valid write command. the success of the write command further up the chain is unknown to the host. if verification is critical, the host should fol - low up any write command with a readall to verify the write by checking the register that was updated or the alrtpec bit of the status register. the pec alert may also be enabled to trigger an alarm through the alrmpec bit of the adccfg register (address 0x08). if no alarms are present following the write command, the host can infer that the write command was successful to all attached devices. to support pec, the host must implement a crc-8 algo - rithm to perform calculations necessary for the pec byte. the crc-8 polynomial is: 8 2 c(x) x x x 1 = + + + all bytes including addresses, command codes, data, and for readall, the data check byte should be pro - cessed by the crc-8 algorithm as input bytes. start , repeated start , stop , and ack/nack bits are not included in the calculation. the bits should be pro - cessed in the order they are received with msb first. the logic implementation can be described as follows. first, the crc is initialized to zero for a new calculation. for each input byte, the byte is first xored with the crc value. this byte is called the remainder. the remainder is left shifted by 1 bit and is sent to a mux as itself or xored with the 8 least significant bits of the polynomial representation. the bit lost in the left-shift operation is able to be ignored because either it is a zero, or if it is a 1, it would be xored with the most significant bit of the polynomial representation to yield a 0. therefore, only bit name description 7 alrm set if the device is in an alarm condition, meaning the alrml pin is high. 6 0 unused, read as 0. 5 0 unused, read as 0. 4 0 unused, read as 0. 3 0 unused, read as 0. 2 0 unused, read as 0. 1 0 unused, read as 0. 0 pecerr during a readall command, the slave returns pecerr = 0 if the master received a valid pec. the slave returns pecerr = 1 if the master received an invalid pec or the master received pecerr = 1. in this way, the system can verify communication not only one layer at a time, but also across all layers.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 68 an 8-bit pipeline is shown for all parts of the circuit. the msb of the remainder controls a mux to select which operation is performed on the left-shifted version of the remainder byte. once the remainder is operated on, it is latched and fed back to the input of the shift register through another mux. this is repeated until eight left shifts have occurred. after eight left-shift operations have been processed, the process is repeated on the next input byte using the working crc value, which is the remainder following the left-shift operations. after all input bytes have been processed, the crc output byte is the final result. figure 42 shows a pseudo-code algo - rithm for the crc-8 logic that can be used in a software or firmware implementation. for write commands that require a pec byte, the host should perform this calculation on the byte sequence that is transmitted. in applications where processing time is extremely critical, it is possible to precalculate the crc value for the first few bytes of common com - mands, or sometimes even for full commands, and store these as constants. then, when those commands are used, the microcontroller can use the stored crc value for the precalculated portion of the message as an initial value and only calculate the portion of a message that may have changed in real time. this can save some pro - cessing time, although the pec algorithm is designed to require a relatively small amount of processing resources in most cases. for a readall command, the host should store the bytes of the received data stream, perform the pec calculation on the relevant bytes, and compare the results to the received pec byte. the pec may also be calculated as each byte is received instead of waiting for the entire message to arrive by storing the running crc value and passing it to the pec calculation function for each new byte. example pec calculation figure 43 shows a typical writeall command that is being sent by the host controller for which the pec byte must be calculated. figure 43 shows 4 bytes preceding the transmission of the pec byte. the first is the broadcast address, which is assumed to be the default of 0x40. the next byte 0x09 is the register address corresponding to the cellen register that is written. the last 2 bytes are the new val - ues of the register with the lsb first. the value of 0x03ff that is written corresponds to enabling the first 10 cells for measurement. these 4 bytes shown above represent all bits included in the pec byte calculation, and would comprise the bytelist() array from the previous pseudo- code algorithm. applying the bytes 0x40, 0x09, 0xff, and 0x03 in sequence to the crc algorithm yields a final crc result of 0x7f, which would be the value of the pec byte that the host should send immediately following the data msb. figure 42. example pseudo-code algorithm for a crc-8 pec calculation function pec_calculation(bytelist(), numberofbytes, crcbyte) { //crcbyte is typically initialized to 0 for each bytelist. if processing time //must be conserved, it is possible to precalculate the crcbyte valu e //for a known set of bytes at the beginning of a message. then, this //crcbyte value for the partial bytelist may be passed into the function //as the initial value along with the remaining bytes of the messag e //resulting in less computation steps. //loop once for each byte in the bytelist for counter1 = 0 to (numberofbytes ?1) ( //bitwise xor the current crc value with the bytelist byte remainder = crcbyte xor bytelist(counter1) //process each of the 8 remainder bits for counter2 = 8 to 1 step -1 ( //determine if msb = 1 prior to left shif t if (remainder and &h80) = &h80 then //when msb = 1, left shift and xor with 8 lsbs of the polynomia l remainder = ((remainder * 2) xor &h7) else //when msb = 0, left shift 1 bi t remainder = (remainder * 2) end if / /truncate the crc value to 8 bits remainder = remainder and &hff //proceed to the next remainder bi t next counter 2 ) crcbyte = remainder / /operate on the next data byte in the bytelist next counter1 ) return crcbyt e }
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 69 figure 43. example writeall bit stream prior to pec transmission power-on-reset (por) event a vaa voltage below the por threshold results in an internal device reset. in this state, the charge pump is disabled, as well as the digital logic. therefore, after vaa and vdd u have decayed below the power-on reset levels, i 2 c communication is ignored and is not forwarded. in some cases, a parasitic power path may exist to vdd l , and therefore vaa, through communi - cation pullup resistors or logic signals from the host. these paths typically supply vdd l at one diode drop below the pullup level. as long as the pullup level is no more than one diode drop above the por threshold, the entire device, including the digital logic remains in reset. supplying vaa or vdd l with a power source above the reset threshold can result in active operation, even though the regulator may be disabled. when the por is not active and vdd u and vdd l are valid, communica - tion proceeds as normal. alert and alarm status functions the MAX11068 offers a comprehensive system to inform the host controller of the devices status. this is done with status alerts and status alarms. status alerts are flag bits reporting various monitoring functions of the device. alerts can be divided into three main groups. cell moni - toring alerts are flags that report conditions related to the cell measurement. they include: u cell undervoltage threshold crossed (uvthrset) u cell overvoltage threshold crossed (ovthrset) u cell voltage mismatch threshold crossed (msmtch) u auxiliary channel temperature measurement thresh - old crossed (ainot, ainut) the second group of alert flags are communication errors. these flags report conditions related to the func - tioning of the smbus ladder. they include: u packet error checking (alrtpec) u acknowledge error (alrtack) the last group of alerts report operational failures of blocks of the ic. these flags aid in detecting conditions that signal if the device is operating correctly. they include: u reset status (rststat) u charge-pump failure (alrtcpuv) u heartbeat signal out of specification (alrthbeat) u voltage reference failure (alrtref) u lower +3.3v supply failure (alrtvddl) u lower gnd failure (alrtgndl) these alerts are activated when the configured thresh - olds are violated for a particular monitored condition or a particular function did not execute as expected. status alerts are indicated by individual flag bits in various reg - isters and must be read through the communication bus and processed by the host controller. status alarms are indicated using the alarm ladder bus comprising the alrm l and alrm u ports. an alarm is the result of an active alert that has been enabled to trigger an alarm. by monitoring the alarm bus with the system controller, the controller has nearly instant vis - ibility of critical status conditions. normally, this alarm bus carries a 16.384khz heartbeat signal from the top device in the smbus ladder to the bottom device. when an alarm is activated in a device, the alarming device pulls the alarm bus to logic high and interrupts the flow of the heartbeat signal. in this way, the alarm function acts as a high-priority interrupt signal to the host control - ler for critical events. bit stream for pec example calculation i 2 c bus link host to ic1 s i 2 c bus forwarding data strea m a a 01000000 00001001 a 11111111 00000011 a
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 70 the topmost device in an smbus ladder stackup is responsible for generating the heartbeat signal when it is not in an active alarm state and after the rststat bit has been cleared. the last device in the stack rec - ognizes itself as the top module when the last address bits of the address register (address 0x01) match its own device address. when this condition is true, usu - ally following the setlastaddress command, and the rststat bit is clear, the top device generates the heart - beat signal. this signal is propagated down the alarm bus and is only stopped if a device replaces it with an active alarm signal. the system controller should monitor the alrm u of the lowest device in the smbus ladder to determine whether an active alarm exists. the controller can then read the status of the smbus ladder to pinpoint the location of the alerts that triggered the alarm. the heartbeat signal propagated down the smbus ladder is received and monitored by the upper port alrm u pin according to figure 44. some alerts may be configured to trigger an alarm condition by using their alarm mask bits. this allows the application to choose which alerts should generate an alarm condition. figure 45 shows how status alert sig - nals and alarm mask bits work together to generate an alarm on the alarm bus. table 38 is a summary of all status alerts present in the MAX11068, the associated threshold levels or trigger condition, and the corresponding mask enable bits. alert bits are cleared by writing the bit to a logic zero unless they are automatically cleared when the alert condition subsides. clearing an alert bit that caused an alarm also clears the alarm. if multiple alerts or multiple devices are triggering an alarm condition, all alerts must be cleared before the heartbeat signal is again propa - gated to the host controller. when the system controller receives an active alarm indi - cation from the alarm bus, it must poll the smbus ladder stack to determine the source of the alarm. a readall command should be issued to read each register that contains alert bits that are enabled to trigger an alarm. after determining the source of the alarm, appropriate actions may be taken by the application. the system controller should periodically poll all registers with alert status bits to monitor the status of the MAX11068 smbus ladder. this ensures any important events are identified in a timely manner. figure 44. alrm u pin and alrthbeat block diagram figure 45. logic diagram of alert conditions and associated alarm enable bits divide by 8 rising edge detect up counter clock reset count < 13 count > 17 32.768khz alrm u clk latch alrthbeat alrm u alert status bit alarm mask enable bit alrm l
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 71 table 38. alert bits with descriptions and corresponding alarm mask bits alert status bit (register.bit) alert description alert threshold or trigger condition alert clear condition alarm mask enable bit (register.bit) status.rststat device reset occurred vaa < v por-fall write alert bit to 0 always enabled status.alrtov overvoltage was detected for at least one cell logical or of bits in the alrtovcell register disable active alert or remove the overvoltage condition adccfg.alrmoven status.alrtuv undervoltage was detected for at least one cell logical or of bits in the alrtuvcell register disable active alert or remove the undervoltage condition adccfg.alrmuven status.alrtmsmtch cell-voltage mismatch between min and max measurements maxcell - mincell > msmtch remove the cause of the mismatch or set the threshold to 0xfff0 to disable the comparison adccfg.alrmmmtchen status.alrttcold auxiliary input overvoltage/ undertemperature ain0 or ain1 > ainut disable the active alert or remove the overvoltage condition adccfg.alrmuten status.alrtthot auxiliary input undervoltage/ overtemperature ain0 or ain1 < ainot disable the active alert or remove the undervoltage condition adccfg.alrmoten status.alrtpec communication pec error pec byte checked for a received packet was incorrect write alert bit to 0 adccfg.alrmpec status.alrtack communication nack error a nack was received when an ack was expected write alert bit to 0 adccfg.alrmack status.alrtfmea at least one alert from fmea register is active logical or of the alert bits in the fmea register clear all alerts in the fmea register none status.alrtain2 auxiliary analog input 1 is outside one of the set thresholds ain1 > ainut or ain1 < ainot disable the active alert or remove the undervoltage or overvoltage condition and take a new measurement none
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 72 table 38. alert bits with descriptions and corresponding alarm mask bits (continued) alert status bit (register.bit) alert description alert threshold or trigger condition alert clear condition alarm mask enable bit (register.bit) status.alrtain1 auxiliary analog input 0 is outside one of the set thresholds ain0 > ainut or ain0 < ainot disable the active alert or remove the undervoltage or overvoltage condition and take a new measurement none alrtcell.alrtcell[n] specifies whether each cell has an overvoltage or undervoltage condition each bit [n] is a logical or of the corresponding bit in the alrtovcell and alrtuvcell registers set cell{n].oven and cell[n].uven to 0 or remove the overvoltage or undervoltage condition from the cell none; use the alrtov and alrtuv status bits as alarm triggers alrtovcell. alrtovcell[n] specifies whether each cell is in an overvoltage state cell[n] > ovthrset and cell[n].oven set to 1 set cell{n].oven to 0 or remove the overvoltage condition from the cell none; use the alrtov status bit as an alarm trigger alrtuvcell. alrtuvcell[n] specifies whether each cell is in an undervoltage state cell[n] < uvthrset and cell[n].uven set to 1 set cell{n].uven to 0 or remove the undervoltage condition from the cell none; use the alrtuv status bit as an alarm trigger fmea.alrtcpuv the charge-pump output vdd u has fallen below the undervoltage threshold vdd u - gnd u < v cpuv remove alert condition and write alert bit to 0 alert condition fmea.alrmcpuv fmea.alrthbeat alarm bus heartbeat signal is out of specification alrm l frequency is more than 12.5 % from nominal remove alert condition and write alert bit to 0 alert condition fmea.alrmhbeat fmea.alrtref ref pin is oscillating, most likely due to an open-circuit condition remove alert condition and write alert bit to 0 alert condition fmea.alrmref fmea.alrtvddl vdd l pin is open circuit vaa - vdd l > 0.3v typical remove alert condition and write alert bit to 0 alert condition fmea.alrmvddl fmea.alrtgndl gnd l pin is open circuit gnd l - agnd > 0.3v typical remove alert condition and write alert bit to 0 alert condition fmea.alrmgndl
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 73 figure 46. shutdown circuit interface shutdown control the shdn pin of the MAX11068 is connected in a man - ner that allows the shutdown/wakeup command to trickle up through the series of smbus-laddered packs. the propagation time is on the order of 3ms per module with the recommended shutdown circuit. the shutdown func - tion is intended to be a reset and power-saving mode for the entire ic. when coming out of shutdown mode, the device goes through the power-up sequence shown for the linear regulator once the shdn pin is above the inactive state threshold. the shutdown function must still operate when the vaa is shut down, so it cannot depend on a schmitt trigger. a special low-current, high-voltage circuit is used to detect the state of the shdn pin. the shutdown pin has a +1.8v threshold. when shdn > 1.8v, the MAX11068 turns on and begins regulating vdd u and vdd l . if shdn < 0.6v, the MAX11068 shuts down. figure 46 shows the shutdown circuit interface of two smbus ladder devices. when shdn is high for the device, the charge pump is enabled and begins to charge the capacitors in the interface circuit. when the voltage of the shdn pin for device (n+1) rises above the v ih threshold, that device begins its power-up sequence. this action propagates up the smbus ladder until the last battery module is enabled. conversely, pulling shdn to gnd l powers down a module and thus propagates the power down to all higher smbus-laddered modules as the charge on their shdn capacitors is dissipated. the zener diodes provide additional esd protection. the filter capacitors and resistors are sized to provide robust noise immunity. the diode from the cp+ pin should be s1b or a similar low-leakage type for high-temperature stability. the shdn pin is a high-voltage input rated to 60v. shdn may be tied to dcin through a resistor instead of using the interface circuit above for applications that do not require use of the shutdown mode. the resistor in that case is necessary for failure-mode effects analysis considerations. if shdn was shorted to the alrm l pin, the alrm l pin must be protected from seeing the full dcin voltage. a resistor value of 100k i is recommended to work across the entire dcin voltage range. the shdn pin has a weak internal pulldown resistor in the order of 12m i . so, a 200k i or similar resistor from shdn to gnd l should be installed to ensure that the shdn pin is pulled low when the active shdn signal is propagated up the smbus ladder. this resistor is not needed for applications that tie shdn high at all times. i 2 c smbus ladder initialization sequence when the MAX11068 becomes functional after any reset event, its i 2 c address, broadcast address, and place in the smbus ladder are set to a default value. prior to performing battery-monitoring tasks, each device must be configured to operate as part of the smbus ladder. the following configuration sequence (figure 47) is rec - ommended to initialize the system of smbus-laddered modules after a power cycle or change in the number of battery stack modules. first, the helloall command is sent to sequentially ini - tialize the individual device addresses. the first device address is specified in the command byte and should be chosen carefully based on the application require - ments. after a successful helloall command, the rollcall command should be sent. this reads the address register of all properly communicating mod - ules. when the host sees two consecutive 0xff bytes, meaning that all valid data has been received, it should send a nack and a stop bit to halt data flow. once the address register data is received, the host can determine how many devices are active on the bus. after ensuring that the number of active devices matches what is expected by the application, the host should send the setlastaddress command to configure the last device in the chain to be the heartbeat initiator. cp+ gnd u device (n) shdn gnd l device (n+1) 150i s1b 1ki 200ki 68nf 5.6v 5.6v 100nf
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 74 figure 47. communication initialization sequence following any reset event or module connection change MAX11068 fully functional MAX11068 communication initialized receive slave data unti l consecutive 0xff bytes , then nack the slave send setlastaddress command ack? alrtpec? clear status register bits to 0 heartbeat on alrm l at host? module count correct? send helloall command send rollcall command host calculates number of modules ack? nack nack ack yes no ack yes no nack yes no ack communication error system error system error communication error send setlastaddress command again communication error ack?
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 75 after the smbus ladder modules are configured for com - munication, they should be configured for operation: 1) perform a readall to check device status: a) the rststat bit should be set in all devices to signify a por event has occurred. b) the last device in the chain shows an alrtack fault because there is no device above it to acknowledge its communication. 2) clear the alrtack status for the last device using a writedevice or writeall command. 3) clear the rststat bit on all devices so that future power-cycle events can be detected. this also allows the last device in the daisy-chain to begin generating the heartbeat signal. 4) change configuration registers as necessary with writeall commands: a) change the broadcast address in register 0x0f if a different one is required. b) configure the undervoltage and overvoltage cell thresholds in registers 0x18 to 0x1b. c) configure the mismatch threshold if required in register 0x1c. d) configure the undertemperature and overtem - perature thresholds used for thermistor measure - ments, if required. e) configure the auxiliary input-acquisition settling time in the acqcfg register if necessary. f) enable the cell input channels that are used for measurement and enable auxiliary channels that are used. g) configure cell-voltage alert enables. h) set desired alarm enable flags in the adccfg and fmea registers. 5) when the device is fully configured, initiate a measure - ment conversion by setting bit 0 of the scanctrl register (address 0x0d). 6) when the first conversion is complete, process the cell and auxiliary input channel data and take any necessary actions. 7) continue monitoring the system status while initiating new measurements. changing the broadcast address if the default broadcast address must be changed for an application, the host should manage the process carefully since the readall and writeall commands rely on this address for proper operation. although a writeall command can be used to change the address at any time, it is recommended that a broadcast address change not be performed until after the smbus ladder is fully initialized so that subsequent rollcall or readall commands may be used to verify the address change for all devices. with the device in a fully initialized state, the new broad - cast address is written to the broadcast address register (address 0x0f) using a writeall command, although a series of writedevice commands may be used as well. prior to changing the broadcast address, the host should save the original address in case it is needed later in the process. once the writeall com - mand is issued, it must be verified. the most straightfor - ward way of accomplishing this is to issue a rollcall command and count the number of active devices using the new address. if the count matches what is expected, the broadcast address change was successful for all modules. if the count is incorrect, at least one device rejected the writeall command and the count signi - fies which module is not responding to the new address. a writedevice command may be used to rewrite to individual modules, or another writeall command may be sent to the old broadcast address. after updating the missing modules, the rollcall procedure should again be used to make sure all devices are responding to the new broadcast address. see figure 48.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 76 figure 48. broadcast address change procedure MAX11068 communication initialized host stores original broadcast address send rollcall command usin g new address proper acks? nack ack communication error send new broadcast address with writeall command to address 0x0f rewrite new broadcast address to register 0x0f of affected modules use module count to determine module needing update host calculates number of modules discard original broadcast addres s broadcast addres s change successful proper acks? nack module count correct no yes communication error
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 77 table 39. system fault modes failure mode and effects analysis high-voltage battery-pack systems can be subjected to severe stresses during in-service fault conditions and could experience similar conditions during the manufacturing and assembly process. the MAX11068 is designed with high regard to these potential states. open and short circuits at the package level must be readily detected for fault diagnosis and should be tolerated whenever possible. a number of circuits are employed within the MAX11068 specifically to detect such conditions and progress to a known device state. table 39 summarizes other conditions typical in a nor - mal manufacturing process along with their effect on the MAX11068 device. see table 40 for the failure-mode effects analysis of the MAX11068. condition effect design recommendation pcb or ic package open or short circuitno stack load see pin-level failure-mode effects analysis spreadsheet available from the factory the built-in features of the MAX11068 should ensure low failure-mode effects risk in most cases. random connection of cells to icno stack load no effect circuit design of figures 4 and 5 ensure protection against random power-supply or ground connections. random connection of modulesno stack load no effect each module is referenced to its neighbor, so no special connection order is necessary. random connect/disconnect of communication busno stack load; ac- or dc-coupled communication from host to the first break in the daisy-chain bus the level-shifted interface design of the MAX11068 ensures that the shdn , gnd u , alrm u communication bus can be connected at any time with no load. random connect/disconnect of communication buswith stack load; ac- or dc-coupled communication from host to the first break in the daisy-chain bus the level-shifted interface design of the MAX11068 ensures that the shdn , gnd u , alrm u communication bus can be connected at any time as long as the power bus is properly connected. connect/disconnect module interconnect (bus bar)no stack load no effect for dc- or ac-coupled communication bus a break in the power bus does not cause a problem as long as there is no load on the stack. removal/fault of module interconnect (bus bar)with stack load no effect for ac-coupled communication bus; device damage for dc-coupled bus an ac-coupled bus with isolation on the shdn pin or a redundant bus bar connection should be used to protect against this case. removal/fault of module interconnect (bus bar)with stack under charge no effect for ac-coupled communication bus; device damage for dc-coupled bus an ac-coupled bus with isolation on the shdn pin or a redundant bus bar connection should be used to protect against this case.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 78 table 40. failure-mode effects analysis pin name action effect 1 dcin open or disconnected i 2 c lost communication. no heartbeat. short to pin 2 alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. 2 cp+ open or disconnected alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. short to pin 3 alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. 3 cp- open or disconnected alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. short to pin 4 alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. 4 vdd u open or disconnected alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. short to pin 5 alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. 5 gnd u open or disconnected i 2 c lost communication. no heartbeat. alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. short to pin 6 the up-device cell registers are read back all 1. alrtack of the status register is set to 1. no effect for the single device or the top device. 6 scl u open or disconnected the up-device cell registers are read back all 1. alrtack and alrtpec of the status register are set to 1. no effect for the single device or the top device. short to pin 7 the up-device cell registers are read back all 1. no effect for the single device or the top device. 7 sda u open or disconnected the up-device cell registers are read back all 1. alrtack of the status register is set to 1. no effect for the single device or the top device. short to pin 8 alrtpec and alrtack of the status register are set to 1. the up-device cell registers are read back as the random number. no effect for the single device or the top device. 8 alrm u open or disconnected alrthbeat of the fmea register is set to 1. alrtfmea of the status register is set to 1. no heartbeat. no effect for the single device or the top device. short to pin 9 no effect. 9 n.c. open or disconnected no effect. short to pin 10 no effect. 10 gpio2 open or disconnected lost the input status or no drive capability. short to pin 11 if both gpio2 and gpio1 are configured as the input or the same status for the output, there is no effect. if they are configured as a different value as the output, it shows the output of 0v and the part is reset.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 79 table 40. failure-mode effects analysis (continued) pin name action effect 11 gpio1 open or disconnected lost the input status or no drive capability. short to pin 12 if both gpio1 and gpio0 are configured as the input or the same status for the output, there is no effect. if they are configured as a different value as the output, it shows the output of 0v and the part is reset. 12 gpio0 open or disconnected lost the input status or no drive capability. short to pin 13 if the gpio0 is configured as input or the high status for the output, there is no effect. if it is configured as low status for the output, the part is reset. 13 vdd l open or disconnected alrtvddl of the fmea register is set to 1. alrtfmea of the status register is set to 1. short to pin 14 i 2 c lost communication. no heartbeat. 14 gnd l open or disconnected i 2 c lost communication. short to pin 15 i 2 c lost communication. 15 scl l open or disconnected i 2 c lost communication. short to pin 16 i 2 c lost communication. 16 sda l open or disconnected i 2 c lost communication. short to pin 17 i 2 c lost communication. no heartbeat. 17 alrm l open or disconnected no heartbeat. short to pin 18 the result is dependent on the circuit that drives the shdn pin. if the circuit has strong drive capability (alrm l follows shdn ), the heartbeat goes away. otherwise the heartbeat is ok as the vaa charged faster than the discharge so the part keeps in the normal working mode. 18 shdn open or disconnected i 2 c lost communication as the device is shut down by the internal pulldown resistor. short to pin 19 the result is dependent on the circuit that drives the shdn pin and auxin2. 19 auxin2 open or disconnected the ain2 register is around 0. 20 thrm open or disconnected external temperature circuit lost the bias supply. so the ain0 and ain1 should be read as close to 0v. otherwise there is no effect. short to pin 21 the ain1 register is close to full scale (0xfff).
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 80 table 40. failure-mode effects analysis (continued) pin name action effect 21 auxin1 open or disconnected the ain1 register is around 0. short to pin 22 the result is dependent on the circuit setup of auxin1. if ref is driven to vaa, all the cell input measurements are lower by 1v. if ref is pulled low to agnd, cells 1 to 10 measurement results are all full scale (5v). the diag register changes to 0x296 from 0x5d4. 22 ref open or disconnected cells 1 to 12 measurement results vary from 3v to 5v. the diag register varies from 0x300 to 0x800. alrtref of the fmea register is set to 1, alrtfmea of the status register is set to 1. short to pin 23 cell 1 to 12 measurement results are all full scale (5v). the diag register changes to 0x296 from 0x5d4. 23 agnd open or disconnected no effect. short to pin 24 i 2 c lost communication and no heartbeat. 24 vaa open or disconnected alrtvddl of the fmea register is set to 1. alrtfmea of the status register is set to 1. short to pin 25 i 2 c lost communication and no heartbeat. 25 c0 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 26 v cell1 = 1v (3v lower). 26 c1 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 27 v cell2 = 0v. 27 c2 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 28 v cell3 = 0v. 28 c3 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 29 v cell4 = 0v. 29 c4 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 30 v cell5 = 0v. 30 c5 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 31 v cell6 = 0v.
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 81 table 40. failure-mode effects analysis (continued) package type package code document no. 38 tssop u38-1 21-0081 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status pin name action effect 31 c6 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 32 v cell7 = 0v. 32 c7 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 33 v cell8 = 0v. 33 c8 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 34 v cell9 = 0v. 34 c9 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 35 v cell10 = 0v. 35 c10 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 36 v cell11 = 0v. 36 c11 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 37 v cell12 = 0v. 37 c12 open or disconnected this situation can be detected by the cell sense line open-circuit detection feature. short to pin 38 alrtcpuv of the fmea register is set to 1. alrtfmea of the status register is set to 1. 38 hv open or disconnected v cell12 = 0.6v (3.4v lower).
12-channel, high-voltage sensor, smart data-acquisition interface MAX11068 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 82 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/10 initial release

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