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never stop thinking. hyb25l512160ac?7.5 hye25l512160ac?7.5 512mbit mobile-ram standard temperature range extended temperature range data sheet, rev. 1.2, feb. 2004 memory products
the information in this document is subject to change without notice. edition 2004-02 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hyb25l512160ac?7.5 hye25l512160ac?7.5 512mbit mobile-ram standard temperature range extended temperature range data sheet, rev. 1.2, feb. 2004 memory products
template: mp_a4_v2.3_2004-01-14.fm hyb25l512160ac?7.5 hye25l512160ac?7.5 revision history: rev. 1.2 2004-02 previous revision: rev. 1.1 2003-01 page subjects (major changes since last revision) 36-38 description of concurrent auto precharge feature modified; figures 40 to 43 added 47 corrected cas latency: f clk and t ac depend on v ddq and cas latency ( table 1 and table 20 ) 10 added v ddq 2.3..3.6v (table 4) 7 deleted function code, added cas latency 2 or 3 ( table 1 ) 18 delete note 1 44 add l/l and l/h deep & exit power down; h/l burst stop enter deep power down 16 chapter 3.2.2.2 description changed all new chapter organization all editorial changes we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hy[b/e]25l512160ac?7.5 512mbit mobile-ram data sheet 5 rev. 1.2, 2004-02 10212003-bspe-77ol 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 power on and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2.1.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1.3 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1.4 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2.1 partial array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2.2 temperature compensated self refresh (tcsr) with on-chip temperature sensor . . . . . . . . 16 3.3 state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4.1 no operation (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.2 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4.3 mode register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.4 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.5 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.5.1 read burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.5.2 clock suspend mode for read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.4.5.3 read - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.5.4 read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.5.5 read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.6 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.6.1 write burst termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.6.2 clock suspend mode for write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4.6.3 write - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.6.4 write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.7 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.4.8 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.8.1 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4.8.2 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.9 auto refresh and self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.9.1 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.9.2 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.4.10 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.4.10.1 deep power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5 function truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents
data sheet 6 rev. 1.2, 2004-02 hy[b/e]25l512160ac?7.5 512mbit mobile-ram figure 1 standard ballout 512m mobile-ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 block diagram of stacked configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 power-up sequence and mode register sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 extended mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7 state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 address / command inputs timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9 no operation command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 active command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 bank activate timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15 basic read timing parameters for dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16 single read burst (cas latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 17 single read burst (cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 18 consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19 random read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20 non-consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 21 terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 22 clock suspend mode for read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 23 read burst - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 24 read to write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 25 read to precharge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 26 write command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 27 basic write timing parameters for dqs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 28 write burst (cas latency = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 29 write burst (cas latency = 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 30 consecutive write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 31 random write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 32 non-consecutive write bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 33 terminating a write burs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 34 clock suspend mode for write bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 35 write burst - dqm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 36 write to read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 37 write to precharge timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 38 burst terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 39 precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 40 read with auto precharge interrupted by read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 41 read with auto precharge interrupted by write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 42 write with auto precharge interrupted by read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 43 write with auto precharge interrupted by write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 figure 44 auto refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 45 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 46 self refresh entry command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 47 self refresh entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 48 power down entry command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 49 power down entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 50 package fbga-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 list of figures
hy[b/e]25l512160ac?7.5 512mbit mobile-ram overview data sheet 7 rev. 1.2, 2004-02 10212003-bspe-77ol 1 overview 1.1 features 2 x 4 banks x 4 mbit x 16 organisation ( two 256mbit chips stacked in multi-chip package) fully synchronous to positive clock edge four internal banks for concurrent operation programmable cas latency: 2, 3 programmable burst length: 1, 2, 4, 8 or full page programmable wrap sequence: sequential or interleaved auto refresh and self refresh modes 8192 refresh cycles / 64ms auto precharge operating temperature range commerical (0c to +70c) extended (-25 o c to +85 o c) 54-ball fbga package (12.0 mm x 8.0 mm x 1.4 mm) power saving features: low supply voltages: v dd = 2.3v .. 3.6v, v ddq = 1.65v .. 1.95v or 2.3v .. 3.6v optimized self refresh (icc6) and standby currents (i cc2 / i cc3 ) programmable partial array self refresh (pasr) temperature compensated self-refresh (tcsr), controllable by on-chip temperature sensor power-down and deep power down modes table 1 performance part number speed code ?7.5 unit v ddq 1.65 ...1.95 2.3 ...3.6 v clock frequency ( f ckmax ) 105 133 mhz access time ( t acmax ) cl = 2 or 3 8.0 6.0 ns clock cycle time ( t ckmin )cl = 3 9.5 7.5 ns cl = 2 9.5 9.5 ns table 2 memory addressing scheme item addresses banks ba0, ba1 rows a0 - a12 columns a0 - a8
hy[b/e]25l512160ac?7.5 512mbit mobile-ram overview data sheet 8 rev. 1.2, 2004-02 10212003-bspe-77ol 1.2 description the hy[b/e]25l512160ac consists of two 256mbit high-speed cmos, dynamic random-access memories each of them containing 268,435,456 bits. each chip is internally configured as a quad-bank dram. the hy[b/e]25l512160ac achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. read and write accesses are burst-oriented; accesses start at a selected location and continue for a programmed number of locations (1, 2, 4, 8 or full page) in a programmed sequence. the device operation is fully synchronous: all inputs are registered at the positive edge of clk. the hy[b/e]25l512160ac is especially designed for mobile applications: it adds many features to save power, like low operating voltages. additionally, current consumption in self refresh mode can further be reduced by using the programmable partial array self refresh (pasr) and temperature compensated self refresh (tcsr). a conventional data-retaining power down (pd) mode is available as well as a non-data-retaining deep power down (dpd) mode. the hy[b/e]25l512160ac is housed in a 54-ball ?chip-size? fbga package. it is available in commercial (0c to 70c) and extended (-25 o c to +85 o c) temperature range. table 3 ordering information type 1) 1) hyb / hye: designator for memory products (hyb: standard temp. range; hye: extended temp. range) 25l: 2.5v mobile-ram 512: 512 mbit density 160: 16 bit interface width a: die revision c : lead-containing product description package commercial temperature range hyb25l512160ac?7.5 133 mhz 2 4 banks 4 mbit 16 lp-sdram fbga-54 extended temperature range hye25l512160ac?7.5 133 mhz 2 4 banks 4 mbit 16 lp-sdram fbga-54
hy[b/e]25l512160ac?7.5 512mbit mobile-ram pin configuration data sheet 9 rev. 1.2, 2004-02 10212003-bspe-77ol 2 pin configuration figure 1 standard ballout 512m mobile-ram note 1. 54 - ball fbga package (top view) figure 2 block diagram of stacked configuration mppd0050 a0 v ssq udqm clk dq14 dq12 dq10 dq8 dq15 v ddq v ssq v ddq v ss v ss a12 a11 a8 a6 a4 cke a9 a7 dq9 dq11 dq13 v ss 123 ba1 dq6 dq4 dq2 v dd 7 ldqs dq0 v ssq v ddq v ssq v dd ba0 a10/ap a1 a3 8 v dd v ddq dq1 dq3 dq5 dq7 9 a b c d f g h j e cas ras we cs0 a2 cs1 a5 mpbd1920 ldqm dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 udqm dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 d0 d1 cs0 cs1 ba0 - ba1: sdrams d0 - d1 a0 - a12: sdrams d0 - d1 ras: sdrams d0 - d1 cas: sdrams d0 - d1 we: sdrams d0 - d1 cke: sdrams d0 - 1 ba0 - ba1 a0 - a12 ras cas we cke0 cs ldqm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udqm i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 cs ldqm i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udqm i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15
hy[b/e]25l512160ac?7.5 512mbit mobile-ram pin configuration data sheet 10 rev. 1.2, 2004-02 10212003-bspe-77ol 2.1 pin description table 4 pin description symbol type function clk input clock: all inputs are sampled on the positive edge of clk. cke input clock enable: cke high activates and cke low deactivates internal clock signals, device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), active power-down (row active in any bank) or suspend (access in progress). input buffers, excluding clk and cke are disabled during power-down and self-refresh. cs (cs0 , cs1 ) input chip select: all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple memory banks. cs is considered part of the command code ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dq0 - dq15 i/o data inputs/output: bi-directional data bus (16 bit) dqm (ldqm, udqm) input input/output mask: input mask signal for write cycles and output enable for read cycles. for writes, dqm acts as a data mask when high. for reads, dqm acts as an output enable and places the output buffers in high-z state when high (two clocks latency) . ldqm corresponds to dq0 - dq7, udqm corresponds to dq8 - dq15. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an activate, read, write or precharge command is being applied. ba0, ba1 also determine which mode register is to be loaded during a mode register set command (mrs or emrs). a0 - a12 input address inputs: a0 - a12 define the row address during an active command cycle. a0 - a8 define the column address during a read or write command cycle. in addition, a10 (= ap) controls auto precharge operation at the end of the burst read or write cycle. during a precharge command, a10 (= ap) in conjunction with ba0, ba1 controls which bank(s) are to be precharged: if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1; if a10 is low, ba0, ba1 define the bank to be precharged. during mode register set commands, the address inputs hold the op-code to be loaded. v ddq supply i/o power supply: isolated power for dq output buffers for improved noise immunity: v ddq = 1.65v..1.95v; or 2.3v..3.6v v ssq supply i/o ground v dd supply power supply: power for the core logic and input buffers. v dd = 2.3v..3.6v v ss supply ground
hy[b/e]25l512160ac?7.5 512mbit mobile-ram pin configuration data sheet 11 rev. 1.2, 2004-02 10212003-bspe-77ol figure 3 functional block diagram cke clk cs ras cas we address register row address mux 13 13 13 refresh counter command decode mode registers control logic bank 0 row address latch & decoder 13 bank column logic column address counter / latch 9 bank 0 memory array (8192 x 512 x 16) sense amplifier 8192 io gating dqm mask logic column decoder 9 15 a0-a12 ba0,ba1 16 dq0- dq15 data output reg. data input reg. 16 ldqm udqm bank 1 bank 2 bank 3 2 2 2 2
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 12 rev. 1.2, 2004-02 10212003-bspe-77ol 3 functional description the 512 mbit mobile-ram consists of two 256mbit high-speed cmos, dynamic random-access memories each of them containing 268,435,456 bits. each chip is internally configured as a quad-bank dram. read and write accesses to the mobile-ram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the banks, a0 - a12 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the mobile-ram must be initialized. the following sections provide detailed information covering device initialization, register definition, command description and device operation. 3.1 power on and initialization the mobile-ram must be powered up and initialized in a predefined manner (see figure 4 ). operational procedures other than those specified may result in undefined operation. figure 4 power-up sequence and mode register sets no power sequencing is specified during power up or power down provided that one of the following two criteria is met: power-up: vdd and ck stable load mode register load ext. mode register = don't care ba0=l ba1=h t rfc t rfc t mrd t mrd t rp 200s t ck all banks dq high-z dqm ba0,ba1 nop ba a10 code nop ra code address code nop ra code command pre arf arf mrs nop nop act mrs cke vdd vddq clk ba0=l ba1=l
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 13 rev. 1.2, 2004-02 10212003-bspe-77ol v dd and v ddq are driven from a single power converter output v ddq is driven after or with v dd such that v ddq < v dd + 0.3 v after all power supply voltages are stable, and the clock is stable, the mobile-ram requires a 200s delay prior to applying a command other than deselect or nop. cke and dqm must be held high throughout the entire power-up sequence. once the 200s delay has been satisfied, the following command sequence shall be applied (see figure 4 ): a precharge all command; at least 8 auto refresh commands; two mode register set commands for the mode register and extended mode register following these cycles, the mobile-ram is ready for normal operation. 3.2 register definition 3.2.1 mode register the mode register is used to define the specific mode of operation of the mobile-ram. this definition includes the selection of a burst length, a burst type, a cas latency, and a write burst mode. the mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. figure 5 mode register definition address bits a0-a2 specify the burst length, a3 the burst type, a4-a6 the cas latency, a9 the write burst mode, while bits a7-a8 and a10-a12 shall be written to zero. a6 a5 a4 cas latency 000 reserved 001 010 2 011 3 100 reserved 101 110 111 a2 a1 a0 burst length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 100 reserved reserved 101 110 1 1 1 full page a9 write burst mode 0burst write 1 single write ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 0 0 0 0 0 wb 0 0 cas latency bt burst length mode register a3 burst type 0 sequential 1 interleave
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 14 rev. 1.2, 2004-02 10212003-bspe-77ol the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements results in unspecified operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. 3.2.1.1 burst length read and write accesses to the mobile-ram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, 8 locations are available for both the sequential and interleaved burst types, and a full-page burst mode is available for the sequential burst type. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-a8 when the burst length is set to two, by a2-a8 when the burst length is set to four and by a3-a8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full page bursts wrap within the page if the boundary is reached. please note that full page bursts do not self- terminate; this implies that full-page read or write bursts with auto precharge are not legal commands. note: 1. for a burst length of two, a1-ai select the two-data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-ai select the four-data-element block; a0-a1 select the first access within the block. 3. for a burst length of eight, a3-ai select the eight-data-element block; a0-a2 select the first access within the block. 4. for a full page burst, a0-ai select the starting data element. 5. whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. table 5 burst definition burst length starting column address order of accesses within a burst a2 a1 a0 sequential interleaved 200 - 10 - 1 11 - 0 1 - 0 4 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 full page n n n cn, cn+1, cn+2, ... not supported
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 15 rev. 1.2, 2004-02 10212003-bspe-77ol 3.2.1.2 burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 5 . 3.2.1.3 cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be programmed to 2 or 3 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available with clock edge n + m (for details please refer to the read command description). 3.2.1.4 write burst mode when a9 = 0, the burst length programmed via a0-a2 applies to both read and write bursts; when a9 = 1, write accesses consist of single data elements only. 3.2.2 extended mode register the extended mode register controls additional low power features of the device. these include the partial array self refresh (pasr) and the temperature compensated self refresh (tcsr). the extended mode register is programmed via the mode register set command (with ba0 = 0 and ba1 = 1) and will retain the stored information until it is programmed again or the device loses power. the extended mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating any subsequent operation. violating either of these requirements result in unspecified operation. figure 6 extended mode register definition address bits a0-a2 specify the partial array self refresh (pasr) and bits a3-a4 the temperature compensated self refresh (tcsr), while bits a5-a12 shall be written to zero. a4 a3 tcsr 00 70c 01 45c 10 15c 11 85c a2 a1 a0 pasr 0 0 0 all banks 0 0 1 1/2 array (ba1 = 0) 0 1 0 1/4 array (ba1 = ba0 = 0) 011 reserved 100 reserved 101 1/8 array (ba1 = ba0 = ra12 = 0) 110 1/8 array (ba1 = ba0 = ra12 = ra11 = 0) 111 reserved ba1 ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address bus 1000000000 tcsr pasr mode register
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 16 rev. 1.2, 2004-02 10212003-bspe-77ol 3.2.2.1 partial array self refresh (pasr) partial array self refresh is power-saving feature specific to mobile-rams. with pasr, self refresh may be restricted to variable portions of the total array. the selection comprises all four banks (default), two banks, one bank, half a bank, and a quarter of one bank. data written to the non activated memory sections will get lost after a period defined by t ref (cf. table 13 ). 3.2.2.2 temperature compensated self re fresh (tcsr) with on-chip temperature sensor dram devices store data as a electrical charge in tiny capacitors that require a periodic refresh in order to retain the stored information. this refresh requirement heavily depends on the die temperature: high temperature corresponds to short refresh period, and low temperature to long refresh period. the mobile-ram is equipped with an on-chip temperature sensor which continuously monitors the current die temperature and adjusts the refresh period in self refresh mode accordingly. by default the on-chip temperature sensor is enabled (tcsr = 00, see figure 6 ); the other three tcsr settings use defined temperature values to adjust the self refresh period with the on-chip temperature sensor being disabled.
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 17 rev. 1.2, 2004-02 10212003-bspe-77ol 3.3 state diagram figure 7 state diagram power on mode register set power applied deep power down dpdsx mrs act self refresh refs refsx idle dpds auto refresh refa active power down ckeh ckel row active w r i t e read write a read a precharge read reada writea reada writea pre read a pre automatic sequence command sequence clock suspend read clock suspend reada clock suspend write clock suspend writea r e a d b s t b s t ckel ckel ckel ckel ckeh ckeh ckeh ckeh preall = precharge all banks refs = enter self refresh refsx = exit self refresh refa = auto refresh dpds = enter deep power down dpdsx = exit deep power down ckel = enter power down ckeh = exit power down read = read w/o auto precharge reada = read with auto precharge write = write w/o auto precharge writea = write with auto precharge precharge all preall ckel ckeh precharge power down write writea write pre pre act = active pre = precharge bst = burst terminate mrs = mode register set
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 18 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4 commands address (a0 - a12, ba0, ba1), write data (dq0 - dq15) and command inputs (cke, cs , ras , cas , we , dqm) are all registered on the positive edge of clk. figure 8 shows the basic timing parameters, which apply to all commands and operations. figure 8 address / command inputs timing parameters table 6 command overview command cs ras cas we dqm address notes nop deselect h x x x x x 1) 1) deselect and nop are functionally interchangeable. no operation l h h h x x 1) act active (select bank and row) l l h h x bank / row 2) 2) ba0, ba1 provide bank address, and a0 - a12 provide row address. rd read (select bank and column and start read burst) l h l h l/h bank / col 3) 3) ba0, ba1 provide bank address, a0 - a8 provide column address; a10 high enables the auto precharge feature (nonpersistent), a10 low disables the auto precharge feature. wr write (select bank and column and start write burst) l h l l l/h bank / col 3) bst burst terminate or deep power down lh h l x x 4) 4) this command is burst terminate if cke is high; deep power down if cke is low. the burst terminate command is defined for read or write bursts with auto precharge disabled only. pre precharge (deactivate row in bank or banks) l l h l x code 5) 5) a10 low: ba0, ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0, ba1 are ?don?t care?. arf auto refresh or self refresh (enter self refresh mode) ll l h x x 6)7) 6) this command is auto refresh if c ke is high; self refresh if cke is low. 7) internal refresh counter controls row and bank addressing; all inputs and i/os are ?don?t care? except for cke. mrs mode register set l l l l x op-code 8) 8) ba0, ba1 select either the mode register (ba0 = 0, ba1 = 0) or the extended mode register (ba0 = 0, ba1 = 1); other combinations of ba0, ba1 are reserved; a0 - a12 provide the op-code to be written to the selected mode register. ? data write / output enable ?? ? ? l ? 9) 9) dqm low: data present on dqs is written to memory during write cycles; dq output buffers are enabled during read cycles; dqm high: data present on dqs are masked and thus not written to memory during write cycles; dq output buffers are placed in high-z state (two clocks latency) during read cycles. ? write mask / output disable (high-z) ?? ? ? h ? 9) = don't care t cl t ch t is t ih t ck *) = a0 - a12, ba0, ba1, dq0 - dq15, dqm, ras, cas, we, cke, cs clk input *) valid valid valid
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 19 rev. 1.2, 2004-02 10212003-bspe-77ol due to shared command, clk and cke pins of this stacked configuration, commands issued to one chip may also impact the state of the second chip, even if that chip is actually deselected. details can be found in the command descriptions below. 3.4.1 no operation (nop) figure 9 no operation command the no operation (nop) command is used to perform a nop to a mobile-ram which is selected (cs = low). this prevents unwanted commands from being registered during idle states. operations already in progress are not affected. 3.4.2 deselect the deselect function (cs = high) prevents new commands from being executed by the mobile-ram. the mobile-ram is effectively deselected. operations already in progress are not affected. when issuing an access command to one chip of this stacked configuration, the other chip shall be deselected by asserting its corresponding cs pin high. table 7 inputs timing parameters parameter symbol ?7.5 unit notes min max clock cycle time v ddq = 2.3v .. 3.6v cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns ? v ddq = 1.65v .. 1.95v cl = 2 or 3 9.5 ? ns ? clock frequency v ddq = 2.3v .. 3.6v cl = 3 f ck ? 133 mhz ? v ddq = 1.65v .. 1.95v cl = 2 or 3 f ck ? 105 mhz clock high-level width t ch 2.5 ? ns clock low-level width t cl 2.5 ? ns address, data and command input setup time t is 1.5 ? ns address, data and command input hold time t ih 0.8 ? ns = don't care we cas cs cke (high) clk a0-a12 ba0,ba1 ras
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 20 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.3 mode register set figure 10 mode register set command the mode registers are loaded via inputs a0 - a12 (see mode register descriptions in chapter 3.2 ). the mode register set command can only be issued when all banks are idle and no bursts are in progress. a subsequent execucommand cannot be issued until t mrd is met. the command may be issued to both chips in parallel (cs0 = cs1 = 0). figure 11 mode register definition = don't care cs cke (high) clk a0-a12 code ba0,ba1 code we cas ras table 8 timing parameters for mode register set command parameter symbol ? 7.5 unit notes min. max. mode register set command period t mrd 2?t ck code = mode register / extended mode register selection (ba0, ba1) and op-code (a0 - a12) t mrd = don't care clk command mrs nop valid address code valid
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 21 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.4 active figure 12 active command before any read or write commands can be issued to a bank within the mobile-ram, a row in that bank must be ?opened? (activated). this is accomplished via the active command and addresses a0 - a12, ba0 and ba1 (see figure 12 ), which decode and select both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active commands to the same bank is defined by t rc . a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active commands to different banks is defined by t rrd . figure 13 bank activate timings = don't care ba = bank address ra = row address ba0,ba1 ba a0-a12 ra we cas ras cs cke (high) clk table 9 timing parameters for mode register set command parameter symbol ? 7.5 unit notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period ; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active bank a to active bank b delay t rrd 15 ? ns 1) t rrd t rcd = don't care clk rd/wr nop nop nop act nop act command row row col a0-a12 ba x ba y ba y ba0, ba1
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 22 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.5 read figure 14 read command subsequent to programming the mode register with cas latency and burst length, read bursts are initiated with a read command, as shown in figure 14 . basic timings for the dqs are shown in figure figure 15 ; they apply to all read operations and therefore are omitted from all subsequent timing diagrams. in order to prevent bus contention on the dqs, care must be taken that a read issued to one chip does not interfere with a read or write being in progress in the other chip of this stacked configuration. figure 15 basic read timing parameters for dqs ba0,ba1 ba we cke (high) clk ras cas a0-a8 ca = don't care ba = bank address ca = column address ap = auto precharge a10 ap disable ap enable ap cs t lz t ac t ac t hz clk = don't care t dqz t oh t oh dqm dq do n+1 do n
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 23 rev. 1.2, 2004-02 10212003-bspe-77ol the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed starts precharge at the completion of the burst, provided t ras has been satisfied. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address is available following the cas latency after the read command. each subsequent data-out element is valid nominally at the next positive clock edge. upon completion of a read burst, assuming no other read command has been initiated, the dqs go to high-z state. figure 16 and figure 17 show single read bursts for each supported cas latency setting. figure 16 single read burst (cas latency = 2) table 10 timing parameters for read parameter symbol ? 7.5 unit notes min. max. access time from clk v ddq = 2.3v .. 3.6v t ac ? 6.0 ns 1) 1) t ac depends on v ddq range; no dependency on cas latency setting v ddq = 1.65v .. 1.95v t ac ? 8.0 ns 1) dq low-impedance time from clk t lz 1.0 ? ns dq high-impedance time from clk t hz 3.0 7.0 ns data out hold time t oh 3.0 ? ns dqm to dq high-z delay (read commands) t dqz ? 2 t ck active to active command period t rc 67 ? ns 2) 2) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period ; round up to next integer. active to read or write delay t rcd 19 ? ns 2) active to precharge command period t ras 45 100k ns 2) precharge command period t rp 19 ? ns 2) ba a, col n = bank a, column n do n = data out from column n burst length = 4 in the case shown. 3 subsequent elements of data out are provi ded in the programmed order following do n. = don't care cl=2 t rcd t ras t rc t rp clk command nop read nop nop nop pre nop act act address ba a, row b ba a, col n ba a, row x a10 (ap) pre bank a pre all dis ap row x row b ap do n+1 do n do n+2 do n+3 dq ap = auto precharge dis ap = disable auto precharge
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 24 rev. 1.2, 2004-02 10212003-bspe-77ol figure 17 single read burst (cas latency = 3) data from any read burst may be concatenated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. a read command can be initiated on any clock cycle following a previous read command, and may be performed to the same or a different (active) bank. the first data element from the new burst follows either the last element of a completed burst ( figure 18 ) or the last desired data element of a longer burst which is being truncated ( figure 19 ). the new read command should be issued x cycles after the first read command, where x equals the number of desired data elements. please note that truncation of a read burst by a subsequent read or write is only possible when both commands are issued to the same chip of this stacked configuration. figure 18 consecutive read bursts ba a, col n = bank a, column n do n = data out from column n burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n. = don't care cl=3 t rcd t rp t ras t rc command nop read nop nop nop pre nop act act nop nop clk ap = auto precharge dis ap = disable auto precharge address a10 (ap) pre bank a pre all dis ap dq do n+1 do n do n+2 do n+3 ba a, row b row b ba a, row x row x ba a, col n ap ba a, col n (b) = bank a, column n (b) do n (b) = data out from column n (b) burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n (b). = don't care clk cl=2 cl=3 command nop read nop nop nop nop nop read nop address ba a, col b ba a, col n dq do n+1 do n do n+2 do n+3 do b+2 do b do b+1 dq do n+1 do n do n+2 do n+3 do b+1 do b
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 25 rev. 1.2, 2004-02 10212003-bspe-77ol figure 19 random read bursts non-consecutive read bursts are shown in figure 20 . figure 20 non-consecutive read bursts ba a, col n etc. = bank a, column n etc. do n etc. = data out from column n etc. burst length = 4 in the case shown; bursts are terminated by consecutive read commands 3 subsequent elements of data out are provi ded in the programmed order following do m. = don't care clk cl=2 cl=3 command read nop nop nop nop read read read nop ba a, col n ba a, col a ba a, col x ba a, col m address dq do m+2 do m+3 do a do n do x do m+1 do m dq do m+2 do a do n do x do m+1 do m ba a, col n (b) = bank a, column n (b) do n (b) = data out from column n (b) burst length = 4 in the case shown. 3 subsequent elements of data out are provided in the programmed order following do n (b). cl=2 cl=3 = don't care clk command nop read nop nop nop nop nop read nop ba a, col n address ba a, col b dq do n+1 do n do n+2 do n+3 do b+1 do b dq do n+1 do n do n+2 do n+3 do b
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 26 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.5.1 read burst termination data from any read burst may be truncated using the burst terminate command (see page 35 ), provided that auto precharge was not activated. the burst terminate latency is equal to the cas latency, i.e. the burst terminate command must be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency for read bursts minus 1. this is shown in figure 21 . the burst terminate command may be used to terminate a full-page read which does not self-terminate. figure 21 terminating a read burst 3.4.5.2 clock suspend mode for read cycles clock suspend mode allows to extend any read burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse(s) will be ignored and data on dq will remain driven, as shown in figure 22 . figure 22 clock suspend mode for read bursts ba a, col n = bank a, column n do n = data out from column n burst length = 4 in the case shown. 2 subsequent elements of data out are provi ded in the programmed order following do n. the burst is terminated after the 3rd data element. = don't care clk cl=2 cl=3 command nop read nop nop nop nop nop bst nop address ba a, col n dq do n+1 do n do n+2 dq do n+1 do n do n+2 ba a, col n etc. = bank a, column n etc. do n etc. = data out from column n etc. cl = 2 in the case shown clock suspend latency t csl is 1 clock cycle = don't care clk t csl t csl t csl cke internal clock command read nop nop nop nop nop ba a, col n address dq do n+2 do n do n+1 do n+1
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 27 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.5.3 read - dqm operation dqm may be used to suppress read data and place the output buffers into high-z state. the generic timing parameters as listed in table 10 also apply to this dqm operation. the read burst in progress is not affected and will continue as programmed. figure 23 read burst - dqm operation 3.4.5.4 read to write a read burst may be followed by or truncated with a write command. the write command can be performed to the same or a different (active) bank. care must be taken to avoid bus contention on the dqs; therefore it is recommended that the dqs are held in high-z state for a minimum of 1 clock cycle. this can be achieved by either delaying the write command, or suppressing the data-out from the read by pulling dqm high two clock cycles prior to the write command, as shown in figure 24 . with the registration of the write command, dqm acts as a write mask: when asserted high, input data will be masked and no write will be performed. please note that truncation of a read burst by a subsequent read or write is only possible when both commands are issued to the same chip of this stacked configuration. ba a, col n = bank a, column n do n = data out from column n cl = 2 in the case shown. dqm read latency t dqz is 2 clock cycles = don't care clk command nop read nop nop nop nop nop nop dqm t dqz address ba a, col n dq do n+2 do n do n+3
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 28 rev. 1.2, 2004-02 10212003-bspe-77ol figure 24 read to write timing 3.4.5.5 read to precharge a read burst may be followed by, or truncated with a precharge command to the same bank (provided that auto precharge was not activated), as shown in figure 25 . the precharge command should be issued x clock cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency for read bursts minus 1. following the precharge command, a subsequent active command to the same bank cannot be issued until t rp is met. please note that part of the row precharge time is hidden during the access of the last data elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 25 read to precharge timing ba a, col n (b) = bank a, column n (b) do n = data out from column n; di b = data in to column b; dqm is asserted high to set dqs to high-z state for 1 clock cycle prior to the write command. = don't care clk cl=2 cl=3 command nop read nop nop nop nop nop write address ba a, col b ba a, col n dqm dq do n di b di b+1 do n+1 high-z di b+2 dq di b di b+1 do n high-z di b+2 ba a, col n = bank a, column n; ba am row = bank a, row x do n = data out from column n burst length = 4 in the case shown. cas latency = 3 in the case shown 3 subsequent elements of data out are provi ded in the programmed order following do n. = don't care cl=3 clk t rp command nop read nop nop nop nop act pre ba a, row a address ba a ba a, col n dis ap pre bank a pre all a10 (ap) ap dq do n+1 do n do n+2 do n+3
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 29 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.6 write figure 26 write command write bursts are initiated with a write command, as shown in figure 26 . basic timings for the dqs are shown in figure 27 ; they apply to all write operations. figure 27 basic write timing parameters for dqs the starting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the write burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element is registered coincident with the write command, and subsequent data elements are registered on each successive positive edge of clk. upon completion of a burst, assuming no other commands have been initiated, the dqs remain in high-z state, and any additional input data is ignored. figure 28 and figure 29 show a single write burst for each supported cas latency setting. ba0,ba1 ba cs cke (high) clk ras cas a0-a8 ca = don't care ba = bank address ca = column address ap = auto precharge a10 ap disable ap enable ap we clk = don't care t is t ih t is t ih dqm dq di n di n+2
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 30 rev. 1.2, 2004-02 10212003-bspe-77ol figure 28 write burst (cas latency = 2) table 11 timing parameters for write parameter symbol ?7.5 unit notes min. max. dq and dqm input setup time t is 1.5 ? ns ? dq and dqm input hold time t ih 0.8 ? ns ? dqm write mask latency t dqw 0 ? t ck ? active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. active to read or write delay t rcd 19 ? ns 1) active to precharge command period t ras 45 100k ns 1) write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1) ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n. = don't care clk t rcd t ras t rc t rp t wr command nop write nop nop nop pre nop act act nop address ba a, row x ba a, col n ba a, row b row x row b dis ap ap pre bank a pre all a10 (ap) dq di n di n+2 di n+3 di n+1
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 31 rev. 1.2, 2004-02 10212003-bspe-77ol figure 29 write burst (cas latency = 3) data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. a write command can be issued on any positive edge of clock following the previous write command. the first data element from the new burst is applied after either the last element of a completed burst ( figure 30 ) or the last desired data element of a longer burst which is being truncated ( figure 31 ). the new write command should be issued x cycles after the first write command, where x equals the number of desired data elements. please note that truncation of a write burst by a subsequent read or write is only possible when both commands are issued to the same chip of this stacked configuration. figure 30 consecutive write bursts ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n. = don't care t rcd t ras t rc t rp t wr clk command nop write nop nop nop pre nop act act nop nop nop address ba a, row n ba a, col n ba a, row b pre bank a pre all row x dis ap ap row b a10 (ap) dq di n di n+2 di n+3 di n+1 ba a, col n (b) = bank a, column n (b) di n (b) = data in to column n (b) burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n (b). command nop nop nop nop nop nop nop write write clk address ba a, col b ba a, col n dq di n di n+1 di n+2 di n+3 di b di b+1 di b+2 di b+3 = don't care
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 32 rev. 1.2, 2004-02 10212003-bspe-77ol figure 31 random write bursts non-consecutive write bursts are shown in figure 32 figure 32 non-consecutive write bursts 3.4.6.1 write burst termination data from any write burst may be truncated using the burst terminate command (see page 35 ), provided that auto precharge was not activated. the input data provided coincident with the burst terminate command will be ignored. this is shown in figure 33 . the burst terminate command may be used to terminate a full-page write which does not self-terminate. ba a, col n etc. = bank a, column n etc. di n etc. = data in to column n etc. burst length = 4 in the case shown; bursts are terminated by consecutive write commands. 3 subsequent elements of data in are provided in the programmed order following di m . = don't care clk command nop nop nop nop nop write write write write address ba a, col m ba a, col x ba a, col a ba a, col n dq di n di a di x di m di m+1 di m+2 di m+3 ba a, col n (b) = bank a, column n (b) di n (b) = data in to column n (b) burst length = 4 in the case shown. 3 subsequent elements of data in are provided in the programmed order following di n (b). = don't care clk write command nop nop nop nop nop nop nop write ba a, col n address ba a, col b di b dq di n di n+1 di n+2 di n+3 di b+1 di b+2
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 33 rev. 1.2, 2004-02 10212003-bspe-77ol figure 33 terminating a write burs 3.4.6.2 clock suspend mode for write cycles clock suspend mode allows to extend any write burst in progress by a variable number of clock cycles. as long as cke is registered low, the following internal clock pulse(s) will be ignored and no data will be captured, as shown in figure 34 . figure 34 clock suspend mode for write bursts ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 2 subsequent elements of data in are written in the programmed order following di n. the burst is terminated after the 3rd data element. = don't care clk command nop nop bst nop nop write nop address ba a, col n dq di n di n+1 di n+2 ba a, col n etc. = bank a, column n etc. do n etc. = data out from column n etc. cl = 2 in the case shown clock suspend latency t csl is 1 clock cycle clk cke internal clock command nop nop nop write nop ba a, col n address dq di n+2 di n di n+1 = don't care t csl t csl t csl
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 34 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.6.3 write - dqm operation dqm may be used to mask write data: when asserted high, input data will be masked and no write will be performed. the generic timing parameters as listed in table 11 also apply to this dqm operation. the write burst in progress is not affected and will continue as programmed. figure 35 write burst - dqm operation 3.4.6.4 write to read a write burst may be followed by, or truncated with a read command. the read command can be performed to the same or a different (active) bank. with the registration of the read command, data inputs will be ignored and no write will be performed, as shown in figure 36 . please note that truncation of a write burst by a subsequent read or write is only possible when both commands are issued to the same chip of this stacked configuration. figure 36 write to read timing ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are pr ovided in the programmed order following di n, with the first element (di n+1) being masked. dqm write latency is 0 clock cycles. = don't care clk command nop nop nop nop nop write address ba a, col n dqm dq di n di n+2 di n+3 ba a, col n (b) = bank a, column n (b) di n = data in to column n; do b = data out from column b; burst length = 4 in the case shown. 3 subsequent elements of data in (out) are provi ded in the programmed order following di n (do b). di n+3 is ignored due to read command. no dqm masking required at this point. = don't care clk write data are ignored cl=2 cl=3 command nop read nop nop nop nop nop write address ba a, col b ba a, col n dq do b do b+1 do b+2 di n di n+1 di n+2 high-z dq do b di b+1 di n di n+1 di n+2 high-z
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 35 rev. 1.2, 2004-02 10212003-bspe-77ol write to precharge a write burst may be followed by, or truncated with a precharge command to the same bank (provided that auto precharge was not activated), as shown in figure 37 . the precharge command should be issued t wr after the clock edge at which the last desired data element of the write burst was registered. additionally, when truncating a write burst, dqm must be pulled to mask input data presented during t wr prior to the precharge command. following the pre-charge command, a subsequent active command to the same bank cannot be issued until t rp is met. in the case of a write being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same write burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address busses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts. figure 37 write to precharge timing 3.4.7 burst terminate . figure 38 burst terminate command the burst terminate command is used to truncate read or write bursts (with auto precharge disabled). the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in figure 21 and figure 33 , respectively ba a, col n = bank a, column n di n = data in to column n burst length = 4 in the case shown. 3 subsequent elements of data in are provi ded in the programmed order following di n. di n+3 is masked due to dqm pulled high during t wr period prior to precharge command. = don't care dq di n di n+1 di n+2 t rp t wr clk dqm command nop nop nop nop nop act pre write address ba a, col n ba a, row a ba a dis ap pre bank a pre all a10 (ap) ap ap = auto precharge dis ap = disable auto precharge = don't care cas cs cke (high) clk a0-a12 ba0,ba1 we ras
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 36 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.8 precharge figure 39 precharge command the precharge command is used to deactivate (close) the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time (t rp ) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. 3.4.8.1 auto precharge auto precharge is a feature which performs the same individual-bank precharge functions described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge (t rp ) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type. ba0,ba1 ba cs cke (high) clk = don't care ba = bank address (if a10 = l, otherwise don't care) ras cas we a10 one bank all banks a0-a9 a11,a12 table 12 timing parameters for precharge parameter symbol ? 7.5 units notes min. max. active to precharge command period t ras 45 100k ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. write recovery time t wr 14 ? ns 1) precharge command period t rp 19 ? ns 1)
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 37 rev. 1.2, 2004-02 10212003-bspe-77ol 3.4.8.2 concurrent auto precharge a read or write burst with auto precharge enabled can be interrupted by a subsequent read or write command issued to a different bank. figure 40 shows a read with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the read to bank m will interrupt the read to bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered. figure 41 shows a read with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin when the write to bank m is registered. dqm should be pulled high two clock cycles prior to the write to prevent bus contention. figure 42 shows a write with auto precharge to bank n, interrupted by a read (with or without auto precharge) to bank m. the precharge to bank n will begin t wr after the new command to bank m is registered. the last valid data-in to bank n is one clock cycle prior to the read to bank m. figure 43 shows a write with auto precharge to bank n, interrupted by a write (with or without auto precharge) to bank m. the precharge to bank n will begin t wr after the write to bank m is registered. the last valid data-in to bank n is one clock cycle prior to the write to bank m. figure 40 read with auto precharge interrupted by read figure 41 read with auto precharge interrupted by write rd-ap = read with auto precharge; read = read with or without auto precharge cl = 2 and burst length = 4 in the case shown read with auto precharge to bank n is interrupted by subsequent read to bank m = don't care cl=2 clk command rd-ap nop nop nop read nop nop nop address bank n col b bank m col x dq do b+1 do b do x do x+1 do x+2 t rp (bank n) rd-ap = read with auto precharge; write = write with or without auto precharge cl = 2 and burst length = 4 in the case shown read with auto precharge to bank n is interrupted by subsequent write to bank m = don't care cl=2 dqm clk command nop rd-ap nop nop nop nop write nop address bank m col x bank n col b dq do b di x+1 di x+2 di x+3 di x t rp (bank n)
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 38 rev. 1.2, 2004-02 10212003-bspe-77ol figure 42 write with auto precharge interrupted by read figure 43 write with auto precharge interrupted by write 3.4.9 auto refresh and self refresh the mobile-ram requires a refresh of all rows in a rolling interval. each refresh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode. 3.4.9.1 auto refresh figure 44 auto refresh command auto refresh is used during normal operation of the mobile-ram. the command is nonpersistent, so it must be issued each time a refresh is required. a minimum row cycle time (t rc ) is required between two auto refresh commands. the same rule applies to any access command after the auto refresh operation. all banks must be precharged prior to the auto refresh command. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the mobile-ram requires auto refresh cycles at an average periodic interval of 7.8 s (max.). partial array mode has no influence on auto refresh mode. wr-ap = write with auto precharge; read = read with or without auto precharge cl = 2 and burst length = 4 in the case shown write with auto precharge to bank n is interrupted by subsequent read to bank m = don't care clk command nop nop nop read nop address bank n col b bank m col x nop nop wr-ap t wr (bank n) t rp (bank n) dq do x do x+1 do x+3 do b+1 do b do x+2 cl=2 wr-ap = write with auto precharge; write = write with or without auto precharge burst length = 4 in the case shown write with auto precharge to bank n is interrupted by subsequent write to bank m = don't care clk t rp (bank n) t wr (bank n) command nop nop nop write nop wr-ap nop nop address bank n col b bank m col x dq di b+1 di b di x di x+1 di x+1 di x+1 = don't care cs cke (high) clk a0-a12 ba0,ba1 cas we ras
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 39 rev. 1.2, 2004-02 10212003-bspe-77ol figure 45 auto refresh 3.4.9.2 self refresh figure 46 self refresh entry command the self refresh command can be used to retain data in the mobile-ram, even if the rest of the system is powered down. when in the self refresh mode, the mobile-ram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is low. input signals except cke and clk are ?don?t care? during self refresh. clk pin may not float. the self refresh command may be issued to both chips at the same time (cs0 = cs1 = 0). the procedure for exiting self refresh requires a stable clock prior to cke returning high. once cke is high, nop commands must be issued for t rc because time is required for a completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended. ba a, row n = bank a, row n t rp t rc t rc = don't care dq high-z a10 (ap) row n pre all address ba a, row n command nop arf nop nop nop nop pre arf act clk = don't care cs cke clk a0-a12 ba0,ba1 cas we ras
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 40 rev. 1.2, 2004-02 10212003-bspe-77ol figure 47 self refresh entry and exit 3.4.10 power down figure 48 power down entry command power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke and clk. in power-down mode, cke low must be maintained, and all other input signals are ?don?t care?. however, power-down duration is limited by the refresh requirements of the device (t ref ). the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). one clock delay is required for power down entry and exit. power-down entry and exit is common to both stacked chips as they share a common cke signal. table 13 timing parameters for auto refresh and self refresh parameter symbol ? 7.5 units notes min. max. active to active command period t rc 67 ? ns 1) 1) these parameters account for the number of clock cycles and depend on the operating frequency as follows: no. of clock cycles = specified delay / clock period; round up to next integer. precharge command period t rp 19 ? ns 1) refresh period ( 8192 rows) t ref ? 64 ms 1) self refresh exit time t srex 1 ? t ck 1) t rp > t rc t rc t rc self refresh entry command self refresh exit command exit from self refresh any command (auto refresh recommended) = don't care t srex a10 (ap) pre all row n clk cke command nop arf nop nop nop pre arf act nop address ba a, row n dq high-z = don't care cs cke clk ras a0-a12 ba0,ba1 we cas
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 41 rev. 1.2, 2004-02 10212003-bspe-77ol figure 49 power down entry and exit 3.4.10.1 deep power down the deep power down mode is an unique function on low power sdram devices with extremly low current consumption. deep power down mode is entered using the burst terminate command (cf. figure 38 ) except that cke is low. all internal voltage generators inside the device are stopped and all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged. the deep power down mode is asynchronously exited by asserting cke high. after the exit, the same command sequence as for power-up initialization has to be applied before any other command may be issued (cf. figure 4 and figure 7 ). = don't care precharge power down mode shown: all banks are idle and trp met when power down entry command is issued any command power down entry t rp exit from power down high-z dq a10 (ap) valid pre all address valid command nop nop nop valid pre cke clk
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 42 rev. 1.2, 2004-02 10212003-bspe-77ol 3.5 function truth tables table 14 current state bank n - command to bank n current state cs ras cas we command / action notes any h x x x deselect (nop / continue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4) the following states must not be interrupted by a command issued to the same bank. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and according to table 15 . precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank is in the ?idle? state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank is in the ?row active? state. read with ap enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. l h h h no operation (nop / continue previous operation) 1) to 6) idle l l h h active (select and activate row) 1) to 6) l l l h auto refresh 1) to 7) llllmode register set 1) to 7) llhlprecharge 1) to 6), 8) row active l h l h read (select column and start read burst) 1) to 6), 9) l h l l write (select column and start write burst) 1) to 6), 9) l l h l precharge (deactivate row in bank or banks) 1) to 6), 10) read (auto- precharge disabled) l h l h read (select column and start new read burst) 1) to 6), 9) l h l l write (select column and start new write burst) 1) to 6), 9) l l h l precharge (truncate read burst, start precharge) 1) to 6), 10) l h h l burst terminate 1) to 6), 11) write (auto- precharge disabled) l h l h read (select column and start read burst) 1) to 6), 9) l h l l write (select column and start write burst) 1) to 6), 9) l l h l precharge (truncate write burst, start precharge) 1) to 6), 10) l h h l burst terminate 1) to 6), 11)
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 43 rev. 1.2, 2004-02 10212003-bspe-77ol 5) the following states must not be interrupted by any exec utable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram is in the ?all banks idle? state. accessing mode register: starts with registration of a mode register set command and ends when t mrd has been met. once t mrd is met, the sdram is in the ?all banks idle? state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks are in the idle state. 6) all states and sequences not shown are illegal or reserved. 7) not bank-specific; requires that all banks are idle and no bursts are in progress. 8) same as nop command in that state. 9) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 10) may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 11) not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. table 15 current state bank n - command to bank m (different bank) current state cs ras cas we command / action notes any h x x x deselect (nop / continue previous operation) 1)2)3)4)5)6) 1) this table applies when cken-1 was high and cken is high and after t rc has been met (if the previous state was self refresh). 2) this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. l h h h no operation (nop / continue previous operation) 1) to 6) idle x x x x any command otherwise allowed to bank n 1) to 6) row activating, active, or precharging l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 8) l l h l precharge (deactivate row in bank or banks) 1) to 6) write (auto- precharge disabled) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7) l h l l write (select column and start write burst) 1) to 7) l l h l precharge (deactivate row in bank or banks) 1) to 6) read (with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7), 9) l h l l write (select column and start write burst) 1) to 9) l l h l precharge (deactivate row in bank or banks) 1) to 6) write (with auto- precharge) l l h h active (select and activate row) 1) to 6) l h l h read (select column and start read burst) 1) to 7), 9) l h l l write (select column and start write burst) 1) to 7), 9) l l h l precharge (deactivate row in bank or banks) 1) to 6)
hy[b/e]25l512160ac?7.5 512mbit mobile-ram functional description data sheet 44 rev. 1.2, 2004-02 10212003-bspe-77ol 3) current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read with ap enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. write with ap enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank is in the idle state. 4) auto refresh, self refresh and mode register set commands may only be issued when all banks are idle. 5) a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) all states and sequences not shown are illegal or reserved. 7) reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8) requires appropriate dqm masking. 9) concurrent auto precharge: bank n will start precharging when its burst has been interrupted by a read or write command to bank m. table 16 truth table - cke cken-1 cken current state command action notes l l power down x maintain power down 1)2)3)4) 1) cken is the logic state of cke at clock edge n; cken-1 was the state of cke at the previous clock edge. 2) current state is the state immediately prior to clock edge n. 3) command n is the command registered at clock edge n; action n is a result of command n. 4) all states and sequences not shown are illegal or reserved. self refresh x maintain self refresh 1) to 4) clock suspend x maintain clock suspend 1) to 4) deep power down x maintain deep power down 1) to 4) l h power down deselect or nop exit power down 1) to 4) self refresh deselect or nop exit self refresh 1) to 5) 5) deselect or nop commands should be issued on any clock edges occurring during t rc period. clock suspend x exit clock suspend 1) to 4) deep power down x exit deep power down 1) to 4) h l all banks idle deselect or nop enter precharge power down 1) to 4) bank(s) active deselect or nop enter active power down 1) to 4) all banks idle auto refresh enter self refresh 1) to 4) all banks idle burst stop enter deep power down 1) to 4) read / write burst (valid) enter clock suspend 1) to 4) h h see table 14 and table 15 1) to 4)
hy[b/e]25l512160ac?7.5 512mbit mobile-ram electrical characteristics data sheet 45 rev. 1.2, 2004-02 10212003-bspe-77ol 4 electrical characteristics 4.1 absolute maximum ratings attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 4.2 dc operation conditions table 17 absolute maximum ratings parameter symbol values unit min. max. power supply voltage v dd -1.0 4.6 v power supply voltage for output buffer v ddq -1.0 4.6 v input voltage v in -1.0 v ddq + 0.5 v output voltage v out -1.0 v ddq + 0.5 v operation case temperature commercial t c 0+70 c extended t c -25 +85 c storage temperature t stg -55 +150 c power dissipation p d ? 0.7 w short circuit output current i out ? 50 ma table 18 dc characteristics 1) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); all voltages referenced to v ss . v ss and v ssq must be at same potential. parameter symbol values unit notes min. max. power supply voltage v dd 2.3 3.6 v ? power supply voltage for dq output buffer v ddq 1.65 or 2.30 1.95 or 3.60 v 2) 2) device is characterized for both ranges of v ddq ; v ddq < v dd +0.3 input high voltage v ih 0.8 v ddq v ddq + 0.3 v 3) 3) v ih may overshoot to v dd + 0.8 v for pulse width < 4 ns; v il may undershoot to -0.8 v for pulse width < 4 ns. pulse width measured at 50% with amplitude measured between peak voltage and dc reference level. input low voltage v il -0.3 0.3 v 3) output high voltage v oh v ddq - 0.2 ? v? output low voltage v ol ? 0.2 v ? input leakage current i il -5 5 a? output leakage current i ol -5 5 a?
hy[b/e]25l512160ac?7.5 512mbit mobile-ram electrical characteristics data sheet 46 rev. 1.2, 2004-02 10212003-bspe-77ol 4.3 pin capacitances table 19 pin capacitances 1)2) 1) these values are not subject to production test but verified by device characterization. 2) input capacitance is measured according to jep147 with vdd, vddq applied and all other pins (except the pin under test) floating. dq?s should be in high impedance state. this may be achieved by pulling cke to low level. parameter symbol values unit min. max. input capacitance: clk c i1 5.0 7.0 pf input capacitance: cs0 , cs1 c i2 3.0 5.0 pf input capacitance: all other input pins c i3 5.0 7.0 pf input/output capacitance: dq c io 7.0 10.0 pf
hy[b/e]25l512160ac?7.5 512mbit mobile-ram electrical characteristics data sheet 47 rev. 1.2, 2004-02 10212003-bspe-77ol 4.4 ac characteristics table 20 ac characteristics 1) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = 2.3v .. 3.6v; v ddq = 1.8 v 0.15 v; or 2.3v .. 3.6v; all parameters assumes proper device initialization. ac timing tests measured at 0.9 v. the transition time is measured between v ih and v il ; all ac characteristics assume t t = 1 ns. parameter symbol - 7.5 unit notes min. max. clock cycle time v ddq = 2.3v .. 3.6v cl = 3 t ck 7.5 ? ns ? cl = 2 9.5 ? ns ? v ddq = 1.65v .. 1.95v cl = 2 or 3 9.5 ? ns ? clock frequency v ddq = 2.3v .. 3.6v cl = 3 f ck ? 133 mhz ? v ddq = 1.65v .. 1.95v cl = 2 or 3 ? 105 mhz access time from clk v ddq = 2.3v .. 3.6v cl = 2 or 3 t ac 6.0 ? ns 2)3) 2) specified t ac and t oh parameters are measured with a 30 pf capacitive load only as shown below: 3) if t t (clk) > 1 ns, a value of ( t t /2 - 0.5) ns has to be added to this parameter. v ddq = 1.65v .. 1.95v 8.0 ? ns ? clock high-level width t ch 2.5 ? ns ? clock low-level width t cl 2.5 ? ns ? address, data and command input setup time t is 1.5 ? ns 4) 4) if t t > 1 ns, a value of ( t t - 1) ns has to be added to this parameter. address, data and command input hold time t ih 0.8 ? ns 4) mode register set command period t mrd 2 ? t ck ? dq low-impedance time from clk t lz 1.0 ? ns ? dq high-impedance time from clk t hz 3.0 7.0 ns ? data out hold time t oh 3.0 ? ns 2)5) 5) these parameter account for the number of clock cycles and depend on the operating frequency, as follows: no. of clock cycles = specified delay / clock period; round up to next integer. dqm to dq high-z delay (read commands) t dqz ? 2t ck ? dqm write mask latency t dqw 0 ? t ck ? active to active command period t rc 67 ? ns 5) active to read or write delay t rcd 19 ? ns 5) active bank a to active bank b delay t rrd 15 ? ns 5) active to precharge command period t ras 45 100k ns 5) write recovery time t wr 14 ? ns 6) 6) the write recovery time of t wr = 14 ns allows the use of one clock cycle for the write recovery time when f ck 72 mhz. with f ck > 72 mhz two clock cycles for t wr are mandatory. infineon technologies recommends to use two clock cycles for the write recovery time in all applications.. precharge command period t rp 19 ? ns 5) refresh period (8192 rows) t ref ? 64 ms ? self refresh exit time t srex 1 ??? 30 pf i/o
hy[b/e]25l512160ac?7.5 512mbit mobile-ram electrical characteristics data sheet 48 rev. 1.2, 2004-02 10212003-bspe-77ol 4.5 operating currents table 21 maximum operating currents 1) 1) 0 c t c 70 c (comm.); -25 c t c 85 c (ext.); v dd = 2.3v .. 3.6v; v ddq = 1.8 v 0.15 v; or 2.3v .. 3.6v; recommended operating conditions unless otherwise noted parameter & test conditions symbol values unit notes - 7.5 operating current: one bank: active / read / precharge, t rc = t rcmin i cc1 85 ma 2)3) 2) these values are measured with t ck = 7.5 ns for - 7.5 parts. 3) all parameters measured with no output loads. precharge standby current in power-down mode: all banks idle, cs v ihmin , cke v ilmax i cc2p 1.2 ma 2) precharge standby current in non-power down mode: all banks idle, cs v ihmin , cke v ihmin , inputs changing once per clock cycle i cc2n 40 ma 2) active standby current in power down mode: one bank active, cs v ihmin , cke v ilmax , inputs changing once per clock cycle i cc3p 7ma 2) active standby current in non-power down mode: one bank active, cs v ihmin , cke v ihmin , inputs changing once per clock cycle i cc3n 50 ma 2) operating current for burst mode: all banks active; continuous burst read, inputs changing once per 2 clock cycles i cc4 100 ma 2)3) auto-refresh current: t rc = t rcmin , ?burst refresh? i cc5 175 ma 2) deep power down mode current i cc7 10 a? table 22 self refresh currents 1) 1) 0 c t c 70 c (comm.) ; -25 c t c 85 c (ext.); v dd = 2.3v .. 3.6v; v ddq = 1.8 v 0.15 v; or 2.3v .. 3.6v; parameter & test conditions max. temperature symbol values units notes max. self refresh current: self refresh mode, cke = 0.2 v, clock off, full array activation (pasr = 000) 85 c i cc6 1600 a 2) 2) target values, to be verified on final product. 70 c 1100 45 c 900 15 c 750 self refresh current: self refresh mode, cke = 0.2 v, clock off, half array activation (pasr = 001) 85 c i cc6 1150 a 2) 70 c 900 45 c 800 15 c 700 self refresh current: self refresh mode, cke = 0.2 v, clock off, quarter array activation (pasr = 010) 85 c i cc6 900 a 2) 70 c 800 45 c 750 15 c 675
hy[b/e]25l512160ac?7.5 512mbit mobile-ram package outline data sheet 49 rev. 1.2, 2004-02 10212003-bspe-77ol 5 package outline figure 50 package fbga-54 p-tfbga-54-2 jedec mo207g var. de compatible all dimensions in mm bottom view top view 12.00 0.10 ball a1 indicator 0.80 1.40 max 0 . 1 2 c 0 . 1 0 c 0.80 ?0.40 8.00 0.10
hy[b/e]25l512160ac?7.5 512mbit mobile-ram package outline data sheet 50 rev. 1.2, 2004-02 10212003-bspe-77ol
published by infineon technologies ag www.infineon.com

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