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? 2005 device engineering inc. page 1 of 17 ds-mw-01016-01 rev a 01/07/2005 features ? two receivers and one transmitter ? industry standard pin for pin replacement part ? wraparound self-test mode ? word length can be configured for 25 bit or 32 bits operation ? parity status and generation of receive and transmit words ? 8 word transmitter buffer ? low power cmos processing ? supports multiple arinc protocols: 429, 571, 575, 706 ? available in extended (-55/+85c) and military (-55/+125c) temperature ranges general description: the dei1016 provides an interface between a st andard avionics type serial digital data bus and a 16-bit-wide digital data bus. the interface circuit consists of a single chan nel transmitter with an 8x32 bit buffer, two independent receive channels, and a hos t programmable control register to select operating options. the two receiver channels operate identically, each providing a dir ect electrical interface to an arinc data bus. the transmitter circuit contains an 8 word by 32 bit buffer memory and control logic which allows the host to write a block of data into the transmitter. the block of data is transmitted automati cally by enabling the transmitter with no further attention by the host computer. data is transmitted in ttl format on the d0(a)/d0(b) output pins. the sign al format is compatible with dei?s extens ive line of arinc 429 line drivers for easy connection to the arinc data bus. dei1016/DEI1016A/dei1016b /dei1016c arinc 429 transceiver family 385 east alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e-mail: info@deiaz.com device engineering incorporated control register tx fifo 8 words x 32 bits receive decoder receive decoder transmit encoder arinc 429 receive 0 arinc 429 receive 1 self test data arinc 429 transmit data bus host interface /dr1, /dr2 txr /oe1, /oe2 /ld1, /ld2 entx /ldcw /dbcen /mr 32 32 32 32 16 16 figure 1: dei1016 block diagram
? 2005 device engineering inc. page 2 of 17 ds-mw-01016-01 rev a 01/07/2005 table 1: dei 1016 absolute maximum ratings parameter symbol min max units supply voltage v dd -0.5 +7.0 v dc input voltage (except pins di1(a,b) and di2(a,b)) v in -0.6 v cc + 0.6 v voltage at pins di1(a,b) and di2(a,b) v in 29 v clamp diode current, any pin except di inputs 25 ma dc output current per pin 25 ma dcv or gnd current per pin 50 ma storage temperature t stg -65 +150 c junction temperature, operating t jmax +145 c lead temperature (soldering, 10 sec) t lead +275 c 1mck clock frequency 1.16 mhz table 2: dei 1016 dc electrical characteristics unless noted, operating conditions: v dd = 5v 10%, extended temp devices: ta = -55oc to +85oc, military temp devices: ta = -55oc to +125oc parameter symbol conditions min typ max units arinc line inputs logic 1 input voltage v ih v diff di(a) and di(b) 6.5 10 13 v logic 0 input voltage v il v diff di(a) and di(b) -6.5 -10 -13 v n ull input voltage v nul v diff di(a) and di(b) -2.5 0 +2.5 v common mode voltage v cm -5 + 5 v differential input impedance r i 12 k ? input impedance to v dd r h 12 k ? input impedance to gnd r g 12 k ? differential input capacitance c i 20 pf input capacitance to v dd c h 20 pf input capacitance to gnd c g 20 pf logic inputs (including bi-directional) low level input voltage v il 0.8 v high level input voltage v ih 2.0 v input leakage current i in v in = gnd to v dd - 10 + 10 a input capacitance c in 15 pf logic outputs (including bi-directional) high level output voltage v oh i oh = 20 a (cmos) i oh = 6ma (ttl) v dd ? 0.1 2.7 v low level output voltage v ol i ol = 20 a (cmos) i ol = 6ma (ttl) 0.1 0.4 v power supply input supply current i dd 1mck = 1mhz 5 10 ma supply voltage v dd 4.5 5 5.5 vdc
? 2005 device engineering inc. page 3 of 17 ds-mw-01016-01 rev a 01/07/2005 table 3: dei 1016 ac electrical characteristics parameter symbol data rate 100kbps data rate 12.5kbps min max min max units 1mck frequency f 1mck 1.01 1.01 mhz 1mck duty cycle ck dc 40 60 40 60 % 1mck rise/fall time t crf 10 10 ns master reset pulse width t mr 200 200 ns transmitter data rate (1mck = 1mhz) t dr 99 101 12.4 12.6 kbps receiver data rate (1mck = 1mhz),(data = 50% bit/ 50% null time) r dr 95 105 8.0 14.5 kbps table 4: pin definitions symbol definition v dd power input. +5vdc 10 % gnd power return and signal ground. di1(a) arinc 429 input. r eceiver channel 1, ?a? input di1(b) arinc 429 input. r eceiver channel 1, ?b? input di2(a) arinc 429 input. r eceiver channel 2, ?a? input di2(b) arinc 429 input. r eceiver channel 2, ?b? input /dr1 logic output. data ready, receiver 1. a low output indicat es valid data in receiver 1. /dr2 logic output. data ready, receiver 2. a low output indi cates valid data in receiver 2. sel logic input. receiver word select. a low input selects recei ver word 1; hi selects word 2 to be read on d[15:0] port. /oe1 logic input. receiver 1 output enable . a low input enables the d[15:0] port to output receiver 1 data. word 1 or word 2 will be output as determined by the sel input. /oe2 logic input. receiver 2 output enable . a low input enables the d[15:0] port to output receiver 2 data. word 1 or word 2 will be output as determined by the sel input. d[15:0] logic input / tri-state output. this 16-bit bi-directional data port is the up data interface. receiver data is read from this port. control register and transmitte r fifo data is written into this port. /ld1 logic input. load transmitter word 1. a low input pulse loads word 1 into the transmitter fifo from d[15:0]. /ld2 logic input. load transmitter word 2. a low input pulse loads word 2 into the transmitter fifo from d[15:0]. txr logic output. transmitter ready. a hi output indicates the transmitter fifo is empt y and ready to accept new data. do(a) logic output. transmitter serial data ?a? output. this is a return-to-zero format signal which will normally feed an arinc 429 line driver ic. a hi output indicates the tr ansmitter data bit is a 1. the signal returns to zero for second half of bit time. do(b) logic output. transmitter serial data ?b? output. this is a return-to-zero format signal which will normally feed an arinc 429 line driver ic. a hi output indicates the tr ansmitter data bit is a 0. the signal returns to zero for second half of bit time. entx logic input. enable tran smitter. a hi input enables the transmitter to send data from the transmitter fifo. this must be low while writing data into transmitter fifo. tr ansmitter memory is cleared by high-to-low transition. /ldcw logic input. load control register. a low input pulse loads the control register from d[15:0]. 1mck logic input. external clock. mast er clock used by both the r eceivers and transmitter. the 1mhz rate is a x10 clock for the hi data rate (100 kbps), and a x80 clock for lo data rate (12.5 kbps). txck logic output. transmitter clock. this outputs a clock fr equency equal to the transmit data rate. the clock is always enabled and in phase with the data. the output is hi during the first half of the data bit time. /mr logic input. master reset. a lo input resets the tr ansmitter fifo, bit counters, word counter, gap timers, /drx, and txr. the control register is not affected . used on power up and system reset. /dbcen logic input with internal pull up to v dd . data bit control enable. a low input enables the transmitter parity bit control function as defined by control register bit 4 (paren ). a hi input forces transmitter parity bit insertion regardless of paren value. the pin is normally left open or tied to ground.
? 2005 device engineering inc. page 4 of 17 ds-mw-01016-01 rev a 01/07/2005 table 6: dei1016 control word n ame data bit description paren d4 transmitter parity enable. enables parity bit inser tion into transmitter data bit 32. parity is always inserted if /dbcen is open or hi. if /dbcen is lo , logic ?0? on paren inserts data on bit 32, and logic ?1? on paren inserts parity on bit 32. /slftst 1 d5 self test enable. logic ?0? enables a ?wrap around ? test mode which internally connects the transmitter outputs to both receiver inputs, bypassi ng the receiver front end. the test data is inverted before going into receiver 2 so that its data is the complement of th at received by receiver 1. the transmitter output is active during test mode. sden1 2 d6 s/d code check enable for receiver 1. logic ?1? enables the source/destination decoder for receiver 1. x1, y1 2 d7, d8 s/d compare code rx1. if the receiver 1 s/d c ode check is enabled (sdenb1=1), then incoming receiver data s/d fields will be comp ared to x1, y1. if they match, the word will be accepted by receiver 1; if not, it will be ignored. x1 (d7) is compared to serial data bit 9, y1 (d8) is compared to serial data bit 10. sden2 2 d9 s/d code check enable for receiver 1. logic ?1? enables the source/destination decoder for receiver 1. x2, y2 2 d10, d11 s/d compare code rx2. if the receiver 2 s/d c ode check is enabled (sdenb2=1), then incoming receiver data s/d fields will be comp ared to x2, y2. if they match, the word will be accepted by receiver 2; if not, it will be ignored. x2 (d10) is compared to serial data bit 9, y2 (d11) is compared to serial data bit 10. parck d12 parity check enable. logic ?1? inverts the transmitter parity bit for test of parity circuits. logic ?0? selects normal odd parity; lo gic ?1? selects even parity. txsel 3 d13 transmitter data rate select. logic ?0? sets the transm itter to the hi data rate. hi rate is equal to the clock rate divided 10. logic ?1? sets the transmitter to the lo data rate. lo rate is equal to the clock rate divided by 80. rcvsel 4 d14 receiver data rate select. logic ?0? sets both receive rs to accept the hi data rate. the nominal hi data rate is the input clock divided by 10. logic ?1? sets both receivers to the lo data rate. the nominal lo data rate is the input clock divided by 80. wlsel 5 d15 word length select. logic ?0? sets the transmitter and receivers to a 32 bit word format. logic ?1? sets them to a 25 bit word format. not used d0-d3 when writing to the control register, the four ?not used bits? are ?don?t care? bits. these four bits will no t be used on the chip. notes 1) the test mode should always conclude with ten null?s. this st ep prevents both receivers from accepting invalid data. 2) sdenbn, xn & yn should be changed within 20 bit times after /drn goes low and the bit stream has been read, or within 30 bit times after a master reset has been removed. 3) txsel should only be changed during the time that txr is high or master reset is low. 4) rcvsel should be changed only during a master reset pulse. if changed at any other time, then the next bit stream from both receiver 1 and receiver 2 should be ignored. 5) when the control word is written the effect of the wlsel bit will take effect immediately on the first complete arinc word r eceived or transmitted following the control word write operation. functional description: the dei 1016 supports a number of various options which are selected by data written into the control register. data is written into the control register from the 16-bit data bus when the /ldcw signal is pulsed to a logic ?0?. the twelve control bits control the following functions: 1) word length (32 or 25 bits) 2) transmitter bit 32 (parity or data) 3) wrap around self test. 4) source destination code checking of received data. 5) transmitter parity (even or odd) 6) transmitter and receiver data rate (100 or 12.5 kbps) table 5: control register format bit symbol bit symbol d15 (msb) wlsel d7 x1 d14 rcvsel d6 sdenb1 d13 txsel d5 /slftst d12 parck d4 paren d11 y2 d3 n ot used d10 x2 d2 n ot used d9 sdenb2 d1 n ot used d8 y1 d0 n ot used
? 2005 device engineering inc. page 5 of 17 ds-mw-01016-01 rev a 01/07/2005 data format: the arinc serial data is shuffled and formatted into two 16 bit words (word1 and word2) used by the bi-directional data bus interface. figure 2 shows the mapping between the 32 bit arinc serial data and the two data words. figure 3 describes the map ping for the 25 bit serial word used when control register bit wlsel is set to logic ?1?. figure 3: mapping of serial data to/from word 1 and word 2 in 25 bit format. figure 3: mapping of serial data to/from word 1 and word 2 in 25 bit format.
? 2005 device engineering inc. page 6 of 17 ds-mw-01016-01 rev a 01/07/2005 receiver operation: since the receivers function identically, only one will be discussed in detail. the recei ver consists of the following circuits. line receiver the front end of the line receiver functions as a voltage level translator. it transforms the 10 volt differential arinc data signals into 5 volt internal logic levels. the line receivers are protected against shorts to 29 volts and p rovides common mode voltage rejection. the outputs of the line receiver are one of two inputs to the self-test data selector. the other input to the data selector is the self-test signal from the transmitter section. the self-test signals are inverted going into receiver 2. the data selector is controled by control register bit d5 (slftst). the received word has an odd num ber of 1?s (no error). logic ?1? indicates the received word ha s an even number of 1?s (error condition). if the data format has data in bit 32 instead of parity, the user software must calculate the value of the 32nd bit. if word 1 and word 2 together have an even number of 1?s, then data bit 32 is a logic ?1?. otherwise, it is a logic ?0?. data access to access the receiver data, the user sets the receiver data select input (sel) to a logic ?0? and pulses the output enable (/oen) line with a logic ?0?. this causes data word 1 to be placed on the 16 bit data bus. to read word 2, the user sets the data select input (sel) to a logic ?1? and pulses the output enable (/oen) low to place word 2 on the data bus. when both word 1 and word 2 have been read, drn will be reset. this reset is triggered by the leading edge of the final /oen pulse. if a new data word is received before the previous data has been read from the receiver buffer (a s indicated by the /drn signal flip-flop), the receive buffer will not be over written by the new data. the new data will remain in the shift register until either the /drn signal is reset and it can be written into the receive b uffer or it is overwritten by the next incoming data word. data in the shift register will be overwritten by new incoming data, while data that has been latched into the receive buffer can not be overwritten. data error conditions if the receiver input data word stri ng is broken before the entire data word is received, the receiver will reset and ignore the partially received data word. if the receiver input data word stri ng is not properly framed with at least 1 null bit before the word and 1 null bit after the word, the receiver will reset and ignore the improperly framed data word. transmitter operation: the transmitter section consists of an 8 word by 32 bit fifo, parity generator, transmitter word gap timer, and a ttl output circuit. fifo buffer the 8x32 buffer memory allows the user to load up to 8 words into the transmitter, enable it, and then ignore it while the transmitter ships out the data without further attention. data is loaded into the buffer by pulsing /ld1 to load the first 16 bits (word 1) from the data bus, and pulsing /ld2 to load word 2. /ld1 must always precede /ld2. the transmitter must always be disabled while loading the buffer (entx = logic "0"). if the buffer is full and new data is pulsed with /ld1 and /ld2, the last 32 bit word in the buffer will be overwritten. data will remain in the buffer until entx is pulsed to a logic ?1?, which will activate the fifo clock and data is shifted out serially to the transmitter driver. figure 4: line receiver block diagram incoming data the incoming data (either self test or ari n c) is triple sampled by the word gap timer to generate a data clock. the start of each bit is first detected and then verified two receive-clock cycles later. the receive clock is 1mhz for hi speed and 125 khz for lo speed operation and is generated by the receiver/tran smitter timing circuit. the receive clock is ten times the normal data rate to ensure no data ambiguity. data clock the derived data clock then shifts the data down a 32 bit long data shift register. the data word length is selectable for either 25 or 32 bits long by control register bit wlsel. as soon as the data word is completely received, an internal signal is generated by the word gap timer circuit to enable loadi ng data into the 32 bit receive buffer latch. s/d decoder the source/destination decoder compares the user set code (x and y) with bits 9 and 10 of the data word. the decoder can be enabled and disabled by the sdenb bit of the control register. if the two codes are matched, a signal is generated to latch in the received data into the receiver b uffer. otherwise the data word is ignored and not latched into the receive buffer. if the data is latched, the data ready flag (/drn) is set to indicate to the user that a valid data word is ready to be read. parity control the parity of the incoming message is checked when either word of the receiver is read. lo g ic ?0? indicates
? 2005 device engineering inc. page 7 of 17 ds-mw-01016-01 rev a 01/07/2005 fifo buffer (continued) the buffer data is transmitted until the last word in the buffer is shifted out. at this time a transmitter ready signal (txr) is set to a logic ?1? indicating that the buffer is empty and ready to receive up to eight more data words. writing into the buffer memory is disabled when entx is set to logic ?1?. transmitter ready signal (txr) the transmitter ready flag (txr) is set to logic ?0? with the first occurrence of an /ld2 pulse to indicate that the buffer is not empty. output register the output register is designed such that it can shift out a word of 25 bits or 32 bits. the length is controlled by control register bit "wlsel". tx word gap timer the tx word gap timer circuit inserts a 4 bit time gap between words. this gives a minimum requir ement of a 29 bit time or a 36 bit time for each word transmission. the 4 bit time gap is also automatically maintained when the next new block of data is loaded into the buffer, which may take less than one bit time. parity generator the parity generator calculates either odd or even parity as specified by control register bit "parck". odd parity is normally used; even parity is available to test the receiver parity check circuit. odd parity means that ther e is an odd number of 1's in the 25 or 32 bit serial word. bit 8 of word one is replaced with a parity bit if parity is selected by the control register bit "paren" and the /dbcen pin. otherwise, bit 8 is passed through as data. transmitter output the transmitter driver outputs three ttl compatible signals: 1) do(a), 2) do(b), and 3) txclk. do(a) and do(b) are the transmitter data in two rail, return-to-zero format. do(a) indicates a logic "1" data bit by going to a "1" for the 1st half of a bit time, then returning to "0" for the 2nd half; do(b) remains at "0" for the whole bit time. in the same fashion, do(b) indicates a logic "0" data bit by pulsing hi while do(a) remains lo. a null bit is indicated when both signals remain lo. it is illegal for both signals to be logic "1". the txclk is a free running clock signal of 50% duty cycle and in phase with transmitter data. the clock will always be logic "1" during the first half of a bit time. power-up reset an internal power-up reset circuit prevents erroneous data transmission before an external master reset has been applied. 25-bit word operation: the transceiver implements a 25 bit word format which may be used in non-arinc applications to enhance data transfer rate. the format is a simplified version of the 32 bit arinc word and is described in figure 3. it consists of an 8 bit label, a 16 bit data word, and a parity bit. the parity bit can optionally be replaced with a 17th data bit. the source/destination code checking option can be enabled in either receiver. it will operate on bits 9 and 10 of the 25 bi t word. self-test operation: by selecting the control register bit (/slftst) self test option, the user may perform a functional test of the transceiver and support circuitry. the user can write data into the transmitter and it will be internally wrapped around into both receivers. the user can then verify reception and integrity of the data. the receiver line interface and the user's line drivers will not be tested. by setting the transmitter to use even parity, the user can test the receiver's parity circuit operation. power-up reset and master reset: the user must apply an active lo pulse to the master reset pin (/mr) after power up or upon system reset. preceding the master reset at power-up an internal power-up reset occurs which will clear the transmitter such that no erroneous serial data stream will be transmitted before master reset. receivers, control register, and internal control logic are reset by master reset. after resetting the device, the user must program the control register before beginning normal operation. the control register may be reprogrammed without additional reset pulses. processor interface: figure 7 shows a typical reset an d initialization sequence. the user must pulse the /mr pin low to reset the device. to load the control register from the data bus, the /ldcw pin is pulsed low while the desired control data is applied on the data bus. figure 5 shows a typical transmitter loading sequence. it begins with the transmitter completing transmission of the previous data block. the txr flag goes hi to notify the user that data may be loaded into the buffer. the user sets entx to lo to disable the transmitter and proceeds to load a total of six arinc words into the buffer. (note that up to eight words could have been loaded). the user then enables the transmitter by setting entx to a logic "1" and the transmitter begins it's sequence of sending out data words. although not shown in the figure, the transmitter loading sequence can be interrupted by receiver reading cycle with no interference between the two operations. figure 6 shows a typical receiver reading sequence. both receivers notify the user of valid data ready by setting their respective /drn lines to logic "0". the user responds by first reading the two data words from receiver 1 and then from receiver 2. the sel line is normally a system address line and may assume any state, but must be valid when the /oen line is pulsed low.
? 2005 device engineering inc. page 8 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 5: typical transmitter load sequence figure 5: typical transmitter load sequence figure 6: typical receiver read sequence figure 6: typical receiver read sequence
? 2005 device engineering inc. page 9 of 17 ds-mw-01016-01 rev a 01/07/2005 valid data mr ldcw d[15:0] t mr t pwld t sdw t hdw figure 7: reset and initialization sequence t hsel t doedr t oeoe t ddroe t pwoe t ssel arinc data bit 31 bit 32 word 1 valid word 2 valid t ddrn /dr1, /dr2 /oe1, /oe2 sel d[15:0] t ddr t dts figure 8: receiver read operation and timing figure 9: transmitter wr ite operation and timing
? 2005 device engineering inc. page 10 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 10: transmitter timing diagram table 7: dei 1016 ac timing characteristics parameter symbol data rate 100kbps data rate 12.5kbps min max min max units write cycle timing /ld1, /ld2 and /ldcw pulse width t pwld 130 130 ns delay between consecutive load pulses t ll 0 0 ns data to /ld ? set-up time t sdw 110 110 ns data to /ld ? hold time t hdw 0 0 ns delay /ld2 ? to txr ? t dtxr 840 840 ns read cycle timing delay, bit 32/25 in to /dr ? t ddrn 16 128 s delay, /drn ? to /oen ? t ddroe 0 0 ns /oe1 or /oe2 pulse width t pwoe 200 200 ns delay between consecutive /oe pulses t oeoe 50 50 ns delay, 2nd /oe ? to /drn ? t doedr 200 200 ns sel to /oe ? to valid data t ssel 20 20 ns sel to /oe ? hold time t hsel 20 20 ns delay /oe ? to valid data t ddr 200 200 ns sel to /oe ? to data hi-z t dts 10 50 10 50 ns transmitter timing delay, entx ? to output data 1 t dtd 25 200 s output data null time t nul 4.95 5.05 39.6 40.4 s output data bit time t bit 4.95 5.05 39.6 40.4 s data skew between txck ? ( ? ) and do ? ( ? ) t sktx 0 50 0 50 ns data word gap time t gap 39.6 40.4 316.8 323.2 s delay, end of tx word to txr ? t dtxr 50 50 ns delay, txr ? to entx ? t dentx 0 0 ns 1. this applies only when there has been a 4-bit null since the end of the transmitted data.
? 2005 device engineering inc. page 11 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 11: terminal connections serial interface: the dei1016 consits of two receive channels and one transmit channel. each receive channel operates independently of each other and the transmitter. the receive data is asynchronous to the transmitter data and can also be at a different data rate than the transmitter. transmitter the transmitter clock is free running and in phase with the transmitter data. the transmitter data (do(a) and do(b)) are ttl level signals. there are always at least 4 null bits between data words. an external arinc line driver is required to inte rface the transmitter to the arinc serial data bus. see arinc 429 line drivers below. receiver the receiver signals (di(a) and di (b)) are differential, bipolar, return-to-zero logic signals. the arinc channels can be connected directly to the receiver with no external components. arinc 429 line driver device engineering offers a complete line of arinc line drivers ics that support the arinc 429, 571, and 575 standards. refer to dei website at: http://www.deiaz.com.
? 2005 device engineering inc. page 12 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 12: typical transceiver/line driver interconnect configuration table 8: dei1016 ordering information dei part number (2) marking (1) package temp range processing dei1016 dei1016 40 sbdip -55 / +125 c ceramic burn in DEI1016A DEI1016A 44 pqfp -55 / +85 c plastic standard dei1016b dei1016b 44 plcc -55 / +85 c plastic standard dei1016c dei1016c 40 pdip -55 / +85 c plastic standard dei1016-qms dei1016-qms 44 pqfp -55 / +125 c plastic standard dei1016-pms dei1016-pms 44 plcc -55 / +125 c plastic standard dei1016-ees dei1016-ees 44 clcc -55 / +85 c ceramic standard dei1016-ems dei1016-ems 44 clcc -55 / +125 c ceramic standard dei1016-emb dei1016-emb 44 clcc -55 / +125 c ceramic burn in dei1016-mes dei1016-mes 56 mlpq -55 / +85 c plastic standard dei1016-mms dei1016-mms 56 mlpq -55 / +125 c plastic standard n otes: 1. all packages marked with lot code and date code 2. suffix legend: -xyz: x = package code, y = temperature range code, z = process flow code
? 2005 device engineering inc. page 13 of 17 ds-mw-01016-01 rev a 01/07/2005 table 9: dei1016 screening process plastic standard ceramic standard ceramic burn in wafer probe electrical test 100% hot @ +125 c 100% hot @ +125 c 100% hot @ +125 c thermal cyclemil-std- 883b m1010.4 condition b no 10 cycles 10 cycles gross & fine leak no yes yes burn inmil-std-883b m1015 condition a no no 96 hrs @ +125 c electrical test: room temperature 100% 100% 100% high temperature 0.1% aoql @ +125 c(miltemp) 0.1% aoql @ >+85 c (exttemp) 100% @ +125 c (mil temp) 100% @ +85 c (ext temp) 100% @ +125 c (mil temp) low temperature 0.1% aoql @ -55c 100% @ -55c 100% @ -55c table 10: dei1016 package characteristics package type 40 lead ceramic side brazed dip 40 lead plastic dip 44 lead plastic quad flat pack 44 lead plastic chip carrier 44 lead ceramic chip carrier 56 lead micro leadfram e pack reference 40 sbdip 40 pdip 44 pqfp 44 plcc 44 clcc 56 mlpq t hermal esistance: ja c/w 55 47 65 46 32 jc c/w 15 25 21 21 jedec moisture sensitivity level & peak body temp n/a hermetic n/a thru- hole msl 2 / 220c msl 3 / 220c n/a hermetic msl 2 / 235c jedec reference ms-015-ce ms-011-ac mo-112-aa- 1 ms-018-ac mo-220- vlld
? 2005 device engineering inc. page 14 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 13: 40 pin ceramic side braze dip mechanical outline (40 sbdip)
? 2005 device engineering inc. page 15 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 15: 44 lead plcc mechanical outline figure 16: 40 pin plastic dip mechanical outline (40 pdip)
? 2005 device engineering inc. page 16 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 17: 44 lead clcc mechanical outline (44 clcc)
? 2005 device engineering inc. page 17 of 17 ds-mw-01016-01 rev a 01/07/2005 figure 18: 56 lead 8x8 mlpq mechanical outline (56 mlpq) dei reserves the right to make changes to any products or specifications herein. de i makes no warranty, representation, or gua rantee regarding suitability of its products for any particular purpose.

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