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d a t a sh eet product speci?cation supersedes data of 1995 nov 29 file under integrated circuits, ic02 1996 jan 25 integrated circuits TDA8310A pal/ntsc colour processor for pip applications
1996 jan 25 2 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A features video switch with 2 cvbs inputs. one input can be switched between cvbs and y/c and the circuit can automatically detect whether the incoming signal is cvbs or y/c integrated chrominance trap and bandpass filters (automatically calibrated) integrated luminance delay line automatic pal/ntsc decoder which can decode all standards available in the world easy interfacing with the tda8395 (secam decoder) for multistandard applications horizontal pll with an alignment-free horizontal oscillator vertical count-down circuit rgb/yuv and fast blanking switch with 3-state output and active clamping low dissipation (560 mw) small amount of peripheral components compared with competition ics. general description the TDA8310A is an alignment-free pal/ntsc colour processor for picture-in-picture (pip) applications. the main difference between the tda8310 and the TDA8310A is that the vision if amplifier has been omitted in the TDA8310A. therefore, the circuit contains an input signal selector, a pal/ntsc colour decoder, horizontal and vertical synchronization and an rgb/yuv switch. the input signal selector has 2 cvbs inputs. one of the inputs can be switched between cvbs and y/c and the circuit can automatically detect whether the incoming signal is cvbs or y/c. the output signals for the pip processor are; luminance signal colour difference signals (u and v) horizontal and vertical synchronization pulses. the rgb/yuv switch can select between two rgb or yuv sources, e.g. between the pip processor and the scart input signal. the supply voltage for the ic is 8 v. it is available in a 52-pin sdip package. ordering information type number package name description version TDA8310A sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
1996 jan 25 3 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A quick reference data symbol parameter min. typ. max. unit v p supply voltage (pins 19 and 41) 7.2 8.0 8.8 v i p supply current - 70 1.4 ma input voltages v 17,20(p-p) cvbs/y input voltage (peak-to-peak value) - 1.0 - v v 16(p-p) chrominance input voltage (peak-to-peak value) - 0.3 - v v i(p-p) rgb/yuv input signal voltage amplitude (peak-to-peak value) -- 1.3 v output signals v o(p-p) luminance output voltage (peak-to-peak value) - 1.4 - v v 50(p-p) (b - y) output voltage (peak-to-peak value) 1.06 1.33 1.6 v v 51(p-p) (r - y) output voltage (peak-to-peak value) 0.84 1.05 1.26 v v 39 horizontal sync pulse output voltage - 4.0 - v v 36 vertical sync pulse output voltage - 4.0 - v g v voltage gain of the rgb switches - 0.5 0 +0.5 db control voltage v control control voltage for hue 0 - 5.0 v
1996 jan 25 4 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram handbook, full pagewidth mgd128 46 45 pll xtal4 ref 44 xtal3 43 xtal2 42 xtal1 r/w colour1 27 26 colour2 25 logic1 24 logic2 23 b y r y 50 51 gnd1 gnd3 18 38 luminance delay line y 49 hue 28 4 ident secam 48 47 16 chroma i 9 17 input selector 20 gnd2 cvbs int syst sw chroma o cvbs ext 31 automatic y/c detector 15 dec ft 32 33, 34 chrominance bandpass chrominance trap filter tuning sync separator vertical sync separator pal/ntsc decoder vco + control phase detector coincidence/ noise detector n.c. 22, 29 i.c. cvbs sw 37 ph1lf 35 dec bg 21 dec dig 41 v p2 30 intb 19 v p1 horizontal/ vertical divider pulse shaper 39 hout 36 vout sandcastle generator 40 sand TDA8310A blank2 52 b2 3 g2 2 r2 1 blank 5 b 6 g 7 r 8 clamp 14 blank1 13 b1 12 g1 11 r1 10 rgb/yuv switch fig.1 block diagram.
1996 jan 25 5 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A pinning symbol pin description r2 1 red input 2 (pip) g2 2 green input 2 (pip) b2 3 blue input 2 (pip) ident 4 colour standard identi?cation output blank 5 blanking output b 6 blue output g 7 green output r 8 red output syst sw 9 cvbs/system switch r1 10 red input 1 g1 11 green input 1 b1 12 blue input 1 blank1 13 blanking input 1 clamp 14 clamping pulse input dec ft 15 decoupling ?lter tuning chroma i 16 chrominance input cvbs ext 17 external cvbs/y input gnd1 18 ground 1 (0 v) v p1 19 supply voltage 1 (+8 v) cvbs int 20 internal cvbs input dec dig 21 decoupling digital supply rail i.c. 22 internally connected (test purposes) logic2 23 crystal logic 2 input/output logic1 24 crystal logic 1 input/output colour2 25 colour system logic 2 input/output colour1 26 colour system logic 1 input/output r/ w 27 read/write selection input hue 28 hue control input i.c. 29 internally connected (test purposes) intb 30 internal bias gnd2 31 ground 2 (0 v) cvbs sw 32 cvbs positive/negative modulation control switch input n.c. 33 not connected n.c. 34 not connected dec bg 35 bandgap decoupling vout 36 vertical sync output pulse ph1lf 37 phase 1 loop ?lter gnd3 38 ground 3 (0 v) hout 39 horizontal sync output pulse sand 40 sandcastle pulse output v p2 41 supply voltage 2 (+8 v) xtal1 42 4.4336 mhz crystal xtal2 43 3.5820 mhz crystal for pal-n xtal3 44 3.5756 mhz crystal for pal-m xtal4 45 3.5795 mhz crystal for ntsc pll 46 pll colour ?lter chroma o 47 chrominance output for tda8395 secam 48 secam reference output y 49 y output b - y50b - y output r - y51r - y output blank2 52 blanking/insertion input 2 (pip) symbol pin description
1996 jan 25 6 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A fig.2 pin configuration. handbook, halfpage TDA8310A mgd127 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 r2 g2 b2 ident blank b g r syst sw r1 g1 b1 blank1 clamp dec ft chroma i cvbs ext gnd1 v p1 cvbs int dec dig i.c. logic2 logic1 colour2 colour1 blank2 r - y b - y y secam chroma o pll xtal4 xtal3 xtal2 xtal1 v p2 sand hout gnd3 ph1lf vout dec bg n.c. n.c. cvbs sw gnd2 intb i.c. hue r/w 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
1996 jan 25 7 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A functional description cvbs switch the circuit contains a 2 input cvbs switch and one of the inputs can be switched between cvbs and y/c. the circuit contains an identification circuit which can automatically switch between the cvbs and y/c signals. it is also possible to force the switch to cvbs or y/c. synchronization circuit the sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. the sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude. the separated sync pulses are fed to the first phase detector and to the coincidence detector. the coincidence detector is used to detect whether the line oscillator is synchronized and for transmitter identification. the first pll has a very high static steepness this ensures that the phase of the picture is independent of the line frequency. the line oscillator operates at twice the line frequency. the oscillator network is internal. because of the spread of internal components an automatic adjustment circuit has been added to the ic. the circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. this results in a free-running frequency which deviates less than 2% from the typical value. the horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. the pulse width of the output pulse is 5.4 m s, the front edge of this pulse coincides with the front edge of the sync pulse at the input. the vertical output pulse is generated by a count-down circuit. the pulse width is approximately 380 m s. both the horizontal and vertical output pulses will always be available at the outputs even when no input signal is available. in addition to the horizontal and vertical sync pulse outputs the ic has a sandcastle pulse output which contains burst key and blanking pulses. integrated video ?lters the circuit contains a chrominance bandpass and trap circuit. the filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. when a y/c signal is supplied to the input the chrominance trap is automatically switched off by the y/c detection circuit however, it is also possible to force the filters in the cvbs or y/c position. the luminance delay line is also realised by gyrator circuits. colour decoder the colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. the 90 phase shift for the reference signal is achieved internally. the colour decoder is very flexible. together with the secam decoder (tda8395) an automatic multistandard decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the ic. the decoder can be forced to one of the standards via the forced mode pins. the crystal pins which are not used must be connected to the positive supply line via a 8.2 k w resistor. it is also possible to connect the non-used pins with one resistor to the positive supply line. in this event the resistor must have a value of 8.2 k w divided by the number of pins. the chrominance output signal of the video switch is externally available and must be used as an input signal for the secam decoder. rgb/yuv switch the rgb/yuv switch is for switching between two rgb or yuv video sources. the outputs of the switch can be set to high-impedance state so that other switches can be used in parallel. the switch is controlled via pins 13 and 52. the details of switch control are shown in table 4.
1996 jan 25 8 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A limiting values in accordance with the absolute maximum rating system (iec134). thermal characteristics characteristics v p =8v; t amb =25 c; unless otherwise speci?ed. symbol parameter min. max. unit v p supply voltage - 9.0 v t stg storage temperature - 25 +150 c t amb operating ambient temperature - 25 +70 c t sld soldering temperature for 5 s - 260 c t j maximum operating junction temperature - 150 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 40 k/w symbol parameter conditions min. typ. max. unit supplies v p supply voltage (pins 19 and 41) 7.2 8.0 8.8 v i p1 supply current (pin 19) 45 65 80 ma i p2 supply current (pin 41) 3 5 10 ma p tot total power dissipation - 560 - mw r bias value of resistor to be connected between pin 30 and the positive supply line - 10 - k w cvbs and y/c switch i nternal cvbs and external cvbs/y inputs ( pins 20 and 17) v 20,17(p-p) cvbs/y input voltage (peak-to-peak value) notes 1 and 3 - 1 1.4 v i 20,17 input current - 46 m a v clamp top sync clamping voltage level - 3.3 - v i clamp clamping input current 80 100 -m a c hrominance input ( pin 16) v 16(p-p) chrominance input voltage (peak-to-peak value) notes 1, 4 and 11 - 0.3 - v v 16(p-p) input signal amplitude before clipping occurs (peak-to-peak value) note 2 1.0 -- v r i chrominance input resistance 14 20 26 k w c i chrominance input capacitance note 1 -- 5pf
1996 jan 25 9 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A c hrominance output ( pin 47) v 47(p-p) output signal voltage amplitude (peak-to-peak value) 0.18 0.20 0.22 v z o output impedance 200 250 300 w v o dc output voltage open-circuit output 1.2 1.4 1.6 v s witch control input for internal / external positive / negative modulation ( pin 32); note 5 v 32 internal cvbs signal selected -- 1.0 v v 32 external cvbs or y/c signal selected 3.9 - v p v z i input impedance 25 -- k w iss suppression of non-selected video input signal note 2 50 -- db s witch control input for external cvbs or y/c selection ( pin 9) v 9 ?lters switched to cvbs condition -- 1.0 v v 9 ?lters switched to y/c condition note 6 2.0 - 3.0 v v 9 automatic selection of cvbs or y/c 3.9 - v p v z i input impedance 25 -- k w chrominance ?lters, luminance delay line and luminance output c hrominance trap circuit f trap trap frequency - f osc - mhz qf trap quality factor notes 2 and 7 - 2 - sr colour subcarrier rejection 20 -- db c hrominance bandpass circuit f c centre frequency - f osc - mhz qbp bandpass quality factor note 2 - 3 - y delay line d t d difference in delay time between the luminance and the demodulated chrominance signals note 2 0 50 100 ns b bandwidth of internal delay line note 2 8 -- mhz y output ( pin 49) v 49(b-w) output signal voltage amplitude (black-to-white value) note 23 0.8 1.0 1.2 v z o output impedance 80 100 120 w v 49(dc) dc output voltage level (top sync) 2.7 2.9 3.1 v i bias internal bias current of npn emitter follower output transistor 0.4 0.5 - ma i source maximum source current -- 2ma symbol parameter conditions min. typ. max. unit
1996 jan 25 10 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A horizontal and vertical synchronization circuits s ync video input ( pins 17 and 20) v 17,20 sync pulse voltage amplitude note 1 50 300 - mv sl slicing level note 8 - 50 - % vertical sync t w width of the vertical sync pulse without sync instability note 9 22 --m s h orizontal oscillator f fr free running frequency - 15625 - hz d f fr spread on free running frequency -- 2% d f osc / d v p frequency variation with respect to the supply voltage v p =8v 10%; note 2 - 0.2 0.5 % d f osc frequency variation with temperature t amb =0to70 c; note 2 -- 80 hz d f osc(max) maximum frequency deviation at the start of the horizontal output no calibration -- 75 % h orizontal pll ( filter connected to pin 37); note 18 f hr holding range pll - 0.9 1.2 khz f cr catching range pll note 2 0.6 0.9 - khz s/n signal-to-noise ratio of the video input signal at which the time constant is switched 14 20 26 db hys hysteresis at the switching point 1 3 6 db h orizontal output ( pin 39) v oh high level output voltage i o = 2 ma 2.4 4.0 - v v ol low level output voltage i o =2ma - 0.3 0.6 v i sink sink current -- 2ma i source source current -- 2ma t w pulse width - 5.4 -m s t d delay between the positive edge of the horizontal output pulse and the start of the horizontal sync pulse at the input - 0 -m s symbol parameter conditions min. typ. max. unit
1996 jan 25 11 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A v ertical output ( pin 36); note 10 f fr free running frequency - 50/60 - hz f lock locking range 45 - 64.5 hz divider value not locked - 625/525 - lines locking range 488 - 722 lines/ frame v oh high level output voltage i ol = 2 ma 2.4 4.0 - v v ol low level output voltage i ol =2ma - 0.3 0.6 v i sink sink current -- 2ma i source source current -- 2ma t w pulse width - 380 -m s t d delay between the start of the vertical sync pulse at the input and the positive edge of the output pulse - 37.5 -m s s andcastle pulse output ( pin 40); note 16 v o output voltage during scan i o = 1 ma; note 24 -- 0.9 v v o output voltage during burst key i o = 1 ma; note 24 4.1 - 5.2 v z o output impedance during blanking 1.0 -- m w t w pulse width burst key 3.3 3.5 3.7 m s line blanking 8.4 8.7 9.0 m s vertical blanking - 14 - lines t d delay of start of burst key to start of sync 5.2 5.4 5.6 m s colour demodulation part c hrominance amplifier acc cr acc control range note 11 26 -- db d v change in amplitude of the output signals over the acc range -- 2db thr on threshold colour killer on - 38 - 41 - 44 db hys off hysteresis colour killer off note 2 strong input signal s/n 3 40 db 0 +3 +6 db noisy input signal 0 +1 +8 db acl circuit chrominance burst ratio at which the acl starts to operate 2.3 - 2.7 symbol parameter conditions min. typ. max. unit
1996 jan 25 12 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A r eference part phase-locked loop; note 12 f cr catching range 300 500 - hz dj phase shift for a 300 hz deviation of the oscillator frequency note 2 -- 2 deg oscillator tc osc temperature coef?cient of f osc note 2 - 2.0 2.5 hz/k d f osc f osc deviation with respect to v p v p =8v 10%; note 2 -- 250 hz r i input resistance (pins 43 to 45) f i = 3.58 mhz; note 1 - 1.5 - k w r i input resistance (pin 42) f i = 4.43 mhz; note 1 - 1 - k w c i input capacitance (pins 42 to 45) note 1 -- 10 pf r required resistance to v p for a crystal pin which is not used note 20 7.8 8.2 8.6 k w h ue control input ( pin 28); note 21 hue cr hue control range see also fig.3 35 40 - deg v control control voltage to switch the colour pll in the free-running mode note 12 v p - 1 -- v r i input resistance 45 -- k w d emodulator outputs ( pins 50 and 51) v 50(p-p) - (b - y) output signal voltage amplitude (peak-to-peak value) note 25 1.06 1.33 1.60 v v 51(p-p) - (r - y) output signal voltage amplitude (peak-to-peak value) note 25 0.84 1.05 1.26 v spread of signal amplitude ratio pal/ntsc note 2 - 1 - +1 db z o output impedance (r - y)/(b - y) output -- 500 w b bandwidth of demodulators - 3 db; note 19 - 650 - khz v 50(p-p) (b - y) residual carrier output voltage (peak-to-peak value) f=f osc -- 1mv f=2f osc -- 5mv v 51(p-p) (r - y) residual carrier output voltage (peak-to-peak value) f=f osc -- 1mv f=2f osc -- 5mv v 51(p-p) h/2 ripple at (r - y) output (peak-to-peak value) only burst fed to input -- 25 mv d v o / d t change of output signal amplitude with temperature note 2 - 0.1 - %/k d v o / d v p change of output signal amplitude with supply voltage note 2 -- 0.1 db i bias internal bias current of npn emitter follower output transistor 0.16 0.20 - ma i source maximum source current -- 1ma symbol parameter conditions min. typ. max. unit
1996 jan 25 13 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A d emodulation angle and gain ratio demodulation angle 85 90 95 deg g gain ratio of both demodulators g(b - y) to g(r - y) 1.60 1.78 1.96 r eference signal output for tda 8395 ( pin 48) f ref reference frequency note 13 - 4.43 - mhz v 48(p-p) output signal amplitude (peak-to-peak value) 0.2 0.25 0.3 v v o output voltage level pal/ntsc identi?ed 1.5 1.6 1.7 v v o output voltage level no pal/ntsc; secam (by tda8395) identi?ed 4.3 4.5 4.7 v i 48 required current to force the decoder in secam mode 120 --m a s tandard identification and forced system switching ( pins 4 and 23 to 27); note 14 v i/o input/output voltage in low condition -- 1.0 v in high condition 4.0 - 5.3 v v i(max) maximum input voltage note 22 -- v p v i load maximum load current (pins 23 to 26) -- 1ma i i input current (pins 23 to 26) in low or high condition -- 1 m a when connected to v p note 22 -- 10 m a r i input resistance (pin 27) 80 -- k w v o output voltage (pin 4) i o = 0.5 ma; notes 17 and 24 during pal -- 0.9 v during secam 4.1 - 5.5 v z o output impedance (pin 4) during ntsc note 17 1 -- m w i load maximum load current (pin 4) -- 0.5 ma rgb switch rgb inputs ( pins 1 to 3 and 10 to 12) v i(p-p) signal voltage amplitude (peak-to-peak value) -- 1.3 v z i input impedance 100 -- k w v clamp active clamping voltage level 2.6 2.8 3.0 v i li input leakage current note 2 -- 3 m a i clamp active clamping current - 200 - +200 m a symbol parameter conditions min. typ. max. unit
1996 jan 25 14 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A f ast blanking / switch inputs ( pins 13 and 52); note 15 i i input current -- 0.2 - 0.3 ma v ih high level input voltage 0.9 - 3.0 v v il low level input voltage 0 - 0.5 v t d delay between input and output pulse -- 50 ns t d delay between switch input and rgb output -- 70 ns v 13 input voltage on pin 13 to make rgb outputs and the fast blanking output high-ohmic 4 - v p v c lamping pulse input ( pin 14) v ih high level input voltage 4.0 4.5 v p v v il low level input voltage -- 1v z i input impedance 1 -- m w rgb outputs ( pins 6 to 8) g v voltage gain of the switches f=1mhz - 0.5 0 +0.5 db g diff gain difference of the three channels -- 0.5 db z o output impedance -- 150 w z o(off) output impedance in the off state f = 10 mhz 100 -- k w v o output voltage during blanking open-circuit output 1.2 1.4 1.6 v v os blanking off-set voltage of the two sources -- 5mv i source(max) maximum source current -- 1ma i bias internal bias current of npn emitter follower output transistor 0.16 0.2 - ma iss input signal suppression when rgb outputs are high-ohmic f = 5 mhz; note 2 60 -- db f = 10 mhz; note 2 50 -- db f = 22 mhz; note 2 40 -- db a ct crosstalk between the two rgb channels f = 5 mhz; note 2 - 60 -- db f = 10 mhz; note 2 - 50 -- db f = 22 mhz; note 2 - 40 -- db b bandwidth of the rgb channels c l = 20 pf; note 2 gain reduction - 0.5 db 5 -- mhz gain reduction - 1db 10 -- mhz gain reduction - 3db 22 -- mhz t d delay from rgb input to output note 2 -- 20 ns symbol parameter conditions min. typ. max. unit
1996 jan 25 15 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A notes 1. this parameter is not tested during production and is just given as application information for the designer of the television receiver. 2. this parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 3. signal with negative-going sync. amplitude includes sync pulse amplitude. 4. burst amplitude; for a colour bar with 75% saturation the chrominance signal amplitude is 660 mv (p-p). 5. the ic has two 3-level switch control inputs for the selection of the video signal for the decoder and synchronization circuits. the video source for internal or external signal is selected via pin 32, also the polarity of the demodulation for the internal signal. when the video switch is in the external position the voltage level of pin 9 determines whether the video filters are switched to cvbs or y/c. it is also possible via pin 9 to select an automatic detection of the y/c signal. 6. this value is internally generated when the pin is left open-circuit (the minimum value of the series resistor is 25 k w ). 7. the - 3 db bandwidth of the circuit can be calculated by means of the following equation: 8. the slicing level is independent of the sync pulse amplitude. 9. the horizontal and vertical sync are stable while processing copy guard signals and signals with phase shifted sync pulses (stretched tapes). trick mode conditions of the vcr will also not disturb the synchronization. the value given is the delay caused by the vertical sync pulse integrator. the integrator has been designed such that the vertical sync is not disturbed for special anti-copy tapes with vertical sync pulses with an on/off time of 10/22 m s. 10. the timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. this divider circuit has 2 search modes of operation: a) the large window mode is switched on when the circuit is not synchronized or, when a non-standard signal is received (the number of lines per frame in the 50 hz mode is between 311 and 314 and in the 60 hz mode between 261 and 264). in the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 hz). b) the narrow window mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window. when the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. consequently, the disturbance of the picture is very small. the circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. f ast blanking output ( pin 5) v oh high level output voltage 2 - 3v v ol low level output voltage 0 - 0.3 v z o output impedance -- 300 w z o(off) output impedance in the off state 100 -- k w t r rise time of the output pulse -- 30 ns t f fall time of the output pulse -- 30 ns t d delay difference between fast blanking and rgb at the outputs -- 30 ns i load maximum load current -- 1ma symbol parameter conditions min. typ. max. unit f 3db C f osc 1 1 2q ------- - C ? ?? =
1996 jan 25 16 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A 11. at a chrominance input voltage of 660 mv (p-p) (colour bar with 75% saturation i.e. burst signal amplitude 300 mv (p-p)) as given in characteristics first parameter of section chrominance input (pin 16) the dynamic range of the acc is +6 and - 20 db. 12. all frequency variations are referenced to 3.58/4.43 mhz carrier frequency. all oscillator specifications are measured with the philips crystal series 9922 520. if the spurious response of the 4.43 mhz crystal is lower than - 3 db with respect to the fundamental frequency for a damping resistance of 1 k w , oscillation at the fundamental frequency is guaranteed. the spurious response of the 3.58 mhz crystal must be lower than - 3 db with respect to the fundamental frequency for a damping resistance of 1.5 k w . the catching and detuning range are measured for nominal crystal parameters. these are: a) load resonance frequency f 0 (c l = 20 pf) = 4.433619 or 3.579545 mhz b) motional capacitance c m = 20.6 ff (4.43 mhz crystal) or 14.7 ff (3.58 mhz crystal) c) parallel capacitance c 0 = 5.5 pf (4.43 mhz crystal) or 4.5 pf (3.58 mhz crystal). the actual load capacitance in the application should be c l = 18 pf to account for parasitic capacitances on and off chip. the free-running frequency of the oscillator can be checked by the hue control pin to the positive supply rail. in that condition the colour killer is not active so that the frequency offset is visible on the screen. when two or more crystals are connected to the ic the circuit must be forced to one of the crystals during this test to prevent the oscillator continuously switching between the various frequencies. 13. the reference signal for the tda8395 is available only when the crystal oscillator is operating at a frequency of 4.43 mhz. when a secam signal is identified this signal is only available during the vertical retrace period thus avoiding crosstalk with the incoming secam signal during scan. 14. the identified colour standard can be read from the ic in two ways: a) from the voltage level of pin 4. the voltage during the demodulation of the various standards is given in the last three parameters of this section. b) from the pins 23 to 26 when pin 27 is in the read mode. when pin 27 is in the write mode the colour decoder can be forced to one of the colour standards. the levels for the various standards are given in tables 1, 2 and 3. 15. the control possibilities of the rgb switch via pins 13 and 52 are shown in table 4. 16. to obtain a simple interface between the TDA8310A and the pip processor the sandcastle output has been designed such that the output is pulled down during scan and pulled up during the burst key pulse. during blanking the output is high-ohmic and therefore the output voltage is determined by the load. 17. the output of pin 4 is designed similar to the sandcastle output. the output is pulled down during pal and pulled up during secam. during ntsc the pin is floating so that the output level is determined by the load. 18. to obtain a good performance for both weak signal and vcr playback the time constant of the first control loop is switched depending on the input signal condition. therefore the circuit contains a noise detector and the time constant is switched to slow when excessive noise is present in the signal. this occurs when the internal video signal is selected or for an external cvbs signal when the chrominance input (pin 16) is left open-circuit. the time constant is always fast when the chrominance input pin is connected to ground and the input is switched to the y/c mode. in the fast mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to head-switching of the vcr are corrected as soon as possible. during weak signal conditions (noise detector active) the phase detector is gated and the width of the gate pulse has a value of 5.7 m s so that the effect of the noise is reduced to a minimum. the output current of the phase detector for the various conditions is shown in table 5. 19. this value indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass filter. the bandwidth of the demodulator low-pass filter is approximately 1 mhz.
1996 jan 25 17 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A 20. the crystal pins which are not used must be connected to the positive supply line via an 8.2 k w resistor. it is also possible to connect the non-used pins together and use a resistor with a value of 8.2 k w divided by the number of pins which are not used. 21. when this pin is left open-circuit the hue control is set to the nominal value. 22. when one or more pins have to be connected to the positive supply line the total current must be limited to 40 m a. this can be achieved by connecting these pins together and connecting them to a positive supply line via a 100 k w resistor. when separate resistors are used a resistor with a higher value must be used so that the total current is limited to the required level. 23. this output signal value is obtained when the cvbs or y input signal at pins 17 and/or 20 has an amplitude of 0.7 v (black-to-white value). 24. the output buffer consists of a combination of a pmos and an nmos. the maximum output impedance in the low state can be calculated by dividing the maximum output voltage (for this parameter 0.9 v) by the specified current. for the high state this resistance can be calculated by dividing the difference between the maximum and minimum output voltage by the specified current. the output impedance is independent of the value of the output current. 25. these output signal values are obtained for a colour bar input signal with 75% saturation.
1996 jan 25 18 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A table 1 read/write pin input (pin 27) table 2 colour system logic (pins 25 and 26) table 3 crystal logic (pins 23 and 24) table 4 control logic rgb switch (pins 13 and 52) mode level decoder automatic low forced decoder mode high pin 25 pin 26 standard low low auto/no colour low high pal high low ntsc high high secam pin 23 pin 24 selected crystal (mhz) low low 4.43 low high 3.579 (ntsc) high low 3.575 (pal-m) high high 3.582 (pal-n) pin 13 pin 52 rgb output fast blanking output low low black low low high rgb 2 high high low rgb 1 high high high rgb 2 high table 5 output current of phase detector current phase detector during scan ( m a) vertical retrace ( m a) gated yes/no weak signal and synchronized 30 30 yes (5.7 m s) strong signal and synchronized 180 270 no not synchronized 180 270 no fig.3 hue control curve. h andbook, halfpage mbe018 40 20 20 40 (deg) 012345 (v) 0
1996 jan 25 19 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot247-1 90-01-22 95-03-11 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 47.9 47.1 14.0 13.7 3.2 2.8 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 d a 2 z 52 1 27 26 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z e a max. 12 a min. a max. sdip52: plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
1996 jan 25 20 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1996 jan 25 21 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A notes
1996 jan 25 22 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A notes
1996 jan 25 23 philips semiconductors product speci?cation pal/ntsc colour processor for pip applications TDA8310A notes
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(02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scds47 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1100/02/pp24 date of release: 1996 jan 25 document order number: 9397 750 00589

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