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| preliminary t his document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue w ork on this proposed product without notice. publication# 20650 rev: b amendment/ 0 issue date: january 1998 AM79C984a enhanced integrated multiport repeater (eimr ) distinctive characteristics n repeater functions comply with ieee 802.3 repeater unit speci?ations n four integral 10base-t transceivers with on- chip ?tering that eliminate the need for external ?ter modules on the 10base-t transmit-data (txd) and receive-data (rxd) lines n one reversible attachment unit interface (raui ) port that can be used either as a standard ieee-compliant aui port for connection to a medium attachment unit (mau), or as a reversed port for direct connection to a media access controller (mac) n low cost suitable for non-managed multiport repeater designs n expandable to increase number of repeater ports with support for up to seven eimr devices without the need for an external arbiter n all ports can be individually isolated (partitioned) in response to excessive collision conditions or fault conditions. n full led support for individual port status leds and network utilization leds n programmable extended distance mode on the rxd lines, allowing connection to cables longer than 100 meters n twisted pair link test capability conforming to the 10base-t standard. the link test function and the transmission of link test pulses can be optionally disabled through the control port to allow devices that do not implement the link test function to work with the eimr device. n programmable option of automatic polarity detection and correction permits automatic recovery due to wiring errors n full amplitude and timing regeneration for retransmitted waveforms n cmos device with a single +5-v supply general description the enhanced integrated multiport repeater (eimr) device is a vlsi integrated circuit that provides a sys- tem-level solution to designing non-managed multiport repeaters. the device integrates the repeater functions speci?d in section 9 of the ieee 802.3 standard and twisted pair transceiver functions complying with the 10base-t standard. the eimr device provides four twisted pair (tp) ports and one raui port for direct connection to a mac. the total number of ports per repeater unit can be in- creased by connecting multiple eimr devices through their expansion ports, hence, minimizing the total cost per repeater port. the device is fabricated in cmos technology and requires a single +5-v supply.
p r e l i m i n a r y 2 AM79C984a ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description AM79C984a enhanced integrated multiport repeater (eimr) temperature range c = commercial (0?c to +70?c) alternate packaging option \w = trimmed and formed in a tray package type j = 84-pin plastic leaded chip carrier (pl 084) k = 100-pin plastic quad flat pack (pqr100) AM79C984a c j speed option not applicable valid combinations AM79C984a jc, kc\w \w p r e l i m i n a r y AM79C984a 3 block diagram 20650b-1 rx mux phase lock loop fifo fifo control preamble jam sequence partitioning link test timers aui port di ci do tp port 0 rxd txd rxd txd reset clock gen clk expansion port dat jam test and control port si so rst sclk amode 20650a-1 rx mux tx mux eimr chip control tp port 3 manchester encoder manchester decoder col ack seli [1:0] selo led interface lda[4:0], ldb[4:0] ldga, ldgb ldc[2:0] act[7:0] p r e l i m i n a r y 4 AM79C984a related amd products part no. description am7990 local area network controller for ethernet (lance) am7992b serial interface adapter (sia) am7996 ieee 802.3/ethernet/cheapernet transceiver am79c90 cmos local area network controller for ethernet (c-lance) am79c98 twisted pair ethernet transceiver (tpex) am79c100 twisted pair ethernet transceiver plus (tpex+) am79c981 integrated multiport repeater plus (imr+ ) am79c982 basic integrated multiport repeater (bimr ) am79c987 hardware implemented management information base (himib ) am79c988 quad integrated ethernet transceiver (quiet ) am79c900 integrated local area communications controller (ilacc ) am79c940 media access controller for ethernet (mace ) am79c960 pcnet -isa single-chip ethernet controller (for isa bus) am79c961 pcnet -isa+ single-chip ethernet controller for isa (with microsoft?plug n play?support) am79c961a pcnet -isa ii full duplex single-chip ethernet controller for isa am79c965 pcnet -32 single-chip 32-bit ethernet controller am79c970 pcnet -pci single-chip ethernet controller (for pci bus) am79c970a pcnet -pci ii full duplex single-chip ethernet controller (for pci bus) am79c974 pcnet -scsi combination ethernet and scsi controller for pci systems am79c983 integrated multiport repeater 2 (imr2 ) am79c985 enhanced integrated multiport repeater plus (eimr+ ) p r e l i m i n a r y AM79C984a 5 table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 standard products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 0 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 related amd products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 connection diagram (pl 084) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35 connection diagram (pqr100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37 pin designations (pl 084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 listed by pin number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38 pin designations (pqr100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 listed by pin number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 aui port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 twisted pair ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 expansion bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-40 control port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 miscellaneous pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-41 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -43 basic repeater functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 repeater function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 signal regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 jabber lockup protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 3 collision handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 fragment extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 auto partitioning/reconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43 detailed functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 aui port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 tp port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 twisted pair transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 twisted pair receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 link test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 polarity reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 visual status monitoring (led) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-45 network activity display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46 expansion bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 internal arbitration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 imr+ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-48 control functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-49 command/response timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 control commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 -50 set (write commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 chip programmable option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 alternate aui partitioning algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 alternate tp partitioning algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 aui port disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 aui port enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 tp port disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 tp port enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 disable link test function (per tp port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 enable link test function (per tp port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 disable link pulse (per tp port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 p r e l i m i n a r y 6 AM79C984a enable link pulse (per tp port). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-52 disable automatic receiver polarity reversal (per tp port) . . . . . . . . . . . . . . . . . 1-53 enable automatic receiver polarity reversal (per tp port) . . . . . . . . . . . . . . . . . 1-53 disable receiver extended distance mode (per tp port) . . . . . . . . . . . . . . . . . . . 1-53 enable receiver extended distance mode (per tp port) . . . . . . . . . . . . . . . . . . . 1-53 disable software override of leds 5 (per port - aui and tp, global) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-53 enable software override of bank a leds (per port - aui and tp, global) . . . . . 1-53 enable software override of bank b leds (per port - aui and tp, global) . . . . . 1-54 software override of led blink rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 get (read commands) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 aui port(s) status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 alternate aui port(s) status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 tp port partitioning status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 bit rate error status of tp ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 link test status of tp ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 receive polarity status of tp ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 mjlp status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 systems applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 eimr to tp port connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 twisted pair transmitters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 twisted pair receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55 mac interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 internal arbitration mode connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 7 imr+ mode external arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-57 visual status display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-59 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-60 dc characteristics over operating ranges unless otherwise speci?d . . . . . . . . . . . . . . . . . 1-60 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-62 key to switching waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64 switching test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-69 p r e l i m i n a r y AM79C984a 7 connection diagram (pl 084) 20650b-2 1 2 3 81 82 83 84 6 7 8 9 4 5 80 76 77 78 79 75 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 43 42 41 40 47 46 45 44 37 36 35 34 39 38 33 48 52 51 50 49 10 22 11 32 53 74 avss di+ di vdd ci+ ci avss do+ do amode vdd dvss vdd vdd vdd rst clk dvss seli_0 seli_1 rext ldc2 ldc1 ldc0 vdd ldgb ldga ldb4 dvss lda4 ldb3 dvss ldb2 lda2 vdd ldb1 lda1 dvss ldb0 lda0 lda3 act7 txd3+ txd3 vdd vdd txd2+ txd2 avss rxd1+ rxd1 rxd2+ rxd2 rxd0+ rxd0 txd1 txd0+ txd0 avss txd1+ vdd rxd3+ rxd3 so si dvss act1 act0 vdd sclk vdd dat ack dvss nc jam act2 act5 act4 act3 dvss act6 col selo eimr AM79C984a 20650a-2 p r e l i m i n a r y 8 AM79C984a connection diagram (pqr100) 20650b-3 28 29 30 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 99 98 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 81 83 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 eimr AM79C984a col dvss nc ack dat vdd jam nc dvss si so sclk vdd act0 act1 act2 dvss act3 act4 act5 vdd nc nc nc ldc2 ldc1 ldc0 vdd ldgb ldga ldb4 dvss lda4 ldb3 lda3 dvss ldb2 lda2 vdd ldb1 lda1 nc dvss ldb0 lda0 act7 nc nc nc act6 rxd3+ rxd2 nc rxd2+ rxd1 rxd1+ rxd0 rxd0+ vdd txd3 txd3+ avss txd2 txd2+ vdd txd1 txd1+ avss txd0 txd0+ rxd3 nc nc nc rext avss di+ di vdd ci+ ci avss do+ do amode vdd dvss vdd vdd vdd rst nc clk dvss seli_0 seli_1 nc nc nc selo p r e l i m i n a r y AM79C984a 9 logic symbol logic diagram 20650b-4 do+ do di+ di ci+ ci sclk clk amode rst dv ss av ss txd+ txd rxd+ rxd v dd AM79C984 aui twisted pair ports (4 ports) jam dat ack col seli [1:0] selo expansion port 20650a-4 test and control port si so led interface lda[4:0], ldb[4:0] ldga, ldgb ldc[2:0] act[7:0] aui control port expansion port twisted pair port 0 twisted pair port 3 20650a-5 repeater state machine led port 20650b-5 p r e l i m i n a r y 10 AM79C984a pin designations (pl 084) listed by pin number pin no . pin name pin no . pin name pin no . pin name pin no. pin name 1 txd3+ 22 amode 43 so 64 lda3 2 txd3- 23 vdd 44 sclk 65 ldb3 3 vdd 24 dvss 45 vdd 66 lda4 4 rxd0+ 25 vdd 46 act0 67 dvss 5 rxd0- 26 vdd 47 act1 68 ldb4 6 rxd1+ 27 vdd 48 act2 69 ldga 7 rxd1- 28 rst 49 dvss 70 ldgb 8 rxd2+ 29 clk 50 act3 71 vdd 9 rxd2- 30 dvss 51 act4 72 ldc0 10 rxd3+ 31 seli_0 52 act5 73 ldc1 11 rxd3- 32 seli_1 53 act6 74 ldc2 12 rext 33 selo 54 act7 75 vdd 13 avss 34 col 55 lda0 76 txd0+ 14 di+ 35 dvss 56 ldb0 77 txd0- 15 di- 36 a ck 57 dvss 78 avss 16 vdd 37 dat 58 lda1 79 txd1+ 17 ci+ 38 vdd 59 ldb1 80 txd1- 18 ci- 39 jam 60 vdd 81 vdd 19 avss 40 nc 61 lda2 82 txd2+ 20 do+ 41 dvss 62 ldb2 83 txd2- 21 do- 42 si 63 dvss 84 avss p r e l i m i n a r y AM79C984a 11 pin designations (pqr100) listed by pin number notes: 1. pin 40 has a bonding option depending on internal device name. 2. nc = no connection. pin no . pin name pin no . pin name pin no . pin name pin no. pin name 1 rxd3- 26 seli_1 51 act6 76 ldc2 2 nc 27 nc 52 nc 77 nc 3 nc 28 nc 53 nc 78 nc 4 nc 29 nc 54 nc 79 nc 5 rext 30 selo 55 act7 80 vdd 6 avss 31 col 56 lda0 81 txd0+ 7 di+ 32 dvss 57 ldb0 82 txd0- 8 di- 33 nc 58 dvss 83 avss 9 vdd 34 a ck 59 nc 84 txd1+ 10 ci+ 35 dat 60 lda1 85 txd1- 11 ci- 36 vdd 61 ldb1 86 vdd 12 avss 37 jam 62 vdd 87 txd2+ 13 do+ 38 nc 63 lda2 88 txd2- 14 do- 39 dvss 64 ldb2 89 avss 15 amode 40 si 65 dvss 90 txd3+ 16 vdd 41 so 66 lda3 91 txd3- 17 dvss 42 sclk 67 ldb3 92 vdd 18 vdd 43 vdd 68 lda4 93 rxd0+ 19 vdd 44 act0 69 dvss 94 rxd0- 20 vdd 45 act1 70 ldb4 95 rxd1+ 21 rst 46 act2 71 ldga 96 rxd1- 22 nc 47 dvss 72 ldgb 97 rxd2+ 23 clk 48 act3 73 vdd 98 nc 24 dvss 49 act4 74 ldc0 99 rxd2- 25 seli_0 50 act5 75 ldc1 100 rxd3+ p r e l i m i n a r y 12 AM79C984a pin description aui port di+, di data in differential input di are differential, manchester receiver pins. the sig- nals comply with ieee 802.3, section 7. do+, do data out differential output do are differential, manchester output driver pins. the signals comply with ieee 802.3, section 7. ci+, ci collision input differential input/output ci are differential, manchester i/o signals. as an input, ci is a collision-receive indicator. as an output, ci gen- erates a 10-mhz signal if the eimr device senses a collision. twisted pair ports txd+ 0-3 , txd 0-3 transmit data differential output txd are 10base-t port differential drivers (4 ports). rxd+ 0-3 , rxd 0-3 receive data differential input rxd are 10base-t port differential receive inputs (4 ports). expansion bus dat data input/output/3-state if the selo and a ck pins are asserted during non- collision conditions, the eimr device drives nrz data onto the dat line, regenerating the preamble if neces- sary. during a collision, when jam is high, dat is used to differentiate between single-port (dat=1) and multi- port (dat=0) collisions. dat is an output when a ck is asserted and the eimr device s ports are active; dat is an input when a ck is asserted and the ports are inactive. if a ck is not asserted, dat is in the high-im- pedance state. it is recommended that dat be pulled up or down via a high value resistor. jam jam input/output/3-state the active eimr device drives jam high, if it detects a collision condition on one or more of its ports. the state of the dat pin is used in conjunction with jam to indicate a single port (dat =1) or multiport (dat=0) col- lision. jam is in the high-impedance state if neither the sel nor a ck signal is asserted. it is recommended that jam be pulled up or down via a high value resistor. seli 0-1 select in input, active low when the expansion bus is con?ured for internal arbi- tration mode, these signals indicate that another eimr device is active; seli 0 or seli 1 is driven by selo from the upstream device. at reset, seli 0 selects between the internal arbitration mode and the imr+ mode of the expansion bus; a high selects the internal arbitration mode and a low selects the imr+ mode. selo select out output, active low if the expansion bus is con?ured for internal arbitration mode, an eimr device drives this pin low when it is active or when either of its seli 0-1 pins is low. an active eimr device is de?ed as having one or more ports receiving or colliding and/or is still transmitting data from the internal fifo, or extending a packet to the minimum of 96 bit times. when the expansion bus is con?ured for imr+ mode, selo is active when the eimr device is active (acquiring the functionality of the req pin on the am79c971 imr+ device). a ck acknowledge input/output, active low, open drain this signal is asserted to indicate that an eimr device is active. it also signals to the other eimr devices the presence of a valid collision status on the jam line and valid data on the dat line. when the eimr device is con?ured for internal arbitration mode, a ck is an i/o, and must be pulled to vdd via a minimum equivalent resistance of 1 k w. when the eimr device is con?ured for imr+ mode, a ck is an input driven by an external arbiter. col collision input/output, active low, open drain when asserted, col indicates that more than one eimr device is active. each eimr device generates the col- lision jam sequence independently. when the eimr de- vice is con?ured for internal arbitration mode, col is seli_1 seli_0 arbitration mode x 1 internal x 0 imr+ p r e l i m i n a r y AM79C984a 13 an i/o and must be pulled to vdd via a minimum equiv- alent resistance of 1 k w. when the eimr device expan- sion port is con?ured for imr+ mode, col is an input driven by an external arbiter. control port amode aui mode input at reset, this pin sets the aui port to either normal or reversed mode. if amode is low at the rising edge of rst , the aui port is set to the normal mode; if amode is high, the aui port is set to the reversed mode. sclk serial clock in input serial data (input or output) is clocked (in or out) on the rising edge of the signal on this pin. sclk is asynchro- nous to clk and can operate at frequencies up to 10 mhz. si serial in input the si pin is used as a test/control serial input port. control commands are clocked in on this pin synchro- nous to sclk input. at reset, si sets the state of the automatic polarity re- versal function. if si is high at the rising edge of rst , automatic polarity reversal is disabled. if si is low at the rising edge of rst , automatic polarity reversal is enabled. so serial out output the so pin is used as a control command serial output port. responses to control commands are clocked out on this pin synchronous to the sclk input. led interface lda 0-4 , ldb 0-4 led drivers output, open drain lda 0-4 and ldb 0-4 drive led bank a and led bank b, respectively. lda 0 and ldb 0 indicate the status of the aui port; lda 1-4 and ldb 1-4 indicate the status of the four tp ports. the port attributes monitored by lda 0-4 and ldb 0-4 are programmed by three pins, ldc 0-2 . ldga global led driver, bank a output, open drain ldga is the global led driver for led bank a. the signal represents global crs or col conditions. in a multiple-eimr con?uration, ldga from each of the eimr devices can be tied together to drive a single glo- bal led in bank a. ldgb global led driver, bank b output, open drain ldgb is the global led driver for led bank b. the signal represents global crs or jab conditions. in a multiple eimr con?uration, ldgb from each of the eimr devices can be tied together to drive a single glo- bal led in bank b. ldc 0-2 led control input these pins select the attributes that will be displayed on lda 0-4 , ldb 0-4 , ldga, and ldgb. if an led is pro- grammed to display two attributes, the attribute associ- ated with the periodic blink takes precedence. act 0-7 activity display output these signals drive the activity leds, which indicate the percentage of network utilization. the display is up- dated every 250 ms. miscellaneous pins rst reset input, active low when rst is low, the eimr device resets to its default state. on the rising (trailing) edge of rst , the eimr also monitors the state of the sel i 0-1 , si, and amode pins, to con?ure the operating mode of the device. in multi- ple eimr systems, the falling (leading) edge of the rst signal must be synchronized to clk. clk master clock in input this pin is a 20-mhz clock input. rext external reference input this pin is used for an internal current reference. it must be tied to vdd via a 13-k w resistor with 1% tolerance. vdd power power pin this pin supplies power to the device. p r e l i m i n a r y 14 AM79C984a avss analog ground ground pin this pin is the ground reference for the differential receivers and drivers. dvss digital ground ground pin this pin is the ground reference for all the digital logic in the eimr device. p r e l i m i n a r y AM79C984a 15 functional description the AM79C984a eimr device is a single-chip imple- mentation of an ieee 802.3/ethernet repeater (or hub). it is offered with four integral 10base-t ports plus one raui port comprising the basic repeater. the eimr de- vice is also expandable, enabling the implementation of high port count repeaters based on several eimr de- vices. the eimr chip complies with the full set of repeater basic functions as de?ed in section 9 of iso 8802.3 (ansi/ieee 802.3c). the basic repeaters functions are summarized in the paragraphs below. basic repeater functions the AM79C984a chip implements the basic repeater functions as de?ed by section 9.5 of the ansi/ieee 802.3 speci?ation. repeater function if any single network port senses the start of a valid packet on its receive lines, the eimr device will retrans- mit the received data to all other enabled network ports (except when contention exists among any of the ports or when the receive port is partitioned). to allow multi- ple eimr device con?urations, the data will also be re- peated on the expansion bus data line (dat). signal regeneration when retransmitting a packet, the eimr device en- sures that the outgoing packet complies with the ieee 802.3 speci?ation in terms of preamble structure and timing characteristics. speci?ally, data packets re- peated by the eimr device will contain a minimum of 56 preamble bits before the start-of-frame delimiter. in addition, the eimr restores the voltage amplitude of the repeated waveform to levels speci?d in the ieee 802.3 speci?ation. finally, the eimr device restores signal symmetry to repeated data packets, removing jit- ter and distortion caused by the network cabling. jitter present at the output of the aui port will be better than 0.5 ns; jitter at the tp outputs will be better than 1.5 ns. the start-of-packet propagation delay for a repeater set is the time delay between the ?st edge transition of a data packet on its input port to the ?st edge transition of the repeated packet on its output ports. the start-of- packet propagation delay for the eimr is within the speci?ation given in section 9.5.5.1 of the ieee 802.3 standard. jabber lockup protection the eimr device implements a built-in jabber protec- tion scheme to ensure that the network is not disabled by the transmission of excessively long data packets. this protection scheme causes the eimr device to in- terrupt transmission for 96 bit-times if the device has been transmitting continuously for more than 65,536 bit times. this is referred to as mau jabber lockup pro- tection (mjlp). the mjlp status for the eimr device can be read through the control port, using the get mjlp status command. collision handling the eimr device will detect and respond to collision conditions as speci?d in the ieee 802.3 speci?ation. repeater con?urations consisting of multiple eimr devices also comply with the ieee 802.3 speci?ation, using status signals provided by the expansion bus. in particular, a repeater based on one or more eimr de- vices will handle the transmit collision and one-port-left collision conditions correctly, as speci?d in section 9 of the ieee 802.3 speci?ation. fragment extension if the total packet length received is less than 96 bits, including preamble, the eimr device will extend the re- peated packet length to 96 bits by appending a jam se- quence to the original fragment. auto partitioning/reconnection any of the tp ports or the aui port can be partitioned if the duration or frequency of collisions becomes exces- sive. the eimr device will continue to transmit data packets to a partitioned port, but will not respond, as a repeater, to activity on the partitioned port s receiver. the eimr device will monitor the port and reconnect it once certain criteria are met. the criteria for reconnec- tion are speci?d by the ieee 802.3 standard. in addi- tion to the standard reconnection algorithm, the eimr device implements an alternative reconnection algo- rithm, which provides a more robust partitioning func- tion for the tp ports and/or aui port. the eimr device partitions each tp port and the aui port separately and independently of other network ports. the eimr device will partition an enabled network port if either of the following conditions occurs at that port: a. a collision condition exists continuously for more than 2048 bit times. (aui port?qe signal active; tp port?imultaneous transmit and receive). b. a collision condition occurs during each of 32 con- secutive attempts to transmit to that port. in the aui port, a collision condition is indicated by an active sqe signal. in a tp port, a collision condition is indicated when the port is simultaneously attempting to transmit and receive. once a network port is partitioned, the eimr device will reconnect that port, according to the selected recon- nection algorithm, as follows: a. standard reconnection algorithm? data packet longer than 512-bit times (nominal) is transmitted or received by the partitioned port without a collision. p r e l i m i n a r y 16 AM79C984a b. alternative reconnection algorithm? data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision. a partitioned port can also be reconnected by disabling and re-enabling the port. all tp ports use the same reconnection algorithm; ei- ther they must all use the standard algorithm, or they must all use the alternative reconnection algorithm. however, the reconnection algorithm for the aui port is programmed independently from that of the tp ports. detailed functions reset the eimr device enters the reset state when the reset (rst ) pin is driven low. after the initial application of power, the rst pin must be held low for a minimum of 150 m s. if the rst pin is subsequently asserted while power is maintained to the eimr device, a reset dura- tion of only 4 m s is required. this allows the eimr de- vice to reset its internal logic. during reset, the eimr registers are set to their default values. also during re- set, the eimr device sets the output signals to their in- active state; that is, all analog outputs are placed in their idle state, no bidirectional signals are driven, all active-high signals are driven low and all active- low signals are driven high. in a multiple eimr sys- tem, the reset signal must be synchronized to clk. see figure 10 in the systems applications section. the eimr device also monitors the state of the sel i 0-1 , si, and amode pins on the rising (trailing) edge of rst to con?ure the operating mode of the device. table 1 summarizes the state of the eimr chip following reset. aui port the aui port is fully compatible with the ieee 802.3, section 7 requirement for an aui port. it has the signals associated with an aui port: do, di, and ci. the aui port has two modes of operation: normal and reverse. when con?ured for normal operation, the functionality is that of an aui port on a mac (ci is an input). when con?ured for reverse operation, the func- tionality is that of an aui on a mau (ci is an output). the mode of the aui port is set during the trailing (ris- ing) edge of the reset pulse, by the state of the amode pin. a low sets the aui port to its normal mode (ci in- put) and a high sets the aui port to its reversed (ci output) mode. the eimr device can be connected directly to a mac through the aui port. this requires that the aui port be con?ured for reverse operation. refer to the systems applications section for more details. tp port interface twisted pair transmitters txd is a differential twisted-pair driver. when properly terminated, txd will meet the electrical requirements for 10base-t transmitters as speci?d in ieee 802.3, section 14.3.1.2. the txd signal is ?tered on the chip to reduce har- monic content per ieee 802.3, section 14.3.2.1 (10base-t). since ?tering is performed in silicon, txd can connect directly to a standard transformer, thereby, eliminating the need for external ?tering modules. proper termination is shown in the systems applica- tions section. twisted pair receivers rxd is a differential twisted-pair receiver. when prop- erly terminated, rxd will meet the electrical require- ments for 10base-t receivers as speci?d in ieee 802.3, section 14.3.1.3. the receivers do not require table 1. eimr states after reset function state after reset pull up/pull down active-low outputs high no active-high outputs low no so output high no dat, jam high impedance either transmitters (tp and aui) idle no receivers (tp and aui) enabled terminated aui partitioning/reconnection algorithm standard algorithm n/a tp partitioning/reconnection algorithm standard algorithm n/a link test functions for tp ports enabled, tp ports in link fail n/a automatic receiver polarity reversal function disabled if si pin is high enabled if si pin is low n/a p r e l i m i n a r y AM79C984a 17 external ?ter modules. proper termination is shown in the systems applications section. the receiver s threshold voltage can be programmed to an extended-distance mode. in this mode, the differen- tial receiver s threshold is reduced to allow a longer cable than the 100 meters speci?d in the ieee 802.3 standard. for programming details, refer to the control commands section. link test the integrated tp ports implement the link test func- tion, as speci?d in the ieee 802.3 10base-t stan- dard. the eimr device will transmit link test pulses to any tp port after that port s transmitter has been inac- tive for more than 8 ms to 17 ms. conversely, if a tp port does not receive any data packets or link test pulses for more than 65 ms to 132 ms and the link test function is enabled for that port, then that port will enter the link-fail state. the eimr device will disable a port in link-fail state (i.e., disable repeater transmit and receive functions) until it receives either four consecutive link test pulses or a data packet. the link test function can be disabled via the eimr control port on a port-by-port basis, to allow the eimr device to operate with pre-10base-t networks that do not implement the link test function. when the link test function is disabled, the eimr device will not allow the tp port to enter link-fail state, even if no link test pulses or data packets are being received. note, how- ever, that the eimr device will always transmit link test pulses to all tp ports, regardless of whether or not the port is enabled, partitioned, in link-fail state, or has its link test function disabled. separate control com- mands exist for enabling and disabling the transmission of link test pulses on a port-by-port basis. polarity reversal the tp ports can be programmed to receive data if a wiring error results in a data packet being received at a tp port with reversed polarity. this function will be en- abled upon reception of a negative end transmit delim- iter (etd) or negative pulses and allows subsequent packets to be received with the correct polarity. the po- larity-reversal function is executed once following reset or link-fail and can be programmed via the control port to be enabled or disabled on a port-by-port basis. the function may be enabled or disabled, following a reset, depending on the level of the si signal on the rising edge of the rst pulse. visual status monitoring (led) support the eimr status port can be connected to leds to fa- cilitate the visual monitoring of repeater port status. the status port has twelve output signals, lda 0-4 , and ldb 0-4 , ldga, and ldgb. lda 0-4 and ldb 0-4 repre- sent the four tp ports and aui port. ldga and ldgb are global indicators. attributes that may be monitored are carrier sense (crs), collision (col), partition (par), link status (link), loopback (lb), port dis- abled (dis), and jabber (jab). three control bits, ldc 0-2 , select the particular attributes to be displayed on the leds. table 2 shows how the programming combinations for ldc 0-2 control the attributes that will be monitored. each led drive pin (ldga, ldgb, lda 0-4 , and ldb 0-4 ) has two states: off and low. when none of the se- lected attributes are true, the driver is off and the diode is unlit. when an attribute is true, the driver is low, and the corresponding leds in bank a or bank b will be lit. some of the settings (ldc 2 = 1) include a blink func- tion. this allows two attributes to be selected for a given state on the pin. as an example when ldc 0-2 = 110, the lda outputs relating to tp ports will be solidly lit when there is a link established at that port. however, whenever there is activity on a port, the corresponding lda pin will switch on (low) and off at a period of 130 ms. note that a partition on that port will also cause the pin to go low. on ldc settings that have two attributes for a state on a pin (blink or solid-on), the attribute causing the output to blink has priority. (those attributes are shown in table 2 with a blink period speci?d next to it.) if an at- tribute has no blink period speci?d, the led indicates the attribute by being solidly lit. the leds can also be controlled via the control port. the enable software override commands turn the leds on regardless of the attributes selected for dis- play through the ldc setting. enable software over- ride of bank a leds causes the lda 0-4 and ldga pins to be driven low, and enable software override of bank b leds causes the ldb 0-4 and ldgb pins to be driven low. the blink rate is set by the software over- ride led blink rate command. the periods are off, 512 ms, 1560 ms, or solid on. p r e l i m i n a r y 18 AM79C984a notes: 1. crs = carrier sense, col = collision, jab = jabber, link = link, lb = loop back, par = partition, dis = port disabled, blk = blink (number = period of blink). 2. for the ldc 0-2 setting of 000: if the port is partitioned, the link led is off. 3. all leds blink 16 times at 260 ms per blink after reset. 4. all leds are on for approximately 4 seconds after reset. 5. ldc 0-2 = ?10 and ?11 are unde?ed. led software override is executed in two stages, by ?st issuing the blink rate (software override of led blink rate) and then issuing the command to enable the particular port leds (enable software override of bank a/b leds). all port combinations selected for software override control will reference the blink rate last issued by the software override of the led blink rate command. lda 0-4 , ldb 0-4 , ldga, and ldgb are open drain out- put drivers that sink 12 ma of current to turn on the leds. in a multiple eimr con?uration, the outputs from the global led drivers (ldga and ldgb) of each chip can be tied together to drive a single pair of global status leds. crs and col are extended to make it easier for visual recognition; that is, they will remain active for some time even if the corresponding condition has expired. once carrier sense is active, crs will remain active for a minimum of 4 ms. once a collision is detected, col is active for at least 4 ms. the exception to this rule is for selection ldc 0-2 = 111. for this selection, col is stretched to 100 m s. when ldc 0-2 = 000 or ldc 0-2 = 001, the loopback at- tribute (lb) for the aui port is displayed on lda 0 . lb is true when do on the mau is successfully looped back to di on the aui port. lb is false (off) if a loopback error is detected, or if the aui port is disabled or in the re- verse mode. transmit carrier sense is sampled at the end of packet to determine the state of lb. the state of lb remains latched until carrier sense is sampled again for the next packet. the default/power-up state for lb is false (off). figure 1 shows the recommended connection of leds. when lda 0-4 , ldb 0-4 , ldga, or ldgb are low, the led lights. figure 1. visual monitoring application?irect led drive network activity display the eimr status port can drive up to eight leds to in- dicate the network-utilization level as a percentage of bandwidth. the status port uses eight dedicated out- puts (act 0-7 ) to drive a series of leds. the number of leds in the series that will be lit increases as the amount of network activity increases. act 0 represents the lowest level of activity; act 7 represents the high- est. act 0-7 are open-drain outputs that typically sink 12 ma of current to turn on the leds. see figure 2. table 2. led attribute-monitoring program options led control global leds tp leds aui leds ldc 2 ldc 1 ldc 0 ldga ldgb lda 1-4 ldb 1-4 lda 0 ldb 0 0 0 0 crs col link (note 2) par lb par 0 0 1 crs col link crs lb crs 0 1 0 reserved (note 5) 0 1 1 reserved (note 5) 1 0 0 crs 260-ms blk col 260-ms blk link crs 260-ms blk par col 260-ms blk crs 260-ms blk par col 260-ms blk 1 0 1 col jab link (note 3) crs 512-ms blk par (note 3) (note 3) crs 512-ms blk par (note 3) 1 1 0 crs col link crs 130-ms blk par or dis crs 130-ms blk par or dis 1 1 1 crs col link (note 4) par 1.56-s blk col (note 4) (note 4) par 1.56-s blk par (note 4) eimr led interface lda[4:0] ldb[4:0] ldga ldgb r v dd typical 20650a-6 20650b-6 p r e l i m i n a r y AM79C984a 19 figure 2. network activity display table 3 shows act 0-7 as a function of the percentage of network utilization. the table uses a scale that is more sensitive at low utilization levels. 100% utilization represents the maximum number of events that could occur in a given window of time. the update rate and corresponding internal sampling window for act[7:0] is 250 ms. during this sampling window, a counter is used to count the number of times repeater transmit activity is true. the counter uses a free-running clock which has the granularity to detect the minimum packet size of 96 bit times. figure 3 shows the timing relationship between the sampling window, counting clock, and transmit activity. figure 3. activity sampling act[0] act[1] act[4] act[5] act[2] act[3] act[6] act[7] eimr led interface v dd 20650a-7 table 3. network utilization number of leds lit by act 7-0 percentage utilization 8 >80% 7 >64% 6 >32% 5 >16% 4 >8% 3 >4% 2 >2% 1 >1% sampling window counting clock xmit activity counter is active next counting cycle latch data; update display; clear counter 20650b-8 p r e l i m i n a r y 20 AM79C984a expansion bus interface the eimr device expansion bus allows multiple eimr devices to be interconnected. the expansion bus supports two modes of operation: internal arbitration mode and imr+ mode. the internal arbitration mode uses a modi?d daisy-chain scheme to eliminate the need for any external arbitration cir- cuitry. the imr+ mode maintains the full functionality of the imr+ (am79c981) expansion bus and bene?s from minimum delays. in this mode, the eimr device requires external circuitry to handle arbitration for con- trol of the bus. the eimr arbitration mode is determined at reset. this occurs on the trailing edge of rst according to the state of seli 0-1 , as illustrated in figure 4. internal arbitration mode the internal arbitration mode uses a daisy-chain (cas- cade) con?uration. seli 0-1 are arbitration inputs and selo is the arbitration output. selo goes low when there is activity on one or more of the eimr ports, or a seli input is low. the sel lines are connected as shown in figure 5. this technique allows activity indica- tion to propagate down the chain to the end device. all unused seli inputs must be tied to vdd. a ck and col are global activity i/o pins. when the eimr device senses activity, it drives a ck low. . figure 4. expansion bus mode selection an eimr device drives col low when it senses more than one device is active; that is, if the device has an active port and a seli input is low, or both seli in- puts are low. in boolean notation, the formula for col is: col = (active port & (seli 1 + seli 0 ))+ (seli 1 & seli 0 ) where & represents the boolean and operation + represents the boolean or operation a ck and col are mutually exclusive. if an eimr driv- ing a ck senses col low, the device will deassert a ck. dat and jam are synchronized to clk. dat is the rep- etition of data from any connected port (either tp or aui port) encoded in nrz format. jam is an internal collision indicator. if jam is high, the active eimr de- vice has detected an internal collision across one or more of its ports. when this occurs, the dat signal dis- tinguishes between single-port collisions and multiport collisions. dat = 1 indicates a single port collision; dat = 0 indicates a multiport collision. the drive capabilities of the i/o signals on the expan- sion bus (dat, jam, a ck , and col ) are suf?ient to allow seven eimr devices to be connected together without the use of external transceivers or buffers. the maximum number of eimr devices that can be daisy chained is limited by the propagation delay of the eimr devices. in practice, the depth of the cascade is limited to three eimr devices, thus allowing a maxi- mum of seven eimr devices connected together via this expansion bus as shown in figure 5. the active device will not drive the data line, dat, until one bit time (100 ns) after selo goes low. this is to avoid a situation where two devices drive dat simultaneously. imr+ mode in imr+ mode, the expansion bus requires an external arbiter. the arbiter allows only one eimr device to con- trol the expansion bus. if more than one device at- tempts to take control, the arbiter terminates all access and signals a collision condition. in imr+ mode, dat and jam retain the same function- ality as in internal arbitration mode, but a ck and col are inputs to the eimr device, driven by the external ar- biter. the arbiter should drive a ck low when exactly one eimr device is active. it should drive col when more than one eimr device is active. selo is an out- put from the eimr device. it indicates that the eimr de- vice has an active port and is requesting access to the bus. when a ck is high, dat and jam are in the high- impedance state. dat and jam go active when a ck goes low. refer to the systems applications section (figure 13) for the con?uration of imr+ mode of operation. note: the imr+ mode is recommended when arbitrating between multiple boards. . 20650b-9 rst seli_0 mode selection seli_1 seli_0 arbitration mode x 1 internal x 0 imr+ p r e l i m i n a r y AM79C984a 21 figure 5. internal arbitration?imr devices in cascade control functions the eimr device receives control commands in the form of byte-length data on the serial input pin, si. if the eimr device is expected to provide data in response to the command, it will send byte-length data to the serial- output pin, so. both the input and output data streams are clocked with the rising edge of the sclk signal. the byte-length data is in rs232 serial-data format; that is, one start bit followed by eight data bits. the ex- ternally generated clock at the sclk pin may be either a free-running clock synchronized to the input bit pat- terns, or a series of individual transitions meeting the setup-and-hold times with respect to the input bit pat- tern. if the latter method is used, 20 sclk clock transi- tions are required for control commands that produce so data, and 14 sclk clock transitions are required for control commands that do not produce so data. v dd 20650a-10 1k w seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col 20650b-10 p r e l i m i n a r y 22 AM79C984a command/response timing figure 6 shows the command/response timing. at the end of a get command, the eimr device waits two sclk cycles and then transmits the response on so. . figure 6. control get command/response control commands the following section details the operation of each con- trol commands available in the eimr device. in all cases, the individual bits in each command are shown with the most-signi?ant bit (bit 7) on the left and the least-signi?ant bit (bit 0) on the right. table 4 and table 5 show a summary of default states and a summary of control commands, respectively. note: data is transmitted and received on the serial data lines least-signi?ant bit ?st and most-signi?ant bit last. st d0 d1 d2 d3 d4 d5 d6 d7 sclk si st d0 d1 d2 d3 d4 d5 d6 d7 so 20650a-11 20650b-11 table 4. summary of default states after reset eimr programmable option? off aui partitioning algorithm normal tp partitioning algorithm normal aui/tp port enabled link test enabled link pulse enabled automatic receiver polarity reversal state of si at reset extended distance mode disabled blink rate off software override of leds disabled p r e l i m i n a r y AM79C984a 23 table 5. control port command summary commands si data so data set (write commands) eimr chip programmable options 0000 10s0 alternate aui partitioning algorithm 0001 1111 alternate tp partitioning algorithm 0001 0000 aui port disable 0010 1111 aui port enable 0011 1111 tp port disable 0010 00## tp port enable 0011 00## disable link test function (per tp port) 0100 00## enable link test function (per tp port) 0101 00## disable link pulse (per tp port) 0100 10## enable link pulse (per tp port) 0101 10## disable automatic receiver polarity reversal (per tp port) 0110 00## enable automatic receiver polarity reversal (per tp port) 0111 00## disable receiver extended distance mode (per tp port) 0110 10## enable receiver extended distance mode (per tp port) 0111 10## disable software override of leds (per port - aui & tp) 1001 #### enable software override of bank a leds (per port - aui & tp, global) 1011 #### enable software override of bank b leds (per port - aui & tp, global) 1100 #### software override led blink rate 1110 1### get (read commands) aui port status (b, s, and l cleared) 1000 1111 pbsl 0000 aui port status (b cleared) 1000 1101 pbsl 0000 aui port status (s, l, cleared) 1000 1011 pbsl 0000 aui port status (none cleared) 1000 1001 pbsl 0000 tp port partitioning status 1000 0000 0000 c3..c0 bit rate error status of tp ports 1010 0000 0000 e3..e0 link test status of tp ports 1101 0000 0000 l3..l0 receive polarity status of tp ports 1110 0000 0000 p3..p0 mjlp status 1111 0000 m000 0000 version 1111 1111 0000 0011 p r e l i m i n a r y 24 AM79C984a set (write commands) chip prog r ammab le option si data 0000 10s0 so data none the eimr chip programmable option can be enabled (or disabled) by setting (or resetting) the s bit in the command string. s aui sqe test mask setting this bit allows the eimr chip to ignore activity on the ci signal pair, during the sqe test window, following a transmission on the aui port. enabling this function does not prevent the reporting of this condition by the eimr device. the two functions operate independently. the sqe test window, as de?ed in ieee 802.3 (sec- tion 7.2.2.2.4) is from 6 bit times to 34 bit times (0.6 m s to 3.4 m s). this includes the delay introduced by a 50- meter aui. ci activity that occurs outside this window is not ignored and is treated as a true collision. alter nate a ui p ar titioning algor ithm si data 0001 1111 so data none invoking this command sets the partition/reconnection scheme for the aui port to the alternate (transmit-only) reconnection algorithm. to return the aui port to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the eimr device. the standard partitioning algorithm is selected on reset. alter nate tp p ar titioning algor ithm si data 0001 0000 so data none invoking this command sets the partition/reconnection scheme for the tp ports to the alternate (transmit-only) reconnection algorithm. to return the tp ports to the standard (transmit or receive) reconnection algorithm, it is necessary to reset the eimr device. the standard partitioning algorithm is selected on reset. a ui p or t disab le si 0010 1111 so data none this command disables the aui port. subsequently, the eimr chip will ignore all inputs to this port and will not transmit a dat or jam pattern on the aui port. disabling the aui port also sets the partitioning state machine of the aui port to the idle state. therefore, a partitioned port can be reconnected by ?st disabling the aui port and then enabling the aui port. a ui p or t enab le si 0011 1111 so data none this command enables the aui port. tp p or t disab le si data 0010 00## so data none this command disables the tp port designated by the two least-signi?ant bits of the command byte. subse- quently, the eimr chip will ignore all inputs to the des- ignated port and will not transmit a dat or jam pattern on that port. disabling the tp port also sets the parti- tioning state machine of that port to the idle state. there- fore, a partitioned port can be reconnected by ?st disabling the port and then enabling it. tp p or t enab le si data 0011 00## so data none this command enables the tp port designated by the two least-signi?ant bits of the command byte. disab le link t est function (p er tp por t) si data 0100 00## so data none this command disables the link test function of the tp port designated by the two least-signi?ant bits of the command data. as a consequence of this, the port will no longer be disconnected if it fails the link test. if a port has the link test disabled, reading the link test status indicates a ?ink pass? enab le link t est function (p er tp por t) si data 0101 00## so data none this command enables the link test function of the tp port designated by the two least-signi?ant bits of the command data. as a consequence of this, the port is disconnected if it fails the link test. disab le link pulse (p er tp p or t) si data 0100 10## so data none this command disables the transmission of the link pulse on the tp port designated by the two least- signi?ant bits of the command byte. enab le link pulse (p er tp p or t) si data 0101 10## so data none this command enables the transmission of the link pulse on the tp port designated by the two least- signi?ant bits of the command byte. p r e l i m i n a r y AM79C984a 25 disab le a utomatic receiv er p olar ity re v ersal (p er tp p or t) si data 0110 00## so data none this command disables the automatic receiver polarity reversal function for the tp port designated by the two least-signi?ant bits in the command byte. if this func- tion is disabled on a tp port receiving with reversed polarity (due to a wiring error), the tp port will fail the link test due to the incorrect polarity of the received link pulses. the state of automatic polarity reversal function is set by si on reset. if si is high at the rising edge of rst , the eimr device disables automatic polarity reversal. if si is low at the rising edge of rst , the eimr device enables automatic polarity reversal. enab le a utomatic receiv er p olar ity re v ersal (p er tp p or t) si data 0111 00## so data none this command enables the automatic receiver polarity reversal function for the tp port designated by the two least-signi?ant bits in the command byte. if enabled in a tp port, the eimr chip will automatically invert the polarity of that port s receiver circuitry if the tp port is detected as having reversed polarity (due to wiring er- ror). after reversing the receiver polarity, the tp port could then receive subsequent (reverse polarity) packets correctly. disab le receiv er extended distance mode (p er tp p or t) si data 0110 10## so data none this command disables the receiver extended distance mode and restores the rxd circuit of the trans- ceiver to normal squelch levels for the tp port driver designated by the two least-signi?ant bits of the com- mand data. enab le receiv er extended distance mode (p er tp p or t) si data 0111 10## so data none this command modi?s the rxd circuit of the trans- ceiver for the tp port driver designated by the two least- signi?ant bits of the command data. the rxd squelch- threshold value is lowered to accommodate signal at- tenuation associated with lines longer than 100 meters. at reset, receiver extended distance mode is disabled and the rxd circuit defaults to normal squelch-thresh- old values. disab le softw are ov err ide of leds (p er p or t - a ui and tp , global) si data 1001 #### so data none this command disables software override of the port leds. individual leds and combinations of leds can be selected via the lower four bits of the command byte as follows: #### p or t(s) aff ected 0000-0011 tp0 - tp3 0100-0111 reserved 1000 aui port 1001 reserved 1010 reserved 1011 all tp ports 1100 all ports 1101 global 1110 reserved 1111 reserved following command execution, the attributes displayed on the leds will be determined by ldc 0-2 . software override of leds is disabled after reset. enab le softw are ov err ide of bank a leds (p er p or t - a ui and tp , global) si data 1011 #### so data none this command forces the leds in bank a to blink. in- dividual leds and combinations of leds can be select- ed via the lower four bits of the command byte as follows: #### p or t(s) aff ected 0000-0011 tp0 - tp3 0100-0111 reserved 1000 aui port 1001 reserved 1010 reserved 1011 all tp ports 1100 all ports 1101 global 1110 reserved 1111 reserved the designated led driver(s) will switch between low and ?ff at the rate set by the software override blink rate command. enable software override of bank a leds references the blink rate last issued and overrides any other attribute speci?d by ldc 0-2 . software over- ride of leds is disabled after reset. p r e l i m i n a r y 26 AM79C984a enab le softw are ov err ide of bank b leds (p er p or t - a ui and tp , global) si data 1100 #### so data none this command forces the leds in bank b to blink. in- dividual leds and combinations of leds can be select- ed via the lower four bits of the command byte as follows: #### p or t(s) aff ected 0000-0011 tp0 - tp3 0100-0111 reserved 1000 aui port 1001 reserved 1010 reserved 1011 all tp ports 1100 all ports 1101 global 1110 reserved 1111 reserved the designated led driver(s) will switch between low and ?ff at the rate set by the software override of led blink rate command. enable software override of bank b leds references the blink rate last issued and overrides any other attribute speci?d by ldc 0-2 . soft- ware override of leds is disabled after reset. softw are ov err ide of led blink rate si data 1110 1### so data none this command sets the blink period of the leds with software override enabled. the duty cycle is 50%. this command defaults to ?ff at reset. setting blink p er iod 1110 1000 off 1110 1001 512 ms 1110 1010 1560 ms 1110 1011 solid on these settings apply to the blink rate for both bank a and bank b. this command must precede the enable software override of bank a/b leds command. all led combinations selected for software override will refer- ence the blink rate last issued. get (read commands) a ui p or t(s) status si data 1000 1111 so data pbsl 0000 the combined aui status of the eimr device allows a single instruction to be used to monitor the aui port. the four local status bits are: p partitioning status this bit is ? if the aui port is partitioned and ? if the aui port is connected. b bit rate error this bit is set to ? if there is an instance of fifo over?w or under?w. the bit is cleared when the eimr device is read. s sqe test status this bit is set to ? if the sqe test error is detected by the eimr chip. the bit is cleared when the status is read. l loopback error the mau attached to the aui port is required to loop- back data transmitted to do onto the di circuit. if the loopback carrier is not detected by the eimr device, this bit is set to ?? this bit is cleared when the status is read. alter nate a ui p or t(s) status there are three further variations of the aui port status command allowing selective clearing of a combination of b,s, and l bits. these are the following: alternate 1: b is not cleared, s and l are cleared si data 1000 1011 so data pbsl 0000 alternate 2: s and l are not cleared, b is cleared si data 1000 1101 so data pbsl 0000 alternate 3: none of s, b, and l are cleared si data 1000 1001 so data pbsl 0000 tp p or t p ar titioning status si data 1000 0000 so data 0000 p3..p0 p n = 0 tp port partitioned p n = 1 tp port connected where n is a port number in the range 0?. the response to this command gives the partitioning status of all four tp ports. if a port is disabled, reading its partitioning status will indicate that it is connected. bit rate error status of tp p or ts si data 1010 0000 so data 0000 e3..e0 e n = 0 no error e n = 1 fifo over?w where n is a port number in the range 0?. the response to this command gives the bit-rate-over- ?w or under?w (data rate mismatch) condition of all the tp ports. a 1 indicates that the fifo has over?wed or under?wed due to the amount of data received by the corresponding port. p r e l i m i n a r y AM79C984a 27 link t est status of tp por ts si data 1101 0000 so data 0000 l3..l0 l n = 0 tp port n in link test failed l n = 1 tp port n in link test passed where n is a port number in the range 0?. the response to this command gives the link test sta- tus of all the tp ports. a disabled port continues to report link test status. re-enabling the port causes the port to be placed in the link test fail state. receiv e p olar ity status of tp p or ts si data 1110 0000 so data 0000 p3......p0 p n = 0 tp port n polarity correct p n = 1 tp port n polarity reversed where n is a port number in the range 0?. the response to this command gives the received po- larity status of all the tp ports. if the polarity is detected as reversed for a tp port, then the eimr device will set the appropriate bit in this command s result only if the polarity reversal function is enabled for that port. mjlp status si data 1111 0000 so data m000 0000 each eimr device contains an independent mau jab- ber lock up protection timer. the timer is designed to inhibit the transmit function of the eimr device if it has been transmitting continuously for more than 65536 bit times. this bit remains set and is only cleared when the mjlp status is read using this command. v ersion si data 1111 1111 so data 0000 0011 the response to this command gives the version of the eimr device. 0011 was chosen to help distinguish the eimr device from the imr (am79c980) and the imr+ (am79c981) devices. systems applications eimr to tp port connection the eimr device provides a system solution to designing non-managed multiport repeaters. the eimr device con- nects directly to ac coupling modules for a 10base-t hub. figure 7 shows the simpli?d connection. twisted pair transmitters txd signals need to be properly terminated to meet the electrical requirement for 10base-t transmitters. prop- er termination is shown in figure 8 which consists of a 110- w resistor and a 1:1 transformer. the load is a twisted- pair cable that meets ieee 802.3, section 14.4 speci? cations. the cable is terminated at the opposite end by 100 w . twisted pair receivers rxd signals need to be properly terminated to meet the electrical requirements for 10base-t receivers. proper termination is shown in figure 9. note that the receivers do not require external ?ter modules. p r e l i m i n a r y 28 AM79C984a figure 7. simpli?d 10base-t connection figure 8. txd termination figure 9. rxd termination 110 100 110 100 110 100 110 100 tp connector tp connector tp connector tp connector eimr txd0+ txd0 rxd0+ rxd0 txd1+ txd1 rxd1+ rxd1 txd2+ txd2 rxd2+ rxd2 txd3+ txd3 rxd3+ rxd3 rst clk 1:1 1:1 1:1 1:1 1:1 1:1 1:1 1:1 20650a-12 1:1 twisted pair 100 110 txd+ txd- 20650a-13 20650b-13 20650a-14 1:1 twisted pair 100 100 rxd+ rxd 20650a-14 20650b-14 p r e l i m i n a r y AM79C984a 29 mac interface the eimr device can be connected directly to a mac through the aui port. this requires that the aui port be con?ured in the reverse mode and connected as shown in figure 10a. notice that di is connected to do of the mac and do is connected to di of the mac, because the reverse con?uration only affects ci. where ci is an input in the normal mode, in the reverse mode, ci is an output. figure 10b shows the normal aui con?uration for reference. figure 10. aui port interconnections internal arbitration mode connection the internal arbitration mode uses a modi?d daisy- chain scheme to eliminate the need for any external arbiter. in this mode, a ck and col need to be pulled up through a minimum resistance of 1 k w. the dat and jam pins also need to be pulled down via a high value resistor. refer to figure 11. imr+ mode external arbitration the imr+ mode maintains the full functionality of amd s imr+ (am79c981) device s expansion bus. in this mode, the eimr device requires external circuitry to handle arbitration for control of the bus. figure 12 shows the con?uration for the imr+ mode of operation. do+ do di+ di ci+ ci di+ di do+ do ci+ ci di+ di do+ do ci+ ci di+ di do+ do ci+ ci a) reverse mode (with mac) b) normal mode (with mau) am79c940 eimr am7996 eimr 0.1 f 0.1 f 0.1 f 0.1 f 39 ?150 0.1 f 40 40 40 40 40 40 40 40 40 40 40 40 ? v 1:1 1:1 1:1 20650a-16 20650b-15 p r e l i m i n a r y 30 AM79C984a figure 11. eimr internal arbitration mode connection figure 12. imr+ mode external arbitration v dd v dd v dd ~1 k w 1 k w ~1 k w d q q p c d q q p c rst 74ls74 20 mhz osc clk dat jam ack col clk dat jam ack col ( note: in a multiple eimr system, the reset signal must be synchronized to clk.) clk dat jam ack col eimr seli_0 seli_1 rst selo eimr seli_0 seli_1 rst selo eimr seli_0 seli_1 rst selo 20650b-16 seli_0 seli_1 selo dat jam ack col seli_0 seli_1 selo dat jam ack col col ack sel1 sel2 sel3 arbiter gcol eimr eimr eimr 1 k w seli_0 seli_1 selo dat jam ack col 20650b-17 p r e l i m i n a r y AM79C984a 31 visual status display lda/b[4:0] and ldga/b provide visual status indicators for the eimr. lda/b[4:0] displays link, carrier sense, collision, and partition information for the tp and aui ports. ldga/b display global carrier sense, collision, and jabber information. in a multiple eimr con?uration, the global led drivers (ldga/b) from each chip can be tied together to drive a single pair of global status leds. the open drain out- put of these drivers facilitate this con?uration. refer to figure 13. figure 13. visual status display connection lda[4:0] ldb[4:0] ldga ldgb lda[4:0] ldb[4:0] ldga ldgb vdd 20650a-19 20650b-18 p r e l i m i n a r y 32 AM79C984a absolute maximum ratings storage temperature . . . . . . . . . . ?5 c to +150 c ambient temperature under bias . . . . 0 c to +70 c supply voltage referenced to av ss or dv ss (av dd , dv dd ) . . . . . . . ?.3 v to +6.0 v stresses above those listed under absolute maxi- mum ratings may cause permanent device failure. functionality at or above these limits is not implied. ex- posure to absolute maximum ratings for extended pe- riods may affect reliability. programming conditions may differ. operating ranges commercial (c) devices temperature (t a ) . . . . . . . . . . . . . . . . . 0 c to +70 c supply voltages (v dd ) . . . . . . . . . . . . . . . . . +5 v 5% operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over operating ranges unless otherwise speci?d parameter symbol parameter description test conditions min max unit digital i/o v il input low voltage v ss = 0.0 v ?.5 0.8 v v ih input high voltage v ss = 0.0 v 2.0 0.5 + v dd v v ol output low voltage i ol = 4.0 ma 0.4 v v oh output high voltage i oh = ?.4 ma 2.4 v i il input leakage current v ss p r e l i m i n a r y AM79C984a 35 switc hing c haracteristics (contin ued) notes: 1. p ar ameter not tested. 2. di pulses narro w er than t pw odi (min) will be rejected; pulses wider than t pw odi (max) will tur n inter nal di carr ier sense on. 3. di pulses narro w er than t pwkdi (min) will maintain inter nal di carr ier on; pulses wider than t pwkdi (max) will tur n inter nal di carr ier sense off . 4. ci pulses narro w er than t pw oci (min) will be rejected; pulses wider than t pw oci (max) will tur n inter nal ci carr ier sense on. 5. ci pulses narro w er than t pwkci (min) will maintain inter nal ci carr ier on; pulses wider than t pwkci (max) will tur n inter nal ci carr ier sense off . 6. rxd pulses narro w er than t pwkrd (min) will maintain inter nal rxd carr ier sense on; a pulse wider than t pwkrd (max) will tur n rxd carr ier sense off . p arameter symbol p arameter description t est conditions min max unit t wisted p air p or t timing t txtd clk rising edge to txd t r ansition dela y 50 ns t tetd t r ansmit end of t r ansmission 250 375 ns t pwkrd rxd pulse width maintain/t ur n-off threshold |v in |>|v ths | (note 6) 136 200 ns t perlp idle signal p er iod 8 24 ms t pwlp idle link t est pulse width 75 120 ns contr ol p or t timing t sclk sclk cloc k p er iod 100 ns t sclkh sclk cloc k high 30 ns t sclkl sclk cloc k lo w 30 ns t sclkr sclk cloc k rise time 10 ns t sclkf sclk cloc k f all time 10 ns t siset si input setup time to sclk rising edge 10 ns t sihld si input hold time from sclk rising edge 10 ns t sodly so output dela y from sclk rising edge c l = 100 pf 40 ns p r e l i m i n a r y 36 AM79C984a key to switching waveforms switching w a veforms figure 14. cloc k timing must be steady ma y change from h to l ma y change from l to h does not apply don? care , an y change p er mitted will be steady will be changing from h to l will be changing from l to h changing, state unkno wn center line is high- impedance ?ff state w a veform inputs outputs ks000010-p al 20650b-19 t clk t clkh t clkl t clkr t clkf clk 20650a-20 p r e l i m i n a r y AM79C984a 37 switching w a veforms (contin ued) figure 15. contr ol p or t timing figure 16. reset timing figure 17. mode initialization t sclkh t sclkl t sodly t sclk t siset t sihld sclk si so t sclkf t sclkr 20650a-21 20650b-20 note: tclk represents internal eimr timing t rst or t prst t rsthld t rstset clk rst tclk 20650a-22 20650b-21 20650b-22 t xrs t xrh amode, seli_0 rst p r e l i m i n a r y 38 AM79C984a switching w a veforms (contin ued) figure 18. expansion bus input timing figure 19. expansion bus output timing 20650b-23 note: tclk represents internal eimr timing clk tclk selo ack col dat/jam t djset t djhold in 20650b-24 clk tclk selo ack col dat/jam t clkhrh t caset t caset t clkhrl t cahld t clkhdr t clkhdz out note: tclk represents internal eimr timing p r e l i m i n a r y AM79C984a 39 switching w a veforms (contin ued) figure 20. expansion bus collision timing figure 21. a ui timing dia gram figure 22. a ui receive dia gram clk tclk selo ack col dat/jam t clkhrh t clkhrl t caset t caset t cahld in in note: tclk represents internal eimr timing 20650a-26 20650b-25 20650b-26 clk do+ do t dotr t dotf t dotd t doetd t pwkdi v asq (t pwkci ) t pwodi (t pwoci ) t pwkdi (t pwkci ) di+ (ci ) 20650a-28 20650b-27 p r e l i m i n a r y 40 AM79C984a switching w a veforms (contin ued) figure 23. tp p or ts output timing dia gram figure 24. tp idle link t est pulse figure 25. tp receive timing dia gram 20650b-28 txd+ 1 0 1 1 1 0 1 0 etd txd 0 1 t txetd clk t txetd 20650a-29 t pwlp t perlp rxd+/ v tsq t pwkrd v tsq+ t pwkrd v ths+ v ths t pwkrd p r e l i m i n a r y AM79C984a 41 switching test circuit figure 26. switc hing t est cir cuit pin test point v dd v ss 20650a-32 20650b-31 p r e l i m i n a r y 42 AM79C984a physical dimensions pl 084 84-pin plastic lcc (measured in inches) top view seating plane 1.185 1.195 1.150 1.156 pin 1 i.d. .026 .032 .050 ref .042 .056 .062 .083 .013 .021 1.000 ref .007 .013 .165 .180 .090 .130 16-038-sq pl 084 df79 8-1-95 ae side view 1.185 1.195 1.150 1.156 1.090 1.130 p r e l i m i n a r y AM79C984a 43 physical dimensions pqr100 100-pin plastic quad flat p ac k pin 100 pin 50 pin 30 pin 1 i.d. 17.00 17.40 12.35 ref 13.90 14.10 18.85 ref 19.90 20.10 23.00 23.40 0.25 min 2.70 2.90 0.65 basic 3.35 max seating plane 16-038-pqr-2 pqr100 da92 8-2-94 ae pin 80 trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. am186, am386, am486, am29000, b imr, eimr, eimr+, gigaphy, himib, ilacc, imr, imr+, imr2, isa-hub, mace, magic packet, pcnet, pcnet- fast , pcnet- fast +, pcnet-mobile, qfex, qfexr, quasi , quest, quiet, taxichip, tpex, and tpex plus are trademarks of advanced micro devices, inc. microsoft is a registered trademark of microsoft corporation. product names used in this publication are for identitcation purposes only and may be trademarks of their respective companies. |
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