View CXB1455R_1356258.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

vga/svga/xga 24-bit transmitter description the CXB1455R is the ic which transmits the 24-bit vga/svga/xga definition moving picture based on the gvif (gigabit video interface) technology. features 1 chip transmitter for serial transmission of 24-bit color vga/svga/xga picture on-chip pll synthesizer on-chip differential cable driver ttl/cmos compatible interface supports 1 pixel/shift clock mode with 1 chip and 2 pixel/shift clock mode with 2 chips single 3.3v power supply low power consumption 48-pin plastic qfp package (7mm 7mm) application gigabit video interface block diagram and pin configuration structure bi-cmos ic absolute maximum ratings power supply v cc 4.2 v operating temperature topr 0 to +85 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 333 mw recommended operating condition supply voltage 3.3 0.3 v ?1 e98y03c1z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXB1455R 48 pin lqfp (plastic) 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd ce lpfa lpfb ckpol sdatap sdatan gndt rext v cc a gnda v dd v dd g2 g3 g4 g5 g6 g7 b0 b1 b2 b3 gnd v dd r0 r1 r2 r3 r4 r5 r6 r7 g0 g1 gnd gnd refreq cntl de sftclk hsync vsync b7 b6 b5 b4 v dd p/s converter cable driver pll encoder fig. 1. block diagram and pin configuration
2 CXB1455R pin description power supply/ground symbol v dd gnd v cc a gnda gndt 12, 24, 36, 48 1, 13, 25, 37 34 35 32 logic power supply; connected to 3.3v 0.3v logic ground; connected to 0v analog power supply; connected to 3.3v 0.3v analog ground; connected to 0v transmission ground; connected to 0v pin no. description digital signal symbol sftclk red (7 to 0) grn (7 to 0) blu (7 to 0) hsync vsync cntl de ce ckpol 41 16, 17, 18, 19, 20, 21, 22, 23 6, 7, 8, 9, 10, 11, 14, 15 44, 45, 46, 47, 2, 3, 4, 5 42 43 39 40 26 29 ttl in 1 ttl in 1 ttl in 1 ttl in 1 ttl in 1 ttl in 1 ttl in 2 ttl in 2 shift clock, for the data fetch at rising or falling edge pixel data. 1 pixel/shift clock input. hsync data vsync data panel control data data enable chip enable sftclk polarity pin no. type equivalent circuit description v dd ttl-in gnd sdatap/n 30, 31 tx serial output and refclk request input v cc a sdatap gndt v dd gnd sdatan gnda v dd ttl-in gnd
3 CXB1455R special refreq 38 ttl out refclk request detection flag v dd ttl-out gnd symbol pin no. equivalent circuit description type symbol rext 33 sdatap/n output current trimming. connect to the external resistor. pin no. equivalent circuit description v cc a gnda gnd rext v dd lpfa/b 27, 28 external loop filter v cc a lpfa gnda gnd v dd lpfb
4 CXB1455R electrical characteristics table 1. absolute maximum ratings item supply voltage ttl dc input voltage ttl h level output current ttl l level output current serial output pin voltage ambient temperature storage temperature v cc v i _t i oh _t i ol _t vsdout ta tstg 0.3 0.5 20 0 v cc 1.2 55 65 4.2 6.5 0 20 v cc + 0.5 120 150 v v ma ' ma v c c under bias symbol min. typ. max. unit remarks table 2. recommended operating conditions item supply voltage (includes v dd and vcca) ambient temperature v cc ta 3.0 0 3.3 3.6 85 v c symbol min. typ. max. unit conditions table 3. dc characteristics (under the recommended operating conditions. see table 2.) item ttl high level input voltage ttl low level input voltage ttl high level input current ttl low level input current ce, ckpol high level input voltage ce, ckpol low level input voltage ce, ckpol high level input current ce, ckpol low level input current ttl high level output voltage ttl low level output voltage sdata high level output current sdata low level output current sdata high level output voltage sdata low level output voltage supply current v ih _t v il _t i ih _t i il _t v ih _c v il _c i ih _c i il _c v oh _t v ol _t i oh _sd i ol _sd v ih _sd v il _sd i cc 2 0 1.0 v cc 0.5 0 1.0 2.4 0.1 14.5 v cc 0.55 44.0 50.0 0 15.7 61.0 71.0 5.5 0.8 1.0 5.5 0.5 1.0 0.4 +0.5 17 v cc 0.76 77.0 92.0 v v a a v v a a v v ma ma v v ma ma v in = v cc v in = 0 v in = v cc v in = 0 i oh = 8ma i ol = 8ma rext = 4.7k ? common mode voltage @65mhz symbol min. typ. max. unit conditions grayscale worstcase see fig. 8 see fig. 7
5 CXB1455R table 4. ac characteristics (under the recommended operating conditions. see table 2.) item ttl input rise time ttl input fall time minimum sftclk frequency maximum sftclk frequency sftclk duty factor pixel/sync/cntl setup time to sftclk pixel/sync/cntl hold time to sftclk sdata rise time sdata fall time clock mode assert time clock mode deassert time idle mode assert time idle mode deassert time pll lock-in time tir tif fsftclk dsftclk tsetup thold tor tof taclk tdclk taidle tdidle tlockin 0.7 0.7 65.0 40 2.5 2.5 200 200 50 10 150 100 0.1 5.0 5.0 25.0 60 ns ns mhz mhz % ns ns ps ps ns ns ns ns ms 0.8 to 2.0v 2.0 to 0.8v vth = 1.4v 20 to 80%, c l = 2pf see fig. 2. symbol min. typ. max. unit conditions CXB1455R rgb, ce vs, hs, de, cntl, ckpol fet probe sampling oscillo- scope v cc 51 100 v cc /a ttl clock gnd/a/t 51 41 30 31 fig. 2. sdata waveform measurement
6 CXB1455R timing chart sftclk tir tif tsetup thold tir 2.0v 2.0v 0.8v 0.8v vth v il _t v ih _t v il _t v ih _t 1/fsftclk redxx vsync hsync de rgb cntl there must be 2 sftclk cycles or more left between the cntl edge and the hsync, vsync and de edges. setup/hold times are referred from falling edge in ckpol = gnd rising edge in ckpol = vcc grnxx bluxx h/vsync cntlx tif min. 2 min. 2 min. 2 min. 2 min. 2 min. 2 (sftclk cycle) dsftclk/fsftclk fig. 4. serial output timing tor 80% 20% 0% 100% sdatap sdatan tof fig. 3. ttl input timing
7 CXB1455R fig. 5. refclk request timing sdatap sdatan refreq reference clock nrz data refrq signal from cxb1454r or cxb1456r taclk tdclk fig. 6. idle mode timing sdatap sdatan ce tdidle taidle nrz data rgb <7, 5, 3, 1> rgb <6, 4, 2, 0> sftclk f f/2 f/2 fig. 7. worst case test pattern f f/16 f/8 f/4 f/2 fix low fix low fix low fix low sftclk rgb <7> rgb <6> rgb <5> rgb <4> rgb <3> rgb <2> rgb <1> rgb <0> fig. 8. 16 grayscale test pattern
8 CXB1455R ce sftclk v cc when the power supply and sftclk stabilize 200 s or more fig. 9. ce timing when power supply is turned on ce sftclk when sftclk does not stabilize when sftclk stabilizes 200 s or more ? ? when sftclk stops or the frequencies of 15mhz or less and 75mhz or more are input. fig. 10. ce timing when sftclk input signal is not stabilized ce pin control the ce pin should be controlled as follows. when the power is turned on or sftclk stops, or when the sftclk input signal falls into the disorder while the sftclk frequency is varied, the ce pin should be set to low level and the ce pin should be set to high level after the sftclk frequency stabilizes. (figs. 9 and 10)
9 CXB1455R applications the CXB1455R gvif transmitter is applied to the digital rgb signal transmission for p/c with lcd monitor video-on-demand system monitoring system graphical controller projector digital tv monitor automobile navigation system with gvif receivers, cxb1454r/cxb1456r. CXB1455R gvif transmitter cxb1454r/cxb1456r gvif receiver parallel to serial converter cable driver pll red (7 to 0) grn (7 to 0) blu (7 to 0) sync/de/cntl shiftclock red (7 to 0) grn (7 to 0) blu (7 to 0) sync/de/cntl shiftclock stp or twin axial 8 8 8 4 encoder serial to parallel converter cable equalizer pll decoder 8 8 8 4 table 5. sftclk polarity ckpol l h falling edge rising edge sftclk data sampling trigger ckpol pin control the ckpol pin selects the sftclk data sampling trigger edge. (see table 5)
10 CXB1455R application circuit (1) chip resistor (1%) (2) chip capacitor (3) formed by the printed circuit pattern (l = 0.5 to 1.0mm/w = 0.5 to 1.0mm) (4) lpf chip capacitor (temperature compensation type) high: rising edge trigger low: falling edge trigger 51 (1) 680p (4) 51 (1) 4.7k (1) 0.1 to 0.4n (3) 0.1 to 0.4n (3) 33 16v v cc v cc v cc differential cable 330 connector 0.1 (2) 7 6 5 4 red data 3 2 1 0 msb lsb v cc 0.1 (2) v cc 0.1 (2) 0.1 (2) v cc 0.1 (2) 7 6 5 4 green data 3 2 1 0 msb lsb 7 6 5 4 blue data 3 cntl sftclk hsync vsync de 2 1 0 msb lsb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 gnd refreq cntl de sftclk hsync vsync CXB1455R b6 b4 b7 b5 v cc gnd b3 b2 b1 b0 g7 g6 g3 g2 g5 g4 v cc v cc gnda v cc a rext gndt sdatan sdatap ckpol lpfb lpfa ce gnd v cc r0 r1 r6 r7 g0 g1 r2 r3 r4 r5 gnd sw2 high: transmission data low: standby v cc 330 sw1 0.01 (4) 1k (1) 1k (1) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
11 CXB1455R recommended printed board structure l1: cu plate (18 m) + solder coat i1: fiber-glass epoxy core (0.3mm) l2: cu plate (36 m) i2: fiber-glass epoxy core (0.8mm) l3: cu plate (36 m) i3: fiber-glass epoxy core (0.3mm) l4: cu plate (18 m) + solder coat 12 13 24 48 37 1 48 37 0.5mm l2 doesn't have the plane in this area. locate the bypass capacitor (0.1 f chip capacitor) as close to the pins as possible. : through hole to the gnda plane (l2) : through hole to the gnd plane (l2) : through hole to the vcca plane (l3) : through hole to the vcc plane (l3) : through hole to the rext resistor (l4) : through hole to the ckpol signal (l4) : through hole to the ce signal (l4) chip capacitor chip resistor r p c g a e t gnd refreq cntl de sftclk hsync vsync blu <7> blu <6> blu <5> blu <4> v cc gnd blu <3> blu <2> blu <1> blu <0> grn <7> grn <6> grn <5> grn <4> grn <3> grn <2> v cc v cc gnda v cc a rext gndt sdatan sdatap ckpol lpfb lpfa ce gnd v cc red <0> red <1> red <2> red <3> red <4> red <5> red <6> red <7> grn <0> grn <1> gnd g p t t t r c e e a g g e g g microstrip line the microstrip line with the characteristic impedance of 50 ? should be used to connect the lsi transmission signal pin sdatap/n to the connector foot printer as gvif transmits the high-speed digital signal with the maximum speed of 2gb/s. the optimal line can be made by forming 0.5mm pattern on l1. (see the board structure shown below.) the line lengths should be the same and the through hole should be not used. normally, l2 should be the mat gnd. termination elements locate the 51 ? termination resistors as close to the lsi as possible. filter device and reference resistor the capacitor and resistor connected to lpfa/b and rext are the filter and the reference resistor. locate them as close to the lsi as possible. decrease the parasitic capacitance by removing the l2 gnd plane under these elements and wiring. recommended printed circuit board pattern example of power supply and special signal routing
12 CXB1455R by-pass capacitor locate a 0.1 f chip capacitor as close to the pin as possible as shown in the recommended circuit diagram. notes on transmission system configuration the gvif uses termination on both the transmitting and receiving ends, built-in equalizers, small amplitude differential signals, etc. in order to more easily resolve problems such as signal reflectance, signal attenuation and emi which interfere with high-speed data transmission. however, a number of cautions must be observed over the entire transmission system shown in the figure below in order to completely resolve these problems. tx lsi rx lsi tx termination 50 ? tx termination 100 ? microstrip line (50 ? ) microstrip line (50 ? ) foot print foot print cable (diff. 100 ? ) connector connector the transmission system has the following four requirements. impedance matching shall be excellent. (reflectance shall be low.) a differential impedance that falls within the template shown on the following page is recommended. attenuation shall be low and regular. for the cxb1454r (built-in equalizer) attenuation of 15 db (conforming to root f attenuation) @ 1 ghz or less is recommended. see the following page. for the cxb1456r (no equalizer) attenuation of 6 db @ 1 ghz or less is recommended. differential signal pos/neg skew shall be small. 12% or less during the time for one bit is recommended. 160 ps @ vga, 100 ps @ svga, 60 ps @ xga emi characteristics shall be excellent. the following measures are effective for satisfying these requirements. use a low attenuation, low skew differential cable with excellent impedance accuracy. a cable with a two-core coaxial (shielded twisted pair) structure is recommended. use low reflectance connectors. take care for the connector pin assignment. select pins so that there is no interference with other signals and so that the positive and negative signal wiring are the same length on the board. use a cable with a double shielded structure.
13 CXB1455R recommended transmission path : differential impedance template 150 zo ( ? ) 110 106 94 90 75 microstrip line microstrip line foot print foot print connector < 500ps < 500ps connector cable recommended transmission path : attennation characteristics loss < 15db measured curve fitting curve 2db 1ghz frequency
14 CXB1455R 1.95gbps sdatap output waveform 100mv/div 100ps/div atten 10db rl 0dbm center 65.00mhz rbw 100khz span 10.00mhz swp 50ms vbw 100khz 10db/ sfclk jitter tolerance: example of power spectrum which can be used for transmission d ref lvl 0dbm
15 CXB1455R package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 48pin lqfp (plastic) 9.0 0.2 ? 7.0 0.1 1 12 13 24 25 36 37 48 (0.22) 0.18 ?0.03 + 0.08 0.2g lqfp-48p-l01 p-lqfp48-7x7-0.5 (8.0) 0.5 0.2 0.127 ?0.02 + 0.05 a 1.5 ?0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.1 0.1 0.5 0.2 0? to 10? detail a 0.13 m 0.5 s s b detail b : palladium 0.127 0.04 0.18 0.03 sony corporation

▲Up To Search▲

Price & Availability of CXB1455R

	To Download CXB1455R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .