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1 jun. 2001 edition 3.0 p r e l i m i n a r y . assp fractional-n pll frequency synthesizer MB15F83UL n description the fujitsu MB15F83UL is fractional-n phase locked loop (pll) frequency synthesizer with fast lock up functional. the fractional-n pll operating up to 2000mhz and the integer pll operating up to 600mhz are integrated on one chip. MB15F83UL is used charge pump which is well-balanced output current with 1.5ma and 6ma selectable by serial data, direct power save control and digital lock detector. in addition, MB15F83UL adopts a new architecture to achieve fast lock. the new package(thin bump chip carrier20) decreases a mount area of MB15F83UL more than 30% comparing with the former b.c.c.16(for dual pll, mb15f03sl). MB15F83UL is ideally suited for wireless mobile communications, such as gsm. n features ? high frequency operation: rf synthesizer : 2000mhz max if synthesizer : 600mhz max ? low power supply voltage: v cc = 2.7 to 3.6 v ? ultra low power supply current : i cc = 5.8 ma typ. (v cc = v p =3.0v, ta=25 c in if, rf locking state) ? direct power saving function : power supply current in power saving mode typ. 0.1 m a(vcc=vp=3.0v, ta=25 c), max. 10 m a(vcc=vp=3.0v) ? fractional function : modulo 13 fixed(implemented in rf-pll) ? dual modulus prescaler : 2000mhz prescaler(16/17fixed) / 600mhz prescaler(8/9 or 16/17) ? serial input programmable reference divider: rf:7bit (3 to 127) / if:14bit (3 to 16383) ? serial input programmable divider consisting of: rf section -binary 4-bit swallow counter: 0 to 15 -binary 10-bit programmable counter: 18 to 1,023 -binary 4-bit fractional counter numerator: 0 to 15 if section - binary 4-bit swallow counter: 0 to 15 -binary 11-bit programmable counter: 3 to 2,047 ? on-chip phase comparator for fast lock and low noise ? operating temperature: ta = ?40 to 85 c ? small package bump chip carrier.0(3.4mm*3.6mm*0.6mm) 20-pad, plastic bcc (lcc-20p-m05) 20-pin, plastic tssop (fpt-20p-m06)
2 MB15F83UL jun. 2001 edition 3.0 n pin assignment top 1 2 3 4 5 6 16 15 14 13 12 11 7 8 10 9 view g n d clock gnd if fin if osc in vcc if data le fin rf vcc rf ps if do if xfin if ps rf do rf ld/fout fpt-20p-m06 lcc-20p-m05 1 2 3 4 5 6 16 15 14 13 12 11 8 10 9 top view gnd gnd if fin if osc in vcc if ps if do if ld/fout clock le fin rf xfin rf gnd rf vcc rf ps rf d o r f xfin rf 17 18 19 20 vp if gnd rf vp rf 7 17 18 19 20 xfin if vp if vp rf data
3 MB15F83UL jun. 2001 edition 3.0 n pin descriptions pin no. pin name i/o descriptions tssop bcc 1 19 osc in i the programmable reference divider input. tcxo should be connected with a ac coupling capacitor. 2 20 gnd - ground for osc input buffer and the shift registor circuit. 3 1 fin if i prescaler input pin for the if-pll. connection to an external vco should be ac coupling. 4 2 xfin if i prescaler complimentary input for the if-pll section. this pin should be grounded via a capacitor. 5 3 gnd if - ground for the if-pll section. 6 4 vcc if - power supply voltage input pin for the if-pll section(except for the charge pump circuit), the shift register and the oscillator input buffer. when power is off, latched data of if-pll is lost. 7 5 ps if i power saving mode control for the if-pll section. this pin must be set at ?l? power-on. (open is prohibited.) ps if = ?h? ; normal mode, ps if = ?l? ; power saving mode 8 6 vp if - power supply voltage input pin for the if-pll charge pump. 9 7 do if o charge pump output for the if-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 10 8 ld/fout o lock detect signal output(ld)/ phase comparator monitoring output (fout). the output signal is selected by a lds bit in a serial data. lds bit = "h" ; outputs fout signal, lds bit = "l" ; outputs ld sihnal 11 9 do rf o charge pump output for the rf-pll section. phase characteristics of the phase detector can be reversed by fc-bit. 12 10 vp rf - power supply voltage input pin for the rf-pll charge pump. 13 11 ps rf i power saving mode control for the rf-pll section. this pin must be set at ?l? power-on. (open is prohibited.) ps rf = ?h? ; normal mode, ps rf = ?l? ; power saving mode 14 12 vcc rf - power supply voltage input pin for the rf-pll section(except for the charge pump circuit). 15 13 gnd rf - ground for the rf-pll section. 16 14 xfin rf i prescaler complimentary input for the rf-pll section. this pin should be grounded via a capacitor. 17 15 fin rf i prescaler input pin for the rf-pll. connction to an external vco should be ac coupling. 18 16 le i load enable signal input (with the schmitt trigger circuit.) on a rising edge of load enable, data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. 19 17 data i serial data input (with the schmitt trigger circuit.) a data is transferred to the corresponding latch (if-ref counter, if-prog. counter, rf-ref. counter, rf-prog. counter) according to the control bit in a serial data. 20 18 clock i clock input for the 23-bit shift register (with the schmitt trigger circuit.) one bit data is shifted into the shift register on a rising edge of the clock.
4 MB15F83UL jun. 2001 edition 3.0 n block diagram 1 3 18 schmitt circuit 19 schmitt circuit 20 schmitt circuit c n 1 23-bit shift register latch selector 6 prescaler (if?pll) 8/9,16/17 power saving if-pll c n 2 binary 4-bit swallow counter (if?pll) binary 11-bit programmable counter (if?pll) phase comp. (if?pll) charge pump (if?pll) 7 4-bit latch 11-bit latch 6-bit latch 14-bit latch binary 14?bit pro- grammable ref. counter(if?pll) 17 prescaler (rf?pll) 16/17 4-bit latch binary 4-bit swallow counter (rf?pll) binary 10-bit programmable counter (rf?pll) 4-bit latch 10-bit latch 7-bit latch binary 7-bit pro- grammable ref. counter (rf?pll) lock det. (if?pll) lock det. (rf?pll) selector ld if ld rf fr if fr rf fp if fp rf do rf 9 16 5 fp if charge pump (rf?pll) 14 2 ps if (5) fin if osc in (19) (15) fin rf xfin rf le (16) (17) (18) data clock vcc rf (12) gnd (20) ld/fout (9) (8) do if (7) vcc if (4) gnd if (3) ld if o -- tssop 20 ( ) -- bcc 20 (1) 4 (2) (14) gnd rf (13) 15 vp rf 11 10 8 vp if (6) 12 (10) xfin if t1 t2 sw c fc c cs c ld s 5-bit latch sc 1 sc 2 fc f cs f f 1 f 2 f 3 f 4 fractional counter 13 c n 3 sc1 sc2 or power saving rf-pll ps rf (11) or sc (rf?pll) md2 md1 phase comp. (rf?pll) fr rf fp rf fp rf fr rf selector 13
5 MB15F83UL jun. 2001 edition 3.0 n absolute maximum ratings note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n recommended operating conditions handling precautions (1) vcc rf, vp rf, vcc if and vp if must supply equal voltage. even if either rf-pll or if-pll is not used, power must be supplied to both vcc rf, vp rf, vcc if and vp if to keep them equal. it is recommended that the non-use pll is controlled by power saving function. (2) to protect against damage by electrostatic discharge, note the following handling precautions: -store and transport devices in conductive containers. -use properly grounded workstations, tools, and equipment. -turn off power before inserting or removing this device into or from a socket. -protect leads with conductive sheet, when transporting a board mounted device. parameter symbol rating unit remark min. max. power supply voltage v cc ?0.5 +4.0 v v p v cc +4.0 v input voltage v i ?0.5 v cc +0.5 v output voltage v o gnd v cc v ld/fout v do gnd v p v do storage temperature t stg ?55 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v v ccrf = v ccif v p v cc 3.0 3.6 v input voltage v i gnd ? v cc v operating temperature t a ?40 ? +85 c
6 MB15F83UL jun. 2001 edition 3.0 n electrical characteristics (v cc = 2.7 to 3.6 v, ta = ?40 to +85 c) (continued) parameter symbol condition value unit min. typ. max. power supply current* 1 i ccif *1 fin if =480mhz vcc if =vp if =3.0v,swc=0 1.0 1.6 2.3 ma i ccrf *1 fin rf =2000mhz vcc rf =vp rf =3.0v 2.8 4.2 5.8 ma power saving current i psif ps= ?l? ? 0.1 *2 10 m a i psrf ps= ?l? ? 0.1 *2 10 m a operating frequency fin if *3 fin if if pll 100 ? 600 mhz fin rf *3 fin rf rf pll 400 ? 2000 mhz osc in fosc ? 3 ? 40 mhz input sensitivity fin if pfin if if pll, 50 w system -15 ? +2 dbm fin rf pfin rf rf pll, 50 w system -15 ? +2 dbm osc in v osc ? 0.5 ? v cc vp-p "h" level input voltage data, clock, le v ih schmitt trigger input vcc 0.7+0.4 ? ? v "l" level input voltage v il schmitt trigger input ? ? vcc 0.3-0.4 "h" level input voltage ps v ih ? vcc 0.7 ? ? v "l" level input voltage v il ? ? ? vcc 0.3 "h" level input current data, clock, le, ps i ih *4 ? ?1.0 ? +1.0 m a "l" level input current i il *4 ? ?1.0 ? +1.0 "h" level input current osc in i ih ? 0 ? +100 m a "l" level input current i il *4 ? ?100 ? 0 "h" level output voltage ld/fout v oh v cc =v p =3.0v, i oh = ? 1ma vcc ? 0.4 ? ? v "l" level output voltage v ol v cc =v p =3.0v, i ol =1ma ? ? 0.4 "h" level output voltage do if do rf v doh v cc =v p =3.0v, i doh =-0.5ma vp ? 0.4 ? ? v "l" level output voltage v dol v cc =v p =3.0v, i dol =0.5ma ? ? 0.4 high impedance cutoff current do if do rf i off v cc =3.0v, v off =0.5v to v p ? 0.5v ? ? 2.5 na "h"level output current ld/fout i oh *4 v cc = vp = 3.0v ? ? -1.0 ma "l" level output current i dol *4 v cc = vp = 3.0v 1.0 ? ?
7 MB15F83UL jun. 2001 edition 3.0 (continued) ta =(v cc = 2.7 to 3.6 v, ta = ?40 to +85 c) *1: conditions; fosc=13mhz, ta = 25 c in locking state. *2: vcc if =vp if =vcc rf =vp rf =3.0v, fosc=13mhz, ta = 25 c, in power saving mode. *3: ac coupling. 1000pf capacitor is connected. *4: the symbol "-"(minus) means direction of current flow. *5: vcc=vp=3.0v, ta=25 c ( ||i 3 | - |i 4 || ) / [( |i 3 | + |i 4 | )/2] x 100(%) *6: vcc=vp=3.0v, ta=25 c [( ||i 2 | - |i 1 || ) /2 ] / [( |i 1 | + |i 2 | )/2] x 100(%) (applied to each i dol , i doh ) *7: vcc=vp=3.0v, [(||i do(85c) | - |i do(-40c) ||) /2] / [(|i do(85c) | + |i do(-40c) |) /2] x 100(%) (applied to each i dol , i doh ) parameter symbol condition value unit min. typ. max. "h"level output current do if do rf i doh *4 v cc =v p =3.0 v v doh =v p /2 ta= 25 c cs bit ="h" ?8.2 ?6.0 ?4.1 ma cs bit ="l" ?2.2 ?1.5 ?0.8 "l" level output current i dol v cc =v p =3.0 v v dol =v p /2 ta= 25 c cs bit ="h" 4.1 6.0 8.2 cs bit ="l" 0.8 1.5 2.2 charge pump current rate i dol / i doh i domt *5 v do =v p /2 ? 3 ? % vs v do i dovd *6 0.5v < v do < v p -0.5v ? 10 ? % vs ta i dota *7 -40 c < ta < 85 c, v do =v p /2 ? 5 ? % output voltage(v) v p /2 v p - 0.5 v p 0.5 i d o l i d o h i 2 i 4 i 1 i 1 i 3 i 2
8 MB15F83UL jun. 2001 edition 3.0 n functional descriptions serial data input serial data is entered using three pins, data pin, clock pin, and le pin. programmable dividers of if/rf-pll sections, programmable reference dividers of if/rf-pll sections are controlled individually. serial data of binary data is entered through data pin. on a rising edge of clock, one bit of serial data is transferred into the shift register. on a rising edge of load enable signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting. table1. control bit (cn3=1 is prohibited) table2. serial data format rc1 to rc14 :divide ratio setting bits for the reference counter of the if(3 to 16383) ac1 to ac4 :divide ratio setting bits for the swallow counter of the if (0 to 31, a 9 MB15F83UL jun. 2001 edition 3.0 1)rf synthesizer data setting(fractional-n) the divide ratio can be calculated using the following equation: fvco rf =n total x fosc / r n total =p x n + a + f/q (a 10 MB15F83UL jun. 2001 edition 3.0 table.5 binary 10-bit programmable counter data setting(n f 1 to n f 10) note: divide ratio less than 18 is prohibited. table.6 binary 4-bit swallow counter data setting(a f 1 to a f 4 ) note: a 11 MB15F83UL jun. 2001 edition 3.0 2)if synthesizer data setting(integer) the divide ratio can be calculated using the following equation: fvco if =[ (p x n) + a ] fosc / r (a 12 MB15F83UL jun. 2001 edition 3.0 table. 13 charge pump current select data setting(cs c ) 3)common setting table. 14 ld/fout output select data setting table. 15 phase comparator phase switching data setting note: z = high?impedance depending upon the vco and lpf polarity, fc bit should be set. when designing a synthesizer, the fc bit setting depends onthe vco and lpf characteristics when the lpf and vco characteristics are similar to (1), set fc bit" high". when the vco characteristics are similar to (2), set fc bit "low" cs c do current 1 +/-6.0ma 0 +/-1.5ma ld/fout lds t1 t2 ld output 0 - - fout output fr if 1 0 0 fr rf 1 1 0 fp if 1 0 1 fp rf 1 1 1 fc f/c = h fc f/c = l do if,rf fr > fp h l fr = fp z z fr < fp l h vco polarity 1 2 vco input voltage vco output frequency (1) (2)
13 MB15F83UL jun. 2001 edition 3.0 4. power saving mode (intermittent mode control) table 16. ps pin setting the intermittent mode control circuit reduces the pll power consumption. by setting the ps pin low, the device enters into the power saving mode, reducing the current consumption. see the electrical characteristics chart for the specific value. the phase detector output, do, becomes high impedance. for the single pll, the lock detector, ld, remains high, indicating a locked condition. for the dual pll, the lock detector, ld, is as shown in the ld output logic table. setting the ps pin high, releases the power saving mode, and the device works normally. the intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation. when the pll is returned to normal operation, the phase comparator output signal is unpredictable. this is because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can cause a major change in the comparator output, resulting in a vco frequency jump and an increase in lockup time. to prevent a major vco frequency jump, the intermittent mode control circuit limits the magnitude of the error signal from the phase detector when it returns to normal operation. note: note: when power (v cc ) is first applied, the device must be in standby mode, ps=low, for at least 1 m s. note: ps pin must be set at ?l? for power on. ps pin status h normal mode l power saving mode (1) ps = l (power saving mode) at power on (2) set serial data 1 m s later after power supply remains stab le(vcc > 2.2v). (3) relase power saving mode (ps: l ? h) 100ns later after setting serial data. on vcc clock data le ps (1) (2) (3) tv > 1 m s tps > 100ns off
14 MB15F83UL jun. 2001 edition 3.0 n serial data input timing msb lsb data clock le t1 t4 t5 t3 on the rising edge of the clock, one bit of data is transferred into the shift register. parameter unit max. typ. min. t1 t2 t3 t4 ns ns ns ns 20 ? ? ? ? ? ? ? ? 20 30 30 100 ? ? ? ? ? ? 20 100 t5 t6 t7 ns ns ns t6 t7 parameter unit max. typ. min. t2 note: le should be "l" when the data is transferred into the shift register. control bit invalid data 1st data 2nd data
15 MB15F83UL jun. 2001 edition 3.0 n phase detector output waveform note: phase error detection range = - 2 p to +2 p pulses on do if/rf signals are output to prevent dead zone. ld output becomes low when phase error is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. t wu and t wl depend on oscin input frequency as follows. t wu > 2/fosc: i.e. t wu > 153.8ns when foscin = 13.0 mhz t wl < 4/fosc: i.e. t wl < 307.7ns when foscin = 13.0 mhz t wu fr if/rf fp if/rf t wl ld (fc bit = high) do if/rf z l (fc bit = low) z h do if/rf if?pll section rf?pll section ld output locking state / power saving state locking state / power saving state locking state / power saving state h l l l unlocking state unlocking state unlocking state locking state / power saving state unlocking state ld output logic table
16 MB15F83UL jun. 2001 edition 3.0 n test circuit (for measuring input sensitivity fin/oscin) p.g fin rf 17 16 1000pf vcc rf gnd rf xfin rf do rf vp rf ps rf MB15F83UL 50 w 1 2 5 4 vcc if 0.1 m f 20 19 18 15 50 w 1000pf 1000pf 0.1 m f vp rf fout oscilloscope 7 3 14 6 p.g 50 w 1000pf 10 12 controller (divide ratio setting) p.g note : tssop-20 13 11 0.1 m f vcc rf 9 8 vp if 0.1 m f 1000pf ld/fout do if vp if ps if vcc if gnd if xfin if fin if gnd oscin le data clock
17 MB15F83UL jun. 2001 edition 3.0 n application example vco lpf tcxo 3.0 v output from controller le xfin rf 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 gnd rf data fin rf vcc rf ps rf 3.0 v 0.1 m f 1000 pf vco lpf output lock det. fin if gnd if vcc if gnd xfin if ps if vp if do if clock, data, le: schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation when open-circuited in the input). MB15F83UL note :tssop-20 20 11 9 10 osc in ld/fout do rf clock 1000 pf 1000 pf 0.1 m f 3.0 v 3.0 v 1000 pf 1000 pf 0.1 m f vp rf 0.1 m f
18 MB15F83UL jun. 2001 edition 3.0 n package dimension 20 pin, plastic ssop (fpt-20p-m06) * : these dimensions do not include resin protrusion. (continued)
19 MB15F83UL jun. 2001 edition 3.0 20 pad, plastic bcc (lcc-20p-m05) (continued)

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