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HM658512A series 4 m psram (512-kword 8-bit) 2 k refresh ade-203-218c(z) rev. 3.0 nov. 1997 description the hitachi HM658512A is a cmos pseudo static ram organized 512-kword 8-bit. it realizes higher density, higher performance and low power consumption by employing 0.8 ? hi-cmos process technology. it offers low power data retention by self refresh mode. it also offers easy non multiplexed address interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery back-up systems. the device is packaged in a small 525-mil sop (460-mil body sop) or a 8 20 mm tsop with thickness of 1.2 mm, or a 600-mil plastic dip. high density custom cards made of tape carrier packages are also available. features single 5 v (?0%) high speed ? access time ce access time: 70/80/100 ns (max) ? cycle time random read/write cycle time: 115/130/160 ns (min) low power ? active: 250 mw (typ) ? standby: 200 ? (typ) directly ttl compatible all inputs and outputs simple address configuration non multiplexed address refresh cycle ? 2048 refresh cycles: 32 ms
HM658512A series 2 easy refresh functions address refresh automatic refresh self refresh ordering information type no. access time package HM658512Alp-7 HM658512Alp-8 HM658512Alp-10 70 ns 80 ns 100 ns 600-mil 32-pin plastic dip (dp-32) HM658512Alp-7v HM658512Alp-8v HM658512Alp-10v 70 ns 80 ns 100 ns HM658512Alfp-7 HM658512Alfp-8 HM658512Alfp-10 70 ns 80 ns 100 ns 525-mil 32-pin plastic sop (fp-32d) HM658512Alfp-7v HM658512Alfp-8v HM658512Alfp-10v 70 ns 80 ns 100 ns HM658512Altt-7 HM658512Altt-8 HM658512Altt-10 70 ns 80 ns 100 ns 400-mil 32-pin plastic tsop (ttp-32d) HM658512Altt-7v HM658512Altt-8v HM658512Altt-10v 70 ns 80 ns 100 ns HM658512Alrr-7 HM658512Alrr-8 HM658512Alrr-10 70 ns 80 ns 100 ns 400-mil 32-pin plastic tsop (ttp-32dr) HM658512Alrr-7v HM658512Alrr-8v HM658512Alrr-10v 70 ns 80 ns 100 ns
HM658512A series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we a13 a8 a9 a11 oe/rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 cc HM658512Alp/alfp series (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss v a15 a17 we a13 a8 a9 a11 oe/rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v cc HM658512Altt series (top view)
HM658512A series 4 pin arrangement (cont.) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss v a15 a17 we a13 a8 a9 a11 oe/rfsh a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v cc HM658512Alrr series (top view) pin description pin name function a0 to a18 address i/o0 to i/o7 input/output ce chip enable oe / rfsh output enable/refresh we write enable v cc power supply v ss ground
HM658512A series 5 block diagram refresh control timing pulse gen. read write control address latch control column decoder column i/o memory matrix row decoder address latch control input data control ce we i/o 7 i/o 0 a0 a10 a11 a18 oe/rfsh (2048 256) 8
HM658512A series 6 pin functions ce : chip enable (input) ce is a basic clock. ram is active when ce is low, and is on standby when ce is high. a0 to a18: address inputs (input) a0 to a10 are row addresses and a11 to a18 are column addresses. the entire addresses a0 to a18 are fetched into ram by the falling edge of ce . oe / rfsh : output enable/refresh (input) this pin has two functions. basically it works as oe when ce is low, and as rfsh when ce is high (in standby mode). after a read or write cycle finishes, refresh does not start if ce goes high while oe / rfsh is held low. in order to start a refresh in standby mode, oe / rfsh must go high to reset the refresh circuits of the ram. after the refresh circuits are reset, the refresh starts when oe / rfsh goes low. i/o0 to i/o7: input/output (inputs and outputs) these pins are data i/o pins. we : write enable (input) ram is in write mode when we is low, and is in read mode when we is high. i/o data is fetched into ram by the rising edge of we or ce (earlier timing) and the data is written into memory cells. refresh there are three refresh modes : address refresh, automatic refresh and self refresh. (1) address refresh: data is refreshed by accessing all 2048 row addresses every 32 ms. a read is one method of accessing those addresses. each row address (2048 addresses of a0 to a10)must be read at least once every 32 ms. in address refresh mode, oe / rfsh can remain high. in this case, the i/o pins remain at high impedance, but the refresh is done within ram. (2) automatic refresh: instead of address refresh, automatic refresh can be used. ram goes to automatic refresh mode if oe / rfsh falls while ce is high and it remains low for at least t fap . one automatic refresh cycle is executed by one low pulse of oe / rfsh . it is not necessary to input the refresh address from outside since it is generated internally by an on-chip address counter. 2048 automatic refresh cycles must be done every 32 ms. (3) self refresh: self refresh mode is suitable for data retention by battery. in standby mode, a self refresh starts automatically when oe / rfsh stays low for more than 8 ?. refresh addresses are automatically specified by the on-chip address counter, and the refresh period is determined by the on-chip timer. automatic refresh and self refresh are distinguished from each other by the width of the oe / rfsh low pulse in standby mode. if the oe / rfsh low pulse is wider than 8 ?, ram becomes into self refresh mode; if the oe / rfsh low pulse is less than 8 ?, it is recognized as an automatic refresh instruction.
HM658512A series 7 at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and oe / rfsh must be kept high. if auto refresh follows self refresh, low transition of oe / rfsh at the beginning of automatic refresh must not occur during t rfs period. notes on using the HM658512A since pseudo static ram consists of dynamic circuits like dram, its clock pins are more noise-sensitive than conventional sram?. (1) if a short ce pulse of a width less than t ce min is applied to ram, an incomplete read occurs and stored data may be destroyed. make sure that ce low pulses of less than t ce min are inhibited. note that a 10 ns ce low pulse may sometimes occur owing to the gate delay on the board if the ce signal is generated by the decoding of higher address signals on the board. avoid these short pulses. (2) oe / rfsh works as refresh control in standby mode. a short oe / rfsh low pulse may cause an incomplete refresh that will destroy data. make sure that oe / rfsh low pulse of less than t fap min are also inhibited. (3) t ohc and t ocd are the timing specs which distinguish the oe function of oe / rfsh from the rfsh function. the t ohc and t ocd specs must be strictly maintained. (4) start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100 ? after the power voltage reaches 4.5 v-5.5 v after power-on. function table ce oe / rfsh we i/o pin mode l l h dout read l x l high-z write l h h high-z h l x high-z refresh h h x high-z standby note: x means h or l.
HM658512A series 8 absolute maximum ratings parameter symbol value unit note terminal voltage with respect to v ss v t ?.0 to +7.0 v 1 power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg ?5 to +125 c storage temperature under bias tbias ?0 to +85 c note: 1. with respect to v ss recommended dc operating conditions (ta = 0 to +70?) parameter symbol min typ max unit notes supply voltage v cc 4.5 5.0 5.5 v v ss 000 v input voltage v ih 2.4 6.0 v v il ?.0 0.8 v 1 note: 1. v il min = ?.0 v for pulse width 30 ns
HM658512A series 9 dc characteristics (ta = 0 to +70?, v cc = 5 v ?10 %, v ss = 0 v) parameter symbol min typ max unit test conditions notes operating power supply current i cc1 75 ma i i/o = 0 ma t cyc = min standby power supply current i sb1 12ma ce = v ih , vin 3 0 v oe / rfsh = v ih i sb2 20 200 m a ce 3 v cc ?0.2 v, vin 3 0 v, oe / rfsh 3 v cc ?0.2 v 1 100 m a ce 3 v cc ?0.2 v, vin 3 0 v, oe / rfsh 3 v cc ?0.2 v 2 operating power supply current in self refresh mode i cc2 12ma ce = v ih , vin 3 0 v, oe / rfsh = v il i cc3 70 200 m a ce 3 v cc ?0.2 v, vin 3 0 v, oe / rfsh 0.2 v 1 40 100 m a ce 3 v cc ?0.2 v, vin 3 0 v, oe / rfsh 0.2 v 2 input leakage current i li ?0 10 m av cc = 5.5 v, vin = v ss to v cc output leakage current i lo ?0 10 m a oe / rfsh = v ih v i/o = v ss to v cc output voltage v ol 0.4 v i ol = 2.1 ma v oh 2.4 v i oh = ? ma notes: 1. only for l-version. 2. only for v-version. capacitance (ta = 25?, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance c in 8 pf v in = 0 v input /output capacitance c i/o ?0 pfv i/o = 0 v note : this parameter is sampled and not 100% tested.
HM658512A series 10 ac characteristics (ta = 0 to +70?, v cc = 5 v ?10%, unless otherwise noted.) test conditions input pulse levels: 0.4 v, 2.4 v input rise and fall time: 5 ns timing measurement level: 0.8 v, 2.2 v reference levels: v oh = 2.0 v, v ol = 0.8 v output load: 1 ttl gate and c l (100 pf) (including scope and jig) HM658512A -7 -8 -10 parameter symbol min max min max min max unit notes random read or write cycle time t rc 115 130 160 ns chip enable access time t cea 70 80 100 ns read-modify- write cycle time t rwc 160 180 220 ns output enable access time t oea ?5 30 ?0 ns chip disable to output in high-z t chz 0 25 0 25 0 25 ns 1, 2 chip enable to output in low-z t clz 20 20 20 ns 2 output disable to output in high-z t ohz 25 25 25 ns 1, 2 output enable to output in low-z t olz 0 0 0 ns2 chip enable pulse width t ce 70 n 10 m 80 n 10 m 100 n 10 m s chip enable precharge time t p 35 40 50 ns address setup time t as 0 0 0 ns address hold time t ah 20 20 25 ns read command setup time t rcs 0 0 0 ns read command hold time t rch 0 0 0 ns write command pulse width t wp 25 25 30 ns chip enable to end of write t cw 70 80 100 ns chip enable to output enable delay time t ocd 0 0 0 ns output enable hold time t ohc 0 0 0 ns
HM658512A series 11 ac characteristics (ta = 0 to +70?, v cc = 5 v ?10%, unless otherwise noted.) (cont.) HM658512A -7 -8 -10 parameter symbol min max min max min max unit notes data in to end of write t dw 20 20 25 ns data in hold time for write t dh 0 0 0 ns output active from end of write t ow 5 5 5 ns2 write to output in high-z t whz 20 20 25 ns 1, 2 transition time (rise and fall) t t 350350350ns6 refresh command delay time t rfd 35 40 50 ns refresh precharge time t fp 35 40 40 ns refresh command pulse width for automatic refresh t fap 70 n 8 m 80 n 8 m 80 n 8 m s automatic refresh cycle time t fc 115 130 160 ns refresh command pulse width for self refresh t fas 8 8 8 m s refresh reset time from self refresh t rfs 600 600 600 ns 9 refresh period t ref 32 32 32 ms 2048 cycle notes: 1. t chz , t ohz , t whz are defined as the time at which the output achieves the open circuit condition. 2. t chz , t clz , t ohz , t olz , t whz and t ow are sampled under the condition of t t = 5 ns and not 100% tested. 3. a write occurs during the overlap of low ce and low we . write end is defined at the earlier of we going high or ce going high. 4. if the ce low transition occurs simultaneously with or from the we low transition, the output buffers remain in high impedance state. 5. in write cycle, oe or we must disable output buffers prior to applying data to the device and at the end of write cycle data inputs must be floated prior to oe or we turning on output buffers. during this period, i/o pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 6. transition time t t is measured between v ih (min) and v il (max). v ih (min) and v il (max) are reference levels for measuring timing of input signals. 7. after power-up, pause for more than 100 m s and execute at least 8 initialization cycles. 8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed within 15 m s after self refresh, in order to meet the refresh specification of 32 ms and 2048 cycles. 9. at the end of self refresh, refresh reset time (t rfs ) is required to reset the internal self refresh operation of the ram. during t rfs , ce and oe / rfsh must be kept high. if automatic refresh follows self refresh, low transition of oe / rfsh at the beginning of automatic refresh must not occur during t rfs period.
HM658512A series 12 timing waveform read cycle t ce address a0 to a18 we oe/rfsh t t tt valid t t t t dout t valid data out t t t rc ce as ah p rch chz ohz oea cea ohc rcs olz
HM658512A series 13 write cycle (1) ( oe high) ce address a0 to a18 we oe/rfsh din t t t tt valid dout valid data in t t tt t t t t t t rc ce as ah cw clz ohz whz wp ocd p dw dh olz ow
HM658512A series 14 write cycle (2) ( oe low) ce address a0 to a18 we oe/rfsh din t t t tt valid dout valid data in t t t t t t t t rc ce p dh cw wp dh dw whz clz ohc ah as
HM658512A series 15 read-modify-write cycle ce address a0 to a18 we oe/rfsh din t t t tt valid dout valid data in t t t t t t t t t valid data out t t t t t t rwc ce cw p rch ocd wp dh dw chz ow as ah rcs cea ohc oea olz clz ohz automatic refresh cycle ce oe/rfsh tt t tt tt rfd fc fp fap fp fap fc
HM658512A series 16 self refresh cycle ce oe/rfsh t t t t rfd fp fas rfs low v cc data retention characteristics (ta = 0 to +70 c) this characteristics is guaranteed only for v-version. parameter symbol min typ max unit test conditions v cc for data retention v dr 3.0 5.5 v self refresh current i ccdr 50 m av cc = 3.0 v, ce 3 v cc ?0.2 v oe / rfsh 0.2 vin 3 0 v 100 m av cc = 5.5 v, ce 3 v cc ?0.2 v oe / rfsh 0.2 vin 3 0 v refresh setup time t fs 0 ns operation recovery time t fr 5 ms
HM658512A series 17 low v cc data retention timing waveform data retention mode vdr fas fs fr rfs t fp 4.5v 2.4v 0.8v 2.4v 0.8v v ce oe/rfsh ce vcc-0.2v oe/rfsh 0.2v cc rfd t tt t t notes: 1. rise time and fall time of power supply voltage must be smaller than 0.05 v/ms. 2. keep ce 3 v cc ?0.2 v during data retention mode. 3. regarding t rfd , t fp , t fas and t rfs , refer to ac characteristics. 4. input voltage should be lower than v cc +1.5 v in data retention mode.
HM658512A series 18 package dimensions HM658512Alp series (dp-32) 0.51 min 2.54 min 5.08 max 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 41.90 42.50 max 13.4 13.7 max 15.24 32 17 1 16 2.30 max 1.20 hitachi code jedec eiaj weight (reference value) dp-32 conforms 5.1 g unit: mm
HM658512A series 19 HM658512Alfp series (fp-32d) 0.15 m 0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max 0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 hitachi code jedec eiaj weight (reference value) fp-32d conforms 1.3 g 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04 unit: mm dimension including the plating thickness base material dimension
HM658512A series 20 HM658512Altt series (ttp-32d) 1.27 0.21 m 0.42 0.08 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.13 0.05 0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 hitachi code jedec eiaj weight (reference value) ttp-32d conforms 0.51 g 0.40 0.06 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
HM658512A series 21 HM658512Alrr series (ttp-32dr) 1.27 0.21 m 0.42 0.08 0.10 10.16 20.95 21.35 max 16 17 1 32 1.20 max 0 ?5 0.13 0.05 0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 hitachi code jedec eiaj weight (reference value) ttp-32dr conforms 0.51 g 0.40 0.06 0.125 0.04 unit: mm dimension including the plating thickness base material dimension
HM658512A series 22 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachi? permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user? unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachi? semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachi? products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachi? sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachi? products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 cop y ri g ht ?hitachi, ltd., 1998. all ri g hts reserved. printed in japan.

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