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AN902/0197 1/19 application note quality and reliability information by the micro divisions introduction we think that maintaining an optimal quality level is very important but we also be- lieve that our customers contribute to the quality chain when they handle or program our mcu devices this application note describes all the stages an sgs-thomsons product need to get over to be qualified, passing the various reliability tests. 1 quality assurance 1.1 the quality chain the main steps of a product life cycle are summarized on the graph below. quality is involved at each step but it is important to notice that the customer also has a major role in quality assurance figure 1. main steps of the quality chain product and technology definition development and pre-production design first silicon qualification production customer application development & coding fabrication spc monitoring assembly qa monitoring customer soldering handling packaging product assembly handling shipping spc monitoring qualification field vr02105a 1
quality assurance 2/19 1.2 quality system at sgs-thomson a maturity number is attributed to each step of the development of a mcu device (de- sign, industrialization or volume production). maturity is an attribute assigned to each product that shows the status of knowledge reached on it and allows to follow its life cycle internally. there are four main steps in a new product development: marketing evaluation , de- sign , engineering and production . the table on page 4 gives a list of the require- ments for each development level. the following procedure is for internal qualification and is applied to new generic semi-conductors products manufactured with a quali- fied wafer fabrication and assembly process. figure 2. product life cycle marketing design engineering end of life 30 production evaluation new product request product design approval certificate qualification certificate 50 60 20 10 maturity level (qualification) new product mature product vr02105b
3/19 quality assurance the reasons to develop a new mcu are market trends and specified requirements from our customers. they will be translated into a specification after additional tech- nical and economical evaluation. to eventually start a new product development with this specification, sgs-thomson constitutes a development council to decide about the realization. the result will be fixed in the target specification, which contains the device functions, technology, and parameters as well as the targets for quality and reliability . design by cad (computer aided design) plays an important role in generating de- sign quality for a new product. since the introduction of cad for the automation of de- sign and its verification, the influence of computer based methods has reduced the amount of time required for a product design. in order to increase the level of perform- ance, design methods are usually standardized. marketing evaluation new product request design design approval certificate engineering product qualification certificate
quality assurance 4/19 once a design successfully passes its review, a trial run takes place in which the product's electrical and mechanical characteristics, quality and reliability are evalu- ated. additional runs are performed in which process conditions are varied deliber- ately, causing characteristic factors to change in mass production. these samples are evaluated to determine the best combination of process conditions but also to check the product behaviour inside the full specification range. reliability tests are then conducted to check the new product's electrical and mechanical stress resist- ance. if no problems are found at this stage, the product is qualified and approved for mass production. the standards for production and control steps are continuously re-examined for pos- sible improvement, even after mass production has started. quality controls and reli- ability monitoring are also performed. maturity level project details samples and data ordering parts 10 new product is designed to get full specifications samples free samples are deliv- ered to selected custom- ers no orders can be entered 20 product is characterised reliability is measured samples to customers (not for qualification) order confirmation is not allowed. in device list with not to be sold 30 product is manufactured and monitored to meet corporate standard process parameters sta- bilised and under compa- ny limits the product is available through regular commer- cial system 50 notification of the deci- sion to stop the product to the customer order confirmation for limited period and control- led quantity 60 product termination is completed production of remaining orders order confirmation forbidden production
5/19 quality assurance 1.3 statistical process control (spc) one of the most efficient tools implemented throughout the production of integrated circuits to control product quality and process stability is spc . the goal of spc is to bring each critical parameter to 6 sigma capability. in a typical wafer processing line, more than 200 variables may be controlled for spc. data is gathered and ana- lysed by on-line computers and provides on-line control charts. the critical process steps are defined by fmea (failure mode and effects analysis). fmea is a disciplined methodology to anticipate and evaluate potential failure modes and to define preventive actions that can be incorporated during development of a product or process. thus costly field failures and redesigns can be easily avoided. a selection of the most important spc steps is regularly available and can help cus- tomers to avoid the costly qualification of new products when the products come from a qualified manufacturing process that is demonstrated to be under control. 1.4 failure analysis failure analysis request (far) is a request made by a customer for the analysis of components delivered by the company that are claimed to have failed during cus- tomer usage. in order to allow sgs-thomson to quickly analyse the possible failure cause, the following elements must be included for each failure analysis request: C the detailed description of the symptoms for each device . C the conditions and the step of occurrence: incoming inspection programming stage manufacturing stage field reliability trials engineering trials C the failure rate . C a sample of mcu devices affected by the problem. for otp devices, a good part must also be shipped with the bad ones to allow comparison (code,...). parts are then analysed and an analysis report is issued. the failure analysis cycle time from far to the final date of report issued by quality organization in charge of far processing is detailed on the following graph.
quality assurance 6/19 figure 3. far information flow vr02105c customer st regional qa st qa organisation sales or sales office mcu far information flow failure analysis request final analysis report % of far processed 7 14 days 50 % 95 % 100 % 21 division
7/19 quality assurance figure 4. far processing flow vr02105d failure analysis request has all requested start a failure analysis electrical testing check memory content failure confirmed data been provided ? (device specifications yes no yes no request missing data from the far requestor check parts on automated test equipment (ate) assign a far number use of starter kit issue of a "fast" failure analysis report send the part back to the requestor (if applicable) information sent to customer if requested typical 1 week at all temperatures) report report continue analysis root cause identification electrical overstress test coverage problem early failure mixing ... x-ray inspection decapsulation die surface inspection (optical microscope) bonding inspection emission microscopy liquid crystal analysis layers removal sem corrective actions st / customer
quality assurance 8/19 1.5 traceability at the end of the assembly stage, each component is marked with a traceability code. traceability is a method enabling to reconstruct the individual history of any compo- nent manufactured in company plants. traceability records are maintained to trace back the component's history. details on technology, technical and electrical data, quality performance, key dates and sites where operations are performed are there- fore recorded using traceability codes. figure 5. traceability code vr02105e wafer fab site assembly site test site lot sequential number first digit may be alphabetical or numerical second digit may be only alphabetic (to avoid any risk of confusion with the date code) date code first 2 digits stand for year last 2 digits stand for the first week of the month when the assembly started country of assembly (origin) vr02105e wa t n n y y w w c
9/19 quality assurance the first nine digits are printed on the inner box label, with a space to emphasis the date code for clarity: watnn yyww . data records provide, as a minimum, 5 years traceability for each product after the last shipment. here are the tables for the first three digits (these lists are just an extract for 8 bits mcu products taken from the full lists. contents are also subject to change without notice): wafer sites codes (first digit) code location country wafer dimension company g rousset france 5 sgs-thomson h carrolton u.s.a. 6 " w ang mo kio singapore 5 4.00 rousset france 6 v agrate italy 6 assembly sites codes (second digit) code location country company 2.00 kirkop malta sgs-thomson 5.00 hong-kong hong-kong asat 9.00 muar malaysia sgs-thomson b manila philippines anam p seoul korea anam n nancy france asat a taipeh taiwan ase test sites codes (third digit) code location country company 2.00 kirkop malta sgs-thomson 9.00 muar malaysia sgs-thomson e rousset france sgs-thomson
quality assurance 10/19 1.6 electrostatic discharge protection and handling precautions electronic components have to be protected from the hazard of static electricity from the manufacturing stage down to where they are utilized. mos devices are typ- ically voltage and electrical field sensitive: the thin oxide layers can be destroyed by an electrical field. this happens mostly because a charged conductor, typically a person, is rapidly discharged through the device. a specific no-compromise strategy is implemented at sgs-thomson for all esd sensitive products. from the wafer level to the shipping of finished goods, each workstation and processing step is guaranteed. for final packing sgs-thomson uses anti-static tubes. this solution assures full esd protection of devices. however, the supplier's greatest efforts are in vain if the end user does not provide the same level of pro- tection and care in application. a relative humidity of 50% to 65% will be the best to prevent electrostatic problems (the lower the relative humidity, the higher the electrostatic voltage). nevertheless, the person handling the semiconductors as well as the equipment will be charged to a certain level. the work environment is very important to protect devices against static electricity. anti-static electricity measures during work (1) conductive mat (2) wrist strap (3) conductive floor mat (4) work suit with anti-static measure (5) conductive shoes grounding the human body grounding the human body (1) wrist ring (2) grounding wire: threaded copper wire, vinyl covered, about 1 meter (3) 250 k w to 1 m w resistance is built in
11/19 quality assurance the following are the basic static control protection rules: anti-static measures device handling static control wrist straps, used and connected properly, must be worn. all tools, persons, testing machines, which could come in contact with device leads, must be conductive and grounded. each table top must be protected with a conductive mat, properly grounded. use static control shoe strap. use vacuum pipes. storage box keep parts in the original packing bags up to the very last moment of the pro- duction line. if bigger containers are used for in-plant transport of devices or pc boards, they must be electrically conductive like the carbon loaded types. avoid use of high dielectric materials (like polystyrene) for sub-assembly con- struction, storing, transportation. equipment and tools use ionized air blowers to neutralize static charges of non-conductive mate- rials. use only the grounded tip variety of soldering iron. use proper power supply systems in testing and application. supply voltage should be applied before and removed after input signals. insertion and re- moval from sockets should be carried out with no power applied. filtration, noise suppression, slow voltage surges should be guaranteed on the supply lines. an open (floating) pin is a potential hazard to the circuit. each pin should be grounded or connected to v dd through a resistance whenever possible.
quality assurance 12/19 1.7 proper use of gang programmers gang programmers are designed for programming up to 10 eprom or otp devices at a time. it can run either in standalone or remote mode under control of a dos com- patible pc. gang programmers are used to program thousands of eprom or otp devices every day. great care has to be taken when handling and removing programmed devices. the following precautions must also be taken to decrease otp failures rates: precautions power supply power supply must be grounded. a power regulator or an ac filter must be used to regulate the incoming volt- age. dust protection clean sockets every day. use covers at the end of the day to protect sockets from dust. misc respect a maximum number of 10 000 insertions / socket before changing sockets.
13/19 reliability tests 2 reliability tests 2.1 definition reliability is the probability of a system or circuit performing its predefined function adequately under specific conditions for a given period of time. thus, the reliability of a microcircuit is a function of both stress conditions and the time of operation. the failure rate is the rate at which failures occur on units surviving to a specific number of hours of operation. failure rates per component-hours (i.e. number of hours of operation multiplied by the number of components) would generally be very small. to avoid reporting such small numbers, failure rates have been defined for greater component-hours. the unit used to define failure rate is called fit , and it rep- resents the absolute failures per billion component-hours . a failure rate of 0.1% / 1 000 000 component hours and 1 fit are equivalent numbers. failure rate over time: the bathtub curve the generic representational graph of failure rate vs. time takes the shape of a bathtub curve. the early failure rate (infant mortality) period starts from initial oper- ation and decreases as time goes on. the next phase of the curve is a very long pe- riod of time where failure rate is nearly constant and very low. after this long period, the failure rate starts to increase slowly. this last phase is known as the wear-out pe- riod . figure 6. failure rate over time vr02105f wear-out failure period random failure period initial failure period failure rate time
reliability tests 14/19 temperature dependency in order to access reliability in a reasonable time, it is necessary to accelerate the in- cidence of the failure modes. higher environmental stress levels than those encoun- tered under normal conditions are needed. the most employed accelerating param- eter is temperature, although voltage and humidity, for example, are also used. this is also done to simulate the behaviour of the component during its use under various conditions. the reliability tests are conducted on samples picked up from the current produc- tion. they are also performed to validate some major changes in the process related to the design, the wafer fabrication or the assembly. in addition, new products intro- duction is always evaluated by several reliability tests which stress the devices to be sure that the production will be safe. real time control tests are performed by our as- sembly sites to check that there are no deviations in their production. if a deviation oc- curs this kind of tests allows to react immediately and to take corrective actions. 2.2 die oriented tests high temperature operating life test (htol) this test is the most die oriented test because it simulates the operation of the device inside its application. the aim of this test is to check the ability of the die to be fully functional for a very long period (i.e. more than 9 years). the life cycle of the device has to be long enough and the only way to check it efficiently (i.e. within a reasonable time frame for both supplier and customer) is by realizing this kind of accelerated test. htol is the most generally accepted accelerated life test because high tempera- ture is known to accelerate many physical and chemical reactions, leading to accel- erated device failure. devices are loaded on burn-in boards designed to exercise the device circuit and placed in a chamber at elevated temperature. test conditions power supply supply voltage + 20% oven temperature 140 c duration 504 hours
15/19 reliability tests retention bake this is an accelerated test aimed to evaluate the ability of the memory cells to retain the programmed data. non volatile memory is programmed and devices are loaded in a chamber at high temperature without any bias. high temperature will give the charges enough energy to move from the floating gate, therefore leading to a reten- tion failure. electrical cycling endurance this test is aimed to verify the erase / write capability of the eeprom memory. erase / write cycles are performed at room temperature and are followed by a reten- tion bake at 150 c. electrostatic discharge (esd) test cmos devices are very sensitive to electro-static discharges. all components are de- signed to withstand normal amounts of electrostatic discharge during assembly, test and handling by the customer. two esd standards are used: the human body model and the machine model. each trial consists of 3 positive pulses and 3 negative pulses separated by 1 second and is performed on three parts for each of the following configurations: C electrical pulse between all pins referenced to all grounds C electrical pulse between all pins referenced to all power supplies C electrical pulse between each pin (except power supplies and grounds) referenced to all other pins connected together test conditions power supply no bias oven temperature 150 c duration 1008 hours test conditions / procedure 300 000 cycles of erase / write retest of the eeprom functi onality and programmation 168 hours of retention bake at 150 c verification of the eeprom contents human body model machine model r = 1.5 k w and c = 100 pf r = 0 w and c = 200 pf 3 positive pulses + 3 negative pulses separated by 1 second device has to pass 2000 v device has to pass 300 v
reliability tests 16/19 latch-up test latch-up is caused by turning on the parasitic pnpn structure in cmos circuits, due to a noise pulse, junction breakdown, or power supply transient overshoot. this will cause the circuit to malfunction temporarily or go into a destructive mode. there are 3 main tests, and each test is given a class letter (a, b or c) depending of the ob- tained result (a for the best result and c for the worst). overvoltage on power supplies : this test simulates an user induced situation where a transient over voltage is applied on power supply. current injection : this test simulates an user or application induced situation where either applied voltage on any pin is greater than v dd or where severe overshoot oc- curs on inputs. power supply sequence : this test simulates an user induced situation where a haz- ardous power supply sequence is applied to the component (board plug-in applica- tion when power supply is on). the final class for the device is the worst class among these three tests. 2.3 package oriented tests thermal cycling this test is made to determine the resistance of devices to exposure at temperature extremes, and especially to alternating extremes. this is also a worst case simulation of systems like cars, where the chip is exposed at very low temperatures during night and to high temperature when the car engine is running. temperature cycling failures are mainly caused by problems due to different thermal expansion coefficients be- tween: die, die attach, lead frame or mould compound. air to air temperature cycling maximum temperature + 150 c minimum temperature - 40 c cycle time 30 minutes duration 1000 cycles
17/19 reliability tests thermal shock thermal shock is the most extreme case of temperature transition: this accelerates any stress related failures with the rapidly changing gradient. that test is very close to thermal cycling, the main difference being the short temperature transition time ob- tained by dipping the devices in liquid. this test is specially aimed at ceramic pack- ages. temperature and humidity test the temperature and humidity test is generally accepted throughout the industry as the standard test for plastic package integrity, especially pertaining to moisture pen- etration. in this test, devices are loaded on boards designed to bias the device with minimum power dissipation (to minimize the drying effect) in a chamber at high tem- perature and humidity. pressure pot pressure pot test determines the survival capability of devices in moulded plastic packages to a hot, humid environment. the test exposes unbiased, plastic packaged devices to saturated steam at 121 c and 2 atm gauge pressure. pressure and the 240 hours of testing allow moisture to penetrate into the die. chemical corrosion of the die metallization may occur if contaminants are present due to passivation layer damage. liquid to liquid cycling maximum temperature + 125 c minimum temperature - 55 c transfer time 10 seconds maximum duration 100 shocks test conditions power supply supply voltage + 10% oven temperature 85 c relative humidity 85% duration 1008 hours test conditions oven temperature 121 c relative humidity 100% oven pressure 2 atm duration 240 hours
reliability tests 18/19 resistance to surface mounting the purpose of this test is to determine the resistance of devices to new techniques of surface-mount technology for assembling integrated circuits on printed boards. pop-corn effect is the cracking of the package during the soldering cycle which can compromise the integrity of surface-mount packages like sop, plcc or pqfp. cracks may occur in the moulding compound, depending on the absorbed moisture level, soldering temperature and time, die size, package structure and moulding com- pound characteristics. solderability the purpose of this test is to verify the solderability behaviour of the products (i.e. the ability of the tin leads to be soldered on the customer's board). test conditions / procedure (1) temperature and humidity test 85 c no bias 85% rh 96 hours 5.5 v (2) solder dipping t = 215 c, 120 s (t = 260 c, 10 s for so packages) 85 c (3) visual inspection for cracks on body electrical test 85% (4) pressure pot test (121 c / 2 atm / 96 hours) 1000 hours (5) electrical test test conditions (1) aging 16 hours / 155 c in dry air for smd 8 hours steam aging for other plastic packages 5.5 v (2) solder dipping t = 215 c (+/- 3 c), 3 s for smd t = 245 c (+/- 5 c), 5 s for other plastic packages 85 c inspection criteria: 95% coverage minimum
19/19 reliability tests glossary information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third par ties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs- thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. eos e lectrical o ver s tress. this expression summarizes all defects generated by the application of electrical conditions which are at least for one parameter out of specification. the main failure modes observed are damaged, melted, or burned out wires. esd e lectro s tatic d ischarge. the discharge of two differently charged elements might result in a discharge process when the elements are touching each other or electric fields influence the charge. due to the high charge voltages, semi-con- ductor structures can be damaged or destroyed along the path of discharge. main failure modes observed are increased leakage currents of input circuits and damaged input buffer structures. failure analysis a post mortem examination of failed devices for the purpose of verifying the re- ported failure and identifying the mode or mechanism of the failure. fit f ailure i n t ime. it is the unit of the failure rate. one fit is equal to one defect within one billion device hours. ppm p arts p er m illion, also defects per million. it is used as a unit to define a defect rate. screening 100% testing of a device, as opposed to sampling. spc s tatistical p rocess c ontrol. used to control the quality of the mass production process by statistical methods when process capability studies have been suc- cessful (based on pre-production data).

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