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| application note introduction to a 10a monolithic switching regulator in multipower-bcd technology by c.diazzi switched mode techniques led to the develop- ment of high efficiency circuits offering space sav- ing and a reduction in costs, mainly of the heatsink and output lc filter. for these applica- tions a new technology, called multipower- bcd, has been developed which allows the inte- gration on the same chip of isolated power dmos elements, bipolar transistors and cmos logic. the technology is particularly suitable for the problems rising in the switch mode field, due to the characteristics of high efficiency, fast switch- ing speed, no secondary breakdown of the power dmos element. the great flexibility that we have at our disposal for the choice of the signal and driving sections components allows optimization and compact- ness of the system. with multipower-bcd it has been possible to implement the family l497x, a new series of fully integrated switching regula- tors suitable for dc-dc converters working in buck configuration. the complete family consists of five devices which differ each other only by the output current value (2a, 3.5a, 5a, 7a, 10a) they can deliver to the load. the devices rated at 2a and 3.5a are assembled in power dip (16+2+2), while the others are assembled in the multiwatt15 package. each device integrates a dmos output power stage, a control section, limiting current and supervisor functions like reset and power fail signal for microprocessors applications. output voltage can be adjusted starting from the internal reference voltage (5.1v) up to 40v, allow- ing a maximum output power of 80w for the 2a version and of 400w for the 10a version. maxi- mum operating supply voltage is 55v. the technology the technology architecture is based on the verti- cal dmos silicon gate process that allows a channel length of 1.5 micron ; using a junction isolation technique it has been possible to mix on the same chip bipolar and cmos transistors along with the dmos power components (fig. 2). figure 1 shows how this process brings a rapid increase in power ic complexity compared to conventional bipolar technology. AN487/0592 the l497x series of high current switching regulator ics exploit multipower-bcd technology to achieve very high output currents with low power dissipation up to 10a in the multiwatt power package and 3.5a in a dip package . figure 1: bcd process and increase in power ics complexity. 1/12
in the 70's class b circuits and dc circuits al- lowed output power in the range of 70w. by 1980 ,with the introduction of switching techniques in power ics, output powers up to 200w were reached ; with bcd technology the output power increased up to 400w. functions and block diagram the complete block diagram of the high power l4970a is shown in fig.3. each block is analysed in the following. power supply the device is provided with an internal stabilized power supply ( vstart =12v ), that provides the supply voltage to the analog and digital control blocks and also the supply voltage to the boot- strap section. the vstart voltage supplies also the internal reference voltage section that provides accurate 5.1v voltage to the control loop. through trimming techniques the 5.1v reference is within +- 2% limits. oscillator and fedforward the oscillator block (fig.4) generates the sawtooth figure 2: cross section of the bcd mixed technology. figure 3: block diagram of the 10a monolithic regulator l4970a. application note 2/12 waveform that sets the switching frequency of the system. the signal, compared with the output voltage of the error amplifier, generates the pwm signal to be sent to the power output stage. the oscillator features a voltage feed-forward tech- nique which is completely integrated and doesn't require any external component. feed-forward function works in the supply voltage range 15- 45v. the rate of increase of the sawtooth wavw- form is directly proportional to the input voltage vcc. as vcc increases, the output pulse-width (transistor on-time) decreases in such a manner as to provide a constant ovolt-second' product to the inductance(fig.5). from fig.5 it is shown that the duty cycle changes due to the ramp increase when vcc increases. the error amplifier output doesn't have to change to keep the loop in regulation. this feature in- creases significantly the line regulation perform- ance. a resistor, between rosc and gnd , defines a current that is mirrored internally to charge the os- cillator capacitor on the cosc pin. the voltage at pin.rosc is a function of vcc value for the imple- mentation of the feed-forward function (oscillator slope proportional to vcc). a comparator is sens- ing the voltage across cosc capacitor and dis- carge it when the ramp exceedes an upper threshold proportional to vcc for the implementa- tion of the feed-forward function. the cosc dis- charge current is internally controlled at a value of about 20 ma. the lower threshold of the compa- rator is about 1.3v (2vbe). here are reported ba- sic equations for the oscillator: i charge = v cc - 9v be r osc. for 15v < v cc < 45v (1) figure 4: oscillator circuit. figure 5: voltage feeforward waveform. application note 3/12 i disch @ 20ma (2) v th.high = v cc - 9v be 9 + 2v be for 15v < undervoltage lockout the chip features a complete built-in under volt- age lock out protection, keeps the power output stage off up to the moment vcc reaches 11v, with an hysteresis of 1v. after reaching the 11v value the system starts with the soft start feature. error amplifier the error amplifier is a transconductance opera- tional amplifier featuring a current output. the simplified schematic is represented in fig.10. the basic characteristics of the uncompensated operational amplifier are the following: -g m = 4ma/v, -r o = 2.5mohm, -a vo =80db, -i source/sink = 200 m a -i input bias current = 0.3 m a the frequency behavior of the uncompensated amplifier is reported in fig.11. neglecting the high frequency behavior (in the hy- potesis that in the overall frequency compensa- tion of the loop the second pole of the operational amplifier is far below the 0 db axis), we can make a first order approx. by which the error amplifier can be schematized by the equivalent circuit of fig.12. by which a v ( s ) = g m ? r o 1 + sr o c o where c o = 3pf. the error amplifier is inserted in the regulation loop and can be easily compensated, thanks to its high output impedance, with a network between its output and ground. the typical compensated network is shown in fig.13. the transfer function is: a v ( s )= g m ? r o ( 1 + s r c c c ) s 2 r o c o r c c c + s ( r o c c + r o c o + r c c c )+ 1 in the hypotesis that rc such a configuration introduces a low frequency pole and two zeros z1 = 1/2 p r1c1 and z2 = 1/2 p r2c2. note that due to the high output im- pedance it is present also a second pole p2 = gm/2 p c1. usually it is better to use the highest possible value for r1, to have a low value for c1 in such a way to put p2 at the highest frequency. limitations to r1 value are put by offset voltage due to opamp. input bias currents. if a resistive divider is used at the output of the power supply, for voltages higher than 5.1v, it is possible to introduce a second zero with the net- work of fig.16. such a configuration introduce 2 zeros at: z 1 = 1 2 p r c c c ;z 2 = 1 2 p r 1 c 1 and 2 poles at: p 1 = 1 2 p r o c c ;p 2 = 1 2 p r x c 1 ;r x = r 1 r 2 r 1 + r 2 application example consider the block diagram of fig.17, representing the internal control loop section, with the applica- tion values: fswitch = 200khz, l = 100 m h, c =1000 m f, po=50w, vo =5.1v, io =10a and fo = 500hz. g loop = pwm ? filter the system requires that dc gain is maximum to achieve good accuracy and line rejection. beyond this a bandwidth of some khz is usually required for a good load transient response. the error am- plifier transfer function must guarantee the above constraints. a compensation network that could be used is shown in fig.19. a ( s ) = ( 1 + sr 1 c 1 )( 1 + sr 2 c 2 ) sr 1 c 1 ( 1 + s c 1 g m ) figure 15: one pole, two zero compensation network. figure 16: compensation network for output voltages higher than 51v. figure 17: block diagram used in stability calculation. figure 18: frequency behavior of the circuit of fig 17. figure 19: compensation network. application note 7/12 the criterium is to define z1, z2 close to the reso- nant pole of the output lc filter. the gm/2 p c 1 pole must be placed at a frequency at which open loop gain is below 0 db axis (fig. 20). current limitation current limitation is implemented intrnally to the chip and doesn't need any external component. the output current is sensed by an internal resis- tor in series with the drain of the power transistor. on chip trimming guarantees +10% accuracy on the value of peak current limitation. current limit protection works pulse by pulse with lowering of tnhe switching frequency. fig.21 shows circuital implementation of current protec- tion. figure 20: bode plot of the regulation loop with the compensation network of fig. 19. figure 21: current protection circuit. application note 8/12 when the comparator senses an overcurrent, the flip-flop is set and an internal inhibit signal is gen- erated. the flip-flop remains set until next reset clock pulse coming from the internal 40 khz oscil- lator. after the reset pulse the regulation loop takes the control of the system and the output current begins to increase to the load value at the switching frequency of the master clock. if the overload condition is still present the protection cycle repeats. this mixed, pulse by pulse, lower- ing frequency current protection method, assures a constant current output when the system is in overload or short circuit and allows to implement a reliable current limitation even at high switching frequency (500 khz) reducing the problems of signal delay through the protection stage. fig.22 shows behavior of the inductance current when the system is in overload. the internal 40 khz oscillator is synchronized with the master clock. when the system works with the master clock at a lower frequency of the internal clock, than the internal clock tracks the master frequency. this assures that the fre- quency does not increas during overload. power fail-reset circuit the l4970a include a voltage sensing circuit that may be used to generate a power on power off reset signal for a microprocessor system. the cir- cuit senses the input supply voltage and the out- put generated voltage and will generate the re- quired reset signal only when both the sensed voltages have reached the required value for cor- rect system operation. the reset signal is gener- ated after a delay time programmable by an ex- ternal capacitor on the delay pin. fig. 23 shows the circuit implementation of reset circuit. the supply voltage is sensed on an external pin, for programmability of the threshold, by a first com- parator. the second comparator has the refer- ence threshold set at slightly less the ref. voltage for the regulation circuit and the other input con- nected internally at the feedback point on the er- ror amplifier. this allows to sense the output regulated voltage. when both the supply voltage and the regulated voltage are in the correct range, transistor q1 turns off and allows the cur- rent generator to charge the delay capacitor. when the capacitor voltage reaches 5v the out- put reset signal is generated. a latch assures that if a spike is present on the sensed voltage the delay capacitor discharges completely before initialization of a new reset cycle. the output gate assures immediate take of reset signal with- figure 22: overload inductance current. figure 23: power fail and reset circuit. application note 9/12 out waiting for complete discharge of delay ca- pacitor. reset output is an open collector transis- tor capable of sinking 20ma at 200mv volt- age.fig. 24 shows reset waveforms. the power stage a simplified schematic of the output stage along with the external filter components is shown in fig.25. power stage and associated driving circuits are among the most critical components to achieve good performances at high switching frequency. an external bootstrap capacitance, charged via diode d1 at 12v, is needed to provide the correct gate drive to the power dmos n-channel transis- tor. the driving circuit is able to deliver a current peak of 0.5a, during turn on and turn off phases, to the gate of power dmos transistor. the circuit- described shows commutation times of 50ns. figure 24: reset and power fail waveforms. figure 25: power stage circuit. application note 10/12 the five devices of l497x family differentiate each other only for the level of current protection, while the control part is the same and power de- vice area is the same to guarantee low power dis- sipation also for low current versions in dip pack- age. table 1 and fig.26 shows electrical characteristics of the power dmos implemented in the chip. thermal protection the thermal protection function operates when the junction temperature reaches 150 c; it acts directly on the power soft start capacitor, dis- charging it. the thermal protection is provided with hysteresis and therefore, after an interven- tion has occurred, it is necessary to wait for the junction temperature to decrease of about 30 de- gree c below the intervention threshold. table 1. b vdss > 60v at i d = 1ma v gs =0v r ds(on) = 100m w at i d = 10a t j =25 cv gs = 10v r ds(on) = 150m w at i d = 10a t j = 150 cv gs = 10v v th =3v ati d = 1ma figure 26: gate-charge curve for the power dmos. application note 11/12 information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs- thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. application note 12/12 |
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