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september 1997 figure 1. block diagram. pin numbers plcc/dip. pbl 3766, pbl 3766/6 subscriber line interface circuit description the pbl 3766 subscriber line interface circuit (slic) is a monolithic integrated circuit, manufactured in 75 v bipolar technology. the pbl 3766 slic facilitates the design of cost effective, high performance on-premises (ons) analog line interface cards for pabx systems and terminal adapters. small package size and few required external components result in a miniaturized design. the pbl 3766 programmable, constant current loop feed system can operate with battery supply voltages between -24 v and -58 v. the slic incorporates loop current and ring trip detection functions as well as a ring relay driver. the two- to four-wire and four- to two-wire voice frequency (vf) signal conversion, i.e. the hybrid function, is provided by the slic in conjunction with either a conven- tional or a programmable codec/filter. the pbl 3766 package is a 22 pin, plastic dual-in-line (batwing) or a 28-pin, plastic j-leaded chip carrier (plcc). the differences between pbl 3766 and pbl 3766/6 are the specifications for balance, output offset voltage, and insertion loss. key features ? low cost ? few external components ? programmable, constant current loop feed ? line feed characteristics independent of battery supply variations ? -24 v to -58 v battery supply voltage range ? detectors C programmable loop current detector C ring trip detector ? ring relay driver ? hybrid function with conventional or programmable codec/filters ? line terminating impedance, complex or real, set by a simple external network or controlled by a programmable codec/filter ? idle noise typ. -83 dbmp, typ. 7 dbrnc ? low on-hoo k power dissipation: 20 mw @ -28 v, 35 mw @ -48 v ? tip-ring open circuit state for subscriber loop power denial ? on-hook transmission pbl3766 pbl 3766 2 1/ 6 1 23/20 27 / 21 20 / 15 21 / 1 6 28 / 2 2 1 1/ 4 1 4/ 7 9 1/ 2 2 4 1 / 9 1 3/ 5 0 1 / 3 1 9/ 2 1 7/ 9 8/ 1 1 4/2 18/13 2/1 3, 6, 10, 17, 24/ 5, 6, 17, 18 ring t rip detector ring relay driver input/output decoder and control loop current detector vf signal t ransmission t wo-wire interface dt tipx hpt hpr ringx vcc vee vb a t gnd line feed controller and longitudinal signal suppression ringr l y c1 c2 e0 det rdc rsg rd vtx rsn 4-1
4-2 pbl 3766 absolute maximum ratings parameter symbol min max unit temperature and humidity storage temperature range t stg -60 +150 c operating temperature range t case -10 +110 c operating junction temperature t j -10 +140 c storage humidity r h 5 95 % rh power supply, -10 c < t amb < 80 c v cc with respect to gnd v cc -0.5 6.5 v v ee with respect to gnd v ee -6.5 0.5 v v bat with respect to gnd v bat -70 v ee +0,7 v power dissipation continuous power dissipation at t amb 70 cp d 1.5 w peak power dissipation at t amb = 70 c, t < 10 ms, t rep > 10 sec. p dp 4w relay driver ring relay supply voltage v rrly v bat 0v ring relay current i rrly 50 ma ring trip comparator input voltage v dt v bat 0v input current i dt -2 2 ma digital inputs, outputs (c1, c2, e0, det ) input voltage v id 0v cc v output voltage ( det disabled) v od 0v cc v output current ( det enabled) i od 5ma tipx or ringx terminals, v bat = -50 v tipx or ringx voltage, continuous, (note 1) v t , v r v bat 0.5 v tipx or ringx pulse = t w < 10 ms, t rep > 10 s (notes 2, 3) v t , v r v bat - 20 5 v tipx or ringx pulse = t w < 1 m s, t rep > 10 s (notes 2, 3) v t , v r v bat - 40 10 v tip or ring pulse = t w < 250 ns, t rep > 10 s (notes 2, 3) v t , v r v bat - 70 15 v tipx or ringx current active i ldc + i lodc 80 ma stand-by i ldc 25 ma recommended operating conditions parameter symbol min max unit case temperature t case 090 c v cc with respect to ground v cc 4.75 5.25 v v ee with respect to ground v ee -5.25 -4.75 v v bat with respect to ground (note 4) v bat -58 -24 v notes 1. with a diode (d 2 ) connected in series with the v bat supply, as shown in figure 11, -70 v may be continuously applied to the tipx or ringx lead. 2. these voltage ratings require a diode (d 2 ) to be installed in series with the v bat supply as shown in figure 11. 3. v t and v r are referenced to ground. t w is the pulse width of a rectangular test pulse and t rep is the pulse repetition rate. 4. -24 v < v bat < -21 v may be used in applications requiring maximum vf signal amplitudes less than 3 v pk (8.75 dbm, 600 ohms).
pbl 3766 4-3 figure 3. longitudinal to metallic (b lme ) and longitudinal to four-wire (b lfe ) balance. 1 << 150 ohms, r lr = r lt = 300 ohms, w c r t = 600 kohms, r rx = 300 kohms figure 2. overload level, v tro , two-wire port. 1 << r l , r l = 600 ohms, w c r t = 600 kohms, r rx = 300 kohms electrical characteristics 0 c < t amb < 70 c, v cc = +5 v 5 %, v ee = -5 v 5 %, v bat = -48 v, r sg = 0 ohm , r dc = 41.7 kohms, r d = , z l = 600 ohms, c hp = 33 nf, c dc = 1.5 m f unless otherwise specified. ref parameter fig. conditions min typ max unit two-wire port overload level, v tro 2z l = 600 ohms, 1% thd, note 1 3.1 v pk input impedance, z trx note 2 longitudinal impedance, z lot , z lor f < 100 hz 25 40 ohm/wire longitudinal current limit, i lot , i lor active state, c2, c1 = 1, 0 20 ma pk /wire longitudinal to metallic balance, b lm ieee standard 455-1985 0.2 khz f 3 khz pbl 3766 53 58 db pbl 3766/6 48 58 db longitudinal to metallic balance, b lme 3|e lo | b lme = 20 log |v tr | 0.05khz f 3.4khz pbl 3766 53 58 db pbl 3766/6 48 58 db longitudinal to four-wire balance, b lfe 3|e lo | b lfe = 20 log |v tx | 0.05khz f 3.4khz pbl 3766 53 58 db pbl 3766/6 48 58 db metallic to longitudinal balance, b mle 4|e tr | b mle = 20 log , e rx = 0 |v lo | 0.2khz f 3.4khz pbl 3766 50 55 db pbl 3766/6 48 55 db four-wire to longitudinal balance, b fle 4|e rx | b fle = 20 log , e tr source removed |v lo | 0.2khz f 3.4khz 40 55 db i ldc r l v tro c r t r rx e rx tipx 27/21 ringx 28/22 vtx 19/14 rsn 16/12 pbl 3766 v tr c r t r rx v tx tipx 27/21 ringx 28/22 vtx 19/14 rsn 16/12 pbl 3766 r lt r lr e l o
4-4 pbl 3766 ref. parameter fig. conditions min typ max unit two-wire return loss, r |z trx + z l | r = 20 log |z trx - z l | z trx ? z l = nom. 600 w, note 3 0.2 khz f 0.5 khz 25 30 db 0.5 khz f 1.0 khz 27 32 db 1.0 khz f 3.4 khz 23 25 db tipx idle voltage, v ti active, i l = 0 -5 v stand-by, i l = 0 0 v ringx idle voltage, v ri active, i l = 0 -43 v stand-by, i l = 0 -48 v four-wire transmit port (vtx) overload level, v txo 5 load impedance > 20 kohms, 3.1 v pk 1% thd, note 4 output offset voltage, d v tx pbl 3766 -40 +40 mv pbl 3766/6 -55 +55 mv output impedance, z tx 0.2 khz < f < 3.4 khz <5.0 20 ohm four-wire receive port (rsn) rsn dc voltage, v rsn i rsn = 0 0 v rsn impedance, z rsn 0.3 khz f 3.4 khz <5 20 ohm rsn current (i rsn ) to metallic loop current 0.3 khz f 3.4 khz 1000 ratio (i l ) gain, a rsn frequency response two-wire to four-wire, g 2-4 6 0.3 khz < f < 3.4 khz relative -0.1 0 +0.1 db to 0 dbu, 1.0 khz. e rx = 0 v four-wire to two-wire, g 4-2 6 0.3 khz < f < 3.4 khz relative -0.1 0 +0.1 db to 0 dbu, 1.0 khz. e l = 0 v four-wire to four-wire, g 4-4 6 0.3 khz < f < 3.4 khz relative -0.1 0 +0.1 db to 0 dbu, 1.0 khz. e l = 0 v insertion loss two-wire to four-wire, g 2-4 6 0 dbm, 1.0 khz, note 5 pbl 3766 -0.20 0 +0.20 db pbl 3766/6 -0.25 0 +0.25 db four-wire to two-wire, g 4-2 6 0 dbm, 1.0 khz, notes 5, 6 pbl 3766 -0.20 0 +0.20 db pbl 3766/6 -0.25 0 +0.25 db four-wire to four-wire, g 4-4 6 0 dbm, 1.0 khz, notes 5, 6 -0.3 0 +0.3 db figure 5. overload level, v txo , four-wire transmit port. 1 << r l , r l = 600 ohms, w c r t = 600 kohms, r rx = 300 kohms figure 4. metallic to longitudinal (b mle ) and four-wire to longitudinal (b fle ) balance. 1 << 150 ohms, r lr = r lt = 300 ohms, w c r t = 600 kohms, r rx = 300 kohms e tr r lr c v l o r t r rx e rx tipx 27/21 ringx 28/22 vtx 19/14 rsn 16/12 pbl 3766 r lt i ldc r l c r t r rx v txo tipx 27/21 ringx 28/22 vtx 19/14 rsn 16/12 pbl 3766 e l
pbl 3766 4-5 figure 6. frequency response, insertion loss, gain tracking. 1 << r l , r l = 600 ohms, w c r t = 600 kohms, r rx = 300 kohms ref parameter fig. conditions min typ max unit gain tracking two-wire to four-wire 6 ref. -10 dbm, 1.0 khz, note 7 -40 dbm to +7 dbm -0.15 0.03 +0.15 db -55 dbm to -40 dbm 0.03 db four-wire to two-wire 6 ref. -10 dbm, 1.0 khz, note 8 -40 dbm to +7 dbm -0.15 0.03 +0.15 db -55 dbm to -40 dbm 0.03 db noise idle channel noise at two-wire note 9 (tipx-ringx) or four-wire (vtx) port psophometrical weighting -83 -78 dbmp c-message weighting 7 12 dbrnc harmonic distortion two-wire to four-wire 0.3 khz f 3.4 khz -65 -54 db four-wire to two-wire 0 dbm, 1.0 khz test signal battery feed characteristics loop current in constant current region, i l active state, c2, c1 = 1, 0 0.85 i l i l 1.15 i l a 2500 i l = r dc + 41700 r dc in ohms stand-by state loop current, i l , stand-by state, c2, c1 = 1, 1 0.75i l i l 1.25i l a tolerance range v bat - 3 i l = r l + 1800 v bat tol. 5%, t amb = 25 c loop current detector on-hook to off-hook threshold, i lthoff r d = , note 10 8.0 ma off-hook to on-hook threshold, i lthon r d = , note 10 7.3 ma detector threshold hysteresis, ? i lth 0.7 ma loop current detector conversion factor on-hook to off-hook, k lthoff 11 375 500 660 v i lthoff = k lthoff + ? r d 62500 ? note 11 loop current detector conversion factor 11 455 v i lthon = k lthon + off-hook to on-hook, k lthon ? r d 62500 ? note 11 ring trip detector offset voltage, d v dtr source resistance, r s = 0 -25 25 mv input bias current, i dt v bat < v dt < 0 v -300 -100 na input common mode range, v dt v bat +1 -2 v ring relay driver on-state voltage, v rrly i rrly = 25 ma -0.5 -0.2 v off state leakage current, i rrly v bat < v rrly < 0 10 m a v tr e rx i ldc r l c r t r rx v tx tipx 27/21 ringx 28/22 vtx 19/14 rsn 16/12 pbl 3766 e l
4-6 pbl 3766 ref. parameter fig. conditions min typ max unit digital inputs (c1, c2, e0) input low voltage, v il 0 0.8 v input high voltage, v ih 2.0 v cc v input low current, i il v il = 0.4 v c1, c2 -200 m a e0 -100 m a input high current, i ih v ih = 2.4 v 40 m a digital output (det) output low voltage, v ol i ol = 2 ma, e0 = 0 0.4 0.6 v output high voltage, v oh i oh = -100 m a, e0 = 0 2.7 v internal pull-up resistor 10 15 20 kohm det short circuit current, i ods e0 = 1, det shorted to ground -330 m a power supply rejection ratio, psrr to two-wire or four-wire port, from note 12 v cc , psrr cc 50 hz f 4 khz 30 35 db 4 khz f 50 khz 30 35 db v ee , psrr ee 50 hz f 4 khz 30 35 db 4 khz f 50 khz 12 18 db v bat , psrr bat 50 hz f 4 khz 40 50 db 4 khz f 50 khz 30 35 db power supply currents (relay driver off) v cc current, i cc open circuit state 1 ma v ee current, i ee c2, c1 = 0, 0 1 ma v bat current, i bat on-hook 0.5 ma v cc current, i cc stand-by state 2 ma v ee current, i ee c2, c1 = 1, 1 1 ma v bat current, i bat on-hook 0.5 ma v cc current, i cc active state 4 ma v ee current, i ee c2, c1 = 1, 0 2 ma v bat current, i bat on-hook 3 ma power dissipation open circuit state total dissipation, p op c2, c1 = 0, 0 25 35 mw on-hook (r l = ) or off-hook (r l = 0) stand-by state total dissipation, p onsb c2, c1 = 1, 1 35 45 mw on-hook (r l = ) active state total dissipation, p onact c2, c1 = 1, 0 160 220 mw on-hook (r l = ) active state total dissipation, c2, c1 = 1, 0, note 13 p offact200 off-hook, r l = 200 ohm 1.35 1.50 w p offact600 off-hook, r l = 600 ohm 1.05 1.20 w temperature guard junction temperature at threshold, t jg 145 160 170 c temperature guard hysteresis, ? t jg 20 c thermal resistance 28-pin plcc, q jp28plcc junction to terminals 3, 6, 10, 17, 24 10 15 c/w connected together, note 14 22-pin plastic dip, q jp22dip junction to terminals 5, 6, 17, 18 10 15 c/w connected together, note 14
pbl 3766 4-7 notes 1. the overload level is specified at the two-wire port with the signal source at the four-wire receive port. 2. the two-wire impedance is programmable by selection of external component values according to: z trx =z t /|g 2-4 a rsn | where z trx = impedance between the tipx and ringx terminals z t = programming network between the v tx and rsn terminals g 2-4 = tipx-ringx to vtx gain, nominally = 1 a rsn = receive current gain, nominally = -1000 (current defined as positive when flowing into the receive summing node, rsn and when flowing from tipx to ringx). 3. higher return loss values can be achieved by adding a reactive component to r t , the two-wire terminating impedance programming resistor, e.g. by dividing r t into two equal halves and connecting a capacitor from the common point to ground. for r t = 600 kohms the capacitance value is approximately 33 pf. 4. the overload level is specified at the four-wire transmit port, vtx, with the signal source at the two-wire port. note that t he gain from the two-wire port to the four-wire transmit port is g 2-4 = 1. 5. fuse resistors r f impact the insertion loss as explained in the text, section transmission. the specified insertion loss is for r f =0. 6. the specified insertion loss tolerance does not include errors caused by external components. 7. the level is specified at the two-wire port. 8. the level is specified at the four-wire receive port and referenced to a 600 ohm impedance level. 9. the two-wire idle noise is specified with the port terminated in 600 ohms (r l ) and with the four-wire receive port grounded (e rx = 0, see figure 6). the four-wire idle noise at vtx is specified with the two-wire port terminated in 600 ohms (r l ). the noise specification is with respect to a 600 ohm impedance level at vtx. the four-wire receive port is grounded (e rx = 0, see figure 6). 10. with the rd terminal left open, the loop current detector on-hook to off-hook threshold is internally set to 8.0 ma and the off- hook to on-hook threshold to 7.3 ma. the loop current detection threshold can be set to higher values by connecting a resistor, r d , between terminal rd and v ee (-5 v), as described in section loop monitoring functions. 11. refer to section loop monitoring functions, loop current detector. 12. power supply rejection ratio test signal is 100 mvrms (sinusoidal). 13. line resistor r f = 0 ohm. 14. junction to ambient thermal resistance will be dependent on external thermal resistance from vbat terminals to ambient.
4-8 pbl 3766 pin description plcc: 28-pin, plastic, j-leaded chip carrier. dip: 22-pin, dual-in-line (batwing), plastic package. refer to figure 7. plcc dip symbol description 1 - ringx sense ringx sense is internally connected to ringx. ringx sense is used during manufacturing, but requires no connection in slic applications, i.e. leave open. 2 1 gnd ground. 3 - vbat refer to plcc, terminal 6 description. 4 2 vcc +5 v power supply. 5 3 ringrly ring relay driver output. open emitter with grounded collector (npn). sources 50 ma from ground to a relay coil connected to a negative voltage. must be protected by external inductive kick-back diode. positive voltage relay driver can be provided as a metal mask option. contact factory for availability. 6, 3, 5, 6, vbat battery supply voltage. negative with respect to gnd. -21 v to -58 v. all vbat terminals 10, 17, 17, 18 should be connected to printed circuit board traces to provide heatsinking. 24 7 4 rsg saturation guard programming resistor, r sg , connects from this terminal to vee. leave open for nominal battery voltages from -24 v to -28 v. connect to vee for a nominal battery voltage of -48 v. for other battery voltages and for detailed information refer to section battery feed. 8 - nc no internal connection. note 1. 9 7 e0 ttl compatible enable input. enables the det output, when set to logic level low and disables the det output, when set to logic level high. refer to section enable input for detailed information. 10 - vbat refer to plcc, terminal 6 description. figure 7. pin configuration, 28-pin plastic leaded chip carrier and 22-pin plastic dual-in-line package, top view. 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 vtx gnd vcc ringrly rsg vbat vbat e0 det c2 c1 rdc ringx tipx dt rd vbat vbat hpr hpt vee rsn 5 6 7 8 9 10 11 25 24 23 22 21 20 19 4 3 2 1 28 27 26 12 13 14 15 16 17 18 nc vbat dt rd hpr hpt vtx ringrly vbat rsg nc e0 vbat det vcc vbat bgnd ringx sense tipx sense tipx ringx c2 c1 rdc nc rsn vbat vee
pbl 3766 4-9 plcc dip symbol description 11 8 det detector output. inputs c1 and c2 select one of the two detectors to be connected to the det output. a logic low level at the enabled (refer to e0) det output indicates a triggered detector condition. the det output is open collector with internal pull-up resistor (approximately 15 kohms) to vcc. 12 9 c2 c1 and c2 are ttl compatible inputs controlling the slic operating states. refer to section 13 10 c1 control inputs for details. 14 11 rdc dc loop feed is programmed by one resistor connected from this pin to the receive summing node (rsn) a decoupling capacitor, c dc , connected from rdc to gnd removes noise and other ac signals from the battery feed control loop. 15 - nc no internal connection. note 1. 16 12 rsn receive summing node. 1000 times the current (dc and ac) flowing into this pin equals the metallic (transversal) current flowing from ringx to tipx. programming networks for constant dc loop current, two-wire impedance and receive gain connect to the receive summing node. 17 - vbat refer to plcc, terminal 6 description. 18 13 vee -5v power supply. 19 14 vtx transmit vf output. the ac voltage difference between tipx and ringx, the ac metallic voltage, is reproduced as an unbalanced gnd referenced signal at vtx with a gain of one. the two-wire termina- ting impedance programming network connects between vtx and rsn. 20 15 hpt tip side of ac/dc separation capacitor c hp . other end of c hp connects to pin, hpr. 21 16 hpr ring side of ac/dc separation capacitor c hp . other end of c hp capacitor connects to pin, hpt. 22 19 rd loop current detector programming resistor r d connects from rd to vee. an optional filter capacitor c d may be connected between terminal rd and ground. with the rd pin left open, the loop current detect threshold is internally set to 8.0 ma. refer to section loop monitoring functions for additional information. 23 20 dt dt is the non-inverting ring trip comparator input. the inverting comparator input is internally connected to v ee . with dt more negative than the inverting input, the detector output, det, is at logic level low, indicating off-hook condition. the ring trip network connects to the dt input. 24 - vbat refer to plcc, terminal 6 description. 25 - nc no internal connection. note 1. 26 - tipx sense tipx sense is internally connected to tipx. tipx sense is used during manufacturing, but requires no connection in slic applications, i.e. leave open. 27 21 tipx the tipx and ringx pins connect to the tip and ring leads of the two-wire interface via overvoltage 28 22 ringx protection components and ring relay (and optional test relays). notes 1. terminals marked nc are not internally connected to the chip. these terminals may be connected to ground for shielding.
4-10 pbl 3766 functional description and applications information transmission general a simplified ac model of the transmission circuits is shown in figure 8. circuit analysis yields: v tr = v tx + i l 2r f (1) v tx v rx i l + = (2) z t z rx 1000 v tr = e l - i l z l (3) where v tx is a ground referenced unity gain version of the ac metallic voltage between the tipx and ringx terminals, i.e. v tx = 1 v trx . v tr is the ac metallic voltage between tip and ring. e l is the line open circuit ac metallic voltage. i l is the ac metallic current. r f is a current limiting resistor in the overvoltage protection network. z l is the line impedance. z t determines the slic tipx to ringx impedance. z rx controls four- to two-wire gain. v rx is the analog ground referenced receive signal. two-wire impedance to calculate z tr , the impedance presented to the two-wire line by the slic including the fuse resistors r f , let v rx = 0. from (1) and (2): z t z tr =+ 2r f 1000 with z tr and r f known z t may be calculated from z t = 1000 (z tr - 2r f ) example: calculate z t to make the terminating impedance z tr = 600 ohms in series with 2.16 m f. r f = 40 ohms. using the expression above 1 z t = 1000 (600 + - 2 40) j w 2.16 10 -6 i.e z t = 520 kohms in series with 2.16 nf. it is necessary to have a high ohmic resistor in parallel with the capacitor. this gives a dc-feedback loop, for low frequency which ensures stability and reduces noise. two-wire to four-wire gain the two-wire to four-wire gain, g 2-4 , is obtained from (1) and (2) with v rx =0: v tx z t /1000 g 2-4 == v tr z t /1000 + 2r f four-wire to two-wire gain the four-wire to two-wire gain, g 4-2 , is derived from (1), (2) and (3) with e l = 0: v tr z t z l g 4-2 == - v rx z rx z t /1000 + 2r f + z l four-wire to four-wire gain the four-wire to four-wire gain, g 4-4 , is derived from (1), (2) and (3) with e l = 0: v tx z t z l + 2r f g 4-4 == - v rx z rx z t /1000 + 2r f + z l hybrid function the pbl 3766 slic forms a particularly flexible and compact line interface when used with programmable codec/filters. the programmable codec/filters allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. it also permits the system controller to adjust transmit and receive gains as well as terminating impedance. refer to pro- grammable codec/filter data sheets for design information. the hybrid function in an implementa- tion utilizing the uncommitted amplifier in a conventional codec/filter combination is shown in figure 9. via impedance z b a current proportional to v rx is injected into the summing node of the combination codec/filter amplifier. as can be seen from the expression for the four-wire to four-wire gain a voltage proportional to v rx is returned to vtx. this voltage is converted by r tx to a current into the same summing node. these currents can be made to cancel by letting: v tx v rx += 0 (e l = 0) r tx z b substituting the four-wire to four-wire gain expression, g 4-4 , for v rx /v tx yields the formula for a balanced network: v rx z rx z t /1000+2r f +z l z b = -r tx = r tx v tx z t z l + 2r f example: z tr = z l = 600 ohms (r l ) in series with 2.16 m f (c l ), r f = 40 ohms, r tx = 20 kohms, g 4-2 = -1. calculate z b . using the z b formula above: z rx 2z l z b = {z l = z tr } = r tx = z t z l + 2r f z l = {g 4-2 = -1} = r tx = z l + 2r f 1 + j w r l c l = r tx 1 + j w (r l + 2r f ) c l a network consisting of r b1 in series with the parallel combination of r b and c b has the same form as the required balance network, z b . basic algebra yields: r l r b1 = r tx = 17.6 kohms r l + 2r f 2r f r b = r tx = 2353 ohms r l + 2r f (r l + 2r f ) 2 c l c b = = 0.62 m f r tx 2r f longitudinal impedance in the active state, a feedback loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. therefore longitudinal disturbances will appear as longitudinal currents and the tipx and ringx terminals will experience very small longitudinal voltage excursions, well within the slic common mode range. this is accomplished by comparing the instantaneous two-wire longitudinal voltage to an internal reference voltage, v bat /2. as shown below, the slic appears as 20 ohms to ground per wire to longitu- dinal disturbances. it should be noted, that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. from figure 10 the longitudi- nal impedance can be calculated: v lo r lo = = 20 ohms i lo 1000 where v lo is the longitudinal voltage i lo is the longitudinal current r lo = 20 kohms sets the longitudinal impedance
pbl 3766 4-11 figure 9. hybrid function. figure 8. simplified ac transmission circuit. figure 10. longitudinal feedback loop. pbl 3766 + - 1 + - 1 + - 19/14 vtx 16/12 rsn i l /1000 tipx 27/21 ringx 28/22 hpt hpr + - e l + - tip ring r f r f z tr z t v tx v rx z rx i l i l r 2 hp r 2 hp + - c hp 20/15 21/16 z l v tr + - v t combination codec/filter r tx r fb z b z rx z t vtx rsn v rx pbl 3766 16/12 19/14 + - 1 1 1 pbl 3766 r r v bat /2 v lo + v bat /2 v lo i lo /1000 r lo = 20 kohms i lo i lo i lo i lo v lo v lo tipx 27/21 ringx 28/22
4-12 pbl 3766 figure 11. single channel subscriber line interface with pbl 3766 and a combination codec/filter. notes 1. the relay coil may be connected to a negative voltage, down to the v bat limit. for v bat = -48 v relay coils with voltage ratings from 5 v to 48 v may be used. 2. the plastic leaded chip carrier terminals 3, 6, 10, 17 and 24 shall all be connected to the v bat supply trace to provide heat sinking. 3. the dual-in line package terminals 5, 6, 17 and 18 shall all be connected to the v bat supply trace to provide heat sinking. 4. the plastic leaded chip carrier terminals 8, 15 and 25 are not internally connected to the chip. these terminals may be connected to ground to provide shielding. 5. it may be desirable to include a ptc or other type of short circuit protection for the ringing generator. 6. the ground terminals of the secondary protection should be connected to the ground terminal of the slic, and to the common ground on the printed board assembly with a track as short and wide as possible, preferable a groundplane. capacitors c tc and c rc the capacitors designated c tc and c rc in figure 11, connected between tipx and ground as well as between ringx and ground, are recommended as an addition to the overvoltage protection network. very fast transients, appearing on tip and ring, may pass by the diode and scr clamps in the overvoltage protection network, before these devices have had time to activate and could damage the slic. c tc and c rc short such very fast transients to ground. the recommended value for c tc and c rc is 2200 pf. higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. c tc and c rc contribute a metallic impedance of 1/( p fc tc ) ? 1/( p fc rc ), a tipx to ground impedance of 1/(2 p fc tc ) and a ringx to ground impedance of 1/(2 p fc rc ). ac - dc separation capacitor, c hp the high pass filter capacitor connected between terminals hpt and hpr pro- vides the separation between circuits sensing tip-ring dc conditions and circuits processing ac signals. a c hp value of 33 nf will position the low end frequency response 3db break point at 12 hz (f 3db ) according to f 3db = 1/(2 p r hp c hp ) where r hp ? 400 k w . battery feed overview the pbl 3766 slic synthesizes a cons- tant current feed system. the block dia- gram in figure 12 shows the pbl 3766 active state battery feed system. the magnitude of the constant current is set by a programming resistor, r dc . to permit the line drive amplifiers to operate without vf signal distortion even on high resistance or open circuit loops, a saturation guard circuit limits the loop voltage, when the tip to ring dc voltage approaches the available battery supply voltage. the saturation guard function allows the pbl 3766 to transmit and receive vf signals with the telephone on- hook. figure 13 shows an example of pbl 3766 active state battery feed. with the slic set to the stand-by state, most of the circuit is disabled, including the line drive amplifiers, to conserve power. u 1 slic (subscriber line interface circuit). pbl 3766 u 2 combination codec/filter, e.g. tp3054 (or programmable codec/filter, e.g. slac) u 3 secordary protection (e g texas instruments tisp pbl1) k r ring relay, 2c contacts. note 1 d 1 , d 2 diode, e.g. 1n4454 d 3 diode, e.g. 1n4004 r f line resistor, 40 w 1% match, e.g. ericsson components pbr 51xx r 1 resistor, 150 k w , 5%, 1 / 4 w r 2 resistor, 2 m w , 5%, 1 / 4 w r b resistor, 17.8 k w , %, 1 / 4 w r bat resistor, 5.1 w , 5%, 1 / 4 w r d optional. refer to paragraph loop current detector. r dc resistor, 41.2 k w , 5%, 1 / 4 w r fb resistor, 24.3 k w , 1%, 1 / 4 w r rx resistor, 261 k w , 1%, 1 / 4 w r rt resistor, 150 w , 5%, 2 w r sg resistor, 0 w (for v bat = -48v) r t resistor, 523 k w , 1%, 1 / 4 w r tx resistor, 20.0 k w , 1%, 1 / 4 w c bat capacitor, 0.47 m f, 20%, 100 v c dc capacitor, 1.5 m f, 20%, 10 v c hp capacitor, 0.033 m f, 20%, 100v c rt capacitor, 0.39 m f, 20%, 100 v c tc , c rc capacitor, 2200 pf, 20%, 100 v c tisp capacitor, 220 nf, 20%, 100 v r rt r c rt r 2 -5v r d -48v tip ring c v bat tisp u 3 note 1 d 1 k r to other line interfaces ptc note 5 ringing (-48v +90v ) rms k1 k2 ag k1 k2 c hp u 1 + - codec/filter r b r t r rx r tx u 2 r dc c dc + c bat d 3 d 2 r bat -48v -5v r sg c r c c tc +5v 1 r f r f hpt rd dt tipx ringx gnd vcc ringrly vbat rsg hpr vtx vee rsn rdc c1 c2 det e0 n/c 20/15 22/19 23/20 27/21 28/22 2/1 4/2 5/3 notes 2 & 3 7/4 21/16 19/14 18/13 16/12 14/11 13/10 12/9 11/8 9/7 note 4 digital interface r fb note 6
pbl 3766 4-13 a 2 x 900 ohm resistive feed substitu- tes for the active state constant current feed. the following paragraphs describe the pbl 3766 battery feed system in detail. case 1: slic in the active state v trdc < v sgref in the active state c1 = 0 and c2 = 1. in this operating state tip to ring voltages v trdc less than v sgref , cause the block titled saturation guard in figure 12 to be disabled, i.e. its output is equal to zero. for this case circuit analysis yields: 2500 i ldc = r dc + 41700 where i ldc = the constant loop current. i ldc is in amperes for r dc in ohms. r dc = the programming resistance, in ohms, which sets the constant loop current magnitude. when the desired constant loop current is known, r dc is calculated from 2500 r dc = - 41700 i ldc capacitor c dc , connected between the rdc terminal and ground, removes noise and vf signals from the battery feed control loop. c dc is calculated according to 1 11 c dc = + 2 p f dc ? 41700 r dc ? where f dc =5 hz r dc = constant current programming resistance in ohms c dc = filter capacitor in farads case 2: slic in the active state v trdc > v sgref in the active state c1 = 0 and c2 = 1. when the tip to ring dc voltage approaches the v bat supply voltage, the saturation guard block shown in figure 12 is engaged and will limit the two-wire voltage to a small additional increase beyond the saturation guard threshold, v sgref . this leaves a sufficient voltage margin to the v bat supply to maintain distortion free vf transmission through the line drive amplifiers. the saturation guard feature makes on-hook transmission possible in the active state. the tip to ring voltage at which the saturation guard becomes active, v sgref , can be calculated from 510 5 v sgref = 12.5 + 25000 + r sg where v sgref is in volts for r sg in ohms r sg is a resistor connected between terminal rsg and v ee (-5 v). r sg = open circuit yields v sgref = 12.5 v r sg = 0 ohm yields v sgref = 32.5 v the loop voltage, v trdc , as a function of the loop resistance, r l , for v trdc > v sgref is described by 16.66 + 5.0010 5 /(25000 + r sg ) v trdc = r l r l + (r dc + 41700) / 600 from which the open loop voltage (i l = 0) is calculated to 5.0010 5 v trdc = 16.66 + 25000 + r sg for r sg = open circuit, the on-hook tip to ring dc voltage is 16.7 v, which is compatible with v bat in the -24 v to -28 v range. for r sg = 0 ohm, the on-hook tip to ring dc voltage is 36.7 v, which is compatible with v bat in the -42 v to -58 v range. for intermediate battery voltage values, v bat , r sg can be calculated from 5.0010 5 r sg = - 25000 v trdc -16.66 where r sg is in ohms for v trdc in volts v trdc is the open loop tip to ring voltage.let v trdc = |v bat | - 8 v to allow distortion free transmission of a 3.1 v pk vf signal in the on-hook mode. the 8 v margin may be reduced if a vf signal of less than 3.1 vpk is to be transmitted in the on-hook mode. case 3: slic in the stand-by state in the stand-by state c1 = 1 and c2 = 1. with the slic operating in the stand-by, power saving state the tip and ring drive amplifiers are disconnected and a resistive battery feed is engaged. the loop current can be calculated from v bat - 3 v i ldc ? r l + 1800 w where i ldc = loop current r l = loop resistance v bat = battery supply voltage -3 v = voltage drop across internal transistors 1800 w = feed resistance (900 w on the tip side, 900 w on the ring side) pbl 3766 power dissipation and derating the tip to ring short circuit total power dissipation, p shtot , is p shtot = i lsh (|v bat | - i lsh 2r f ) + p onact where i lsh = 2500/(41700 + r dc ) is the short circuit loop current p onact is the active state on-hook dissipa- tion, typically 160 mw v bat = -48v the permissible maximum device dissipation is 1.5 w. the maximum allowable junction temperature is 140 c for normal reliability requirements and 110 c for extreme reliability requirements. the junction temperature is calculated from t j = p shtot ( q jp + q pa ) + t amb , t j < 140 c where q jp = q jp28plcc = q jp22dip is the thermal resistance from junction to all vbat terminals, typically 10 c/w q pa is the thermal resistance from all vbat terminals to ambient. the q pa value will be depend- ent on line-card thermal design. t amb is the ambient temperature in c. loop monitoring functions overview the pbl 3766 slic contains detectors for loop current and ring trip. these two detectors report their status via the shared det output. a triggered detector is indicated by a logic low level at the det output. the detector to be connected to the det output is selected via the control interface c1 and c2. refer to section control inputs for a description of the control interface. enable input e0 sets the det output to either active or high imped- ance state. loop current detector the loop current detector is connected to the det output in the stand-by (c2, c1 = 1, 1) and the active (c2, c1 = 1, 0) states. refer to figure 14. the loop current value, i lthoff , at which the loop current detector changes from indicating on-hook to indicating off-hook is internally programmed to 8.0 ma.
4-14 pbl 3766 output to toggle between the on-hook and off-hook states at the ringing frequency. however, with the telephone off-hook, the det output will be at logic low level for more than half the time. therefore, by sampling the det output, a software routine can discriminate between on-hook and off-hook through examination of the duty cycle. full removal of the ringing frequency from the dt input, while maintaining ringtrip within required time limits (approximately < 100 ms), usually mandates a second order filter rather than the first order shown in figure 15. the software approach minimizes the number of line card components. in the balanced ringing system shown in figure 16, r rt1 and r rt2 are the ringing feed and loop current sensing resistors. with the telephone on-hook, no dc loop current flows to cause a dc voltage drop across resistor r rt1 . voltage divider r 1 , r 2 and r 3 biases the ringtrip comparator input dt to be more positive than v ee during on-hook. with the telephone off- hook during ringing dc loop current will flow, causing a voltage drop across resistor r rt1 , which will make comparator input dt more negative than v ee . this will set the det output to logic low level, indicating ringtrip condition. capacitors c 1 and c 2 filter the ringing voltage at the comparator input. with component values according to figure 16, 20 hz ringing will be attenuated by 20 db and 30 hz ringing will be attenuated by 23 db before reach- ing the dt input. relay driver the pbl 3766 slic incorporates a ring relay driver designed as open emitter with grounded collector (npn) having a current sourcing capability of 50 ma. the relay coil must be connected to a negative voltage |v bat |. an external inductive kick- back clamp diode must be employed to protect the drive transistor. control inputs overview the pbl 3766 slic has two ttl compatible control inputs, c1 and c2. a decoder in the slic interprets the control input conditions and sets up the com- manded operating state. open circuit state (c2, c1 = 0, 0) in the open circuit state the tipx and ringx line drive amplifiers as well as other circuit blocks are powered down. the internally set loop current detector threshold, i lthon , for the off-hook to on- hook transition is 7.3 ma. an external resistor, r d , may be connected from terminal rd to v ee to increase the loop current detector thresholds. when the desired on-hook to off-hook loop current threshold, i lthoff , is known, the r d value is calculated from 1 r d = i lthoff /500 - 1/62500 where r d is in ohms for i lthoff in amperes the off-hook to on-hook loop current detector threshold, i lthon , for the selected r d value is calculated from 11 i lthon = k lthon + ? r d 62500 ? where i lthon is in amperes for r d in ohms. i lthon > 7.3 ma, k lthon = 455 v the on-hook to off-hook loop current detector threshold, i lthoff , for a specific r d value is calculated from 11 i lthoff = k lthoff + ? r d 62500 ? where i lthoff is in amperes for r d in ohms. i lthoff > 8.0 ma, k lthoff = 500 v with a lower voltage battery it may be desirable to decrease the loop current detector thresholds. for more information on this issue, please contact the factory. during dial pulsing the loop current detector is aided by a speed-up circuit, acting on the rdc output at loop closures. the speed-up circuit will charge the c dc capacitor at a more rapid rate than that set by the (c dc r dc 41700)/(r dc + 41700) time constant, resulting in the loop current reaching the detector threshold value faster and therefore minimizing dial pulse distortion. loop current detector - filter capacitor to increase the loop current detector noise immunity, a filter capacitor may be added from terminal rd to ground. a suggested value for c d is r d + 62500 c d = 2 p (r d 62500) f 3db where c d is in farads for r d in ohms f 3db = 500 hz note that c d may not be required if the det output is software filtered. ring trip detector ring trip detection is accomplished by monitoring the two-wire line for presence of dc current while ringing is applied. when the subscriber goes off-hook during ringing, dc loop current starts to flow. the slic ring trip comparator detects this current flow via an interface network. the dt comparator input is connected to pin 23/20. the other comparator input is internally connected to v ee . the result of the comparison is presented at the det output with logic low level indicating off- hook. the ring trip comparator is automatically connected to the det output, when the slic control inputs are set to the ringing state (c2, c1 = 0, 1). when off-hook during ringing is detected, the line card or system controller will proceed to disconnect the ringing source (software ringtrip) by re-setting the control input logic states. alternatively, the det output may be monitored by circuits on the line card, which perform the ringtrip function (hardware ringtrip). the ringing source may be balanced or unbalanced, superimposed on the v bat supply voltage. a ring relay, energized by the slic ring relay driver, connects the ringing source to tip and ring. for unbal- anced ringing systems the loop current sensing resistor, r rt , is placed in series with the return lead to ground. figures 15 and 16 show examples of unbalanced and balanced ringing systems. for either ringing system the ringtrip detection function is based on a polarity change at the inputs of the ringtrip comparator. in the unbalanced case the dc voltage drop across resistor r rt is zero, as long as the telephone remains on-hook. with the telephone off-hook during ringing, dc loop current will flow, causing a voltage drop across r rt . the r rt voltage is applied to the comparator input dt via resistor r 1 . r 2 shifts the voltage level to be compatible with the inverting input v ee reference voltage. c rt removes part of the ac component of the ringing signal. the inverting comparator input is biased at v ee , which is more negative than dt when the telephone is on-hook and is more positive than dt when the telephone goes off-hook during ringing. complete removal of the ringing signal ac component at the dt input is not necessary. some residual ac component at the dt input may, under certain operating conditions, cause the det
pbl 3766 4-15 figure 12. battery feed (c2, c1 = 1, 0; active state). 510 5 v sgref = 12.5 + r sg + 25 k w 3.010 5 v sg = -7.50 e r sg + 25 k w on-hook to off-hook loop current threshold, i lthoff : i lthoff = 8.0 ma for r d ? for i lthoff > 8.0 ma: 1 r d =, i lthoff /k lthoff - 1/62500 k lthoff = 500 v (includes factor k) figure 14. loop current detector. figure 13. pbl 3766 loop feed examples. r sg = 0 ohms v bat = -58 v to -42 v + - 1 + - comp tipx 27/21 ringx 28/22 pbl 3766 rsg 7/4 saturation guard r dc v sg i ldc r l r sg gnd v bat v sg ref c dc i ldc v tr 0.6 16/12 rsn 14/11 rdc 41.7 k w v tr > v sg ref 1 v tr < v sg ref 0 v ee v tr - 2.5 v i ldc 1000 r dc = 21.0 kohms r dc =41.2kohms r dc = 82.5 kohms 0 10 20 30 40 i l 0 500 1000 1500 2000 r l (ohms) (ma) pbl 3766 + - 2-wire interface input decoder mux ring trip comparator tipx 27/21 ringx 28/22 13/10 c1 12/9 c2 11/8 det 9/7 e0 r d c d 62.5 k w - 5v v cc 18/13 vee 22/19 rd 1.25v i ltipx i lringx 2 k i ltipx - i lringx v ee
4-16 pbl 3766 active state (c2, c1 = 1, 0) tipx is the terminal closest to ground potential and sources loop current, while ringx is the more negative terminal and sinks loop current. vf signal transmission is normal. the loop current detector is activated and connected to the det output. stand-by state (c2, c1 = 1, 1) in the stand-by state the line drive amp- lifiers are disconnected. the loop feed is converted to resistive form according to figure 15. example ring trip network, unbalanced ringing. note: ericsson components unbalanced ring trip network pba 3310 contains a two-pole filter. figure 16. example ring trip network, balanced ringing. this causes the slic to present a high impedance to the line. power dissipation is at a minimum. no detectors are active. ringing state (c2, c1 = 0, 1) the ring relay driver, ringrly, is activ- ated and the ring trip comparator is connected to the detector out-put, det . the tipx and ringx terminals are in the high impedance state and signal trans- mission is inhibited. v bat - 3 v i l ? r l + 1800 w where i l = loop current (a) v bat = battery supply voltage (v) r l = loop resistance (ohm) the short circuit loop current (i lsh ) for v bat = -48v is then limited to i lsh ? 25.0 ma. the loop current detector is activated in the stand-by state and is gated to the det output. table 1 summarizes the above description of the control inputs. + - pbl 3766 ring tip v ee k r e rg r 2 c rt r rt v bat dt 23/20 dr to det r 1 ring tip v ee k r dt 23/20 dr to det e rg- tipx 27/21 ringx 28/22 -48v + - r f1 e rg+ protection pbl 3766 r f2 r rt1 150 w r 1 150k w r 2 150k w r 3 3.1m w r rt2 150 w c 1 470nf c 2 470nf -48v
pbl 3766 4-17 enable input (e0) ttl compatible enable input e0 controls the function of the det output. e0, when set to logic level low, enables the det output, which is a collector output with internal pull-up resistor (approx. 15 kohms) to v cc . a det output at logic level low indicates triggered detector condition (loop current above threshold current or telephone off-hook during ringing). a det output at logic level high indicates a non triggered detector condition. e0, when set to logic level high disables the det output; i.e. it appears as a resist- or connected to v cc . table 2 summarizes the above descrip- tion of the enable input. overvoltage protection the pbl 3766 slic must be protected against overvoltages and power crosses. refer to maximum ratings, tipx and ringx terminals for maximum allowable continuous and transient voltages, that may be applied to the slic. the circuit shown in figure 11 utilizes series resistors (r f , r f ) together with a programmable overvoltage protector (e g texas instru- ment tisp pbl1), serving as a secondary protection. the protection network in figure 11 is designed to meet requirements in ccitt k20, table 1. the tisp pbl1 is a dual forward-conducting buffered p-gate overvoltage protector. the protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage, v bat ). as the protection voltage will track the negative supply voltage the overvoltage stress on the slic is minimised. positive overvoltages are clamped to ground by an internal diode. negative overvoltages are initially clamped close to the slic negative supply rail voltage. if sufficient current is available from the overvoltage, then the protector will crow- bar into a low voltage on-state condition, clamping the over-voltage close to ground. a gate decoupling capacitor, c tisp is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. without the capacitor even the low inductance in the track to the v bat supply will limit the current and delay the activation of the thyristor clamp. the fuse resistors r f serve the dual purposes of being non-destructive energy power-up sequence the voltage at pin vbat sets the sub- strate voltage, which must at all times be kept more negative than the voltage at any other terminal. this is to maintain correct junction isolation between devices on the chip. to prevent possible latch-up, the correct power-up sequence is to connect ground and v bat , then other supply voltages and signal leads. should the v bat supply voltage be absent, a diode with a 2 a current rating, connected with its cathode to v ee and anode to v bat , ensures the presence of the most negative supply voltage at the vbat terminals. the v bat voltage should not be applied at a faster rate than ? v bat / ? t = 4 v/ m sec or with a time constant formed by a 5.1 ohm resistor in series with the vbat pin and a 0.47 microfarad capacitor from the vbat pin to ground. one resistor may be shared by several slics. printed circuit board layout care in pcb layout is essential for proper function. the components connecting to the rsn input should be placed in close proximity to that pin, such that no interference is injected into the rsn terminal. a ground plane surrounding the rsn pin is advisable. the c hp capacitor should be placed close to terminals hpt and hpr to avoid un-wanted disturb- ances. table 1. pbl 3766 operating states state slic number c2 c1 operating state active detector det output note 1. 1 0 0 open circuit no active detector logic level high 2 0 1 ringing ring trip detector ring trip status 3 1 0 active loop curr. detector loop current status 4 1 1 stand-by loop curr. detector loop current status note 1. e0 = 0, i.e. the det output is enabled. a logic low level at the det output indicates a triggered detector. table 2. enable input e0 enable state e0 det output status active detector 1 0 active loop current or ring trip detector note 1. 2 1 high impedance none note 2. notes 1. detector selected according to table 1. 2. in the high impedance state the det output appears as a 15 kohms resistor to v cc dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. ericsson components ab offers a series of thick film resistors networks (e g pbr 51-series and pbr 53-series) designed for this application. also devices with a build in resetable fuse function is offered (e g pbr 52- series) including positive temperature coefficient (ptc) resistors, working as resetable fuses, in series with thick film resistors. note that it is important to always use ptc's in series with resistors not sensitive to temperature, as the ptc will act as a capacitance for fast transients and therefore the ability to protect the slic will be reduced. if there is a risk for overvoltages on the v bat terminal on the slic, then this terminal should also be protected. overtemperature protection a ring lead to ground short circuit fault condition, as well as other improper operating modes, may cause excessive slic power dissipation. if junction temperature increases beyond 160 c, the temperature guard will trigger, causing the slic to be set to a high impedance state. in this high impedance state power dissipation is reduced and the junction temperature will return to a safe value. once below 140 c junction temperature the slic is returned back to its normal operating mode and will remain in that state assuming the fault condition has been removed.
4-18 pbl 3766 specifications subject to change without notice. 1522-pbl 3766 uen rev. b ? ericsson components ab september 1997 ericsson components ab s-164 81 kista-stockholm, sweden telephone: (08) 757 50 00 information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson components ab. these products are sold only according to ericsson components ab' general conditions of sale, unless otherwise confirmed in writing. ordering information package temp. range part no. plastic dip 22 pin 0 c to 70 c pbl 3766n plastic dip 22 pin 0 c to 70 c pbl 3766/6n plcc 28 pin 0 c to 70 c pbl 3766qn plcc 28 pin 0 c to 70 c pbl 3766/6qn this product is an original ericsson product protected by us, european and other patents.

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