1 tm fn3146.3 HI-516 16-channel/differential 8-channel, cmos high speed analog multiplexer the hl-516 is a monolithic, dielectrically isolated, high- speed, high-performance cmos analog multiplexer. it offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. the dual function of address input a 3 enables the hl-516 to be user programmed either as a single ended 16-channel multiplexer by connecting ?out a? to ?out b? and using a 3 as a digital address input, or as an 8-channel differential multiplexer by connecting a 3 to the v- supply. the substrate leakages and parasitic capacitances are reduced substantially by using the intersil dielectric isolation process to achieve optimum performance in both high and low level signal applications. the low output leakage current (l d(off) < 100pa at 25 o c) and fast settling (t settle = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. for mil-std-883 compliant parts, request the hl-516/883 data sheet. features ? access time (typical) . . . . . . . . . . . . . . . . . . . . . . . 130ns ? settling time . . . . . . . . . . . . . . . . . . . . . . . . 250ns (0.1%) ? low leakage (typical) -i s(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10pa -i d(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30pa ? low capacitance (max) -c s(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10pf -c d(off) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25pf ? off isolation at 500khz . . . . . . . . . . . . . . . . . . 55db (min) ? low charge injection error . . . . . . . . . . . . . . . . . . . 20mv ? single ended to differential selectable (sds) ? logic level selectable (lls) applications ? data acquisition systems ? precision instrumentation ? industrial control pinout HI-516 (pdip) top view ordering information part number temp. range ( o c) package pkg. no. hi3-0516-5 0 to 75 28 ld pdip e28.6 v+ out b nc in 16/8b in 15/7b in 14/6b in 13/5b in 12/4b in 11/3b in 10/2b in 9/1b gnd v dd /lls a 3 /sds out a in 8/8a in 7/7a in 6/6a in 5/5a in 3/3a in 1/1a enable a 0 a 1 a 2 v- in 4/4a in 2/2a 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 data sheet october 1999 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | copyright ? intersil corporation 2000
2 truth tables HI-516 used as a 16-channel multiplexer or dual 8-channel multiplexer (note 1) use a 3 as digital address input on channel to enable a 3 a 2 a 1 a 0 out a out b l xxxxnonenone h llll1a none h lllh2a none h llhl3a none h llhh4a none hlhll5anone hlhlh6anone h l hhl 7a none h l hhh8a none h hlllnone1b h hllhnone2b hhlhlnone3b hhlhhnone4b h hhl l none5b h hhl hnone6b h hhhl none7b h hhhhnone8b note: 1. for 16-channel single-ended function, tie ?out a? to ?out b?; for dual 8-channel function use the a 3 address pin to select between mux a and mux b, where mux a is selected with a 3 low. HI-516 used as a differential 8-channel multiplexer a 3 connected to v- supply on channel to enable a 2 a 1 a 0 out a out b l x x x none none hlll1a1b hllh2a2b hlhl3a3b hlhh4a4b hhll5a5b hhlh6a6b hhhl7a7b h hhh 8a 8b HI-516
3 functional block diagram a 3 decode a 3 qq hhl llh v- l l a 3 decoder n p n p in 1a out a in 8a n p n p in 1b out b in 8b v dd /lls multiplexer switches input buffer and decoders q q en a 0 a 1 a 2 a 3 decoder decoder HI-516
4 absolute maximum ratings thermal information v+ to v- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33v analog signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v in , v out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v-) -2v to (v+) +2v digital input voltage: ttl levels selected (v dd /lls pin = gnd or open) v a0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6v to +6v v a3/sds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v-) -2v to (v+) +2v cmos levels selected (v dd /lls pin = v dd ) v a0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2v to (v+) +2v operating conditions temperature ranges HI-516-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 2) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 maximum junction temperature plastic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 2. ja is measured with the component mounted on an evaluation pc board in free air. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v, v al (logic level low) = 0.8v; v dd /lls = gnd. (note 3) unless otherwise specified parameter test conditions temp ( o c) -5 units min typ max dynamic characteristics access time, t a 25 - 130 175 ns full - - 225 ns break-before-make delay, t open 25 10 20 - ns enable delay (on), t on(en) 25 - 120 175 ns enable delay (off), t off(en) 25 - 140 175 ns settling time to 0.1% 25 - 250 - ns to 0.01% 25 - 800 - ns charge injection error note 6 25 - - 20 mv off isolation note 7 25 55 - - db channel input capacitance, c s(off) 25 - - 10 pf channel output capacitance, c d(off) 25 - - 25 pf digital input capacitance, c a 25 - - 10 pf input to output capacitance, c ds(off) 25 - 0.02 - pf digital input characteristics input low threshold, v al (ttl) note 3 full - - 0.8 v input high threshold, v ah (ttl) note 3 full 2.4 - - v input low threshold, v al (cmos) note 3 full - - 0.3v dd v input high threshold, v ah (cmos) note 3 full 0.7v dd --v input leakage current, i ah (high) full - - 1 a HI-516
5 input leakage current, i al (low) full - - 25 a analog channel characteristics analog signal range, v in note 4 full -15 - +15 v on resistance, r on note 5 25 - 620 750 ? full - - 1,000 ? off input leakage current, l s(off) 25 - 0.01 - na full - - 50 na off output leakage current, i d(off) 25 - 0.03 - na full - - 100 na on channel leakage current, i d(on) 25 - 0.04 - na power supply characteristics power dissipation, p d full - - 900 mw i+, current v en = 2.4v full - - 30 ma i-, current full - - 30 ma notes: 3. v dd /lls pin = open or grounded for ttl compatibility. v dd /lls pin = v dd for cmos compatibility. 4. at temperatures above 90 o c, care must be taken to assure v in remains at least 1v below the v supply for proper operation. 5. v in = 10v, i out = -100 a. 6. v in = 0v, c l = 100pf, enable input pulse = 3v, f = 500khz. 7. v en = 0.8v, v in = 3v rms , f = 500khz, c l = 40pf, r l = 1k, pin 3 grounded. electrical specifications supplies = +15v, -15v; v ah (logic level high) = 2.4v, v al (logic level low) = 0.8v; v dd /lls = gnd. (note 3) unless otherwise specified (continued) parameter test conditions temp ( o c) -5 units min typ max HI-516
6 test circuits and waveforms v dd /lls = gnd, unless otherwise specified. figure 1. on resistance test circuit figure 2. i d(off) test circuit (note 8) figure 3. i s(off) test circuit (note 8) figure 4. i d(on) test circuit (note 8) figure 5a. measurement points figure 5b. test circuit note: 8. two measurements per channel: 10v and 10v. (two measurements per device for i d(off) 10v and 10v). figure 6. access time out in v in v 2 i out 100 a r on = v 2 100 a 10v out 10v en 0.8v 10v a i d(off) out en 10v a i s(off) 0.8v 10v out 10v en 2.4v 10v a i d(on) 50% 3.5v 10% +10v 0v output -10v t a address drive (v a ) 10v +15v v+ v- in 1 in 2-15 in 16 out b a 0 en a 1 10 50 k ? pf -15v a 3 /sds a 2 50 ? v a 2.4v gnd v dd /lls 10v out a HI-516
7 figure 7a. measurement points figure 7b. test circuit figure 7. break-before-make delay figure 8a. measurement points figure 8b. test circuit figure 8. enable delays figure 9a. measurement points figure 9b. test circuit ? v o is the measured voltage error due to charge injection. the error in coulombs is q = c l x ? v o . figure 9. charge injection test circuits and waveforms v dd /lls = gnd, unless otherwise specified. (continued) 50% 50% 3.5v 0v output address drive (v a ) t open s 1 on s 16 on +5v +15v v+ v- in 1 in 2-15 in 16 outb a 0 en a 1 12.5pf 800 v out -15v a 3 a 2 50 ? v a 2.4v gnd v dd /lls ? outa 3.5v 0v output t off(en) 50% 90% t on(en) 10% 50% enable drive (v a ) 0v +10v +15v v+ v- in 1 in 2-16 outa a 0 en a 1 12.5pf 800 -15v a 3 a 2 50 v a gnd v dd /lls ? ? v out 0v ? v o 3.0v v a v out 2.4v +15v v- a 0 , a 1 , a 2 , en -15v gnd v dd /lls a 3 /sds in out a or b v out cl = 100pf v+ v a HI-516
8 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com die characteristics die dimensions: 2250 m x 3720 m x 485 m metallization: type: cual thickness: 16k ? 2k ? passivation: type: nitride over silox nitride thickness: 3.5k ? 1k ? silox thickness: 12k ? 2k ? worst case current density: 1.64 x 10 5 a/cm 2 metallization mask layout HI-516 (1) +v (2) out b enable (18) a 0 (17) a 2 (15) a 3 /sds (14) a 1 (16) v dd /lls (13) gnd (12) in 1/1a (19) in 2/2a (20) in 3/3a (21) in 4/4a (22) in 5/5a (23) in 6/6a (24) in 7/7a (25) in 8/8a (26) (28) out a (27) -v (5) in 14/6b (4) in 15/7b (3) in 16/8b (10) in 9/1b (9) in 10/2b (8) in 11/3b (7) in 12/4b (6) in 13/5b HI-516
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