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1 dual ultra low noise wideband amplifiers el5236, el5237 the el5236 is a dual, low noise, 300mhz gain bandwidth product voltage feedback op am p (vfa). the minimum operating gain of 2 comes with a very low input noise voltage of 1.5nv/ hz and 1.8pa/ hz current noise. this makes this dual device ideal for low noise differential active filters, dual channel photodiode detectors, differential receivers with equalization, and any other wideband, high dynamic range application. each channel requires only 5.8ma on a 6v supply. minimal performance change over a supply range of 2.5v to 6v is provided (or single +5v ->+1 2v). where system power is paramount, the el5237 dual with disable allows the amplifiers to be separately powered down to less than 20a/ch. the 8 ld dual el5236 is available in the industry standard pinout so-8 or space saving msop-8. the 10 ld el5237 is available in an msop-10. features ? bandwidth (-3db) of 250mhz @ a v = +2 ? gain bandwidth product: 300mhz ?voltage noise: 1.5nv/ hz ?current noise: 1.8pa/ hz ?i s : 5.8ma/channel ? 100ma i out ? fast enable/disable (el5237 only) ? 2.5v to 6v supply range operation applications ? differential adc driver ? complementary dac output driver ? ultrasound input amplifiers ? agc and pll active filters ?transimpedance designs related products ? isl28290 , dual, 80mhz, 1nv/ hz ? isl55290 , dual, 700mhz, 1.1nv/ hz - + - + 77 77 25 25 1.27nf 1.27nf +3.3v 255 200 100 100 270pf 270pf 130pf 130pf 255 isl5861ib low power 12-bit dac 130msps 0 to 20ma 20ma to 0 - + - + 215 422 215 4.66k 337 422 180pf 180pf 0.1f +5v 39pf 30pf 30pf 39pf 422 422 +5v +5v -5v -5v 0v centered 4v p-p differential ? isl5236 ? isl5236 ? isl5236 ? isl5236 figure 1. typical application low power, low noise, differential dac output trans impedance with a 5th order, 5mhz, butterworth filter caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. march 31, 2011 fn7833.0
el5236, el5237 2 fn7833.0 march 31, 2011 pin configurations el5236 (8 ld soic, 8 ld msop) top view el5237 (10 ld msop) top view vs- vs+ vina+ vina- vouta voutb vinb- vinb+ 1 2 3 4 8 7 6 5 - + - + vinb+ vina- vs- ena vina+ vouta vs+ vinb- enb voutb 1 2 3 4 10 9 8 7 5 6 - + - + pin descriptions el5236 (8 ld soic and 8 ld msop) el5237 (10 ld msop) pin name description 1 9 vouta output of op amp a 2 10 vina- inverting input of op amp a 31vina+non-inverting input of op amp a 4 3 vs- negative supply voltage 55vinb+non-inverting input of op amp b 6 6 vinb- inverting input of op amp b 7 7 voutb output of op amp b 8 8 vs+ positive supply voltage -2ena low enable op amp a -4enb low enable op amp b
el5236, el5237 3 fn7833.0 march 31, 2011 ordering information part number (notes 1, 2, 3) part marking temp range (c) package (pb-free) pkg. dwg. # el5236iyz bbbsa -40 to +85 8 ld msop (3.0mm) m8.118a EL5236ISZ 5236isz -40 to +85 8 ld soic (150 mil) m8.15e el5237iyz bbbta -40 to +85 10 ld msop (3.0mm) m10.118a notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for el5236 , el5237 . for more information on msl please see techbrief tb363 .
el5236, el5237 4 fn7833.0 march 31, 2011 important note: all parameters having min/max specifications are guaranteed. typ values are for information purposes only. unles s otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a absolute maximum ratings (t a = +25c) thermal information supply voltage between v s + and v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s - -0.3v, v s +0.3v maximum continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . 40ma maximum die temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000v machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000v latch up (class 2, level a) . . . . . . . . . . . . . . . . . . . . . . . . .passed at +85c thermal resistance (typical, notes 4, 5) ja (c/w) jc (c/w) 8 ld msop package. . . . . . . . . . . . . . . . . . . 160 60 10 ld msop package . . . . . . . . . . . . . . . . . 160 60 8 ld soic package. . . . . . . . . . . . . . . . . . . . 125 90 storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications v s + = +6v, v s - = -6v, r l = 500 ? , r f = r g = 620 ? , v cm = 0v, and t a = +25c, unless otherwise specified. parameter symbol conditions min (note 6) typ max (note 6) unit dynamic performance gain bandwidth product gbwp 300 mhz -3db bandwidth bw1 a v = -1 175 mhz -3db bandwidth bw2 a v = +2 250 mhz 2nd harmonic distortion hd2 f = 1mhz, v o = 2v p-p , r l = 500 ? -110 dbc r l = 100 ? -105 dbc 3rd harmonic distortion hd3 f = 1mhz, v o = 2v p-p , r l = 500 ? -110 dbc r l = 100 ? -108 dbc slew rate sr v o = 2.5v square wave, measured 25% to 75% 90 128 v/s settling to 0.1% (a v = +2) t s a v = +2, v o = 1v 20 ns voltage noise e n f = 100khz 1.5 nv/ hz current noise i n f = 100khz 1.8 pa/ hz input characteristics input offset voltage v os v cm = 0v -3 0.1 3 mv average offset voltage drift tcv os -0.3 v/c input bias current i b v cm = 0v 6.5 9 a input offset current i os -500 50 500 na input impedance r in 12 m ? input capacitance c in 1.6 pf common-mode input range cmir -4.5 +5.5 v common-mode rejection ratio cmrr for v in from -4.4v to 5.4v 90 110 db open-loop gain a vol v o = 2.5v 75 80 db
el5236, el5237 5 fn7833.0 march 31, 2011 output characteristics output swing high v oh r l = 500 ? 4.8 4.9 v r l = 150 ? 4.5 4.7 v output swing low v ol r l = 500 ? -4.8 -4.7 v r l = 150 ? -4.6 -4.5 v short circuit current i sc r l = 10 ? (sourcing and sinking) 110 160 ma power supply performance power supply rejection ratio psrr v s is moved from 5.4v to 6.6v 75 85 db supply current enable (per amplifier) i s on no load 5.8 7 ma supply current disable (per amplifier) (el5237) i s off +v s 220a -v s -26 -16 a operating range v s single supply 5 12 v enable (el5237) enable time t en 125 ns disable time t dis 336 ns en pin input high current i ihen en = v s +1720a en pin input low current i ilen en = v s --10.1a en pin input high voltage for power-down v ihen v s + -1 v en pin input low voltage for power-up v ihen v s - +3 v electrical specifications v s + = +6v, v s - = -6v, r l = 500 ? , r f = r g = 620 ? , v cm = 0v, and t a = +25c, unless otherwise specified. (continued) parameter symbol conditions min (note 6) typ max (note 6) unit electrical specifications v s + = +2.5v, v s - = -2.5v, r l = 500 ? , r f = r g = 620 ? , v cm = 0v, and t a = +25c, unless otherwise specified. parameter symbol conditions min (note 6) typ max (note 6) unit dynamic performance gain bandwidth product gbwp 300 mhz slew rate sr v o = 1.25v square wave, measured 25% to 75% 80 110 v/s settling to 0.1% (a v = +2) t s a v = +2, v o = 1v 25 ns -3db bandwidth bw1 a v = -1 175 mhz -3db bandwidth bw2 a v = +2 250 mhz 2nd harmonic distortion hd2 f = 1mhz, v o = 2v p-p , r l = 500 -94 dbc 3rd harmonic distortion hd3 f = 1mhz, v o = 2v p-p , r l = 500 -100 dbc voltage noise e n f = 100khz 1.5 nv/ hz current noise i n f = 100khz 1.7 pa/ hz input characteristics input offset voltage v os v cm = 0v -3 -0.2 +3 mv average offset voltage drift tcv os -0.3 v/c input bias current i b v cm = 0v 6.5 9 a input offset current i os -500 50 500 na
el5236, el5237 6 fn7833.0 march 31, 2011 input impedance r in 2m input capacitance c in 1.6 pf common-mode input range cmir -1.3 +1.7 v common-mode rejection ratio cmrr for v in from -1.3v to +1.7v 85 105 db open-loop gain a vol v o = 1.25v 70 75 db output characteristics output swing high v oh r l = 500 ? 1.5 1.6 v r l = 150 ? 1.4 1.5 v output swing low v ol r l = 500 ? -1.45 -1.35 v r l = 150 ? -1.37 -1.25 v short circuit current i sc r l = 10 ? (sourcing and sinking) 60 75 ma power supply performance power supply rejection ratio psrr v s is moved from 2.25v to 2.75v 75 80 db supply current enable (per amplifier) i s on no load 5.7 7 ma supply current disable (per amplifier) (el5237) i s off +v s 220a -v s -21 -16 a operating range v s single supply 5 12 v enable (el5237) enable time t en 125 ns disable time t dis 336 ns en pin input high current i ihen en = v s +1620a en pin input low current i ilen en = v s --10.1a en pin input high voltage for power-down v ihen v s + -1 v en pin input low voltage for power-up v ihen v s - +3 v note: 6. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications v s + = +2.5v, v s - = -2.5v, r l = 500 ? , r f = r g = 620 ? , v cm = 0v, and t a = +25c, unless otherwise specified. (continued) parameter symbol conditions min (note 6) typ max (note 6) unit
el5236, el5237 7 fn7833.0 march 31, 2011 typical performance curves v s = 6v, t a +25c, a v = +2v/v, r f = 402 ? , r load = 500 ? , unless otherwise specified. figure 2. non-inverting small signal frequency reponse vs gain figure 3. inverting small signal frequency response figure 4. non-inverting large signal response figure 5. inve rting large signal response figure 6. input spot noise figure 7. input of fset voltage and current vs temperature 1m 10m 100m 1g -9 -6 -3 0 3 frequency (hz) normalized gain (db) a v = 2 a v = 4 a v = 6 a v = 8 1m 10m 100m 1g -9 -6 -3 0 3 frequency (hz) normalized gain (db) a v = -1 a v = -2 a v = -8 a v = -4 1m 10m 100m 1g -6 -3 0 3 6 9 frequency (hz) gain (db) 100mv p-p 500mv p-p 1v p-p 2v p-p 1m 10m 100m 1g -6 -3 0 3 6 9 frequency (hz) gain (db) 500mv p-p 2v p-p 1v p-p 100mv p-p 1 10 100 100 1k 10k 100k 1m 10m frequency (hz) spot voltage (nv/ hz) and current noise (pa/ hz) e n i n -10 10 30 50 70 90 110 130 150 0 20 40 60 80 100 120 140 160 180 200 -50 0 50 100 150 200 temperature (c) input offset voltage (v) input offset current (na) ios vio
el5236, el5237 8 fn7833.0 march 31, 2011 figure 8. non-inverting hd2 and hd3 vs ga in figure 9. inverting hd2 and hd3 vs gain figure 10. non-inverting hd2 and hd3 vs output v p-p figure 11. inverting hd2 and hd3 vs output v p-p figure 12. non-inverting hd2 and hd3 vs r load figure 13. inverting hd2 and hd3 vs r load typical performance curves v s = 6v, t a +25c, a v = +2v/v, r f = 402 ? , r load = 500 ? , unless otherwise specified. (continued) -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 1m 10m frequency (hz) harmonic distortion (dbc) a v = +2 2nd hd(dbc) a v = +6 2nd hd(dbc) a v = +4 2nd hd(dbc) a v = +8 3rd hd(dbc) a v = +8 2nd hd(dbc) a v = +4 3rd hd(dbc) a v = +2 3rd hd(dbc) a v = +6 3rd hd(dbc) 2v opp -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 frequency (hz) harmonic distortion (dbc) a v = -1 2nd hd(dbc) a v = -1 3rd hd(dbc) a v = -8 3rd hd(dbc) a v = -8 2nd hd(dbc) a v = -4 3rd hd(dbc) a v = -2 3rd hd(dbc) a v = -4 2nd hd(dbc) a v = -2 2nd hd(dbc) 2v opp 1m 10m -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 v o = 2v p-p 2nd hd(dbc) v o = 500mv p-p 3rd hd(dbc) v o = 1v p-p 2nd hd(dbc) v o = 2v p-p 3rd hd(dbc) v o = 1v p-p 3rd hd(dbc) v o = 500mv p-p 2nd hd(dbc) frequency (hz) harmonic distortion (dbc) 1m 10m -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 frequency (hz) harmonic distortion (dbc) v o = 500mv p-p 3rd hd(dbc) v o = 500mv p-p 2nd hd(dbc) v o = 2v p-p 3rd hd(dbc) v o = 2v p-p 2nd hd(dbc) v o = 1v p-p 2nd hd(dbc) v o = 1v p-p 3rd hd(dbc) 1m 10m -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 frequency (hz) harmonic distortion (dbc) r l = 500 ? 2nd hd(dbc) r l = 1k ? 2nd hd(dbc) r l = 200 ? 3rd hd(dbc) r l = 200 ? 2nd hd(dbc) r l = 500 ? 3rd hd(dbc) r l = 100 ? 3rd hd(dbc) r l = 100 ? 2nd hd(dbc) r l = 1k ? 3rd hd(dbc) 1m 10m 2v opp -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 frequency (hz) harmonic distortion (dbc) r l = 100 ? 3rd hd(dbc) r l = 100 ? 2nd hd(dbc) r l = 1k ? 2nd hd(dbc) r l = 200 ? 3rd hd(dbc) r l = 1k ? 3rd hd(dbc) r l = 500 ? 3rd hd(dbc) r l = 200 ? 2nd hd(dbc) r l = 500 ? 2nd hd(dbc) 1m 10m 2v opp
el5236, el5237 9 fn7833.0 march 31, 2011 figure 14. non-inverting large and small signal step response figure 15. inverting large and small signal step response figure 16. non-inverting overdrive recove ry figure 17. inverting overdrive recovery figure 18. differential gain and phase vs video loads figure 19. channel-to-channel isolation typical performance curves v s = 6v, t a +25c, a v = +2v/v, r f = 402 ? , r load = 500 ? , unless otherwise specified. (continued) -2.50 -2.00 -1.50 -1.00 -0.5 0 0.50 1.00 1.50 2.00 2.50 step response 20ns/div 100mv/div 200mv 1v 2v -2.50 -2.00 -1.50 -1.00 -0.50 0 0.50 1.00 1.50 2.00 2.50 step response 20ns/div 100mv/div 200mv 1v 2v vs = 6v av = 2 2v/div av = -2 2v/div 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 1234 number of 150 ? loads diff gain (%), diff phase () diff phase diff gain -160 -140 -120 -100 -80 -60 -40 -20 0 1e+05 1e+06 1e+07 1e+08 1e+09 channel-to-channel isolation (db) frequency (hz) a===>b rl = 100 ? a===>b rl = 200 ? a===>b rl = 500 ? power off a===>b rl = 500 ? a===>b rl = 50 ?
el5236, el5237 10 fn7833.0 march 31, 2011 figure 20. open loop gain figure 21. cmrr and psrr figure 22. supply current and output current over-temperature figure 23. closed loop output impedance vs gain figure 24. non-inverting turn on and turn off dela y figure 25. inverting turn on and turn off delay typical performance curves v s = 6v, t a +25c, a v = +2v/v, r f = 402 ? , r load = 500 ? , unless otherwise specified. (continued) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 -20 -10 0 10 20 30 40 50 60 70 80 90 1k 10k 100k 1m 10m 100m 1g frequency (hz) open loop gain (db) p h a s e ( ) gain phase 0 20 40 60 80 100 120 100k 1m 10m 100m 1g p s r r ( d b ) frequency (hz) cmrr psrr- psrr+ 100 110 120 130 140 150 160 170 180 190 200 0 2 4 6 8 10 12 14 16 18 20 -50 0 50 100 150 temperature (c) v s = 6v supply current (ma) output current (ma) output current supply current 0.001 0.01 0.1 1 10 100 1k 10k 100k 1m 10m 100m frequency (hz) impedance ( ? ) 18db 6db 12db 15.6db
el5236, el5237 11 fn7833.0 march 31, 2011 figure 26. non-inverting small signal response vs supply voltage figure 27. inverting small signal response vs supply voltage figure 28. non-inverting hd2 and hd3 vs supply voltag e figure 29. inverting hd2 and hd3 vs supply voltage figure 30. supply current vs supply voltage figur e 31. common mode input range and output swing vs supply voltage typical performance curves v s = 6v, t a +25c, a v = +2v/v, r f = 402 ? , r load = 500 ? , unless otherwise specified. (continued) 1m 10m 100m 1g -6 -3 0 3 6 9 frequency (hz) normalized gain (db) v s = 2.5v v s = 4v v s = 3v v s = 5v v s = 3v -9 -6 -3 0 3 frequency (hz) normalized gain (db) v s = 2.5v v s = 5v v s = 3v v s = 4v v s = 6v 1m 10m 100m 1g -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 frequency (hz) normalized gain (db) v s = 2.5v 3rd hd(dbc) v s = 5v 3rd hd(dbc) v s = 2.5v 2nd hd(dbc) v s = 6v 2nd hd(dbc) v s = 5v 2nd hd(dbc) 1m 10m 2v opp -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 frequency (hz) normalized gain (db) v s = 2.5v 3rd hd(dbc) v s = 5v 2nd hd(dbc) v s = 6v 3rd hd(dbc) v s = 5v 3rd hd(dbc) v s = 2.5v 2nd hd(dbc) 1m 10m 2v opp 5.4 5.5 5.6 5.7 5.8 5.9 6.0 6.1 6.2 6.3 6.4 0 20 40 60 80 100 120 140 160 180 200 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output current (ma) supply current (ma) +i o (ma) -i o (ma) i q (ma) supply voltage (v) -6 -4 -2 0 2 4 6 23456 supply voltage (v) voltage range (v) input (+v) output (+v) output (-v) input (-v)
el5236, el5237 12 fn7833.0 march 31, 2011 typical performance curves v s = 2.5v, t a +25c, a v = +2v/v, r f = 402 ? , r load = 500 ? , unless otherwise specified. figure 32. non-inverting small signal response vs gain figure 33. inverti ng small signal response vs gain figure 34. non-inverting large signal response figure 35. inverting large signal response figure 36. input spot noise voltage and current 1m 10m 100m 1g -9 -6 -3 0 3 frequency (hz) normalized gain (db) a v = 2 a v = 4 a v = 6 a v = 8 -9 -6 -3 0 3 frequency (hz) normalized gain (db) a v = 1 a v = -2 a v = -8 a v = -4 1m 10m 100m 1g -9 -6 -3 0 3 6 9 12 15 frequency (hz) gain (db) 100mv p-p 500mv p-p 1v p-p 2v p-p 1m 10m 100m 1g gain (db) 500mv p-p 2v p-p 1v p-p 100mv p-p -6 -3 0 3 6 9 12 15 frequency (hz) 1m 10m 100m 1g 1 10 100 100 1k 10k 100k 1m 10m frequency (hz) spot voltage (nv/ hz) and current noise (pa/ hz) e n i n
el5236, el5237 13 fn7833.0 march 31, 2011 applications information non-inverting operation the dual wideband el5236 (and el 5237 with disable) provides a very power efficient low gain optimized amplifier solution using a slightly decompensated vfa design. this gives a lower input referred voltage noise and higher slew rate at the very low 5.6ma/ch nominal supply current. unity gain operation is possible with external compen sation but most high speed designs are at a gain > 1. figure 37 shows the gain of +2v/v configuration used for most of the characterization curves. as most lab equipment is expecting a 50 ? termination at the source, the non-inverting input and output show a 50 ? termination. the 402 ? feedback and gain resistors give a good compromi se between several parasitic factors. these include the added noise of those resistors, loading effects, and to minimize the loss of phase margin back to the inverting node. a wide range of values can be used, where lower values will reduce noise with more output loading and higher values will start to dominate the output noise and introduce more phase margin loss into th e loop. the el5236 macromodel is a very good tool to predict the impact of these different values. tests over gain (figures 2, 8) held the feedback r = 402 ? and varied the rg element to achieve different gain settings. inverting operation figure 38 shows the inverting gain configuration used for the inverting mode characterization curves. in this case, the feedback resistor is held at 402 ? while both the rg and rt elements are adjusted. rg is adjusted to get different gains while rt is adjusted to retain the input impedance at 50 ? . this does give a different loop gain (and hence bandwidth vs. gain) profile over gain as reflected in figure 39. in a system application, rm can be used to match the source impedance to get bias current cancellation. for the lowest noise, include a de-coupling capacitor across that resistor (0.1f in figure 38). getting the lowest noise a very low noise op amp like th e el5236 will only deliver a low output noise if the resistor values used to implement the design add a noise contribution that is also low. figure 39 shows the full noise model for a non-inverting configuration. each of these voltage and current noise terms will contribute to an output noise power. getting the gains for each, then squaring, summing, and then taking the square root will give the combined output spot noise using the model of figure 39 as shown in equation 1: the source resistor shows up combining with the op amps non-inverting input voltage noise to give a total non-inverting input noise that then gets the full noise gain to the output. as a point of reference, solve for wh ere those noise terms equal the contribution from just the op amp voltage noise. this is given in equation 2 and evaluating this for the 1.5nv and 1.8pa input noise terms gives rs = 136 ? . similarly, compare the output noise due to just the non-inverting input noise voltage to the terms on the inverting node in equation 1. solving for equality there (to get a maximum rf value to limit the inverting side noise contributions at the output), gives equation 3. evaluating this for 1.5nv and 1.8pa input noise terms at a ng = 2 gives an rf = 272 ? . this simplified analysis indicates the 402 ? used for the non-inverting characterization is already starting to dominate the output noise at a gain of 2. going up in gain, with a fixed rf = 402 ? , will quickly make those input side terms dominant. - + 50 402 402 rg 50 +6v ? isl5236 vo vi -6v rf 50 load 50 source rg rf vi vo + = 1 figure 37. g = +2v/v ch aracterization circuit - + rm 402 402 rg 50 +6v ? isl5236 vo vi -6v rf 50 load 50 source 0.1f 57.6 rg rf vi vo ? = figure 38. g = -1v/v characterization circuit - + rg e o rs rf in en i i ktrs 4 ktrs 4 ktrs 4 rg rf noisegain + = 1 figure 39. op amp non-inverting noise analysis circuit () ( ) () () () ng ktr r i ng ktr r i e e f f i s s n n o 4 4 2 2 2 2 + + ? + + = (eq. 1) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 1 2 1 2 2 2 kt i e i kt r n n n s (eq. 2) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = 1 2 1 2 2 2 kt i e ng i kt r n n n f (eq. 3)
el5236, el5237 14 fn7833.0 march 31, 2011 this approximate analysis is inte nded to show the importance of working with relatively low resistor values if the low noise of the el5236 is to be retained. it also shows why, with an inverting configuration, it is important to either keep a low impedance on the non-inverting input and/or add a noise shunting capacitor across it. dc precision the el5236 offers extremely low input offset voltage and input offset current. to take full advantage of the very low offset current (<500na), the source resi stance looking out of the two inputs must be matched. figure 40 shows the output dc offset analysis circuit. if rs = rf||rg is imposed on the design, the total output offset will be given by equation 4: putting in the specified worst case limits of 3mv for the offset voltage and 500na for the offset current into a ng = 2 and rf = 402 ? condition would give an output dc error envelope of 6.2mv. this is assuming the rs is set to 201 ? . to change figure 37 to a 201 ? rs, add a 175 ? in series with the v+ node from the 50 ? termination. this will reduce the output offset induced from the ib terms to the 0.2mv part of the 6.0mv computed above ? at the cost of a bit higher input noise. a second issue would be the tempco of the output offset voltage. to the extent that the output is dominated by the offset voltage term, its drift will dominate. the specified typical input vos drift is -300nv/c. continuing this example, that would give a typical output drift of -0.6v/c. over a +50c ambient range, this would map to only a 30v shift in the output offset voltage. active filter designs being a low gain stable wideband vfa op amp, the el5236 is particularly suited to differential i/o active filters, as shown in figure 1. that relatively complex example gives a 5 th order butterworth filter as part of an output stage interface to a complementary dac output current. these dac output stages generate both a common mode vo ltage and a differential signal at the termination resistors to ground. the design of figure 1 gets the real pole as part of that termination then implements the two complex pole pairs as an skf stage followed by an mfb stage. this gives much better stop band rejection using the 2 nd mfb stage and allows an easy place to introduce a common mode level shift to remove the dac output common mode. this was used to return the final output to be a ground centered differential signal. the mfb desi gn of the output stage uses a feedback capacitor inside the filt er that normally expects a unity gain stable op amp for impl ementation. adding the two capacitors to ground on the inverting inputs of this stage shapes the noise gain up at higher freq uencies holding this stage stable. simpler designs are possible as shown in figure 41. this is a single stage gain of 2 butterworth filter with a 20mhz cutoff. even with the 300mhz gain bandwidth product of th e el5236, this is a fairly high frequency filter to attempt with this relatively limited amplifier bandwidth margin. in this case, the rf = rg = 649 ? is also being set to get bias current cancellation for improved output dc precision along with the necessary gain of 2 setting for the design. this design was produced using the intersil online active filter designer which includes an amplifier bandwidth adjustment in the r1 and r2 values. it is a general active filter tool tailored to the available precision and high speed op amps from intersil. it is available at the following link: http://web.transim.com/isimf ilter/pages/designreq.aspx as shown in the simulated vs. ideal curves of figure 42, the design is doing a very good job of matching the ideal response through 80mhz. all skf filters deviate from the ideal roll-off at higher frequencies due to the increase in output impedance as the amplifier bandwidth is approached. - + rg v os rs rf i b v io i b ? isl5236 figure 40. output dc offset analysis circuit f os io os r i ng v v * ? = (eq. 4) - + 97.6 649 649 rg 226 +vs ? isl5236 vo vi -vs rf 47pf 47pf figure 41. gain = +2v/v, 20mhz 2nd order butterworth low pass active filter 10 5 0 -5 -10 -15 -20 gain (db) 1e7 1e8 frequency (hz) figure 42. simulated vs ideal filter response comparison
el5236, el5237 15 fn7833.0 march 31, 2011 shutdown operation (el5237 only) el5237 has the feature to enable or disable each amplifier to save power when not in use. pulling low will enable the amplifier and pulling high will disable the amplifier. refer to the ?electrical specifications? tables for appropriate values to use. power supply de-coupling and layout short feedback loop is essentia l in the layout of the op amp board as well as minimizing the capacitance around the inverting/non-inverting input pins and output pins. a 0.1f ceramic capacitor placed close to the supply pins allows for proper supply de-coupling.
el5236, el5237 16 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7833.0 march 31, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: el5236 , el5237 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 31, 2011 fn7833.0 initial release
el5236, el5237 17 fn7833.0 march 31, 2011 package outline drawing m8.118a 8 lead mini small outlin e plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop 8l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to jedec mo-187-aa 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view side view 2 included. included. gauge plane 33 0.25 c a b b 0.10 c 0.08 c a b a 0.25 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 4.40 3.00 5.80 0.65 3.00.1 4.90.15 1.40 0.40 0.65 bsc pin# 1 id detail "x" 0.33 +0.07/ -0.08 0.10 0.05 3.00.1 1 2 8 0.860.09 seating plane and amse y14.5m-1994.
el5236, el5237 18 fn7833.0 march 31, 2011 package outline drawing m10.118a (jedec mo-187-ba) 10 lead mini small outline plastic package (msop) rev 0, 9/09 plastic or metal protrusions of 0.15mm max per side are not dimensions ?d? and ?e1? are measured at datum plane ?h?. this replaces existing drawing # mdp0043 msop10l. plastic interlead protrusions of 0.25mm max per side are not dimensioning and tolerancing conform to amse y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "x" side view 1 typical recommended land pattern top view gauge plane 33 0.25 0.25 c a b a b 0.10 c 0.08 c a b 0.55 0.15 0.95 bsc 0.18 0.05 1.10 max c h 5.80 3.00 4.40 0.50 0.30 1.40 pin# 1 id 1 2 10 detail "x" seating plane 0.5 bsc 0.23 +0.07/ -0.08 3.0 0.1 4.9 0.15 3.0 0.1 0.10 0.05 0.86 0.09 side view 2 included. included.
el5236, el5237 19 fn7833.0 march 31, 2011 package outline drawing m8.15e 8 lead narrow body small outline plastic package rev 0, 08/09 unless otherwise specified, tolerance : decimal 0.05 the pin #1 identifier may be either a mold or mark feature. interlead flash or protrusions shall not exceed 0.25mm per side. dimension does not include interlead flash or protrusions. dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: detail "a" side view ?a typical recommended land pattern top view a b 4 4 0.25 a mc b c 0.10 c 5 id mark pin no.1 (0.35) x 45 seating plane gauge plane 0.25 (5.40) (1.50) 4.90 0.10 3.90 0.10 1.27 0.43 0.076 0.63 0.23 4 4 detail "a" 0.22 0.03 0.175 0.075 1.45 0.1 1.75 max (1.27) (0.60) 6.0 0.20 reference to jedec ms-012. 6. side view ?b?

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