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DD-03296 96-channel discrete-to-digital interface description the DD-03296 device is a 96-channel discrete-to-digital interface with uni- versal hlrf-isolated inputs that accept 28 v/open, open/gnd and 28 v/gnd signals. the output is an addressable 8- or 16-bit tri-state port, selectable for channel data, status, bounce, built-in self-test (bist) and major fault, and is compatible with ttl logic. applications the DD-03296 is specifically designed to address built-in self-test autonomy, fault isolation and toler- ance. because of its high reliability and low cost, these features enable the dd- 03296 to satisfy a variety of interface requirements in aerospace applica- tions, including flight critical, essen- tial, and nonessential functions. features ? hirf layer ? universal inputs 28 v/gnd open/gnd 28 v/open ? built-in self-test ? soft failure reporting higher mtbur ? arinc 429 output port reference input discrete inputs reference input processor and test matrix shift h/l test matrix transfer bounce data bit fault dual redundant clock and control logic arinc data en discrete data en enable lo discrete address decoder enable hi 8/16 bus enable* reset* 1 mhz sel2 sel1 sel0 address (a5..a0) arinc 429 data rate arinc 429 message rate note: (*) indicates active low. data ready (ttl) arinc 429 output fault* data (8/16 bits) data bus fault processing circuitry arinc 429 xmitter data bus ready 10s clock 80s clock tri-state enables arinc 429 tri-state drivers arinc data transfer verifier discrete data transfer verifier discrete tri-state drivers transfer fault discrete fault transfer fault bit fault arinc fault 96 96 96 96 96 96 3 3 5 5 2 16 16 96 figure 1. DD-03296 block diagram ? 1993, 1999 data device corporation u.s. patent no. 5526288
2 note 1: arinc 429 bit rate is derived from the clock. refer to arinc 429 bit rate to avoid interference. arinc 429-14 (january 4, 1993), paragraph 2.4 timing related elements contains a commentary section following subparagraph 2.1.4.2 (low-speed operation) that cautions against using precisely 100 kilobits per second. what is a discrete? advisory circular (faa), airworthiness approval of traffic alert and collision avoidance systems (tcas ii) and mode s transponders, ac20-131, defines a discrete as a separate, complete and distinct signal. in many instances these signals are binary, on or off, 28 v-based signals; they are typically open/gnd, 28 v/open, or 28 v/gnd with very low bandwidth (dc to 200 hz). although the translation of these signals to ttl-levels that are compatible with digital avionics may seem simple, rtca do- 160 power, lightning and high-intensity-radiated-fields (hirf) are complicating factors. add to that the desire to have a stan- dardized, addressable, reliable interface and the challenge becomes apparent. todays systems address the interface requirements with cir- cuits tailored for each interface comprised of r-c input filters, divider networks, diode isolation and comparators. multichannel interfacing to a processor requires additional logic and latches. the resulting circuit generally lacks any built-in test capability, consumes considerable pc-board real estate (up to one sq. in. per channel) and offers no chip-level redundancy. functional integration using the aggregated signal definition and functional require- ments of industry, ilc data device corporation has developed a discrete interface with universal hirf-isolated inputs to han- dle 28v/open, open/gnd and 28v/gnd signals. each channel is routed through a hirf filter and comparator. its output is a selectable 8- or 16-bit tri-state port, addressable for channel data, status, bounce, built-in self-test and major fault informa- tion. this design specifically addresses built-in self-test autonomy, fault isolation and tolerance; moreover, its functional integration results in significant added reliability. a comparative look at mtbf, calculated in accordance with mil-hbk-217 for airborne inhabited cargo environments at 64c, indicates an order of magnitude improvement (1,400,000 hours vs. 173,000 hours) for a plastic packaged integrated approach vs. a similarly pack- aged discrete-component implementation. in addition, the real estate used is reduced from as much as 64 to 5 square inches. additional key DD-03296 features include: bounce: relays and switches, as mechanical devices, have a characteristic bounce to their signal transition. it is desirable to mask this bounce by delaying the output digital transition accordingly. this sampling rate of the device can be varied to allow for debounce of relay/switch inputs. in addition, the triple- sampling of a given comparator enables a consistent reading of otherwise asynchronous signals. bounce is an addressable sta- 20.0 23.5 (5.84 x 5.84) 0.83 2.3 x 2.3 (gm) (cm) oz in 1,400,000 hrs. plastic c/w weight size inhabited cargo at 64c mtbf per mil-hbk-217 for airborne q ca 5.0 c/w physical characteristics q jc junction temperature 210 c (body, 2 sec. duration) 280 c (localized, 1 sec. duration) lead temperature 150 -65 c storage temp 85 -40 c n type 2 operating temperature thermal 250.0 125.0 mw p d power dissipation 45 25 ma (total v dd , analog & digital) i dd (v dd = +5v [digital outputs unloaded]) power supply requirements see figure 4 analog inputs 0.4 v n v ol (l oh = 4ma) 2.4 v n v oh (i oh = -4ma) v dd -0.5 v n v oh (l oh = -1ma) digital outputs 1.01 1.00 0.99 mhz clock input (see note 1) -400 -40 a n v il (v in = 0) 0.8 2.0 v v n v il n v ih digital inputs cmos ttl/ logic compatibiliy inputs/outputs digital 5.5 4.5 v supply voltages (v dd ) operating conditions v dd +0.3 80 -0.3 -80 v v digital inputs discrete inputs 80 -80 v reference inputs 7.0 5.0 -0.3 v supply voitages (v cc , v dd ) absolute maximum ratings max typ mln units parameter table 1. DD-03296 specifications
3 sented to the device. the addressed data will be available with- in 100 nsec. after the data is read, the enable line should be returned to a logic 1 level before the address is changed. all of the data within the device is guaranteed to remain stable for at least 20 sec after the high-to-low transition of the ready signal (see figure 3). analog inputs analog input channels: (pins 161, 162, 1-6, 8-15, 19-26, 29-36, 45-52, 55-62, 66-73, 76-83, 85-92, 95-102, 105-112, 115-122) 600k w input resistance, 500s time constant, respon- sive to open/gnd (when configured with appropriate external pull-up), 28v/open and 28/gnd input with hirf/lightning immu- nity. refer to figure 4 for detail of the input structure. reference: configured for 28v tracking discretes. user adjustable for other reference levels by connecting external resistors between corresponding trim and ref inputs. figure 4 also shows the reference structure. each set of ref/trim inputs are configured by the user for a bank of 32- channel inputs. (see figure 4 and table 8) ref a, b, c: (pins 37, 65, and 75) input to the divider supply- ing the reference voltage to the a, b and c group of 96 input channels. trim a, b, c: (pins 38, 64, and 74) junction of the first resistor and the rest of the reference a, b and c divider. digital inputs debounce (sel2...sel0): (pins 158-160) the input discrete sampling rate (debounce time) is user-programmable via the three select lines (sel2...sel0) in accordance with table 2. the intent of this function is to mask the bounce of the input dis- tus that allows the user to detect bouncing or intermittent relays/switches. ground differentials: when the reference inputs are con- nected to the 28v supply, the thresholds are designed to tolerate 3.5v ground differences. registers: 8- or 16-bit selectable data or status are available via tri-state buffers for interfacing to any system processor. arinc 429 port: a serial arinc 429 output is available for data-concentrator applications. this enables the transfer of data to other systems with a minimum of wiring and processor load- ing. hirf: the device incorporates passive circuitry to isolate the intelligence from both lightning effects and radiated fields as defined in do-160. this protection is applicable to the discrete inputs, reference inputs and their relationship to each other and to ground. test patterns: internal test patterns can be selected to produce alternating 1s and 0s to verify that all address and data bits are operational. while these outputs are always avail- able, regardless of ready state, they must be addressed by the user (a5... a0) in accordance with tables 3 and 4. dissimilar paths: errors are reported through registers and the arinc 429 port as cross-checks. intelligence: the devices built-in self-test, status reporting scheme and isolation significantly reduces application software requirements. figure 1 illustrates the model DD-03296 func- tional block diagram. asynchronous sampling: the device takes three sam- ples on each encode because input discrete transition is asyn- chronous and reports the majority state. microprocessor interface read cycle timing the DD-03296 is configured with either an 8- or 16-bit micro- processor. figure 2 illustrates this interface. the read cycle(s) should be preceded by polling the devices ready bit located within the status register. the status register can be read at any time regardless of the state of the ready signal (pin 16) from the device. if the ready bit is a logic 1 (this can be easily tested by a branch if negative statement), the address of the desired regis- ter, along with the negative true enable signal, should be pre- table 2. discrete sampling rate select (sel 2 . . sel 0) sample rate 000 5 msec 001 10 msec 010 20 msec 011 50 msec 100 100 msec 101 200 msec 110 500 msec 111 1000 msec
4 chan 1..96 ref a, b, c sel 2..0 1 mhz cmos clock osc. DD-03296 cpu d15..d0 a5..a0 ready enable 8/16* bits +5v * indicates active low signal note: 1) if 8/16* bits pin is tied to +5v, then the DD-03296 is configured for 8-bit mode. the following must also be modified: d0 tied to d8 d1 tied to d9 d2 tied to d10 d3 tied to d11 d4 tied to d12 d5 tied to d13 d6 tied to d14 d7 tied to d15 2) if the arinc 429 option is not used, then pin 153 (429strbi) must be grounded for the "bounce" circuit to operate properly. figure 2. DD-03296-to-cpu interface ready address enable* data tra 10 ns min (see note 3) 10 ns min tea - 10 ns min 100 ns min tedoff 50 ns min ted tavail 20 s note: 1) tra = time ready address 2) tae = time address enable 3) tea = time enable to address 4) ted = time enable data 5) tedoff = time enable off - data off 6) tavail = time ready* - data available 7) (*) indicates active low. 8) the ready "on-time" = (sample rate - 440 s) sample rate is programmable via sel0 - sel2 (see table 2) tae figure 3. read cycle timing
5 figure 4. DD-03296 input structure crete appropriate to its characteristic performance. see bounce on page 2. enable: (pin 147) the enable line controls the tri-state dri- vers of the 8- or 16-bit data bus outputs. the tri-state data bus drivers are enabled when this signal is a logic 0, and are tri- stated when this signal is a logic 1. enable is a read signal and should only be low during read cycles. 8 /16 bits: (pin 104) a logic 0 selects the 16-bit data bus out- put and a logic 1 selects the 8-bit data bus output. address lines (a5...a0): (pins 139, 140 and 143-146) the six address lines (a5... a0, where a0 is the lsb) provide for the selection of the desired 8- or 16-bit data bus information in accordance with table 3 and table 4 (word/byte modes). clock (1mhz clk): (pin 28) the user must supply a 1 mhz clock whose stability is of no importance except to the serial bit rate of the arinc 429 port (see note 1 of table 1). the clock is brought into the internal asic at two widely separated points designated as clock_a (primary) and clock_b (secondary) path. the primary clock path will be selected and drive the device unless a primary clock path fault is detected, in which case the operation of the device will get switched over to the secondary clock path. both clock paths are continually monitored for status and this information is available as separate bits in the status register. factory test inputs: (pins 39, 40, 149 and 150) the tmux, tmode, fmux and fmode input signals are used for factory testing and should be tied to logic 1 for the device to operate properly. reset: (pin 41) the reset signal is used to reset the device during factory testing. it may be connected to an external rc network to provide a power-on-reset for the device. under nor- mal operating conditions this pin should be a no-connect. if there is some reason to reset the device from external circuitry this pin can be momentarily pulled to logic 0 through an open collector device. do not hard wire this pin to +5v or ground. outputs data (d15...d0): (pins 123-138) 8-bit byte or 16-bit byte word information is available on the data bus depending on the logic state of the bus select line as described above. in the byte mode the upper and lower bytes are enabled sepa- rately so that bit 0 can be hard-wired to bit 8, bit 1 to bit 9 etc., thereby providing an 8-bit data bus. it is important that the 8-bit mode be selected if these data bits are wired together or corrupted data will result. the available data can be found under the address lines section found on page 5. fault: (pin 148) the fault flag was designed to serve as an interrupt to the microprocessor when a hard error has been detected within the device (see note 2 of tables 3 and 4). if this channel n input ref a trim a 600k w 60k w .01 f comparator - + .1 f 5.72k w 93.3k w 1.0k w output to logic to other comparators identical reference structure for ref b and ref c
6 table 4. byte mode (8-bit bus) address (a5. . a0) data (d7..d0) 00 0000 bounce ch_08 ch_01 00 0001 bounce ch_16 ch_09 00 0010 bounce ch_24 ch_17 00 0011 bounce ch_32 ch_25 00 0100 bounce ch_40 ch_33 00 0101 bounce ch_48 ch_41 00 0110 bounce ch_56 ch_49 00 0111 bounce ch_64 ch_57 00 1000 bounce ch_73 ch_65 00 1001 bounce ch_80 ch_74 00 1010 bounce ch_88 ch_81 00 1011 bounce ch_96 ch_89 00 1100 fault ch_08 ch_01 00 1101 fault ch_16 ch_09 00 1110 fault ch_24 ch_17 00 1111 fault ch_32 ch_25 01 0000 fault ch_40 ch_33 01 0001 fault ch_48 ch_41 01 0010 fault ch_56 ch_49 01 0011 fault ch_64 ch_57 01 0100 test pattern 0s and 1s 01 0101 test pattern 0s and 1s 01 0110 fault ch_73 ch_65 01 0111 fault ch_80 ch_74 01 1000 fault ch_88 ch_81 01 1001 fault ch_96 ch_89 01 1010 data ch_08..ch_01 01 1011 data ch_16..ch_09 01 1100 data ch_24..ch_17 01 1101 data ch_32..ch_25 01 1110 data ch_40..ch_33 01 1111 data ch_48..ch_41 10 0000 data ch_56..ch_49 10 0001 data ch_64..ch_57 10 0010 data ch_72..ch_65 10 0011 data ch_80..ch_73 10 0100 data ch_88..ch_81 10 0101 data ch_96..ch_89 10 0110 not used 10 0111 not used 10 1000 status register lo 10 1001 status register hi 10 1010 test pattern 1s and 0s 10 1011 test pattern 1s and 0s 11 0000 10 1100 test word 3 lo test word 1 lo 11 0111 11 0011 10 1111 11 0100 11 0010 10 1110 11 0001 10 1101 : test word 4 hi test word 2 hi not used test word 4 lo test word 2 lo test word 3 hi test word 1 hi 11 1111 not used not used 11 111x : 11 011x not used 11 010x factory test word 4 11 001x factory test word 3 11 000x factory test word 2 10 111x factory test word 1 10 110x test pattern 1s and 0s 10 101x status register 10 100x not used 10 011x data ch_96..ch_81 10 010x data ch_80..ch_65 10 001x data ch_64..ch_49 10 000x data ch_48..ch_33 01 111x data ch_32..ch_17 01 110x data ch_16..ch_01 01 101x fault ch_96..ch_81 01 100x fault ch_80..ch_65 01 011x test pattern 0s and 1s 01 010x fault ch_64..ch_49 01 001x fault ch_48..ch_33 01 000x fault ch_32..ch_17 00 111x fault ch_16..ch_01 00 110x bounce ch_96 ch_81 00 101x bounce ch_80 ch_65 00 100x bounce ch_64 ch_49 00 011x bounce ch_48 ch_33 00 010x bounce ch_32 ch_17 00 001x bounce ch_16 ch_01 00 000x data (d15..d0) address (a5 . . a0) table 3. word mode (16-bit bus) notes for tables 3 and 4. note 2: a fault bit that is true indicates that the associated channel has a major problem and that the associated data should not be believed. a fault indication is a hard fault condition indicating that the built-in-test has failed. note 1: a true bounce bit indicates that the input signal of the associat- ed channel changed in an alternating fashion, i.e., off-on-off or on- off-on in three successive samples at the selected sampled rate. note 3: a data bit indicates the input discrete state for the associat- ed channel over the last two data samples taken. note 4: the two available test patterns contain an alternating string of 1s and 0s, and 0s and 1s, which can be used to verify that all of the data bits are operational (i.e., there are no stuck bits). the two test patterns have been located at addresses of alternating address bits so that the address decoder bits are tested at the same time.
7 table 5. status word bit map bit signal 00 (lsb) bit fault 01 discrete fault 02 arinc fault 03 arinc ready 04 clock_a fault 05 clock_b fault 06 no clock 07 discrete transfer fault 08 logic low (high byte) 09 logic low 10 logic low 11 logic low 12 logic low 13 logic low 14 logic low 15 (msb) ready note: all bits available regardless of ready-state. signal is asserted (logic 0) the status register should be read to determine the nature of the fault. thereafter more detailed information can be found in the associated addressable regis- ters. the fault flag will remain at a logic 0 for as long as the fault condition persists. figure 5 illustrates the fault logic tree. note: depending on the exact nature of the fault, the fault flag may return to logic 0 during the built-in-test interval (when the ready signal is at logic 0) if there is a persistent fault condition. fault conditions: fault is logic 0 for any of the following fault conditions. the reason for the fault can be obtained from the status register which is accessible regardless of ready state. table 5 shows the contents of the status register. a definition of each bit is as follows: bit fault: a logic 1 for this bit indicates that one of the chan- nels has failed the built-in-test sequence; this bit sequence is performed prior to every input sample taken. these signals are reset at the start of each built-in-test sequence, and will be set if any of the tests in the sequence fail. discrete fault: a logic 1 for this bit indicates that one of the channels detected that the discrete input data word did not transfer to the data bus output properly when it was read. if a hard fault was detected the offending channel can be deter- mined by reading the associated fault data registers. if it was generated by a transfer error the discrete transfer fault bit in this status register will be set to logic 1. arinc fault: a logic 1 for this bit indicates that one of the channels detected a hard failure during built-in-test sequence, or that the discrete input data word did not transfer to the arinc transmitter section properly. if a hard fault was detected the offending channel can be determined by reading the associated fault data registers. if it was generated by a transfer error then no fault bits in the sta- tus register will be set to logic 1. arinc ready: a logic 0 for this bit indicates that an arinc transmission is currently in progress. a logic 1 indicates that no arinc transmission is in progress. clock_a fault: a logic 1 for this bit indicates that the primary 1 mhz clock circuitry is defective and that the device is running off the secondary 1 mhz clock. clock_b fault: a logic 1 for this bit indicates that the secondary 1 mhz clock currently is defective and and cannot be used as a backup. no clock: a logic 1 for this bit indicates that there is no 1 mhz clock being supplied to the device, or that both have failed. discrete transfer fault: a logic 1 for this bit indicates that the discrete data word(s) did not transfer properly during the associated microprocessor read cycle (i.e., the word present on the data bus did not agree with internal data). the most likely cause of this type of fault condition is a collision on the data bus during the read cycle. note: this condition is only monitored for the discrete data words, not for all of the available data. clktst: (pin 157) this signal is used for factory testing and should not be connected to any external circuitry or normal oper- ation of the device could be affected. specifically, this signal is a low drive internal test point connected to the primary clock sig- nal. grounding this signal forces the device to switch to the sec- ondary internal clock. ready: (pin 16) a logic 1 for this bit indicates that all of the available data is stable and can be read. a logic 0 indicates that the device is in built-in-test mode, or taking a sample of dis- crete input data lines. the signal should be polled directly by reading the status word prior to performing any read cycles. the internal data is guaran- teed to be stable for 20 sec after the logic 1 to logic 0 tran- sition (ready to not ready) of this signal. therefore, it should not be necessary to repoll the signal after the read.
8 arinc 429 port this port enables the transmission of discrete data via a serial arinc 429 (cmos levels) output simultaneously with the 8/16- bit bus output. the following features and pins apply: arinc 429 data rate (429drate): (pin 156) a logic 1 (or a no-connect) for this input selects the arinc 429 low-speed data rate of 12.5 khz. a logic 0 selects the high-speed data rate of 100 khz. arinc 429 message rate (429mrate): (pin 155) the message rate of the arinc 429 output is selectable at either a fixed 100 ms rate or at the selected sampling rate of the input discretes. a logic 1 selects the input sampling rate as the mes- sage rate, and a logic 0 selects the fixed 100 ms message rate. note: if the low-speed arinc 429 bit rate is selected (12.5 khz) an entire arinc message will take about 52 ms to complete. therefore, input discrete sampling rates of 5 msec, 10 msec, and 20 msec cannot be utilized or the arinc message will be truncated unless the fixed 100 ms message rate is select- ed. 429 strobe in (429strbi): (pin 153) this pin is utilized in the special case where the device is being used as a remote arinc 429 serial port and is not connected to a local microprocessor. when the device is being used in this specific configuration the associated 429 strobe out should be connected to this pin. in other cases this pin must be grounded. related information: because the bounce data is momentar- illy latched within the device, this information is normally reset by a read to the associated bounce data words. in the instances when there is no microprocessor, and therefore no reads to the bounce data, this connection provides a mechanism to reset the source of the bounce information (just after it is trans- ferred to the arinc transmitter section) at the start of each arinc message. 429 strobe out (429strbo): (pin 154) this signal is used in conjunction with the 429 strobe in described above. it is a 500 ns positive pulse which occurs at the start of each 429 mes- sage. for further information concerning the use of this signal, see the 429 strobe in section. arinc_lo and arinc_hi: (pin 151 and 152) these two sig- nals comprise the arinc 429 serial output transmission. both are ttl-compatible signals where the arinc_lo signal con- tains the logic 0 serial transmission and the arinc_hi signal figure 5. fault logic tree fault bounce bit fail (status reg) matrix circuit discrete transfer fault no clock (status reg) (status reg) (status reg) discrete fault (status reg) bit fault (status reg) fault* (pin 148) r s q q s r clock a missing clock b missing read status clear strobe 1 2 3 3 2 1 2 3 2 1 1 1 2 3 96 96 96 3 note: (*) indicates active low.
9 021 0 0 0 1 0 0 0 1 h g c f e d d d d d d d d d d d d d d d d b a p data 48..33 020 0 0 0 1 0 0 0 0 h g c f e d d d d d d d d d d d d d d d d b a p data 32..17 017 0 0 0 0 1 1 1 1 h g c f e d d d d d d d d d d d d d d d d b a p data 16..1 016 0 0 0 0 1 1 1 0 h g c f e d d d d d d d d d d d d d d d d b a p bounce 96..81 012 0 0 0 0 1 0 1 0 h g c f e d d d d d d d d d d d d d d d d b a p bounce 64..49 011 0 0 0 0 1 0 0 1 h g c f e d d d d d d d d d d d d d d d d b a p bounce 48..33 010 0 0 0 0 1 0 0 0 h g c f e d d d d d d d d d d d d d d d d b a p bounce 32..17 007 0 0 0 0 0 1 1 1 h g c f e d d d d d d d d d d d d d d d d b a p bounce 16..1 006 0 0 0 0 0 1 1 0 h g c f e d d d d d d d d d d d d d d d d b a p fault 96..81 005 0 0 0 0 0 1 0 1 h g c f e d d d d d d d d d d d d d d d d b a p fault 80..65 004 0 0 0 0 0 1 0 0 h g c f e d d d d d d d d d d d d d d d d b a p fault 64..49 002 0 0 0 0 0 0 1 0 h g c f e d d d d d d d d d label reversed octal d d d d d d d sdi b c f a l s b p fault 32..17 m s b 16 bit data m s b ssm p a r 001 0 0 0 0 0 0 0 1 h g c f e d d d d d d d d d d d d d d d d b a p fault 16..1 table 6. arinc bit description 024 023 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 h h g g c c f f e e d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d b b a a p p data 96..81 data 80..65 022 0 0 0 1 0 0 1 0 h g c f e d d d d d d d d d d d d d d d d b a p data 64..49 015 0 0 0 0 1 1 0 1 h g c f e d d d d d d d d d d d d d d d d b a p bounce 80..65 014 0 0 0 0 1 1 0 0 h g c f e 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 p test as 013 0 0 0 0 1 0 1 1 h g c f e 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 p test 5s 003 0 0 0 0 0 0 1 1 h g c f e d d d d d d d d d d d d d d d d b a p fault 48..33 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 arinc 429 bits 14 l s b notes: a b = 0 0 if there are no major faults. a b = 1 1 if major faults exist (data is bad). c = 0 when 429 data rate is 100 kbps; c = 1 when data rate is 12.5 kbps. d = data bit. f = 1 if the discrete interface output has any major faults (429 data may still be good). p = arinc 429 parity bit. e = 1 if there is a bit fault g h = the value of these two locations will track channel 1 and 2 or can be hard-wired (via channel 1 and 2) to determine which r0d3 the 429 word came from. the 20 words are transmitted in order shown from top to bottom. contains the logic 1 serial transmission. these two signals must be connected to a 429 line driver (dd-03182) to obtain a single-ended arinc 429 transmition signal. figure 7 illus- trates this interface. the content and word order of the arinc 429 transmission is shown in table 6. as noted, these features are only guaranteed and tested if the arinc 429 option is selected. in addition, the clock frequency (1 mhz) must be selected carefully so as not to interfere with other avionic communications as detailed in arinc 429. the arinc 429 option bit rate is derived from the (1 mhz) clock. refer to arinc 429 bit rate to avoid interference. arinc 429-14 (january 4, 1993), paragraph 2.4 timing related elements contains a commentary section following subparagraph 2.1.4.2 (low-speed operation) that cautions against using precisely 100 kilobits per second. 429 line-driver if you use the 429 option for the DD-03296, you can use a line- driver chip to transmit the data on the serial data bus. ddc has such a device, the dd-03182, which will support arinc 429, 571, and 575 bus standards (see table 7), and is available in four package types as indicated in figures 8, 9 and 10. the serial data is presented on data (a) and data (b) inputs in a dual-rail format. the driver is enabled by the sync and clock inputs. the output voltage level is programmed by the v ref input and is nor- mally tied to +5 vdc, along with v 1 , to produce output levels of +5 v, 0 v and -5 v on each output for 10v differential outputs (see figure 6). the output resistance is 75 ohms 20%; 37.5 ohms on each output. the outputs are fused for fail-safe protection against shorts to aircraft power. the output slew rate is controlled by external timing capacitors on c a and c b . typical values are 75 pf for 100 khz data and 500 pf for 12.5 khz data.
10 0v 0v a b +v a -v -v +v b in in ref out ref ref out ref note: the output slew rates are controlled by timing capacitors c a and c b . they are charged by +/- 200 ua (nominal). slew rate (sr) is calculated by sr = 200/c (v/us) where c is in pf. chan 1..96 ref a, b, c sel 2..0 1 mhz clock osc. DD-03296 dd-03182 429 line- driver arinc arinc hi arinc lo +5v note: 1) 429 mrate and drate can either be tied to gnd or +5v (refer to page 8). 2) if the arinc 429 option is not used, then pin 153 (429strbi) must be grounded for the "bounce" circuit to operate properly. +15v -15v 429drate 429mrate 429strbo 429strbi figure 7. DD-03296 to arinc 429 interface figure 6. arinc 429 waveform
11 note: refer to dd-03182 data sheet for more information. dd-03182 line driver pin descriptions see figures 8, 9 and 10 for reference. v ref (input) C the voltage on v ref sets the output voltage levels on a out and b out . the output logic level swings between +v ref volts, 0 volts and -v ref volts. n/c C no connection sync (input) C logic 0 will force outputs to null or mark state. logic 1 enables data transmission. clock (input) C logic 0 will force outputs to null or mark state. logic 1 enables data transmission. data(a)/data(b) (inputs) C signals containing the serial data to be transmitted on the arinc 429 data bus. c a /c b (analog) C external timing capacitors are tied from these points to ground to establish the output signal slew rate. typically, c a = c b = 75 pf for 100 khz data and c a = c b = 500 pf for 12.5 khz data. a out /b out (outputs) C line driver outputs which are connected to the aircraft serial data bus. -v (input) C negative supply input (-15 vdc nominal). gnd C ground. +v (input) C positive supply input (+15 vdc nominal). v 1 (input) C logic supply input (+5 vdc nominal). +125 +85 +150 +300 75 95 115 130 175 -55 -40 -65 c c c c c/w c/w c/w c/w c thermal operating ambient temperature ceramic plastic storage temperature lead temperature (localized 10 sec duration) thermal resistance: junction to ambient q ja dd-03182dc dd-03182pp dd-03182gp dd-03182vp junction temperature 16.5 -16.5 5.25 5.25 15 -15 5 5 11.4 -11.4 4.75 4.75 0 vdc vdc vdc vdc vdc power supply requirements +v -v v 1 v ref (for arinc 429) v ref (for other applications) 40 7 6 v v v absolute maximum ratings voltage between pins +v and -v v 1 and gnd v ref and gnd max typ min units parameter table 7. dd-03182 line driver specifications
12 top view 1 26 4 3 2 25 24 23 22 21 20 19 18 17 15 16 5 7 8 11 10 9 6 dd-03182pp plcc data (a) n/c n/c n/c n/c n/c s y n c g n d n / c v r e f v 1 n / c n / c c a c b n/c n/c n/c n/c data (b) clock n / c -v +v a o u t b o u t n / c g n d 14 12 13 28 27 figure 10. dd-03182pp pin configuration top view n/c 1 2 15 16 n/c v 1 13 14 data(b) clock 3 4 sync data(a) 5 6 11 12 9 10 n/c 7 8 -v +v gnd a b out out a b c c figure 9. dd-03182dc and gp pin configuration top view n/c 1 2 13 14 v 1 11 12 data(b) clock 3 4 sync data(a) 5 6 9 10 8 +v 7 -v gnd a b out out a b c c figure 8. dd-03182vp pin configuration
13 0.785 max (19.939) lead #1 0.025 rad (0.635) 0.291 max (7.391) 0.050 max (1.270) 0.060 0.005 (1.524 0.127) 0.160 max (4.064) 0.020 - 0.070 (0.508 - 1.778) 0.100 0.010 (2.540 0.254) 0.018 0.002 (0.457 0.051) 0.125 min (3.175) 0.385 0.025 (9.779 0.635) 0.290 - 0.320 (7.39 - 8.13) 0.008 - 0.012 (0.203 - 0.305) dimensions are in inches (mm) 0 - 10 deg. 0.014 min 0.019 max (0.36 min 0.48 max) 0.003 min 0.012 max (0.076 min 0.30 max) 0.047min 0.053 max (1.19 min 1.35 max) 0.397 min 0.413 max (10.08 min 10.49 max) 0.092 min 0.094 max (2.34 min 2.39 max) 0.291 min 0.300 max (7.39 min 7.62 max) 0.007 min 0.013 max (0.18 min 0.33 max) 0.015 min 0.050 max (0.38 min 1.27 max) 0.393 min 0.420 max (9.98 min 10.67 max) 0.026 min 0.032 max (0.66 min 0.81 max) dimensions are in inches (mm) lead coplanarity 0.004 max pin 1 figure 11. dd-03182dc 16-pin ceramic dip (je) mechanical outline figure 12. dd-03182gp 16-pin surface mount (soic) mechanical outline
14 0.014 - 0.018 (0.356 - 0.457) 0.004 - 0.008 (0.102 - 0.203) 0.05 (1.270) bsc 0.336 - 0.344 (8.534 - 8.737) 0.053 - 0.069 (1.346 - 1.753) 0.150 - 0.158 (3.810 - 4.013) 0.007 - 0.009 (0.178 - 0.229) 0.018 - 0.022 (0.457 - 0.559) dimensions are in inches (mm) pin 1 0.181 - 0.205 (4.597 - 5.207) 0.228 - 0.244 (5.791 - 6.198) 3? - 6? 0.018 [0.46] min 0.100 [2.54] 0.175 [4.45] orientation mark denotes pin 1 0.020 [0.51] min 0.029 [0.74] (typ) 0.005 0.490 [12.45)] 0.050 [1.27] (typ) 1. lead cluster to be centralized about case centerline within 0.010. 2. dimensions shown are in inches [millimeters]. 0.002 0.454 [11.53] 0.002 0.454 [11.53] 0.002 0.490 [12.45] 6 eq. sp @ 0.050 = 0.300 (tol noncum) (typ) 1 0.020 0.410 [10.41] 1 notes: figure 13. dd-03182vp 14-pin surface mount (soic) mechanical outline figure 14. dd-03182pp 28-pin (plcc) mechanical outline
15 ch_02 162 ch_77 108 n/c 54 ch_01 161 ch_78 107 n/c 53 sel2 160 ch_79 106 ch_40 52 sel1 159 ch_80 105 ch_39 51 sel0 158 8/16 bits 104 ch_38 50 clktest 157 (note 3) gnd (analog) 103 (note 1) ch_37 49 429_drate 156 ch_81 102 ch_36 48 429_mrate 155 ch_82 101 ch_35 47 429_strbo 154 ch_83 100 ch_34 46 429_strbi 153 (note 4) ch_84 99 ch_33 45 arinc_hi 152 ch_85 98 n/c 44 arinc_lo 151 ch_86 97 n/c 43 fmode 150 (note 2) ch_87 96 n/c 42 fmux 149 (note 2) ch_88 95 reset 41 fault 148 n/c 94 tmux 40 (note 2) enable 147 n/c 93 tmode 39 (note 2) a00 146 ch_89 92 trim: ch_ 01-32 38 a01 145 ch_90 91 ref: ch_ 01-32 37 a02 144 ch_91 90 ch_32 36 a03 143 ch_92 89 ch_31 35 vdd (digital) 142 (note 1) ch_93 88 ch_30 34 gnd (digital) ch_94 87 ch_29 33 a04 140 ch_95 86 ch_28 32 a05 139 ch_96 85 ch_27 31 d00 138 n/c 84 ch_26 30 d01 137 ch_64 83 ch_25 29 d02 136 ch_63 82 1 mhz clk 28 d03 135 ch_62 81 vdd (analog) 27 (note 1) d04 134 ch_61 80 ch_24 26 d05 133 ch_60 79 ch_23 25 d06 132 ch_59 78 ch_22 24 d07 131 ch_58 77 ch_21 23 d08 130 ch_57 76 ch_20 22 d09 129 ref: ch_33-64 75 ch_19 21 d10 128 trim: ch_33-64 74 ch_18 20 d11 127 ch_56 73 ch_17 19 d12 126 ch_55 72 n/c 18 d13 125 ch_54 71 n/c 17 d14 124 ch_53 70 ready 16 d15 123 ch_52 69 ch_16 15 ch_65 122 ch_51 68 ch_15 14 ch_66 121 ch_50 67 ch_14 13 ch_67 120 ch_49 66 ch_13 12 ch_68 119 ref: ch_65-96 65 ch_12 11 ch_69 118 trim: ch_ 65-96 64 ch_11 10 ch_70 117 n/c 63 ch_10 9 ch_71 116 ch_48 62 ch_09 8 ch_72 115 ch_47 61 n/c 7 n/c 114 ch_46 60 ch_08 6 n/c 113 ch_45 59 ch_07 5 ch_73 112 ch_44 58 ch_06 4 ch_74 111 ch_43 57 ch_05 3 ch_75 110 ch_42 56 ch_04 2 ch_76 109 ch_41 55 ch_03 1 function pin number function pin number function pin number table 8. DD-03296 pin functions 141 (note 1) notes for table 8: 1. vdd (digital) and vdd (analog) must be connected to the same power source; gnd (digital) and gnd (analog) must be connected to the same gnd potential. 2. these signals should be tied to +5v. 3. do not connect 4. this pin must be grounded if 429 arinc is not implemented .
16 0.015 (0.38) [typ] 0.020 (0.51) r max [typ] 0.185 (4.70) [ref] detail "a" nts 0.075 (1.91) [typ] 0.065 (1.65) [typ] 41 eq. sp @ 0.050 = 2.050 (1.27 = 52.07) [tol non cum] 0.425 (10.80) 0.010 41 eq. sp @ 0.050 = 2.050 (1.27 = 52.07) [tol non cum] 2.300 (58.42) +0.010 -0.000 1 index mark denotes pin 1 0.125 (3.18) 0.010 2.300 (58.42) +0.010 -0.000 0.010 2.675 [typ] (67.95) .010 0.185 (4.69) component envelope 0.250 max (6.35) note: dimensions are in inches (millimeters). 0.018 (0.46) [typ] 0.050 (1.27) [typ] 0.040 (1.02) 0.010 (0.25) [typ] 0.002 162 121 120 85 84 43 42 35 eq. sp @ 0.050 = 1.750 (1.27 = 44.45) [tol non cum] see detail "a" 0.125 (3.18) 0.010 0.005 0.025 (0.635) figure 15. DD-03296 mechanical outline
17 ordering information DD-03296fp-xx0 screening: 0 = standard ddc procedures temperature range: 2 = -40 to +85c asic package type: p = plastic package style: f = surface mount other applicable documents rtca/do-160d: environmental conditions and test procedure for airborne equipment optional hardware dd-03182xx-xxxx C arinc 429 line driver t = tape and reel (gp and vp only) options: 0 = with resistors and fuses 1 = with resistors, no fuses* screening: 0 = standard ddc procedures 2 = burn-in (ceramic only) temperature range: 1 = -55 to +125c (ceramic only) 2 = -40 to +85c 9 = -55 to +85c (gp package only) package style/type: dc = 16-pin ceramic dip gp = 16-pin plastic soic pp = 28-pin plastic plcc vp = 14-pin plastic soic *vp version only.
18 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. ilc data device corporation registered to iso 9001 file no. a5976 c-06/98-1m 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7402 headquarters - tel: (631) 567-5600 ext. 7402, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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