1. abstract this paper focuses on the structural aspects of two basic types of rf power mosfets: the dmos and the ldmos. the comparison of the dmos and ldmos structures reveals the basic fundamentals of the rf mosfet device technology and the challenges that exist to improve their rf performance and reliability. to date, mosfet (metal-oxide-semiconductor field effect transistor) research has predominately focused on vlsi technology, which has been driven by computer ic market pressures. vlsi devices employ physical structures similar to rf power mosfets, but vlsi devices utilize much smaller physical dimensions. the salient differences between rf mosfets and vlsi devices are larger channel lengths, greater junction depths and thicker gate oxides, employed by the former, as required to obtain the high power needed for most rf applications. todays power rf applications need higher gain and more power without complicated peripheral circuitry. the rf market is being driven by the need for higher reliability, gain, linearity and output power requirements that will be constrained by the applications dc power supply limitations. most high power rf applications are using dc supply voltages ranging from 20 to 50 volts. 2. mosfets. there are two major structural categories of rf mosfets in use today. these structures, dmos (double-diffused metal-oxide-semiconductor) and ldmos (laterally diffused metal-oxide-semiconductor), have unique behaviors: semiconductor process and geometry dependent. these acronyms can be confusing, especially since the acronym ldmos is a concatenation of acronyms that have been used to designate various aspects of the lateral device and often stands for lateral current (l) double-diffused mos (dmos). these devices can be created in two common types, the pmos (p-type mosfet) and nmos (n-type mosfet), but this paper will focus on nmos only. figures 1 and 2 depict the physical structures of dmos and ldmos, respectively. from these figures, it is apparent ldmos is predominately a lateral, surface-effect device, while the dmos geometry incorporates large vertical and lateral structures forcing the time and current density of the spatial dependent vector to contain significant vertical and lateral component. both of these mosfets are composed of three terminal devices (assuming substrate shorted to source), commonly identified as the source, gate and drain, where the voltage on the gate controls the current flowing from the drain to the source. the most common circuit configuration for these devices is the common source (cs) configuration, which is comparable (in some respects) to the common emitter configuration of the bipolar transistor. considering this, any frequency-dependent source to ground connection will introduce negative feedback. other configurations are used but under the cs configuration the drain is connected to the high dc voltage while the source is grounded. the gate is used to induce a field-enhanced depletion region between the source and drain, and thereby creating a channel. the acronym nmos was derived from the fact that the p-type channel has been inverted, july 2000 1/4 AN1226 application note understanding ldmos device fundamentals john pritiskutch - brett hanson
AN1226 - application note 2/4 p body n epi n+ substrate n+ source polysilicon gate oxide source terminal gate terminal drain terminal cdg drain-source depletion width cgs creating an effective n-type material due to the depletion of the holes in the p-type channel. a high concentration of electrons is left with energy near the conduction band due to the barrier lowering caused by the gate field, and the electrons can then accelerate due to the field produced by the drain to source biasing. the details of the above mentioned gate-induced channel are critical to mos operation. the ldmos channel is predominately defined by the physical size of the gate structure (ignoring secondary effects due to diffusion vagaries) that overlies the graded p-type threshold adjust, implantation and diffusion area. the source and drain regions are on the laterally opposing sides of the gate area, and the diffusion process may produce an undercut region below the gate due to the single-step lateral diffusion process that defines the source and drain regions. the source and drain regions under bias create depletion regions that are connected by the gate induced depletion region in the p-body, and this connection defines the effective channel length which is a measure of the distance between the source and drain depletion edges. for nmos, the depletion region is a region where the high electric field lowers the energy barrier to the electron conduction band. once the barrier is lowered sufficiently, current easily flows between source and drain. ldmos channel current is controlled by the vertical electric field induced by the gate and the lateral field that exists between the source and drain. figure 1: basic dmos structure the depletion region between the source and drain is dependent on the junction doping profiles. in general, the depletion region will reach farther into a lower doped region than a higher doped region. the depletion region will extend into the channel region reducing the actual channel length formed by diffusion to the effective channel length. this creates the possibility of undesired behavior in the form of hot carrier injection due to the high electric fields, drain induced barrier lowering (dibl) and short channel effects (sce). a carefully designed, lightly doped drain, and threshold adjust p-body (that is graded appropriately) will mitigate the undesired behavior. in contrast to the ldmos, the dmos structure consists of an n-type substrate on which is grown an n- epitaxial layer that forms the large drain region. the gate region is formed on the surface that overlies the graded p-type body implantation and diffusion area. the source regions are implanted and diffused on either side of the gate to form two separate transistors with a common drain region. the depletion regions
AN1226 - application note 3/4 p+ substrate source terminal p epi n+ source polysilicon gate oxide source-sinker short gate terminal drain terminal p+ threshold adjus t p+ sinker n- drain n+ drain drain-source depletion width cgs cdg will form around the source and p-body and these depletion regions can be connected by the field induced depletion region formed by the gate. the depletion region connecting the drain and source defines the channel and its dimensions are determined by the source and body doping. another fundamental difference between the dmos and ldmos is the characteristic of the source connection to the outside world. the source of a dmos is located at the surface of the die, while the drain is formed by the substrate region and therefore wire bonds must be used to connect the source to the external circuitry. these wire bonds form a dependant frequency element reducing gain at high frequencies due to negative feedback. in addition, the common surface connection dictates that insulating material (beo) can be used to isolate the drain. this insulating material is a thermal impedance that must be considered for power dissipation. the source of the ldmos is also on the surface, however its common connection is formed by diffusing a highly doped p-type region, which acts like an ohmic connection from the source at the surface of the substrate, eliminating the need for parasitic wire bonds. this method also eliminates the ceramic interface (that exists in dmos) and improves the junction to case thermal resistance, and therefore, relieves some of the associated power dissipation issues. in summary, the ldmos channel is determined by the gate length, source diffusion and drain diffusion. figure 2: basic ldmos structure the dmos channel is determined by the lateral source diffusion edge and p-body diffusion edge. the differences in the electrical field distributions influence each of the mosfets behaviors due to the fact that the dmos has significant lateral and vertical components, whereas the ldmos is predominately a lateral field device. the differences in the source connections are significant in terms of the high frequency behavior, in that the dmos will have greater negative feedback. these inherent differences establish the appropriate domain of applications for each of these mosfet structures. the salient parameters that distinguish the differences in the circuit-level performance (as used in spice) for dmos and ldmos are v ds(on) , c iss , and c rss (see figures 1 and 2). v ds(on) is the inverse of r ds(on) . in contrast to dmos, the ldmos contains an additional p-type sinker element which has a graded doping concentration subsequent to diffusion. this is a portion of r ds(on) and optimization of this element is critical to reducing r ds(on) . the shallow junctions of the ldmos and subsequent reduction of gate overlap, reduce the input capacitance (c iss ). one of the most significant differences between ldmos and dmos in terms of circuit performance pertains to the feedback capacitance (c rss ). c rss in
AN1226 - application note 4/4 the ldmos structure is primarily composed of the gate drain overlap which is minimal compared to the dmos. the dmos c rss is larger because the entire drain contributes to the c rss. the other significant parameters that are important for circuit behavior are not critically dependent on the dmos and ldmos specific structures. for example, the transconductance is directly proportional to the channel width/length ratio, and the voltage threshold is always determined by the doping of the channel, gate oxide thickness..., etc. 3. conclusion this brief description of the fundamental structure of the ldmos and dmos invites a comparison of the critical parameters which determine the unique behavior of these two different mosfet devices. from this comparison one can speculate on the qualitative aspect of ldmos and dmos. for example, if con- templating which structure is most susceptible to drain to source punch-through, one would consider the depletion regions. the ldmos channel length and doping must prevent the drain and source depletion edges from meeting. the geometry and doping profiles are the keys to understanding many other issues as well. the following paper in this series (an1228 - related ldmos device parameters to rf performance) investigates the root causes of the various failure mechanisms that are endemic to dmos and ldmos. this investigation will require the understanding of the microscopic aspects of semiconductor physics and processing and will therefore enlighten the reader on some of the esoteric phenomena that exist with mosfets. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a trademark of stmicroelectronics ? 2000 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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