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2.5 v to 5.5 v, parallel interface octal voltage output 8-/10-/12-bit dacs ad5346/AD5347/ad5348 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . features ad5346: oc tal 8-b i t d a c AD5347: oc tal 10-b i t d a c ad5348: oc tal 12-b i t d a c l o w p o w e r oper a t ion: 1.4 m a (ma x ) @ 3.6 v p o w e r- do wn to 120 na @ 3 v , 400 na @ 5 v guarantee d m o n o ton i c b y d e s i gn ov er al l c o d e s ra il -t o - r a il ou tp u t r a nge : 0 v t o v re f or 0 v to 2 v re f po w e r - o n r e s e t t o 0 v simu lt aneo us upd a te of d a c outputs via ld a c pi n as y n c h r o n o u s clr facilit y read b a ck buffere d /un b uff e red refere n c e in puts 20 ns wr time 38-lead t ssop / 6 mm 6 mm 40-lead lfcsp p a ck aging t e mper a t ure r a nge: C40c to +105c a pplic a t io ns p o rt a b l e b a t t e ry - p o w e r e d i n s t r u m e n t s di g i ta l ga i n and off s e t adjustme n t progr a mma b l e v o lt ag e an d current s o urc e s op ti c a l ne tw ork i ng a u t o ma tic test equ i pm ent mob i le c o mmunica t ions progr a mma b l e a tten u ators industria l p r oc e ss c o n t r o l general de scription the ad5346/AD5347/ad5348 1 a r e o c tal 8-, 10 -, a nd 12-b i t d a cs, o p era t ing f r o m a 2.5 v to 5.5 v s u p p l y . th es e de vices i n c o r p or ate a n on - c h i p output bu f f e r t h a t c a n d r ive t h e output t o bo th s u p p l y ra ils, a nd als o al lo w a c h o i c e o f b u f f er ed o r u n bu f f e r e d re f e re nc e i n put . the ad5346/AD5347/ad5348 ha v e a p a ral l e l in t e r f ace . cs s e le c t s t h e de vic e a nd da t a is lo ade d in t o t h e in pu t r e g i s t ers o n th e ri si n g ed ge o f wr . a r e a d ba ck f e a t ur e allo w s t h e i n t e rn al d a c re g i ste r s t o b e re a d b a ck t h rou g h t h e d i g i t a l p o r t . the gai n p i n o n t h e s e de vice s al lo ws t h e o u t p u t ra n g e t o b e se t a t 0 v t o v re f o r 0 v t o 2 v ref . i n p u t da t a t o t h e d a cs is dou b l e -b uf f e r e d , al lo win g sim u l t an e - ou s up d a te of m u lt ipl e d a c s i n a s y ste m u s i n g t h e ld a c pi n . an asy n chr o n o us clr in p u t is a l s o p r o v ide d , w h ich r e s e ts t h e co n t e n ts o f t h e i n p u t r e g i st er and t h e d a c r e g i st er t o al l zer o s. th e s e de vices al s o in co r p o r a t e a p o w e r - o n r e s e t cir c ui t t h a t e n su re s t h a t t h e d a c output p o we r s on to 0 v a n d re m a i n s th e r e un t i l v a lid da ta i s w r i t t e n t o th e de v i ce . al l thr e e p a r t s a r e p i n com p a t i b le , whic h al lo ws us ers t o s e le c t t h e a m ou n t of re s o lut i on a ppro p r i a t e f o r t h e i r appl i c a t i o n w i th o u t r e d e s i gn i n g th e i r c i r c u i t b o a r d . function al block di ag ram input register dac register string dac c string dac a string dac b string dac d string dac e string dac f string dac g string dac h dgnd v out b v out c v out d v out e v out g v out h v out f v dd power-on reset v out a v ref ef v ref ab pd inter- face logic gain db11 db0 cs wr a0 a1 clr ldac . . . buf a2 rd v ref gh v ref cd agnd b u ffe r b u ffe r b u ffe r b u ffe r b u ffe r b u ffe r b u ffe r b u ffe r input register input register input register input register input register input register input register dac register dac register dac register dac register dac register dac register dac register ad5348 power-down logic 03331- 0- 001 fi g u r e 1 . 1 protected by u. s. patent n o . 5, 969, 6 57; other patents pending.
ad5346/AD5347/ad5348 rev. 0 | page 2 of 24 table of contents specifications ..................................................................................... 3 ac characteristics ............................................................................ 4 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 ad5346 pin configurations and function descriptions ........... 7 AD5347 pin configurations and function descriptions ........... 8 ad5348 pin configurations and function descriptions ........... 9 te r m i no l o g y .................................................................................... 10 typical performance characteristics ........................................... 12 functional description .................................................................. 16 digital-to-analog section ......................................................... 16 resistor string ............................................................................. 16 dac reference input ................................................................. 16 output amplifier ........................................................................ 16 parallel interface ......................................................................... 17 power-on reset .......................................................................... 17 power-down mode .................................................................... 17 suggested data bus formats ..................................................... 18 applications information .............................................................. 19 typical application circuits ..................................................... 19 driving v dd from the reference voltage ................................. 19 bipolar operation using the ad5346/AD5347/ad5348 ..... 19 decoding multiple ad5346/AD5347/ad5348s .................... 20 ad5346/AD5347/ad5348 as digitally programmable window detectors ...................................................................... 20 programmable current source ................................................ 20 coarse and fine adjustment using the ad5346/AD5347/ad5348 ....................................................... 21 power supply bypassing and grounding ................................ 21 outline dimensions ....................................................................... 23 ordering guides ......................................................................... 24 revision history revision 0: initial version
ad5346/AD5347/ad5348 rev. 0 | page 3 of 24 specifications table 1. v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted b version 1 parameter 2 min typ max unit conditions/comments dc performance 3 , 4 ad5346 resolution 8 bits relative accuracy 0.15 1 lsb differential nonlinearity 0.02 0.25 lsb guaranteed monotonic by design over all codes AD5347 resolution 10 bits relative accuracy 0.5 4 lsb differential nonlinearity 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5348 resolution 12 bits relative accuracy 2 16 lsb differential nonlinearity 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 % of fsr gain error 0.1 1 % of fsr lower deadband 5 10 60 mv lower deadband exis ts only if offset error is negative upper deadband 5 10 60 mv v dd = 5 v; upper deadband exists only if v ref = v dd offset error drift 6 C12 ppm of fsr/c gain error drift 6 C5 ppm of fsr/c dc power supply rejection ratio 6 C60 db ?v dd = 10% dc crosstalk 6 200 v r l = 2 k? to gnd, 2 k? to v dd ; c l = 200 pf to gnd; gain = +1 dac reference input 6 v ref input range 1 v dd v buffered reference mode v ref input range 0.25 v dd v unbuffered reference mode v ref input impedance >10 m? buffere d reference mode and power-down mode 90 k? gain = +1; input impedance = r dac 45 k? gain = +2; input impedance = r dac reference feedthrough C90 db frequency = 10 khz channel-to-channel isolation C75 db frequency = 10 khz output characteristics 6 minimum output voltage 4, 7 0.001 v min rail-to-rail operation maximum output voltage 4, 7 v dd C 0.001 v max dc output impedance 0.5 ? short circuit current 25 ma v dd = 5 v 16 ma v dd = 3 v power-up time 2.5 s coming out of power-down mode; v dd = 5 v 5 s coming out of power-down mode; v dd = 3 v logic inputs 6 input current 1 a v il , input low voltage 0.8 v v dd = 5 v 10% 0.7 v v dd = 3 v 10% 0.6 v v dd = 2.5 v v ih , input high voltage 1.7 v v dd = 2.5 v to 5.5 v pin capacitance 5 pf
ad5346/AD5347/ad 5348 rev. 0 | page 4 of 2 4 b version 1 parameter 2 min typ max unit conditions/comments logic outputs 6 v dd = 4.5 v to 5. 5 v output low voltage, v ol 0.4 v i sin k = 200 a output high vol t age, v oh v dd C 1 v i sou r ce = 200 a v dd = 2.5 v to 3. 6 v output low voltage, v ol 0.4 v i sin k = 200 a output high vol t age, v oh v dd C 0.5 v i sou r ce = 200 a power requir emen ts v dd 2.5 5.5 v i dd (normal mode) v ih = v dd , v il = gnd v dd = 4.5 v to 5. 5 v 1 1.65 ma all da cs in unbuffered mode. i n buffered mod e , v dd = 2.5 v to 3. 6 v 0.8 1.4 ma extra current is typically x a per dac, where x = 5 a + v ref /r dac i dd (pow er-down mode) v ih = v dd , v il = gnd v dd = 4.5 v to 5. 5 v 0.4 1 a v dd = 2.5 v to 3. 6 v 0.12 1 a see footnotes after the ac characteristics table. ac characteristics 6 table 2. v dd = 2.5 v to 5.5 v; r l = 2 k? to g n d; c l = 200 pf to gnd; all sp ecification s t min to t max , u n l e s s ot herwi s e not e d b version 1 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = 2 v ad5346 6 8 s 1/4 scale to 3/4 scale change (4 0 h to c0 h ) AD5347 7 9 s 1/4 scale to 3/ 4 scale change (1 00 h to 300 h ) ad5348 8 10 s 1/4 scale to 3/4 scale change (4 00 h to c00 h ) slew rate 0.7 v/s maj o r code trans i tion gl itch energy 8 nv-s 1 lsb change ar ound major carr y digital feedthrough 0.5 nv-s digital crossta l k 1 nv-s analog cros stal k 1 nv-s dac-to-dac cr osstalk 3.5 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p; unbuffered mode t o tal harmonic distortion C70 d b v ref = 2 . v 0. 1 v p- p; f r e q ue n c y = 10 khz; unbuff ered mode 1 temper atur e r a n g e: b ver s io n: C40 c to +10 5 c ; typical specifications a r e at 25 c. 2 see termino l ogy section. 3 linearity is tested using a reduced c ode ran g e: ad5 3 4 6 (code 8 to 25 5); ad53 47 (c ode 2 8 to 10 23); ad 534 8 ( c ode 1 15 t o 4 095) . 4 dc specifications tested with ou tpu t s unlo aded. 5 this corr esponds to x codes. x = deadband vol t ag e/ls b size. 6 gua r anteed by d e sign and cha r act e rization, no t pro d uction tested. 7 f o r th e amp l if ie r outp ut to re ac h its min i m u m vo lta g e , offs e t e rro r m u s t b e n e gative . f o r t h e amp l ifie r ou tp ut to re ac h its ma x i mum v o lta g e, v re f = v dd an d the offset pl us g a in er r o r m u st be p o sitive. i oh i ol to output pin v oh (min) + v ol (max) 2 c l 50pf 200 a 200 a 03331-0-002 f i gure 2 . l o a d cir c ui t fo r di g i ta l o u tput t i m i ng sp eci f ic ati o ns
ad5346/AD5347/ad 5348 rev. 0 | page 5 of 2 4 timing characteristics 1, 2, 3 table 3. v dd = 2.5 v to 5.5 v; all specificatio ns t min to t max , unles s ot herw i s e not e d parameter limit at t min , t ma x unit condition/com m ents data write mode (figure 3) t 1 0 ns min cs to wr setup time t 2 0 ns min cs to wr hold time t 3 20 ns min wr pulse wid t h t 4 5 ns min data, gain, buf setup time t 5 4.5 ns min data, gain, buf hold time t 6 5 ns min synchronous m o de. wr falling to ldac falling. t 7 5 ns min synchronous m o de. ldac falling to wr rising. t 8 4.5 ns min synchronous m o de. wr rising to ldac rising. t 9 5 ns min asynchronous mode. ldac rising to wr rising. t 10 4.5 ns min asynchronous mode. wr rising to ldac falling. t 11 20 ns min ldac pulse wid t h t 12 10 ns min clr pulse wid t h t 13 20 ns min time between wr cycles t 14 20 ns min a0, a1, a2 setup time t 15 0 ns min a0, a1, a2 hold time data readback mode (figure 4 ) t 16 0 ns min a0, a1, a2 to cs setup time t 17 0 ns min a0, a1, a2 to cs h o ld time t 18 0 ns min cs to falling edge of rd t 19 20 ns min rd pulse wid t h; v dd = 3.6 v to 5.5 v 30 ns min rd pulse wid t h; v dd = 2.5 v to 3.6 v t 20 0 ns min cs to rd hold time t 21 22 ns max data access time after falling edge of rd ; v dd = 3.6 v to 5.5 v 30 ns max data access time after falling edge of rd v dd = 2.5 v to 3.6 v t 22 4 ns min bus relin q uish time after rising ed ge of rd 30 ns max t 23 22 ns max cs falling edge to data; v dd = 3.6 v to 5.5 v 30 ns max cs falling edge to data; v dd = 2.5 v to 3.6 v t 24 3 0 n s m i n time between rd cycles t 25 3 0 n s m i n time from rd to wr t 26 3 0 n s m i n time from wr to rd , v dd = 3.6 v to 5.5 v 5 0 n s m i n time from wr to rd , v dd = 2.5 v to 3.6 v 1 guaranteed by d e sign and cha r act e rization, no t pro d uction tested. 2 a l l input sig n al s ar e specified with tr = tf = 5 ns ( 1 0 % to 90 % of v dd ) an d timed f r om a vo lt age level of (v il + v ih )/2. 3 see fig u r e 2. cs wr data, gain, buf ldac 1 ldac 2 cl r notes 1. synchronous ldac update mode 2. asynchronous ldac update mode a0 ? a 2 t 1 t 2 t 3 t 4 t 7 t 9 t 10 t 11 t 12 t 5 t 15 t 8 t 14 t 6 t 13 03331-0-003 cs a0 ? a 2 rd wr data t 16 t 18 t 25 t 20 t 22 t 21 t 17 t 26 t 24 t 19 t 23 03331-0-004 f i gure 3. p a r a ll el in ter f a c e w r ite t i m i n g d i ag r a m f i gure 4. p a r a ll el in ter f a c e r e ad t i mi n g d i ag r a m
ad5346/AD5347/ad 5348 rev. 0 | page 6 of 2 4 absolute maximum ratings table 4. t a = 2 5 c, u n les s ot herwi s e not e d p a r a m e t e r r a t i n g v dd to gnd C0.3 v to +7 v digital input voltage to gnd C0.3 v to v dd + 0.3 v digital output v o ltage to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v v ou t to gnd C0.3 v to v dd + 0.3 v operating tem p erature range industrial (b version) C40c to +105c storage temperature range C65c to +150c junction tempe r ature 150c 38-lead tssop package power dissi pati on ( t j max ? t a )/ ja mw ja thermal impedance 98.3c/w jc thermal imp e dance 8.9c/w 40-lead lfcsp package power dissi pati on ( t j max ? t a )/ ja mw ja thermal imp e dance (3-layer board) 29.6c/w lead temperature, soldering (10 sec) 300c ir reflow, peak temperature 220c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5346/AD5347/ad 5348 rev. 0 | page 7 of 2 4 ad5346 pin configurations and function descriptions top view (not to scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ad5346 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 0 db 1 db 2 clr gain db 7 db 6 db 3 db 4 db 5 8-bit v out h v out g v out f v out e dgnd a2 rd buf dgnd dgnd dgnd dgnd 03331-0-005 f i g u re 5. a d 53 46 p i n conf ig ur at io n t ssop 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ldac a1 a0 wr cs agnd v out d v re f cd v re f ef v re f gh v out c v out b v out a v re f ab pd v dd db 0 db 1 db 2 clr gain db 7 db 6 db 3 db 4 db 5 v out h v out g v out f v out e dgnd a2 rd buf agnd v dd top view (not to scale) ad5346 8-bit dgnd dgnd dgnd dgnd 03331-0-006 f i g u re 6. a d 53 46 p i n conf ig ur at io n lfcsp ta ble 5. a d 53 46 pi n f u nct i o n d e s c ri pt i o ns pin number t s s o p l f c s p m n e m o n i c f u n c t i o n 1 35 v ref gh reference input for dacs g and h. 2 36 v ref ef reference input for dacs e and f. 3 37 v ref cd reference input for dacs c and d. 4 38, 39 v dd power supply pi n(s). t h is part can operate from 2. 5 v to 5.5 v, and the su pply should be decoupl e d with a 10 f cap a citor in par a lle l with a 0.1 f capacitor to gnd. both v dd pins on the lfcsp package must be at the same potential. 5 40 v ref ab reference input for dacs a and b. 6C9, 11C14 1C4, 7C10 v ou t x output of dac x. buffered ou tp ut with rail-to-rail operati on. 10 5, 6 agnd analog ground. ground reference for analog circuitry. 15, 21C24 11, 17C20 dgnd digital ground. ground reference for digital circuitry. 16 12 buf buffer control pin. controls whe t her the re ference input to the dac is buffered or unbuffered. 17 13 ldac active low control input. upd a tes the dac registers with the contents of the input registers, which allo ws a ll dac o utputs to be simultaneously upd a ted . 18 14 a0 lsb address pin. selects which dac is to be written to. 19 15 a1 ad d r ess pin. selects which dac is to be written to. 20 16 a2 m s b ad d r ess pin. selects whi c h dac is to be written to. 2 5 C 3 2 2 1 C 2 8 db 0 Cdb 7 eight parallel data inputs. db 7 is the msb of these eight bits. 33 29 cs active low chip select input. used in conjunctio n with wr to write data to the parallel interface, or with rd to read back data from a dac. 34 30 rd active low read input. used in conjunction wit h cs to read data b a ck from the int e rnal dacs. 35 31 wr active low write input. used in conjunctio n wit h cs to write data to the parallel int e rface. 36 32 gain gain control pin. controls whet her the output r a nge from the dac is 0 v to v ref or 0 v to 2 v ref . 37 33 clr asynchronous active low control in put. clears all in put registers and dac registers to zeros. 38 34 pd power-dow n pin. t h is active lo w control pin p uts all dacs into power-d ow n m o d e .
ad5346/AD5347/ad 5348 rev. 0 | page 8 of 2 4 AD5347 pin configurations and function descriptions top view (not to scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 AD5347 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 2 db 3 db 4 clr gain db 9 db 8 db 5 db 6 db 7 10-bit v out h v out g v out f v out e dgnd a2 rd buf db 0 dgnd db 1 dgnd 03331-0-007 f i g u re 7. a d 53 47 p i n conf ig ur at io n t ssop 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ldac a1 a0 wr cs agnd v out d v re f cd v re f ef v re f gh v out c v out b v out a v re f ab pd v dd db 2 db 3 db 4 clr gain db 9 db 8 db 5 db 6 db 7 v out h v out g v out f v out e dgnd a2 rd buf agnd v dd top view (not to scale) AD5347 10-bit db 1 db 0 dgnd dgnd 03331-0-008 f i g u re 8. a d 53 47 p i n conf ig ur at io n lfcsp ta ble 6. a d 53 47 pi n f u nct i o n d e s c ri pt i o ns pin number t s s o p l f c s p m n e m o n i c f u n c t i o n 1 3 5 v ref gh reference input for dacs g and h. 2 3 6 v ref ef reference input for dacs e and f. 3 3 7 v ref cd reference input for dacs c and d. 4 3 8 , 3 9 v dd power supply pi n(s). t h is part can operate from 2. 5 v to 5.5 v, and the su pply should be decoupl e d with a 10 f cap a citor in par a lle l with a 0.1 f capacitor to gnd. both v dd pins on the lfcsp package must be at the same potential . 5 4 0 v ref ab reference input for dacs a and b. 6C9, 11C14 1C4, 7C10 v ou t x output of dac x. buffered ou tp ut with rail-to-rail operati on. 10 5, 6 agnd analog ground. ground reference for analog circuitry. 15, 21C22 11, 17C18 dgnd digital ground. ground reference for digital circuitry. 16 12 buf buffer control pin. controls whe t her the refe rence input to the dac is buffered or unbuffered. 1 7 1 3 ldac active low control input. upd a tes the dac registers with the contents of the input registers, which allo ws a ll dac o utputs to be simultaneously upd a ted . 1 8 1 4 a0 lsb ad d r ess pin. selects whic h dac is to be written to. 19 15 a1 ad d r ess pin. selects which dac is to be written to. 20 16 a2 m s b ad d r ess pin. selects whi c h dac is to be written to. 2 3 C 3 2 1 9 C 2 8 db 0 Cdb 9 t e n parallel dat a inputs. db 9 is the msb of these ten bits. 3 3 2 9 cs active low chip select input. used in conjunctio n with wr to write data to the parallel interface, or with rd to read back data from a dac. 3 4 3 0 rd active low read input. used in conjunction wit h cs to read data back from the internal dacs. 3 5 3 1 wr active low write input. used in conjunctio n wit h cs to write data to the parallel interface. 36 32 gain gain control pin . controls w h ether the output r a nge from the dac is 0 v to v ref or 0 v to 2 v ref . 3 7 3 3 clr asynchronous active low control in put. clears all in put registers and dac registers to zeros. 3 8 3 4 pd power-dow n pin. t h is active lo w control pin p uts all dacs into power-d ow n m o d e .
ad5346/AD5347/ad 5348 rev. 0 | page 9 of 2 4 ad5348 pin configurations and function descriptions top view (not to scale) 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ad5348 ldac a1 a0 wr cs agnd v out d v ref cd v ref ef v ref gh v out c v out b v out a v ref ab pd v dd db 4 db 5 db 6 clr gain db 11 db 10 db 7 db 8 db 9 12-bit v out h v out g v out f v out e dgnd a2 rd buf db 2 db 0 db 3 db 1 03331-0-009 f i g u re 9. a d 53 48 p i n conf ig ur at io n t ssop 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 ldac a1 a0 wr cs agnd v out d v re f cd v re f ef v re f gh v out c v out b v out a v re f ab pd v dd db 4 db 5 db 6 clr gain db 11 db 10 db 7 db 8 db 9 v out h v out g v out f v out e dgnd a2 rd buf agnd v dd top view (not to scale) ad5348 12-bit db 3 db 2 db 1 db 0 03331-0-010 f i gur e 1 0 . ad53 48 p i n co nfi g ur a t io nlf csp ta ble 7. a d 53 48 pi n f u nct i o n d e s c ri pt i o ns pin number t s s o p l f c s p m n e m o n i c f u n c t i o n 1 35 v ref gh reference input for dacs g and h. 2 36 v ref ef reference input for dacs e and f. 3 37 v ref cd reference input for dacs c and d. 4 38, 39 v dd power supply pi n(s). t h is part can operate from 2.5 v to 5.5 v, and the supply sh ould be decoupl e d with a 10 f capacitor i n parallel with a 0.1 f capacitor to gnd. both v dd pins on the lfcsp package must be at the same poten tial. 5 40 v ref ab reference input for dacs a and b. 6C9, 11C14 1C4, 7C10 v ou t x output of dac x. buffered ou tp ut with rail-to-rail operati on. 10 5, 6 agnd analog ground. ground reference for analog circuitry. 15 11 dgnd digital ground. ground reference for digital circuitry. 16 12 buf buffer control pin. controls whe t her the re ference input to the dac is buffered or unbuffered. 17 13 ldac active low control input. upd a tes the dac registers with the contents of the input registers, which allows all dac outputs to be s imultane o usly upd a ted . 18 14 a0 lsb address pin. selects which dac is to be written to. 19 15 a1 ad d r ess pin. selects which dac is to be written to. 20 16 a2 m s b ad d r ess pin. selects whi c h dac is to be written to. 21C32 17C28 db 0 Cdb 11 twelve parallel data inputs. db 11 is the msb of these 12 bits. 33 29 cs active low chip select input. used in conjunctio n with wr to write data to the parallel interface, or with rd to read back data from a dac. 34 30 rd active low read input. used in conjunction wit h cs to read data b a ck from the int e rnal dacs. 35 31 wr active low write input. used in conjunctio n wit h cs to write data to the parallel int e rface. 36 32 gain gain control pin. controls whet her the output r a nge from the dac is 0 v to v ref or 0 v to 2 v ref . 37 33 clr asynchronous active low control in put. clears all in put registers and dac registers to zeros. 38 34 pd power-dow n pin. t h is active lo w control pin p uts all dacs into power-d ow n m o d e .
ad5346/AD5347/ad 5348 rev. 0 | page 10 of 24 terminology relativ e accuracy f o r th e d a c, r e la ti ve acc u rac y o r in t e g r al n o nl in e a r i ty (inl) is a me asur e o f t h e max i m u m d e v i a t io n, i n ls bs, f r o m a st ra ig h t lin e p a s s in g t h ro ug h t h e ac t u al end p o i n t s o f t h e d a c t r a n sfer f u n c t i on. t y p i ca l i n l vers u s c o de pl o t s can b e s e en i n f i gure 1 4 , f i gur e 15, a nd f i gur e 16. differe ntial no nlinearity dif f er en t i al n o n l in e a r i ty (d nl) is t h e dif f er en c e b e tw e e n t h e m e as ur ed c h a n g e a n d t h e i d e a l 1 l s b c h a n g e b e t w een a n y t w o ad jacen t co des. a s p ec if ied dif f er en tia l n o nlin e a r i ty o f 1 ls b max i m u m en su r e s m o n o to nic i t y . this d a c is g u a r a n te e d m o n o t o nic b y desig n . t y p i cal dnl v e rs us co de p l o t s ca n be s e e n i n fi g u r e 1 7 , fi g u r e 1 8 , a n d fi g u r e 1 9 . gain error this is a m e asu r e o f t h e sp a n er r o r o f t h e d a c, in cl u d in g an y er r o r in t h e ga i n o f t h e b u f f er a m plif ier . i t is t h e de v i a t io n i n s l o p e o f t h e ac t u al d a c t r an sfer cha r ac t e r i s t ic f r o m t h e ide a l a nd is exp r es s e d as a p e r c en ta ge o f th e f u l l -s cale ra n g e . this is ill u s t ra t e d in f i gur e 11. offset error this is a m e as u r e o f t h e o f fs et er r o r o f t h e d a c a nd t h e o u t p u t a m plif ier . i t is exp r es s e d as a p e r c en t a ge o f t h e f u l l -s cale ra n g e . i f th e o f fse t v o l t a g e i s posi ti v e , th e o u t p u t v o l t a g e s t ill posi ti v e a t zer o in pu t co d e . this is sh o w n i n f i gur e 12. b e c a us e t h e d a cs op e r a t e f r om a s i ng l e supply , a n e g a t i v e of f s e t c a n n o t a p p e ar at t h e o u t p ut o f t h e b u f f er a m plif i e r . i n s t e a d , t h ere is a co de clos e t o zer o a t w h ich t h e am plif ier ou t p ut s a t u ra t e s (a m p lif i er fo o t r o o m ). b e lo w t h is co de t h ere is a de ad b a nd o v er w h ich t h e o u t p ut v o l t a g e d o es n o t ch a n ge . this is i l l u st ra t e d in f i gur e 13. output v oltage dac code positive gain error negative gain error actual ideal 03331-0-011 f i gure 11. g a in e r ror output voltage dac code positive offset gain error and offset error actual ideal 03331-0-012 f i gur e 1 2 . p o si t i v e o ffse t er r o r a n d gai n err o r amplifier footroom (~1mv) negative offset output voltage dac code gain error and offset error deadband codes actual ideal negative offset 03331-0-013 f i gure 13. neg a tive o ffs et e r r o r a n d g a in e rror
ad5346/AD5347/ad5348 rev. 0 | page 11 of 24 offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. dc power-supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated, i.e., ldac is high. it is expressed in db. channel-to-channel isolation this is a ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference inputs of the other dacs. it is measured by grounding one v ref pin and applying a 10 khz, 4 v p-p sine wave to the other v ref pins. it is expressed in db. major-code transition glitch energy this is the energy of the impulse injected into the analog output when the dac changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough this is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device, but it is measured when the dac is not being written to, cs held high. it is specified in nv-s and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac pin set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in db.
ad5346/AD5347/ad 5348 rev. 0 | page 12 of 24 typical perf orm ance cha r acte ristics code 250 100 0 5 0 150 200 inl e rror (ls b ) 1.0 0.5 ? 1.0 0 ? 0.5 03331-0-014 t a = 25 c v dd = 5v f i gur e 1 4 . ad53 46 t y pi c a l inl p l o t code inl e rror (ls b ) 3 0 200 1000 400 600 800 0 ? 1 ? 2 ? 3 2 1 t a = 25 c v dd = 5v 03331-0-015 f i gur e 1 5 . ad53 47 t y pi c a l inl p l o t code inl e rror (ls b ) 12 0 ? 4 ? 8 8 4 0 4000 1000 2000 3000 ? 12 t a = 25 c v dd = 5v 03331-0-016 f i gur e 1 6 . ad53 48 t y pi c a l inl p l o t code dnl e r ror (ls b ) 250 100 150 0 5 0 200 ? 0.1 ? 0.2 ? 0.3 0.3 0.1 0.2 0 03331-0-017 t a = 25 c v dd = 5v f i gur e 1 7 . ad53 46 t y pi c a l dnl p l o t code dnl e rror (ls b ) 0.4 ? 0.4 600 400 800 1000 0 ? 0.6 0.6 0.2 ? 0.2 200 0 t a = 25 c v dd = 5v 03331-0-018 f i gur e 1 8 . ad53 47 t y pi c a l dnl p l o t code 2000 3000 4000 dnl e rror (ls b ) 0.5 0 ?1.0 1.0 ?0.5 1000 0 03331-0-019 t a = 25 c v dd = 5v f i gur e 1 9 . ad53 48 t y pi c a l dnl p l o t
ad5346/AD5347/ad 5348 rev. 0 | page 13 of 24 v ref (v) e rror (ls b ) 0.5 0.3 0.2 0.1 0.4 ?0.5 ?0.4 0 ?0.3 ?0.2 ?0.1 01 2 3 4 5 max inl max dnl min inl min dnl 03331-0-031 v dd = 5v t a = 25 c f i gur e 2 0 . ad53 46 inl a n d dnl err o r v s . v ref temperature ( c) e rror (ls b ) 0.5 0.2 ? 0.5 ? 40 0 ?2 04 0 20 0 ? 0.2 60 80 100 ? 0.4 ? 0.3 ? 0.1 0.1 0.3 0.4 max inl max dnl min inl 03331-0-032 v dd = 5v v ref = 2v min dnl f i gur e 2 1 . ad53 46 inl a n d dnl err o r v s . t e m p e r a t ur e temperature ( c) ?1.0 03331-0-033 e rror (% fs r) 1.0 0.5 ? 4 0 ? 20 0 4 0 20 0 ?0.5 80 60 100 offset error gain error v dd = 5v v ref = 2v f i gur e 2 2 . ad53 46 o ffse t er r o r a n d gai n err o r vs . t e m p er a t ur e v dd (v) e rror (% fs r) 0.2 0 ? 0.6 0 2 1 3 ? 0.4 ? 0.2 45 6 ? 0.5 ? 0.3 ? 0.1 0.1 03331-0-034 t a = 25 c v ref = 2v offset error gain error f i gure 23. o ffs et e r r o r a n d g a in e rror v s . v dd sink/source current (ma) v out (v ) 5 0 0 2 1 3 3 45 6 1 2 4 03331-0-035 5v source 3v source 5v sink 3v sink f i g u re 24. v ou t s o u r c e and sink curr ent c a pab i lit y dac code i dd (ma) 1.0 0.8 0 zero scale half scale 0.2 0.4 full scale 0.1 0.3 0.5 0.6 0.7 0.9 03331-0-036 v dd = 5v t a = 25 c f i gure 25. sup p l y current v s . d a c cod e
ad5346/AD5347/ad 5348 rev. 0 | page 14 of 24 supply voltage (v) i dd (ma) 1.4 1.2 0 2.5 3.5 3.0 4.0 0.4 0.8 4.5 5.0 5.5 0.2 0.6 1.0 03331-0-037 t a = +105 c t a = +25 c t a = ? 40 c v ref = 2v gain = 1 unbuffered f i gure 26. sup p l y current v s . sup p ly v o ltag e 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 i dd p o we r-down ( a) t a = 25c 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v dd (v) 03331-0-038 f i gure 27. p o wer - d o wn cur r ent vs. su p p ly v o ltage vlogic (v) i dd (ma) 2.5 0 0 3 2 1 4 1.5 5 0.5 1.0 2.0 03331-0-039 t a = 25 c v dd = 5v v dd = 3v f i gure 28. sup p l y current v s . l o gic i n p u t v o ltag e ch2 ch1 v out a t a = 25c v dd = 5v v ref = 5v 03331-0-040 ch1 1v, ch2 5v, time base = 1 s/div ldac f i g u re 29. h a lf -s c a l e s e t t ling ( ? to ? s c a l e code) ch2 ch1 ch1 2v, ch2 200mv, time base = 200 s/div v out a v dd 03331-0-041 t a = 25 c v dd = 5v v ref = 2v f i g u re 30. p o wer - o n r e s e t to 0 v ch1 ch2 ch1 2.00v, ch2 1.00v, time base = 20 s/div v out 1 03331-0-042 pd f i g u re 31. e x it ing p o wer - d o wn to m i d s c a l e
ad5346/AD5347/ad 5348 rev. 0 | page 15 of 24 0 3 6 9 12 15 18 21 fre q ue ncy i dd (ma) 0.8 0.6 1.0 1.2 1.4 03331-0-043 v dd = 3v v dd = 5v f i g u re 32. i dd hi st ogr a m wi th v dd = 3 v and v dd = 5 v v out (v ) 2.47 2.49 2.48 2.50 1 s/div 03331-0-044 f i gur e 3 3 . ad53 48 ma j o r co de t r a n si t i o n gli t c h ene r gy frequency (hz) db 10 ? 10 ? 60 10 1k 100 10k ? 40 ? 30 100k 1m 10m ? 50 ? 20 0 03331-0-045 f i gure 34. multip lying band width (s ma ll si gnal f r equenc y resp o n se) v ref (v) full-s cale e rror (v ) 0.02 0.01 ? 0.02 0 2 1 3 ? 0.01 0 45 6 03331-0-046 v dd = 5v t a = 25 c f i gure 35. f u ll- s c al e e rror v s . v ref 0 1.996 1.997 1.998 1.999 511 475 450 425 400 375 350 325 300 275 250 225 200 175 150 125 100 75 50 25 03331-0-047 f i gure 36. d a c-to -d a c crosstalk
ad5346/AD5347/ad 5348 rev. 0 | page 16 of 24 functional description the ad5346/AD5347/ad5348 a r e o c tal r e sis t or -s tr in g d a cs fa b r ica t e d b y a cm os p r o c es s wi t h r e s o l u tio n s o f 8, 10, a n d 12 b i ts, r e sp e c t i ve ly . the y a r e wr i t te n t o usin g a p a r a l l e l in ter f ace . they o p er a t e f r o m sin g le s u p p l i es o f 2.5 v t o 5.5 v , a nd t h e output bu f f e r am pl i f i e r s of f e r r a i l - t o - r a i l output s w i n g . t h e g a i n o f th e b u f f er a m p l if iers ca n be s e t t o 1 o r 2 t o g i v e a n o u t p u t v o l t a g e ra n g e o f 0 v t o v ref o r 0 v t o 2 v ref . th e ad5346 / AD5347/ad53 48 ha v e r e f e r e nce in p u ts tha t ma y be b u f f er ed to dra w vir t ual l y no c u r r en t f r o m th e r e fer e nce s o ur ce . th e de vic e s h a v e a p o w e r - d o w n f e atu r e t h at re du c e s c u r r e n t c o n s u m pt i o n t o o n l y 100 na @ 3 v . digi tal-to- a nalog se ctio n t h e arch ite c tu re of one d a c c h an nel c o ns i s t s of a re f e re nc e bu f f e r and a re s i stor - s t r i n g d a c f o l l owe d by an output bu f f e r a m plif ier . th e vol t a g e a t t h e v re f p i n p r o v ides t h e r e fer e nce v o l t a g e fo r t h e d a c. f i gur e 37 s h o w s a b l o c k dia g ram o f t h e d a c a r chi t e c t u r e . b e ca us e t h e i n p u t c o di n g t o t h e d a c is st ra ig h t b i na r y , t h e id e a l o u t p u t v o l t a g e is g i v e n b y gain d v v n ref out = 2 w h er e: d is t h e de cima l e q ui va len t o f t h e b i na r y co de , w h ich is lo ade d t o t h e d a c r e g i s t er : 0C255 f o r ad5346 (8 b i ts) 0C1023 f o r AD5347 (10 b i ts) 0C4095 f o r ad5348 (12 b i ts) n i s th e d a c r e so l u ti o n . ga i n is t h e o u t p u t a m plif ier ga i n (1 o r 2). v out a (gain = +1 or +2) v ref ab buf dac register input register resistor string output buffer amplifier reference buffer 03331- 0- 020 f i gure 37. sing le da c chann e l a r ch itectur e resistor string the r e sis t o r s t r i n g s e c t ion is sho w n in f i gur e 3 8 . i t is sim p l y a s t r i n g o f r e sis t o r s, eac h o f val u e r . th e dig i tal c o de lo aded t o t h e d a c r e g i s t e r det e r m i n es a t w h a t no de on t h e st r i n g t h e v o l t a g e is t a p p e d o f f t o be f e d in t o the o u t p u t am p l if ier . the v o l t a g e is t a p p e d o f f b y closin g o n e o f t h e s w i t ch es co nne c t i n g th e s t r i ng t o the a m p l if ier . b e c a us e i t is a s t r i n g o f r e sis t o r s, i t is g u ar an t e e d monoton i c . to output amplifier r r r r r v ref 03331-0-021 f i gur e 3 8 . resi st or str i ng dac reference input the d a cs o p er a t e wi th an ext e r n al r e f e r e n c e . the ad5346/ AD5347/ad53 48 ha v e a r e f e r e n c e in p u t f o r eac h p a ir o f d a cs . the r e fer e n c e i n p u ts ma y b e c o nf igur e d as b u f f er e d o r un b u f f er ed . this o p tio n is co n t r o l l ed b y th e b u f p i n. i n b u f f er e d m o de (b uf = 1), t h e c u r r en t dra w n f r o m a n ext e r n al r e fer e n c e v o l t a g e is vir t ual l y zer o b e ca u s e t h e im p e d- a n c e is a t le as t 1 0 m?. th e r e fer e n c e in p u t ra n g e is 1 v t o v dd . i n u n b u f f er e d m o de (b uf = 0 ) , t h e us er ca n ha v e a r e fer e n c e vol t a g e as lo w a s 0.25 v a n d as hig h as v dd b e c a us e t h er e is n o re st r i c t i o n d u e t o he a d ro o m a n d f o ot ro om of t h e re f e re n c e a m plif ier . th e i m p e dance is st i l l la rge a t typ i c a l l y 90 k? fo r 0 v to v ref m o de and 45 k? f o r 0 v t o 2 v ref mo d e . i f usin g a n ext e r n al b u f f er ed r e f e r e n c e (s uc h as ref192), th er e is n o n e e d t o us e t h e on-chi p b u f f er . outpu t am plifier the o u t p u t b u f f er a m plif ier is c a p a b l e o f ge n e ra t i n g ou t p u t v o l t a g es t o wi t h in 1 mv o f ei t h er ra i l . i t s ac t u al ra n g e dep e n d s on v ref , g a i n , t h e l o a d o n v ou t , a n d o f fs et er r o r . i f a ga in o f +1 is s e lec t e d (gai n = 0), th e o u t p u t ra n g e is 0.001 v t o v ref . i f a ga in o f +2 is s e lec t e d (gai n = +1), th e o u t p u t ra n g e is 0.001 v t o 2 v ref . h o w e v e r , b e c a u s e o f c l a m p i n g , t h e max i m u m o u tpu t is limite d to v dd C 0.001 v . the o u t p u t am plif ier is ca p a b l e o f dr i v in g a lo ad o f 2 k? t o gnd o r v dd , in p a ral l e l wi t h 50 0 pf t o gnd o r v dd . t h e s o u r c e a n d s i nk ca pa b i l i ti e s o f th e o u t p u t a m p l i f i e r ca n be see n in f i gur e 24. t h e s l ew ra t e is 0 . 7 v/ s wi th a half-s cale s e t t lin g ti m e t o 0. 5 ls b (a t 8 b i ts) o f 6 s wi t h t h e o u t p u t unlo aded . s e e f i gur e 29.
ad5346/AD5347/ad 5348 rev. 0 | page 17 of 24 parallel interf ace the ad5346/AD5347/ad5348 lo ad th eir da ta as a sin g le 8 - , 10-, o r 12-b i t wo r d . doub le -bu f fe re d inte rfa c e the ad5346/AD5347/ad5348 d a cs al l ha ve do u b le-b uf f e r e d in t e r f aces con s ist i n g o f a n in put r e g i st er an d a d a c r e g i st er . d a c da t a , b u f , a n d gai n i n pu ts a r e wr i t t e n to t h e i n p u t r e g i s - t e r un d e r co n t r o l o f th e ch i p s e lect ( cs ) a n d w r i t e ( wr ) p i n s . a cces s t o t h e d a c r e g i s t er is c o n t r o l l ed b y th e ld a c fu n c ti o n . wh e n ld a c is hig h , t h e d a c r e g i s t er is la t c h e d and t h e i n p u t r e g i s t er ma y cha n g e s t a t e w i t h ou t a f fe c t in g t h e co n t e n ts o f t h e da c r e g i s t e r . h o w e v e r , w h e n ld a c is b r o u g h t lo w , t h e d a c r e g i s t er b e com e s t r a n s p a r en t and t h e co n t en ts of t h e in p u t r e g i s t er a r e t r a n sfer r e d t o i t . the ga in and b u f f e r co n t r o l sig n als a r e a l s o do ub le- b uf fer e d an d a r e u p da te d o n ly w h en ld a c is tak e n lo w . this is us ef u l if t h e us er r e q u ir e s sim u l t an e o us u p da t i n g o f a l l d a cs and p e r i ph erals. th e us er ca n wr i t e t o al l in p u t r e g i s t ers indivi d u a l ly and t h e n , b y p u lsin g t h e ld a c in p u t lo w , al l o u t p u t s u p da t e sim u l t an e o us l y . th e s e p a r t s co n t a i n a n ext r a fe a t ur e w h er eb y t h e d a c r e g i st er is n o t u p da t e d u n les s i t s in pu t r e g i s t er has b e e n u p da te d si n c e th e la s t t i m e tha t ld a c was b r o u g h t l o w . n o r m a l ly , w h e n ld a c is b r o u g h t lo w , t h e d a c r e g i s t e r s a r e f i l l e d wi t h t h e co n t en ts o f t h e in p u t r e g i st ers. i n the cas e o f the ad5346 / AD5347/ad53 48, th e p a r t u p da t e s t h e d a c r e g i s t er o n l y if the in p u t r e g i s t er has b e en chan g e d si n c e t h e l a s t t i me t h e d a c re g i ste r was up d a te d. this re move s u n ne c e ss ar y c r o sst a l k. clea r inpu t ( clr ) clr is a n ac ti ve lo w , asy n c h r o n o us c l ea r tha t r e s e ts t h e in p u t an d d a c re g i st e r s . chip select input ( cs ) cs i s a n a c ti v e lo w i n p u t tha t se lec t s th e d e v i ce . write input ( wr ) wr is a n ac ti ve lo w in p u t tha t co n t r o ls wr i t in g o f da ta t o th e de vice . d a t a is l a t c h e d i n t o t h e i n p u t r e g i st er o n t h e r i sin g e d ge of wr . read inpu t ( rd ) rd is a n ac ti ve lo w in p u t tha t co n t r o ls wh en da t a is r e ad bac k f r o m t h e i n t e r n al d a c r e g i s t ers. on t h e fal l in g e d g e o f rd , d a t a i s s h i f t e d o n t o th e da ta b u s . u n d e r th e co n d i t i o n s o f a h i gh ca p a c i t i v e lo ad a n d hig h s u p p li es, t h e us er m u st en s u r e t h a t t h e d y na mic c u r r en t r e ma in s a t an accep t ab le le ve l, t h er efo r e en s u r i n g t h a t t h e die t e m p era t u r e is wi t h in s p e c if ica t ion. th e die t e m p er a t ur e ca n b e calc u l a t e d as t di e = t am bient + v dd ( i dd + i d n a m i c ) a w h er e i d n a m i c = c v f a n d c = ca p a ci t a n c e o r th e da ta b u s v = v dd f = r e a d b a c k f r e q u e n c y load dac i n p u t ( ldac ) ld a c t r a n sfers da t a f r o m t h e in pu t reg i s t er t o t h e d a c r e g i s t er , a n d t h er efo r e u p da t e s t h e ou t p u t s. th e ld a c fu n c tio n e n a b l e s do ub le- b uf fer i n g o f t h e d a c d a t a , gai n da t a , and b u f . t h er e are t w o ld a c mo d e s : ? sy n c h r o n o u s mo d e . i n th i s m o de , th e d a c r e gi s t e r i s u p da ted a f t e r n e w da ta is r e ad i n on t h e r i s i ng e d ge of t h e wr in p u t. ld a c ca n b e tied pe rm a n en tl y lo w o r p u lsed a s shown i n f i g u re 3 . ? a s y n chr o no us m o de . i n th i s m o de , th e o u t p u t s a r e n o t u p da ted a t t h e s a m e tim e tha t t h e in p u t r e g i s t er is wr i t t e n to . w h e n ld a c g o es lo w , t h e d a c r e g i s t er is u p da t e d w i t h t h e con t e n ts o f t h e i n p u t r e g i s t er . power-on reset the ad5346/AD5347/ad5348 ha v e a p o w e r - on r e s e t f u n c tio n , s o tha t t h ey p o w e r u p in a def i n e d s t a t e . th e p o w e r - o n s t a t e is ? no r m a l o p e r a t i o n ? refer e nce i n p u t b u f f er e d ? 0 v t o v ref output r a nge ? ou t p u t v o l t a g e se t t o 0 v b o t h in p u t and d a c r e g i sters ar e f i l l e d w i t h ze r o s a n d r e main s o un til a valid wr i t e s e q u en ce is m a de t o t h e device . this is p a r t ic u l a r ly us e f u l in a p plic a t ion s w h er e i t is i m p o r t a n t t o k n o w t h e st a t e o f t h e d a c o u t p u t s w h i l e t h e de vic e i s p o w e r i n g u p . power-down mode the ad5346/AD5347/ad5348 ha v e lo w p o w e r co n s um p t io n, dis s i p a t in g typ i cal l y 2.4 mw wi th a 3 v s u p p l y a n d 5 mw wi t h a 5 v s u p p l y . p o w e r co n s um p t ion can be f u r t h e r r e d u ced w h en t h e d a cs a r e no t in us e b y p u t t in g t h em i n t o p o w e r - do wn m o de , w h ich is s e le c t e d b y t a k i n g t h e pd pi n l o w . w h en t h e pd p i n is hig h , t h e d a cs w o r k n o r m al l y wi t h a typ i - cal p o w e r co n s u m p t ion o f 1 ma a t 5 v (0.8 ma a t 3 v). i n p o w e r - do wn mo de , h o wev e r , the s u p p l y c u r r en t fal l s t o 400 na a t 5 v (120 na a t 3 v) w h en t h e d a cs a r e p o w e r e d do wn. n o t o n ly do es t h e s u p p ly c u r r en t dr o p , b u t t h e o u t p u t s t a g e is als o in t e r n al l y s w i t ch e d f r o m the o u t p u t o f t h e am p l if ier , m a kin g i t o p en-c ir c u i t . this has t h e advan t a g e t h a t t h e ou t p uts a r e t h r e e - s t a t e w h i l e t h e p a r t is in p o w e r - do w n m o de , and p r o v ides a def i n e d i n p u t cond i t ion fo r w h a t e v er is con n e c te d to t h e o u tpu t s o f t h e d a c a m pli f ie r s . th e o u t p u t sta g e i s il l u stra t e d in f i gur e 39. resistor string dac power-down circuitry amplifier v ou t 03331-0-022 f i gure 39. o u tput s t age d u r i ng p o wer-d o wn
ad5346/AD5347/ad 5348 rev. 0 | page 18 of 24 the b i as g e n e ra t o r , t h e o u t p u t am plif ier , t h e r e sis t o r s t r i n g , and al l o t h e r as s o cia t ed lin e a r cir c ui tr y a r e al l s h u t do wn w h en t h e p o w e r - do wn m o de is ac ti va ted . h o w e v e r , th e c o n t en ts o f the r e g i s t ers a r e una f fe c t e d w h e n i n p o w e r - down. the t i m e t o exi t p o w e r - do wn is typ i cal l y 2.5 s f o r v dd = 5 v a n d 5 s w h en v dd = 3 v . this is t h e t i m e f r o m a r i sing edg e o n the pd pi n to w h e n t h e o u t p ut v o l t ag e de v i a t es f r o m i t s p o w e r - dow n v o l t a g e . s e e f i gur e 31. suggested data bus formats in m a n y app l i c at i o n s , t h e g a i n a n d bu f pi n s a r e h a rd w i re d . h o w e v e r , if m o re f l exi b i l i t y is r e q u ir e d , t h e y c a n b e i n cl ude d in a da t a b u s. thi s ena b les t h e us er t o s o f t wa r e p r o g ra m gai n , gi v i n g th e o p ti o n o f d o u b lin g t h e r e so l u ti o n in th e lo w e r h a lf o f t h e d a c r a n g e. i n a b u s e d sy ste m , gai n an d b u f ma y b e tr ea t e d a s da ta in p u t s be ca u s e th ey a r e w r i t t e n t o th e de v i ce d u r i n g a wr i t e o p era t ion an d t a k e ef fe c t w h e n ld a c is t a k e n lo w . this m e a n s t h a t t h e r e fer e nce b u f f ers a n d t h e o u t p ut a m plif ier ga in of m u l t i p le d a c de vices c a n b e c o n t r o l l e d usin g co mm o n gain a n d b u f lin e s. n o t e tha t gain a n d b u f a r e not re a d b a c k du r i ng an rd op e r a t i o n . the AD5347 and ad5348 da t a b u s m u s t be a t l e as t 10 and 12 b i t s w i de, re sp e c t i vely , and are b e st su i t e d to a 1 6 - bi t da t a b u s sys t em. e x am pl es o f da t a fo r m a t s fo r p u t t ing gai n and b u f o n a 16-b i t da ta b u s a r e s h own in f i gur e 40. n o t e tha t an y un us e d b i ts a b o v e t h e ac t u al d a c da t a ma y b e us e d fo r gain and b u f . 03331-0-048 db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 gain x x buf x x = unused bit x db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 gain x x buf db11 db10 AD5347 ad5348 f i gur e 4 0 . ad53 47 /ad5 34 8 d a ta f o r m a t fo r w o r d l o a d wi th g a in a n d b u f d a ta on 1 6 - bi t bus table 8. ad53 46/AD5347/a d 5348 truth table clr ldac cs wr rd a2 a1 a0 functio n 1 1 1 x x x x x no data transfer 1 1 x 1 1 x x x no data transfer 0 x x x x x x x clear all registers 1 1 0 0 1 1 0 0 0 load dac a inp ut register 1 1 0 0 1 1 0 0 1 load dac b input register 1 1 0 0 1 1 0 1 0 load dac c input register 1 1 0 0 1 1 0 1 1 load dac d inp ut register 1 1 0 0 1 1 1 0 0 load dac e inp ut register 1 1 0 0 1 1 1 0 1 load dac f input register 1 1 0 0 1 1 1 1 0 load dac g inp ut register 1 1 0 0 1 1 1 1 1 load dac h inp ut register 1 x 0 1 1 0 0 0 0 read back dac register a 1 x 0 1 1 0 0 0 1 read back dac register b 1 x 0 1 1 0 0 1 0 read back dac register c 1 x 0 1 1 0 0 1 1 read back dac register d 1 x 0 1 1 0 1 0 0 read back dac register e 1 x 0 1 1 0 1 0 1 read back dac register f 1 x 0 1 1 0 1 1 0 read back dac register g 1 x 0 1 1 0 1 1 1 read back dac register h 1 0 x x 1 x x x update dac re gisters x x 0 0 0 x x x invalid operation x = dont care
ad5346/AD5347/ad 5348 rev. 0 | page 19 of 24 appli c ations inf ormati o n ty pical a p plicati o n circuits the ad5346/AD5347/ad5348 ca n be us e d wi t h a wide ra n g e o f r e fer e n c e v o l t a g es, es p e c i al ly i f t h e r e fer e n c e i n p u ts a r e co nf igur e d as u n b u f f er e d , in w h ich c a s e t h e de vices o f fer f u l l , o n e - q u adran t m u l t i p ly in g c a p a b i li ty o v er a r e fer e n c e ran g e o f 0.25 v t o v dd . m o r e typ i cal l y , t h es e de vices ma y b e us e d w i t h a f i x e d, pre c i s i o n re f e re nc e vo lt ag e. f i g u re 4 1 sho w s a t y pi c a l s e t u p fo r t h e de vices w h en using a n ext e r n al r e fer e n c e c o n n e c t e d to t h e re f e re nc e i n put s . su it abl e re f e re nc e s f o r 5 v o p era t ion a r e t h e ad780, ad r3 81, a n d ref192 (2.5 v r e f e r - en ces). f o r 2.5 v o p era t ion, s u i t a b le ext e r n al r e fer e n c es a r e t h e ad589 an d t h e ad1580 (1.2 v ba nd ga p r e f e r e n c es). ad5346/AD5347/ ad5348 v out * 0.1 f v dd = 2.5v to 5.5v v dd gnd ad780/adr381/ref192 with v dd = 5v or ad589/ad1580 with v dd = 2.5v v ref * gnd *only one channel of v ref and v out shown 10 f v out v in ext ref 03331-0-024 f i gur e 4 1 . ad53 46 /ad5 34 7/ ad534 8 u s i n g a n ex t e rnal refe r e nc e drivi n g v dd from the reference voltage i f an output r a n g e of 0 v to v dd is r e q u ir e d , t h e sim p lest so l u ti o n i s t o co n n ec t th e r e f e r e n c e i n p u t s t o v dd . b e c a u s e t h i s s u p p l y m a y n o t be v e r y acc u ra te a n d ma y b e no isy , th e de vices c a n b e p o we re d f r om t h e re f e re nc e vo lt age, f o r e x am pl e, by usin g a 5 v r e f e r e n c e s u ch as t h e ad m663 o r ad m666, as s h own in f i gur e 42. ad5346/AD5347/ ad5348 v out * 0.1 f 6v to 16v v dd gnd v ref * gnd *only one channel of v ref and v out shown 10 f v out(2) v in ext ref 0.1 f gnd sense shdn vset adm663/adm666 03331-0-025 f i gur e 4 2 . usi n g a n adm6 63 / a dm 66 6 a s p o w e r a n d re fe r e nc e to the a d 5 346 / a d5 34 7/ ad5 3 4 8 bipolar operation using the ad5346/AD5347/ad534 8 the ad5346/AD5347/ad5348 ha v e been desig n e d f o r sin g le- s u p p l y o p era t io n, b u t a b i p o la r o u t p u t ra n g e is als o p o s s i b le b y usin g t h e cir c ui t s h o w n in f i gure 43. this cir c ui t has an o u t p u t v o l t a g e ra n g e o f 5 v . r a i l -t o-rai l o p era t ion a t t h e am plif ier o u t p u t is ac hieva b le usin g a n ad820, a n ad85 19, o r a n o p 196 as t h e o u t p u t am plif ier . 5v ext ref gnd v out r2 20k ? r1 10k ? r4 20k ? r3 10k ? 5 v +5v ?5v *only one channel of v ref and v out shown 0.1 f 0.1 f 10 f ad820/ad8519/ op196 v in gnd ad5346/AD5347/ ad5348 v out * v dd v ref * 03331- 0- 026 f i gur e 4 3 . bi po la r op e r a t i o n wi th the ad5 346 / ad53 47 /ad5 34 8 the o u t p u t v o l t a g e fo r a n y i n p u t co de c a n b e ca lc u l a t e d as fol l o w s: v ou t = [(1 + r4 / r3 ) ( r2 /( r1 + r2 ) (2 v ref d/2 n )] C r4 v ref / r3 w h er e: d is th e decim a l eq ui valen t o f th e co de lo ade d t o th e d a c. n i s th e d a c r e so l u ti o n . v ref is t h e r e feren c e v o l t a g e in pu t. wi t h : v ref = 5 v r1 = r3 = 10 k ? r2 = r4 = 20 k ? v dd = 5 v gain = 2 v ou t = (10 d /2 n ) C 5
ad5346/AD5347/ad 5348 rev. 0 | page 20 of 24 decoding multiple ad5346/AD5347/ad5348 s the cs p i n o n t h es e de vices can b e us ed in a p p l ic a t io n s t o deco de a n u m b er o f d a cs. i n t h is a p p l ica t io n, al l d a cs in the sys t em r e ce i v e t h e s a me da t a and wr p u ls es, b u t o n ly t h e cs to o n e o f th e d a c s w i ll b e a c ti v e a t a n y o n e ti m e , so d a ta w i ll o n l y b e wr it te n to t h e d a c w h o s e cs is lo w . the 74h c139 is us ed as a 2-line t o 4-lin e de co der t o addr es s a n y o f th e d a cs i n t h e s y s t em . t o p r ev en t t i m i n g e r r o r s f r o m o c c u r r i n g , t h e e n a b le i n p u t sh ou ld b e b r o u g h t to i t s inac t i ve s t a t e w h i l e t h e c o de d addr es s i n p u ts a r e chan g i n g s t a t e . f i gur e 44 s h o w s a dia g ram o f a typ i cal s e t u p f o r deco din g m u l t i p le de vice s in a sys t e m . on ce da t a has be en wr i t t e n seq u en t i all y t o all d a c s in a sy s t em , all t h e d a c s ca n b e u p da ted sim u l t an eo us l y usin g a co mm o n ld a c lin e . a co m- mo n clr lin e c a n al s o be us e d t o r e s e t al l d a c o u t p u t s t o 0 v . enable coded a ddress 1g 1a 1b v dd v cc 74hc139 dgnd 1y0 1y1 1y2 1y3 a0 a1 a2 wr l dac cl r data inputs data inputs data inputs data inputs dat a bus a0 a1 a2 wr ld a c cl r cs a0 a1 a2 wr ld a c cl r cs ad5346/AD5347 /ad5348 a0 a1 a2 wr ld a c cl r cs a0 a1 a2 wr ld a c cl r cs ad5346/AD5347 /ad5348 ad5346/AD5347 /ad5348 ad5346/AD5347 /ad5348 03331- 0- 027 f i g u re 44. d e c o d i n g m u lt ip le da c d e v i c e s ad5346/AD5347/ad534 8 as digitally pr ogr a m m a ble w i n d ow de te c t ors a d i gi tall y p r ogra m m a b l e u p per/lo w e r lim i t d e t e ct o r usin g tw o o f th e d a cs in th e ad5346 /AD5347/ad5348 is s h o w n in f i gur e 45. an y p a ir o f d a cs in th e de vice ma y be us e d , b u t f o r sim p lici ty th e descr i p t io n r e f e r s t o d a cs a a n d b . t h e u p p e r a n d lo w e r lim i ts f o r th e t e s t a r e lo ad e d t o d a cs a a n d b w h ic h, in t u r n , s e t t h e limi ts o n t h e cmp04. i f a sig n al a t th e v in in p u t is n o t w i t h i n t h e pr og ra mm e d wi ndo w , a n led indic a t e s t h e f a i l co ndi t ion. 5v gnd v ref ab v dd v in fail pass 1k ? 1k ? pass/ fail 1/6 74hc05 1/2 cmp04 v ref 0.1 f 10 f v out b v out a ad5346/AD5347/ ad5348 03331- 0- 028 f i g u re 45. p r og r a m m ab le w i ndow d e t e c t o r programmable curre nt source f i gur e 46 s h o w s th e ad5346/AD5347/ad5348 us ed as t h e co n t r o l e l e m en t o f a p r og ra mma b l e c u r r en t s o ur ce . i n t h is exa m ple , t h e f u l l -s cale c u r r en t i s s e t t o 1 ma. th e o u t p ut v o l t a g e f r o m t h e d a c is a p plie d acr o s s t h e c u r r en t s e t t in g r e sis t o r o f 4.7 k? in s e r i es wi t h the 470 ? ad j u s t m e n t p o te n t i o me te r , w h i c h g i ve s an adj u st me n t of ab ou t 5 %. s u i t a b le t r a n sisto r s t o p l ace in t h e fe e d back lo op o f t h e a m p l i- f i er in c l ude t h e b c 107 an d t h e 2n3904, which ena b le t h e c u r r en t s o ur ce t o o p era t e f r o m a minim u m v so ur c e o f 6 v . th e o p era t i n g ra n g e is det e r m i n e d b y t h e o p er a t in g cha r ac t e r i s t ics o f th e tra n sis t o r . s u i t a b le am p l if iers in c l ude the ad820 an d t h e o p 295, bo th ha vin g rail-t o-rail o p era t ion o n t h eir o u t p u t s. th e c u r r en t fo r a n y dig i t a l in p u t co de an d r e sisto r va l u e can b e calc u l a t ed as f o l l o w s: ma r d v g i n ref ) 2 ( = wher e: g is th e ga in o f th e b u f f er a m p l if ier (1 o r 2). d is t h e dig i t a l i n p u t c o de . n is the d a c r e s o l u tio n (8, 10, o r 12 b i ts). r is t h e su m o f t h e r e sisto r pl us ad j u st me n t p o te n t iome t e r in k? . v dd = 5v 5v load v source ext ref gnd v out 4.7k ? 470 ? *only one channel of v ref and v out shown 0.1 f 0.1 f 10 f v in gnd ad5346/AD5347/ ad5348 v dd v ref *v out * 03331-0-029 f i g u re 46. p r og r a m m ab le cur r ent s o u r c e
ad5346/AD5347/ad 5348 rev. 0 | page 21 of 24 coarse and fine adju stment us ing the ad5346/AD5347/a d 5348 t w o o f the d a cs in t h e ad53 46/AD5347 /ad5348 ca n be p a ir ed t o g e t h er t o f o r m a co a r s e a nd f i n e ad j u s t m e n t f u n c tio n , as sh o w n in f i g u r e 47. a s wi t h t h e wi ndo w co m p a r a t o r p r e v io u s ly d e s c r i b e d , t h e de s c r i pt ion refer s to d a cs a and b . d a c a p r o v ide s t h e co a r s e ad j u s t m e n t , w h i l e d a c b p r o v ide s t h e f i n e ad j u s t m e n t . v a r y in g t h e r a t i o o f r1 a nd r2 cha n g e s t h e r e la t i v e ef f e c t o f th e co a r s e and f i n e ad j u s t m e n t s. w i th t h e re s i stor v a lu e s show n , t h e output am pl i f i e r h a s u n it y g a i n f o r t h e d a c a ou t p u t , s o t h e o u t p u t ra n g e is 0 v t o (v ref C 1 ls b). f o r d a c b , t h e a m plif ier has a ga in o f 7.6 10 C3 , g i vin g d a c b a ra n g e e q ual t o 2 ls bs o f d a c a. t h e c i rc u i t i s s h ow n w i t h a 2 . 5 v re f e re nc e, but re f e re nc e volt age s up to v dd ma y b e us e d . the o p a m ps i ndic a te d a l lo w a ra il-t o-ra il o u t p u t swin g. ad780/adr381/ref192 with v dd = 5v v dd = 5v v out 5v ext ref v out v in gnd gnd ad5346/AD5347/ ad5348 v out b v out a v dd v ref ab r1 390 ? r4 390 ? r2 51.2k ? r3 51.2k ? 0.1 f 0.1 f 10 f 03331-0-030 fi g u r e 4 7 . c o a r s e a n d fi n e a d j u s t m e n t power supply bypass ing and gr ounding i n a n y ci r c ui t wh e r e ac cu ra c y is im p o r t a n t , ca r e f u l co n s i d e r a t i o n o f t h e p o w e r sup p ly a nd g r o u nd r e t u r n l a yo u t h e l p s to en sur e t h e r a te d p e r f o r ma nce. the p r in ted cir c ui t bo a r d o n whic h the ad5346 /AD5347 / ad5348 is m o u n t e d sh o u ld be desig n e d s o tha t th e a n alog a nd dig i t a l s e c t io n s a r e s e p a r a te d and a r e co nf i n e d to cer t a i n a r e a s o f t h e b o a r d . this faci li t a t e s t h e us e o f g r o u n d plan es t h a t can b e s e p a r a t e d e a s i ly . a minim u m et ch te chni q u e is g e n e ral l y b e s t fo r g r o u n d planes b e ca us e i t g i ves t h e b e s t s h i e lding. dig i t al and a n alog g r o u n d plan es sh o u ld b e jo i n e d in one place o n ly . i f t h e ad5346/ad53 47/ad5348 is t h e onl y de vice req u ir in g an a g n d - t o- d g n d co nn ecti o n , th en th e gr o u n d p l a n e s s h o u ld be co nnec t e d a t th e a g nd an d d g nd p i n s o f th e ad5346 / AD5347/ad53 48. i f th e ad53 46/AD5347 /ad5348 is in a sys t em w h er e m u l t i p le de vi ces r e q u ir e a g nd- t o-d g nd co nne c t io n s , t h e co nn e c t i on sho u ld b e made a t o n e p o in t o n ly , a s t a r g r o u nd p o i n t t h a t sh o u ld b e es t a b l ishe d as clos e as p o s s i b le t o th e ad5346 /AD5347/ad53 48. the ad5346/AD5347/ad5348 s h o u ld ha v e a m p l e s u p p l y b y p a s s in g o f 10 f in p a ral l e l wi th 0.1 f o n t h e s u p p l y lo ca t e d as clos e t o t h e p a cka g e as p o s s i b le , ide a l l y r i g h t u p a g a i ns t t h e de vice . the 10 f ca p a ci t o rs a r e t h e t a n t al um b e ad ty p e . th e 0.1 f ca p a ci t o r s h o u ld ha v e lo w ef fe c t i v e s e r i es r e sis t a n c e (es r ) a n d ef f e c t i v e ser i es in d u c t a n ce (es i ), s u c h as t h e co mm o n ceramic typ e s tha t p r o v ide a lo w im p e dan c e p a th t o g r o u n d a t hig h f r e q uen c ies t o ha ndle t r a n sie n t c u r r en ts d u e t o in t e r n a l log i c swi t chi n g. the p o w e r s u p p ly lin e s o f t h e de v i ce sh o u ld us e t h e la rg es t t r ace p o s s i b le t o p r o v ide lo w im p e dan c e p a t h s and to r e d u ce t h e ef fe c t s o f g l i t ches o n t h e p o w e r s u p p ly line . f a st swi t chin g sig n als s u c h as clo c ks sh o u ld be s h ie lde d wi t h dig i t a l g r o u nd t o a v oi d r a d i a t i n g noi s e to ot he r p a r t s of t h e b o ar d, an d s h ou l d ne v e r b e r u n n e a r t h e r e fer e n c e in p u ts. a v oid cros s o v e r o f dig i t a l an d analog sig n als. t r aces o n o p p o si te sides o f t h e bo a r d s h o u ld r u n a t r i g h t a n g l es t o e a ch o t h e r t o r e d u ce t h e ef fe c t s o f f eed th r o u g h th r o u g h th e boa r d . a m i cr os tri p t e c h n i q u e i s b y fa r t h e b e st, b u t n o t alwa ys p o s s ib le wi t h a do u b le -side d b o a r d . i n t h is te chni q u e, t h e com p on e n t s i de o f t h e b o a r d is de dic a te d to g r o u n d pl an e , w h i l e sig n al t r ace s a r e place d o n t h e s o lder side.
ad5346/AD5347/ad5348 rev. 0 | page 22 of 24 table 9. overview of ad53xx parallel devices additional pin functions part no. resolution dnl v ref pins settling time buf gain hben clr package pins singles ad5330 8 0.25 1 6 s 9 9 9 tssop 20 ad5331 10 0.5 1 7 s 9 9 tssop 20 ad5340 12 1.0 1 8 s 9 9 9 tssop 24 ad5341 12 1.0 1 8 s 9 9 9 9 tssop 20 duals ad5332 8 0.25 2 6 s 9 tssop 20 ad5333 10 0.5 2 7 s 9 9 9 tssop 24 ad5342 12 1.0 2 8 s 9 9 9 tssop 28 ad5343 12 1.0 1 8 s 9 9 tssop 20 quads ad5334 8 0.25 2 6 s 9 9 tssop 24 ad5335 10 0.5 2 7 s 9 9 tssop 24 ad5336 10 0.5 4 7 s 9 9 tssop 28 ad5344 12 1.0 4 8 s tssop 28 octals ad5346 8 0.25 4 6 s 9 9 9 tssop, lfcsp 38, 40 AD5347 10 0.5 4 7 s 9 9 9 tssop, lfcsp 38, 40 ad4348 12 1.0 4 8 s 9 9 9 tssop, lfcsp 38, 40 table 10. overview of ad53xx serial devices part no. resolution dnl v ref pins settling time interface package pins singles ad5300 8 0.25 0 (v ref = v dd ) 4 s spi? sot-23, msop 6, 8 ad5310 10 0.5 0 (v ref = v dd ) 6 s spi sot-23, msop 6, 8 ad5320 12 1.0 0 (v ref = v dd ) 8 s spi sot-23, msop 6, 8 ad5301 8 0.25 0 (v ref = v dd ) 6 s 2-wire sot-23, msop 6, 8 ad5311 10 0.5 0 (v ref = v dd ) 7 s 2-wire sot-23, msop 6, 8 ad5321 12 1.0 0 (v ref = v dd ) 8 s 2-wire sot-23, msop 6, 8 duals ad5302 8 0.25 2 6 s spi msop 8 ad5312 10 0.5 2 7 s spi msop 8 ad5322 12 1.0 2 8 s spi msop 8 ad5303 8 0.25 2 6 s spi tssop 16 ad5313 10 0.5 2 7 s spi tssop 16 ad5323 12 1.0 2 8 s spi tssop 16 quads ad5304 8 0.25 1 6 s spi msop 10 ad5314 10 0.5 1 7 s spi msop 10 ad5324 12 1.0 1 8 s spi msop 10 ad5305 8 0.25 1 6 s 2-wire msop 10 ad5315 10 0.5 1 7 s 2-wire msop 10 ad5325 12 1.0 1 8 s 2-wire msop 10 ad5306 8 0.25 4 6 s 2-wire tssop 16 ad5316 10 0.5 4 7 s 2-wire tssop 16 ad5326 12 1.0 4 8 s 2-wire tssop 16 ad5307 8 0.25 2 6 s spi tssop 16 ad5317 10 0.5 2 7 s spi tssop 16 ad5327 12 1.0 2 8 s spi tssop 16 octals ad5308 8 0.25 2 6 s spi tssop 16 ad5318 10 0.5 2 7 s spi tssop 16 ad5328 12 1.0 2 8 s spi tssop 16
ad5346/AD5347/ad 5348 rev. 0 | page 23 of 24 outline dimensions 38 20 19 1 9.80 9.70 9.60 pin 1 seating plane 0.15 0.05 0.50 bsc 1.20 max 0.27 0.17 0.20 0.09 8 0 4.50 4.40 4.30 6.40 bsc 0.70 0.60 0.45 compliant to jedec standards mo-153bd-1 coplanarity 0.10 f i gure 48. 3 8 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 38) di me nsio ns sho w n i n mi ll im e t e r s 1 40 10 11 31 30 21 20 bottom view 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicato r 5.75 bs c s q 12 max 0.30 0.23 0.18 0. 20 re f seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0. 80 m a x 0.65 typ 4.50 re f 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0. 25 m i n compliant to jedec standards mo-220-vjjd-2 f i gure 49. 4 0 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] (c p - 4 0 ) di me nsio ns sho w n i n mi ll im e t e r s
ad5346/AD5347/ad 5348 rev. 0 | page 24 of 24 ordering guides table 11. a d 5 346 or dering guide model temperature r a nge package descri ption package option ad5346bru C40c to +105c tssop (thin sh r i nk small outline package) ru-38 ad5346bru-re el C40c to +105c tssop (thin shr i nk small outline package) ru-38 ad5346bru-re el7 C40c to +105c tssop (thi n shr i nk small outline package) ru-38 ad5346bcp C40c to +105c lfcsp (lead fra me chip scale p a ckage) cp-40 ad5346bcp-ree l C40c to +105c lfcsp (lea d fra me chip scale p a ckage) cp-40 ad5346bcp-ree l7 C40c to +105c lfcsp (l ead fra me chip scale p a ckage) cp-40 table 12. a d 5 347 or dering guide model temperature r a nge package descri ption package option AD5347bru C40c to +105c tssop (thin sh r i nk small outline package) ru-38 AD5347bru-re el C40c to +105c tssop (thin shr i nk small outline package) ru-38 AD5347bru-re el7 C40c to +105c tssop (thi n shr i nk small outline package) ru-38 AD5347bcp C40c to +105c lfcsp (lead fra me chip scale p a ckage) cp-40 AD5347bcp-ree l C40c to +105c lfcsp (lea d fra me chip scale p a ckage) cp-40 AD5347bcp-ree l7 C40c to +105c lfcsp (l ead fra me chip scale p a ckage) cp-40 table 13. a d 5 348 or dering guide model temperature r a nge package descri ption package option ad5348bru C40c to +105c tssop (thin sh r i nk small outline package) ru-38 ad5348bru-re el C40c to +105c tssop (thin shr i nk small outline package) ru-38 ad5348bru-re el7 C40c to +105c tssop (thi n shr i nk small outline package) ru-38 ad5348bcp C40c to +105c lfcsp (lead fra me chip scale p a ckage) cp-40 ad5348bcp-ree l C40c to +105c lfcsp (lea d fra me chip scale p a ckage) cp-40 ad5348bcp-ree l7 C40c to +105c lfcsp (l ead fra me chip scale p a ckage) cp-40 ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03331C0 C 11/03(0)

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