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" for more information + ! " implementing a common layout for amd mirrorbit? and intel strataflash? memory devices application note publication number 25627 revision a amendment +3 issue date march 5, 2003
publication# 25627 rev: a amendment/ +3 issue date: march 5, 2003 implementing a comm on layout for amd mirrorbit tm and intel strataflash tm memory devices application note overview this document describes the benefits of designing with amd mirrorbit ? flash memory and the ease with which system designers can layout a board to accom- modate high-density flash devices from both amd and intel. the layouts shown accept amd?s single-bit per cell lv family, amd?s new two-bit per cell mirrorbit fam- ily, and intel strataflash ? 32mb-128mb flash memory devices. what are amd mirrorbit devices amd?s patented mirrorbit technology is a breakthrough flash architecture solution that enables amd flash memory devices to hold twice as much data per tran- sistor cell as a standard flash product. what?s revolu- tionary about this accomplishment is that for the first time, this enhanced density is being delivered without sacrificing device performance, endurance, and reli- ability. amd provides this technology in devices start- ing at 32mb density. these products are pinout and functionally compatible with previous single-bit per cell lv family devices and provide an easy migration path from lower density 2 megabit to 64megabit lv devices up to 1 gigabit mirrorbit devices. for more information on the specifics of mirrorbit architecture visit the amd web site for a comprehensive white paper and online reference material. advantages of designing with amd mirrorbit amd?s new mirrorbit technology provides a low-cost, more reliable alternative to multi-level cell (mlc) so- lutions. mlc products such as intel?s strataflash suffer from performance and reliability concerns inherent when detecting between multiple charge levels in a sin- gle flash cell. the following table 1 provides a com- parison between amd?s mirrorbit and intel?s strataflash device features. table 1. amd and intel 64 mb flash memory comparison specification amd lv amd mirrorbit intel strataflash notes bus width x8 only, x8/x16, and x16 only x8 only, x8/x16, and x16 only x8/x16 both selectable via byte# pin core supply voltage 2.7?3.6 v or 3.0?3.6 v 2.7?3.6 v or 3.0?3.6 v 2.7 v?3.6 v same core voltage range i/o voltage range 2.7?3.6 v or 3.0?3.6 v 1.65 v?3.6 v 2.7 v?3.6 v amd features enhanced v i/o range 1.65v - 3.6v sector size 64kbyte 64kbyte 128kbyte 64kb is amd standard sector size random access time 90 ns 90 ns 120 ns access times unchanged on mirrorbit technology page access time n/a 25 ns 25 ns page length n/a 4 word 4 word word programming 11us 15 us 13.625 us mirrorbit and strataflash calculated using write buffer (see note) sector erase time (typ) 1600ms 400 ms 1000 ms mirrorbit technology improves erase times for amd devices operating temp. range ?40c to 85c ?40c to 85c ?40c to 85c
2 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices note: for information on increasing the speed of programming operations using the write buffer functionality, refer to publication number 25539, mirrorbit flash memory write buffer programming and page buffer read . amd provides customers with a superior memory solu- tion at each associated density, and pinout compatible migration from lower densities. density upgrade paths are available in industry-standard tsop and fbga packaging. figure 1 illustrates amd?s migration path in tsop packages. the added 56-pin tsop package used for high-density devices (64 mb and above) will include the same internal footprint as the legacy 48-pin tsop package. for a detailed view of tsop and bga migration paths available for mirrorbit devices, refer to publication number 25694, ?mirrorbit packages.? figure 1. amd tsop pinout migration for 3v lv family data retention 20 years @ 125c 20 years @125c not guaranteed intel does not specify a data retention guarantee write/erase cycles (endurance) 1 million 100k 100k amd?s target for mirrorbit is 1 million cycles security region (otp sector) 256bytes 256bytes 128 bit current consumption read current erase/program current standby mode current 9 ma 26 ma 0.20 a 30 ma 50 ma 1 a 40 ma 35 ma 50 a typical values using byte read at 200ns intervals with cmos inputs. table 1. amd and intel 64 mb flash memory comparison (continued) specification amd lv amd mirrorbit intel strataflash notes 3 18 4 1 2 5 6 7 8 9 10 19 20 21 22 23 24 11 12 13 14 15 16 17 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 46 45 48 47 44 43 42 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 41 54 53 55 56 52 51 50 49 46 45 48 47 44 43 42 41 39 38 37 36 35 34 33 32 31 30 nc a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# wp#/acc ry/by# a17 a7 a6 a5 a23 a22 a4 a3 dq10 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq2 dq9 dq1 dq8 dq13 dq5 dq12 dq4 v cc dq11 dq3 a24 a25 am29lv320 am29lv 64mb?1gb 56-pin tsop 48-pin tsop 25 26 27 28 21 22 23 24 29 a2 a1 a18 a17 a7 a6 a5 a4 a3 a2 a1 nc nc dq0 oe# v ss ce# a0 dq10 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq2 dq9 dq1 dq8 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq0 oe# v ss ce# a0 v io rfu (256 mb) (128 mb) (512 mb) (1 gb) (64 mb)
implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices 3 implementing a multi-sourced layout customers wanting to take advantage of the benefits and savings associated with amd?s mirror-bit technol- ogy as well as the security of a second source supplier can implement a multi-sourced board layout. this sec- tion describes the changes that may be required to en- able an amd lv, amd mirrorbit and intel strataflash dual-source layout for 32mb, 64mb, and 128mb de- signs. pinout differences the amd lv-mirror-bit family and intel strataflash de- vices are not pin-compatible or drop-in replacements, however the differences are documented below and in most cases, they can be worked around. in those cases where an easy work-around is not possible, this section helps a design engineer choose a minimal fea- ture-set common to both product families. dual footprint layouts designing a dual footprint layout is relatively easy with routing software. as an example, three dual footprint designs are included. the layouts show that standard design rules are sufficient: 6/7 mil track and spacing, 10 mil vias (20 mil pad size/10 mil drill size), and 45 rout- ing. the designs are all done with only two routing lay- ers and separate power and ground planes. although these layouts can be used as shown, it is highly recom- mended that system designers develop their own lay- outs to optimize routing characteristics for their boards. these layouts were generated using innoveta?s (pads) powerpcb ? design studio. sample power- pcb files, gerber schematics, and bit-map images can be obtained from amd?s website or by contacting your local amd sales representative. table 2. amd and intel pinout compatibility feature amd pin(s) intel compatible pin(s) design notes chip enable ce# ce0, ce1, ce2 intel?s 3 chip enable pins could potentially replace chip select logic for cascaded memory arrays for up to eight devices. most designers place such chip select logic in a pld/asic already on board. connect amd?s ce pin to intel?s ce0 pin and tie ce1 and ce2 to gnd. status pin ry/by# sts in default mode the sts functions like ry/by. both are open-drain outputs and should be tied to v cc with a pull-up resistor. hardware write protection wp# v pen wp# can be pulled low to protect first or last two (boot) sectors of memory. strataflash does not have wp# functionality but does use v pen to protect the entire device from alteration. program accelerate pin acc n/a intel chose to remove this functionality on its 3v strata. amd uses the wp#/acc pin as a dual function pin. chip reset reset# rp# both pins reset the device and are active low. i/o buffer power v io v ccq a separate pin for the i/o buffer voltage supply allowing the device to interface with lower voltage range bus signals. available on selected amd memories. address pins dq15/a-1, a0-a23, a24-a25 a0, a1-a24 in byte mode the amd dq15/a-1 pin functions as the byte selector where intel uses a0. remaining pins are connected in sequence amd a0-a23 to intel a1-a24. amd supports a24-a25 for densities up to 1gbit data pins dq0?dq15 dq0?dq15 connect data pins together. byte enable byte# byte# byte# selects between byte mode (x8) and word mode (x16)
4 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices layout i for designs where board space comes at a significant premium, one solution is to place the footprint of an amd am29lvxxx fortified bga inside the footprint of a 56-pin tsop strataflash. the dual footprint effec- tively occupies the same space as a 56-pin tsop foot- print. the appropriate pads from each footprint are then connected together to allow either device to be placed on the board. figure 2. multi-sourced layout for 64-ball fbga amd am29lv640 and 56tsop intel 28f640j3a (layout i) top routing layer bottom routing layer
implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices 5 layout ii a much simpler dual footprint can be achieved using two tsop packages and offsetting the pads for each package. the degree of offset is dependent on the de- sign rules and will define the total amount of board space required for this solution. in this example dual footprint effectively covers 1.5x the same space as a 56-pin tsop footprint. the tighter the design rules the closer the two devices can be placed together. figure 3. multi-sourced layout for amd 56-pin tsop am29lv640m and 56-pin tsop intel 28f640j3a (layout ii) top routing layer bottom routing layer
6 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices layout iii for designs where components can be placed on op- posite sides of the pcb board, amd?s reverse tsop packaging option on some devices allows for an easy dual footprint. in this example the lv640m 56-pin re- verse tsop is placed on one side of the board and intel 56tsop on the other. because of the incompati- ble pinouts between the two devices, the devices can- not be placed directly over each other unless the number of routing layers is increased beyond 2 layers. figure 4. multi-sourced layout for amd 56-pin reverse tsop am29lv640m and 56-pin tsop intel 28f640j3a (layout iii) top routing layer bottom routing layer am29lv640m 28f640j3a
implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices 7 command sets and software compatibility designing dual footprints to insure hardware compati- bility is just one step of implementing a multi-sourced layout. just as much emphasis needs to be placed on software adaptability. amd and intel each use different command sets. amd uses two to six bus cycle com- mands to better prevent unintended commands from being executed due to system noise or errant code ex- ecution. this method provides an additional level of software write protection. most intel commands require only two bus write cycles. figure 3 lists amd and in- tel?s equivalent commands for their ?standard com- mand set? in the address/data format. table 3. amd and intel pinout compatibility for applications that require only minimal flash opera- tions such as reading and programming a device and do not require a highly optimized driver, designers can choose to implement a flash driver that queries the flash device identification (id) and branches to that vendor?s associated instruction set. in this case a man- ufacturer id can be read from internal registers within the flash device to determine which instruction set to use. a sample algorithm has been included that en- ables a flash driver to distinguish between amd and intel devices and branches to the appropriate algo- rithms. device id changes on amd mirrorbit devices amd?s new generation of lv family devices using the breakthrough mirrorbit technology are designed to function as drop-in replacements to the traditional lv devices. the only modification a design engineer must take into account is the new 3-byte device ids amd will implement in this and future generations of flash de- vices. the 3-byte device ids are a change from the tra- ditional single byte ids used in the past and will require the software to use three read-cycles to gather all the information instead of one (see figure 5). for a com- plete up-to-date description of changes to device code structure, refer to publication number 25538: migrating from single-byte to three-byte device ids application note , and datasheets posted on www.amd.com. write buffer and page read buffer options a write buffer is implemented in mirrorbit flash mem- ory devices to speed programming operations. the write buffer is a set of registers that can be used to hold several words that are to be programmed as a group. overall write performance is increased because the overhead operations required to program each byte or word are only performed once for the entire group of words. similarly, a page read buffer in mirrorbit de- vices can be used to increase read performance. for more details on using the write of read buffers, refer to publication number 25539: mirrorbit flash memory write buffer programming and page buffer read ap- plication note . command amd (addr/data) intel (addr/data) read device id 5555h/aah, 2aaah/55h 5555h/90h xxxxh/90h read (reset) mode xxxxh/f0h xxxxh/ffh sector (blk) erase 5555h/aah, 2aaah/55h, 5555h/80h, 5555h/aah, 2aaah/55h, blk addr/30h blk addr/20h, blk addr/d0h program (write) 5555h/aah, 2aaah/55h, 5555h/a0h, addr/data addr/40h, addr/data erase suspend xxxxh/b0h xxxxh/b0h erase resume xxxxh/30h xxxxh/d0h
8 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices figure 5. selecting between amd and intel command sets write aah to address aaah start write 55h to address 555h write 90h to address aaah write f0h to any address write ffh to any address manufacturers id = 01h ? places flash device into amd read identifier (autoselect) mode. intel device ignores first two commands and places flash device into intel read identifier mode. store amd manufacturer?s id and device id in volatile memory. for 3-cycle id devices, device id must be read across 4th, 5th, and 6th cycles. terminate amd read identifier mode by writing a software reset command. intel device is already in read identifier mode. store intel manufacturer?s id and device id in volatile memory. terminate intel read identifier mode (place back in read array mode) . ye s no manufacturers id = 89h ? no read manufacturer?s id from address x00h read manufacturer?s id from address x00h no read manufacturer?s id from address x01h read device id addresses x02h, x1ch, x1eh device is amd flash. use amd command set. ye s device is intel flash. use intel command set. non amd or intel device. note: addresses given are based on byte mode. correct address depends upon device configuration. see application note publication number 22279 for more details.
implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices 9 implementing flexible device drivers with cfi for applications requiring a more optimized driver that will take advantage of device specific functions such as different sector sizes, sector protection, write buffers, or precise timing characteristics system designers can take advantage of a table that stores this data within each flash device. command flash interface (cfi) is a standardized data structure and command set that was specifically created to allow system designers to query the installed flash device to determine its command sets and configuration data. flexible drivers can then be written to take advantage of manufacturer-specific command sets or device-specific features. to use cfi the software must know where to locate vendor-specific information, in what format the data ap- pears, and which parameters are of interest. figure 6 shows an example of a cfi query algorithm that can be used to gather the required information from both amd and intel cfi compliant devices. this algorithm as- sumes you have used an algorithm similar to figure 5 to determine the proper device id and manufacturer id. the first step is to enter cfi mode by sending com- mand 98h to address 55h. the device must be in read array mode to accept this command. a list of address locations can then be read in any order to access any required information in the cfi table. the entire table is structured in two main sections. the first holds stan- dard device identifiers and command sets common to all flash devices such as voltage ranges, timing param- eters and device geometry. the second section con- tains vendor-specific commands such as page mode, sector protection schemes, and top/bottom boot flags. for more detailed information on cfi table structure refer to cfi publication 100 found at www.amd.com/ http://www.amd.com/products/nvd/overview/cfi.html. the algorithm below focuses on the first half of the cfi table by detecting device si ze, erase sector architec- ture, and device timeouts. it can easily be extended to query vendor-specific information.
10 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices figure 6. using cfi to implement flexible drivers write 98h to address 55h start read address 10h, 11h, 12h data = qry ? device is in read array mode issue cfi query to flash device (in word mode) . read unique ascii string "qry" to be sure device is cfi compliant. device size = 2^n bytes. separate read for each erase region found in address 2ch. for uniform devices: number of erase regions = 1. for boot devices: number of erase regions > 1. maximum write buffer size = 2^n bytes. only required if device must be fully optimized for timeouts. can be used to find details on page read buffers and sector protection, etc. return to read array mode. no no ye s uniform sectors ? ye s no read device size: address 27h read timeouts: addresses 1fh?26h no read address for extended commands: address 15h read number of identical sectors: address 2dh read maximum write buffer size: address 2ah read erase block region 1: address 2dh?30h read erase block region 2: address 31h?34h device is not cfi compliant. determine device specific features supported by the vendor?s device. write f0h to any address
implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices 11 uniform vs. boot sectors boot sector devices differ from uniform sector devices because they contain a group of smaller sectors either at the top (top boot device) or bottom (bottom boot de- vice) of the memory map. these smaller sectors are usually used to store boot code or parametric data that can be protected or updated separate from the remain- ing sectors. the cfi algorithm in figure 6 can be used to detect whether a device has uniform or boot sectors. amd?s current lv320 is only offered with boot sectors while intel?s strataflash devices are only offered with uniform sectors. additional software would be required to support both architectures in a dual layout. software for use with boot sector devices must be able to handle these different sector sizes. systems that are read-only or use chip-erase to erase the entire device need not worry about sector architecture. for more de- tails on the differences between uniform or boot sec- tors and the software requirements that need to be considered, refer to amd application note 22374 (mi- grating between boot and uniform sectored flash de- vice). design considerations for ac timing specs systems designers must account for differences in ac timing specifications for both read and write opera- tions. one way to implement flexibility in the design is to design the software to account for the worst-case scenario using max timings of the slowest device, in which case the tables below provide a clear compari- son between vendors. read timings as shown in table 5, are much faster for amd devices. if a designer wants to take full advantage of faster access times for amd devices, the software driver can be written to fully opti- mize timing characteristics by using cfi to query de- vice timings to provide data for the appropriate timing variables. table 4. ac characteristics for read operations for write operations, the ac timings between amd and intel devices differ far more because the two compa- nies take a different approach to address and data latching. amd devices latch the address and data on opposite ends of the write enable pulse (we#). intel latches both address and data on the rising edge of the write pulse. this results in some timing specifications being defined differently between the two companies. as a result, it is difficult to simply write a driver that que- ries cfi and sets the appropriate variables to optimize for program timings. for write operations, the design should allow adequate time for the address and data to be set up and latched on both the rising and falling edges of the write enable pulse (see figure 7). jedec spec description amd (ns) intel (ns) 32mb, 64mb 128mb, 256mb 32mb 64mb 128mb t avav read cycle time (min) 90 100 110 120 150 t avqv address to output delay 90 100 110 120 150 t elqv ce# to output delay 90 100 110 120 150 t glqv oe# to output delay 30 50 t ehqz ce# to output high z 16 55 t ghqz oe# to output high z 16 15
12 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices note: address must be on the bus long enough to be latched at both ends of we#. figure 7. amd and intel address/data latching techniques table 5. ac characteristics for write operations status notification schemes both amd and intel have simplified the work required to design in flash by embedding the algorithms for many common functions of the flash device. this al- lows the device to act both as a memory device and a peripheral unit to the cpu. as with any peripheral unit, amd and intel flash devices also provide a method of monitoring the status of these embedded operations. the actual implementation however, does differ be- tween the two manufacturers. amd provides a status register called the operation status bits that are multiplexed with the data pins after a program or erase operation begins. this register can then be accessed by data polling the device using a simple read cycle. the host system is then free to per- form other task and can poll the device periodically to get latest status of the device. intel uses a similar status register, however the cpu must issue a separate software command to poll the register and a second command to clear the register. ac write spec amd (ns) 32mb-128mb intel (ns) 32mb?128mb notes total write cycle t wc 90 (32, 64mb) 100 (128, 256mb) t wp + t wph 100 minimum time between wp# assertions address setup t avwl 0t avwh 55 setup and hold times differ because of different techniques used by amd and intel to latch address data address hold t wlax 45 t whax 0 data setup t dvwh 45 t dvwh 50 data must be setup earlier to accommodate for intel?s longer setup times data hold t whdx 0t whdx 0 write pulse width t wlwh 35 t wph 70 write pulse width is directly related to data setup time command address program address address ce# we# data data data address address + data address + data address cd cd amd address/data latching intel address/data latching
implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices 13 this method creates added overhead on the host sys- tem and renders the device inactive until the clear sta- tus register command is given. amd and intel both offer a second method for checking the status of the flash device, by using the ready/busy (ry/by# for amd devices, sts# for intel devices) pin. this pin can then be tied directly to an interrupt input of the microprocessor. this way the host system is not re- quired to actively poll the flash device for status infor- mation freeing it to perform other tasks. in default mode intel?s sts# functions just like amd?s ry/by#. both are open-drain outputs and should be tied to v cc with a pull-up resistor. summary the design techniques described in this application note allows designers to take advantage of amd?s su- perior lv family and mirrorbit family flash memory de- vices while having the security of a second source supplier. most mirrorbit memories are footprint compat- ible to amd?s single-bit per cell lv family of flash de- vices. this allows one memory layout to support superior and cost-competitive flash solutions for de- signers requiring densities from 2megabit to 1gigabit.
14 implementing a common layout for amd mirrorbit tm and intel strataflash tm memory devices revision summary revision a (january 2, 2002) initial release. revision a+1 (april 12, 2002) corrected illustrations in figure 3. revision a+2 (october 21, 2002) corrected pinout in figure 1. revision a + 3 (march 5, 2003) updated table 1. updated figure 1. updated table 4. updated table 5. trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are regi stered trademarks of advanced micro devices, inc. product names used in this publication ar e for identification purposes only and may be trademarks of their respective companies .

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