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1 triple, 180 out-of-phase, synchronous step-down pwm controller ISL9444 the ISL9444 is a triple-output synchronous buck controller that integrates three pwm controllers which are fully featured and designed to provide multi-rail power for use in products such as cable and satellite set-top boxes, voip gateways, cable modems, and other home connectivity produc ts as well as a variety of industrial and general purpose applications. each output is adjustable down to 0.7v. the pwms are synchronized at 180 out-of-phase, thus reducing the input rms current and ripple voltage. the ISL9444 offers independent power-good indicators, programmable soft-start and tracking functions for ease of supply rail sequencing and integrated uv/ov/oc/ot protections in a space conscious 5mmx5mm qfn package. switching frequency can be se t between 200khz and 1200khz using a resistor. the ISL9444 can be synchronized to another ISL9444 to reduce any beat frequency. the ISL9444 utilizes internal lo op compensation to keep minimum peripheral components for a compact design and a low total solution cost. these devices are implemented with current mode control with feed-forward to cover various applications even with fixe d internal compensations. related literature ? technical brief tb389 ?pcb land pattern design and surface mount guidelines for qfn (mlfp) packages? features ? three integrated synchronous buck pwm controllers - internal bootstrap diodes - independent programmable output voltage - independent power-good indicators, soft-starting and tracking ?power failure monitor ? light load efficiency enhancement - low ripple diode emulation mode with pulse skipping ? supports pre-biased output ? programmable frequency: 200khz to 1200khz ? adaptive shoot-through protection ? out-of-phase switching (0/180/0) ? no external current sense resistor - uses lower mosfet?s r ds(on) ? complete protection - overcurrent, overvoltage, over-temperature ? wide input voltage range: 4.5v to 26v ? pb-free (rohs compliant) applications ? vox gateway devices ?nas/san devices ? atx power supplies vin ISL9444 vcc_5v pfi pfo extbias fb1 en2,3 isen1 phase1 boot1 ugate1 lgate1 isen2 phase2 boot2 ugate2 lgate2 isen3 phase3 boot3 ugate3 lgate3 + co1 l1 1.0h + cin1 cin2 +12v pgnd sgnd +12v cb1 q1 c1 4.7f cb2 0.1f 0.1f resn1 1.3k ? q2 l2 2.2h resn2 vout1 +1.0v, 6a 100f 1.3k ? vout2 +3.3v, 6a + co2 100f clkout ocset1 r1 10k ? r2 62k ? r3 31.6k ? r4 15.8k ? q3 +12v mode/sync r5 100k ? 0.1f cb3 resn3 1.3k ? l3 3.3h vout3 +5.0v, 6a + co3 100f fb2 ocset2 r6 200k ? pgood1,2,3 ocset2 r7 200k ? fb3 r8 3.09k ? r9 11.5k ? r3 1.74k ? r4 10.7k ? tk/ss2,3 en/ss1 css 10nf rt 49.9k ? rt figure 1. typical application caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. may 23, 2011 fn7665.0
ISL9444 2 fn7665.0 may 23, 2011 pin configuration ISL9444 (40 ld 5x5 qfn) top view ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL9444irz ISL9444 irz -40 to +85 40 ld 5x5 qfn l40.5x5b notes: 1. add ?-t*? for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL9444 . for more information on msl please see techbrief tb363 . phase1 boot1 ugate1 lgate1 lgate2 ugate2 boot2 phase2 fb3 en2 sgnd ocset2 tk/ss2 fb2 en/ss1 rt vcc_5v vin pgood1 ocset1 fb1 tk/ss3 pgnd lgate3 ugate3 boot3 phase3 isen3 clkout 1 isen2 extbias 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 pfi pfo pgood2 pg3_dly ocstet3 pgood3 mode/sync en3 isen1 pin descriptions pin name function 1pfo output of the auxiliary power monitor. pfo goes high if the voltage on pfi is gr eater than 1.2v (typical). otherwise the pfo outputs low. 2 pfi input to the auxiliary power monitor. the internal threshold voltage is 1.2v (typical). 3 extbias input from an optional external 5v bias supply. there is an internal switch from this pin to vcc_5v. this switch closes and supplies the ic power, bypassing the internal linear regulator, when voltage at extbias is higher than 4.7v (typ). do not allow voltage at the extbias pi n to exceed vin at any time. decouple this pin to ground with a small ceramic capacitor (0 .1f to 1f) when it is in use, otherwise tie this pin to ground. do not float this pin. 4 vcc_5v output of the internal 5v linear regulator. this output supplies bias for the ic, the low side gate drivers, and the ext ernal boot circuitry for the high-side gate drivers. the vcc_5v pi n must be always decoupled to power ground with a minimum of 4.7f ceramic capacitor, placed very close to the pin. do not allow the voltage at vcc_5v to exceed vin at any time. 5 vin this pin should be tied to the input rail. it provides power to the internal linear drive circuitry and is also used by the feed-forward controller to adjust the amplitude of each pw m sawtooth. decouple this pin with a small ceramic capacitor (0.1f to 1f) to ground.
ISL9444 3 fn7665.0 may 23, 2011 6 en/ss1 this pin provides an enable/disable function and soft-sta rting for pwm1 output. the output is disabled when the pin is pulled to gnd. during start-up, a regulated 1.55a soft-start current charges an external capacitor connected at this pin. when the voltage on the en/ss1 pin reaches 1.3v, the pwm1 output becomes active. from 1.3v to 2.0v, the reference voltage of the pwm1 is clamped to the voltage at en/ss1 mi nus 1.3v. the capacitance of the soft-start capacitors sets the soft-starting time and enable delay time. setting the soft-starting time too short might create undesirable overshoot at the output during start-up. vcc_5v uvlo di scharges the en/ss1 via an internal mosfet. 7 fb1 pwm1 feedback input. connect fb1 to a resistive voltage divider from the output of pwm1 to gnd to adjust the output voltage. 8 ocset1 a resistor from this pin to ground adjusts the overcurrent threshold for pwm1. 9 rt a resistor from this pin to ground adjusts the switching frequency from 200khz to 1.2mhz. the switching frequency of the pwm controller is determined by the resistor, r t , where t sw is the switching period in s. 10 pgood1 open drain logic output used to indicate the status of th e pwm1 output voltage. this pin is pulled down when the pwm1 output is not within 11% of the nominal voltage. 11 pgood2 open drain logic output used to indicate the status of th e pwm2 output voltage. this pin is pulled down when the pwm2 output is not within 11% of the nominal voltage. 12 pgood3 open drain logic output used to indicate the status of th e pwm3 output voltage. this pin is pulled down when the pwm3 output is not within 11% of the nominal voltage. 13 pg3_dly a capacitor connected between this pin and ground sets a delay between pwm3 output voltage reaching 11% of regulation and pgood3 going high. there is no delay when pwm3 goes out of regulation and pgood3 is pulled low. 14 en2 enable/disable input for pwm2. the output of pwm2 is enable d when this pin is pulled high, and disabled when this pin is pulled low. pgood2 is pulled low 1s after en2 is pulled low. do not leave this pin floating. 15 sgnd this is the small-signal ground common to all 3 controllers. it is suggested to route this separately from the high curre nt ground (pgnd). sgnd and pgnd can be tied together if there is one solid ground plane with no noisy currents around the chip. all voltage levels are measured with respect to this pin. 16 ocset2 a resistor from this pin to ground adjusts the overcurrent threshold for pwm2. 17 fb2 pwm2 feedback input. connect fb2 to a resistive voltage divider from the output of pwm2 to gnd to adjust the output voltage. 18 tk/ss2 dual function pin. the re ference voltage of pwm2 is clamped to the voltage at tk/ss2 during start-up. when this pin is used for tracking, another channel is conf igured as the master and the output vo ltage of the master channel is applied to this pin via a resistor divider. when used for soft-starting control, a soft -start capacitor is connected from this pi n to gnd. a regulated 1.55a soft-starting current charges up the soft-start capacitor. value of the soft-start capacitor sets the pwm2 output voltage ramp. 19 ocset3 a resistor from this pin to ground adjusts the overcurrent threshold for pwm3. 20 fb3 pwm3 feedback input. connect fb3 to a resistive voltage divider from the output of pwm3 to gnd to adjust the output voltage. 21 tk/ss3 dual function pin. the re ference voltage of pwm3 is clamped to the voltage at tk/ss3 during start-up. when this pin is used for tracking, another channel is conf igured as the master and the output vo ltage of the master channel is applied to this pin via a resistor divider. when used for soft-starting control, a soft -start capacitor is connected from this pi n to gnd. a regulated 1.55a soft-starting current charges up the soft-start capacitor. value of the soft-start capacitor sets the pwm3 output voltage ramp. 22 en3 enable/disable input for pwm3. the output of pwm3 is enable d when this pin is pulled high, and disabled when this pin is pulled low. pgood3 is pulled low 1s after en3 is pulled low. do not leave this pin floating. 23 mode/sync dual function pin. tie this pin to ground or vcc_5v for light load operation mode selection. connect this pin to gro und to select diode emulation mode with pulse skipping at light load. while connected to vcc_5v, the controllers operate in pwm mode at light load. connect this pin to clkout of another ISL9444 or an external clock for synchronization. th e controller operates in pwm at light load when synchronized with another ISL9444 or with an external clock. pin descriptions (continued) pin name function r t 23.36 1.5 t sw 0.36 ? () () k ? = (eq. 1)
ISL9444 4 fn7665.0 may 23, 2011 24 isen3 current signal input for pwm3. this pin is used to moni tor the voltage drop across the lower mosfet for current loop feedback and overcurrent protection. 25 phase3 phase node connection for pwm3. this pin is connected to the junction of the upper mosfet?s source, output filter induc tor, and lower mosfet?s drain. phase3 is the in ternal lower supply rail for the ugate3. 26 boot3 bootstrap pin to provide bias for pwm3 high-side driver. th e positive terminal of the boot strap capacitor connects to th is pin. the bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. 27 ugate3 high-side mosfet gate driver output for pwm3. 28 lgate3 low-side mosfet gate driver output for pwm3. 29 pgnd power ground connection for all thr ee pwm channels. this pin should be connec ted to the sources of the lower mosfets and the (-) terminals of the external input capacitors 30 clkout clock signal output. the frequency of the clock signal is two times of the ISL9444 switching frequency set by the resis tor from rt to ground. 31 isen2 current signal input for pwm2. this pin is used to moni tor the voltage drop across the lower mosfet for current loop feedback and overcurrent protection. 32 phase2 phase node connection for pwm2. this pin is connected to the junction of the upper mosfet?s source, output filter induc tor, and lower mosfet?s drain. phase2 is the in ternal lower supply rail for the ugate2. 33 boot2 bootstrap pin to provide bias for pwm2 high-side driver. th e positive terminal of the boot strap capacitor connects to th is pin. the bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. 34 ugate2 high-side mosfet gate driver output for pwm2. 35 lgate2 low-side mosfet gate driver output for pwm2. 36 lgate1 low-side mosfet gate driver output for pwm1. 37 ugate1 high-side mosfet gate driver output for pwm1. 38 boot1 bootstrap pin to provide bias for pwm1 high-side driver. th e positive terminal of the boot strap capacitor connects to th is pin. the bootstrap diodes are integrated to help reduce total cost and reduce layout complexity. 39 phase1 phase node connection for pwm1. this pin is connected to the junction of the up per mosfet?s source, output filter induc tor, and lower mosfet?s drain. phase1 is the in ternal lower supply rail for the ugate1. 40 isen1 current signal input for pwm1. this pin is used to monitor the voltage drop across the lower mosfet for current loop feedback and overcurrent protection. - epad epad at ground potential. solder it directly to gnd plane for better thermal performance. pin descriptions (continued) pin name function
ISL9444 5 fn7665.0 may 23, 2011 block diagram pgood2 pgood1 pgood3 en/ss1 en2 vcc_5v en3 pwm1 oc1 vcc_5v vcc_5v vcc_5v ocp oc2 channel 2 fb2 pwm2 oc3 oc2 oc1 pgnd error amp 1 fb1 180k ? + 0.7v 15pf 1000k ? ref 16k ? _ + isen2 ocset2 2 clock cycles same state for required to latch overcurrent fault channel 3 pwm3 oc3 fb3 isen3 ocset3 fb3 fb2 fb1 ov phase1 ugate1 boot1 lgate1 adaptive dead-time v/i sample timing vin vcc_5v adaptive dead-time phase2 ugate2 boot2 lgate2 pgnd v/i sample timing vcc_5v vcc_5v vcc_5v isen1 sample current sample current + 1.75v reference ocset1 _ + _ + - + rt adaptive dead-time phase3 ugate3 boot3 lgate3 pgnd v/i sample timing channel 1 por fault latch reference enable bias supplies en/ss1 1.55a en/ss1 minimum soft-start tk/ss3 tk/ss2 extbias sgnd 0.7v ref _ + error amp 3 + 1.3v en3 en3 vin sw thres. + _ pfi + _ pfo pf ref clkout duty cycle ramp generator pwm channel phase control mode/sync pg3_dly 2a pgnd (see note 6)
ISL9444 6 fn7665.0 may 23, 2011 typical application - ISL9444 vcc_5v 4 c2 4.7f + pgood3 +12v ugate2 phase2 ISL9444 cin1 r5 co2 37 32 36 7 lgate2 19 isen2 r4 c6 boot2 vin 31 39 r6 38 fb1 ugate1 phase1 co1 lgate1 isen1 r3 c5 boot1 r2 ocset3 40 35 34 33 5 l2 17 sgnd q1 vout1 r1 q2 fb2 vout2 r9 +3.3v, 6a c3 c4 l1 +1.05v, 6a 100f 100k 1.5h 1.0h irf7907 irf7907 30.9k 115k 1.3k 1.3k 10.5k 16.5k 0.1f 10f 47f 10f 0.1f ugate3 phase3 r11 25 lgate3 isen3 r10 c11 boot3 24 r12 28 27 26 l3 20 q3 fb3 vout3 +1.8v, 6a 1.5h irf7907 31.6k 15.8k 1.1k 0.1f c10 10f +12v 8 ocset1 r7 100k 16 ocset2 r8 100k 10 14 pgood1 en2 15 6 21 18 pgnd 29 9 20 vout1 v r13 100k c1 1f 1000pf c12 en/ss1 tk/ss3 tk/ss2 c ss1 10nf c7 470pf c8 47pf c9 dnp pgood rt r15 49.9k r14 25.5k vout2 v pgood1 pgood1 vout1 v r18 100k 49.9k r t extbias 3 100f co3 47f 22 en3 pgood2 19 30 23 mode/sync 2 pfi 1 pfo clkout 13 pg3_dly cdly 47nf c ss2 10nf
ISL9444 7 fn7665.0 may 23, 2011 typical application - ISL9444 sgnd 15 pgnd 29 9 rt r t 118k 30 + en3 +19v ugate2 phase2 ISL9444 + cin2 r6 c8 37 32 36 7 lgate2 19 isen2 r5 c4 boot2 vin 31 29 r7 38 fb1 ugate1 phase1 + c6 lgate1 isen1 r4 c3 boot1 r1 ocset3 vcc_5v 4 40 35 34 33 5 l2 17 q2 vout2 r2 q5 fb2 vout1 r13 +5.0v, 18a cin5 cin7 l1 c2 + 12.0v, 15a 150f 200k 2.2h 2.2h rjk0329dpb 1.74k 10.7k 3.92k 2.0k 3.24k 52.3k 0.22f 10f 4.7f 180f 10f 0.22f 330f ugate3 phase3 + r9 c10 25 lgate3 isen3 r8 c9 boot3 24 r10 27 27 26 l3 20 q7 fb3 vout3 +3.3v, 15a 1.5h 3.09k 11.5k 3.92k 330f cin9 10f +16v 8 ocset1 r11 200k 16 ocset2 r12 200k 11 1 pgood2 pfo 18 21 22 pgood1 + c5 330f + c7 180f c1 0.1f 22pf cff3 tk/ss2 tk/ss3 cin3 150f + cin4 10f cff1 4700pf cff2 1000pf rjk0332dpb q3 q4 rjk0332dpb q6 rjk0329dpb rjk0332dpb cin6 10f extbias rjk0329dpb cin8 10f 0.22f q1 + c11 330f + cin1 150f pgood2 vout1 v rpg 100k 3 extbias c10 0.1f pfo c ss3 47nf 2 pfi 14 en2 +16v v r14 64.9k r15 10k c ss2 47nf 10 pgood1 pgood1 6 en/ss1 c ss1 47nf pgood2 pgood pgood3 12 mode/sync 23 13 pg3_dly clkout r16 200 r3 200 vout1 can be connected to extbias for lower ic power dissipatio n and ic self-bias. external boot diode may be added for pwm2. care must be taken to ensure vin does not drop below extbias.
ISL9444 8 fn7665.0 may 23, 2011 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 typical performance curves of ISL9444 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 internal 5v linear regulator (vcc_5v) and ex ternal vcc bias supply (extbias) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 enable signals and soft-start op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 tracking operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 light load efficiency enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pre-biased power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 frequency synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 out-of-phase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power failure monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 gate control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adaptive dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 internal bootstrap diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power-good indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 protection circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 over-temperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 feedback loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 general powerpad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 component selection guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 mosfet considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output inductor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ISL9444 9 fn7665.0 may 23, 2011 absolute maximum rating s thermal information vcc_5v to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.2v extbias to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc_5v+0.3v vin to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +30v boot1,2,3/ugate1,2,3 to phase1,2,3 . . . . . . . . . -0.3v to vcc_5v+0.3v phase1,2,3 and isen1, 2,3, to gnd . . . . . . . . . . . -5v (<100ns, 10j)/-0.3v (dc) to +28v en/ss1, en2, en3, fb1, fb2, fb3, to gnd . . . . . . -0.3v to vcc_5v+0.3v ocset1, ocset2, ocset3, pg3_ dly, tkss2, tkss3, clkout, lgate1, lgate2, lgate3, to gnd . . . . . . . . . . . . -0.3v to vcc_5v+0.3v rt, mode/sync to gnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc_5v+0.3v pfi, pfo , pgood1, 2, 3, to gnd. . . . . . . . . . . . . . . . -0.3v to vcc_5v+0.3v vcc_5v short circuit to gnd duration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1s esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . 3000v machine model (tested per jesd22-115-c) . . . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c110d) . . . . . . . . . . . . 2000v latch up (tested per jesd78c; class ii, level a, +85c) . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 40 ld qfn package (notes 4, 5) . . . . . . . . 30 2.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . .-55c to +150c maximum operating temperature . . . . . . . . . . . . . . . . . . . . -40c to +85c maximum storage temperature. . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v to 28v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram on page 5 and typical application schematics on pages 6 and 7. v in = 5.0v to 28v, or vcc_5v = 5v 10%, c_vcc_5v = 4.7f, t a = -40c to +85c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 9) typ max (note 9) units v in supply v in input voltage range 4.5 12.0 28.0 v v in supply current i vinq shutdown current (note 7) en/ss1 = en2 = en3 = 0 pgoodx are floating 32 40 a i vinop operating current (note 8) pgood1, pgood2, pgood3 are floating 5 6 ma vcc_5v supply (note 6) v cc operation voltage v in = 12v, i l = 0ma 5.1 5.4 5.7 v internal ldo output voltage v in = 4.5v, i l = 30ma 4.05 4.35 v internal ldo output voltage v in > 5.6v, i l = 75ma 4.5 5.4 v i vcc_max maximum supply current of internal ldo v vcc_5v = 0v, v in = 12v 150 250 ma extbias supply (note 6) v ext_thr switch over threshold voltage, rising extbias voltage 4.5 4.7 4.9 v v ext_thf switch over threshold voltage, falling extbias voltage 4.35 4.5 4.65 v r ext internal switch on resistance v in = 12v 0.5 1.0 undervoltage lockout v uvlothr undervoltage lockout, rising vcc_5v voltage 3.4 3.95 4.45 v v uvlothf undervoltage lockout, falling vcc_5v voltage 3.05 3.60 4.15 v en/ss1, en2, en3 threshold v enss_th en/ss1 threshold 1.10 1.30 1.5 v v en_thr en2, en3 logic th reshold, rising 1.40 1.7 2.00 v v en_thf en2, en3 logic th reshold, falling 1.10 1.25 1.40 v
ISL9444 10 fn7665.0 may 23, 2011 soft-start current i ss en/ss1, tk/ssx soft-start charge current ven/ss1 = vtk/ssx = 0v 1.05 1.55 2.05 a default internal minimum soft-starting t ss_min default internal output ramping time 1.3 2.1 2.9 ms power-fail monitor v pfi_ref pfi input threshold voltage, rising 1.16 1.22 1.28 v v pfi_fal pfi input threshold voltage, falling 1.05 1.12 1.19 v v pfo_l pfo output voltage low i_sink = 1ma 0.3 v v pfo_h pfo output voltage high i_source = 1ma vcc_5v -0.3 v power-good monitors v pgov pgoodx upper threshold, pwm 1, 2 and 3 105.5 111 115.5 % v pguv pgoodx lower threshold, pwm 1, 2 and 3 85 89 94 % v pglow pgoodx low level voltage i_sink = 2ma 0.3 v i pglkg pgoodx leakage current pgoodx = 5v 1 150 na pgood rise time rpullup = 10k to 3.3v 0.05 s pgood fall time rpullup = 10k to 3.3v 0.05 s pgood1, pgood2 timing t pgr vout rising threshold to pgood rising 0.7 1.1 1.5 ms t pgf vout falling threshold to pgood falling 40 75 110 s en2, en3 falling threshold to pgood falling 1.2 1.7 s pgood3 timing pg3_dly charge current v pg3_dly = 1.2v 1.2 1.9 2.6 a pg3_dly threshold voltage (note 9) 1.16 1.195 1.23 v reference section v ref internal reference voltage 0.700 v reference voltage accuracy t a = 0c to +85c -1.0 +1.0 % t a = -40c to +85c -1.15 +1.0 % i fblkg fb bias current (note 9) 100 na pwm controller error amplifiers dc gain (note 9) 88 db gbw gain-bw product (note 9) 15 mhz sr slew rate (note 9) 2.0 v/s pwm regulator t off_min minimum off time rfs = 169k 95 125 155 ns d v ramp peak-to-peak saw-tooth amplitude (note 9) v in = 12v 1.2 v v in = 5.0v 0.55 v ramp offset 1 v electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram on page 5 and typical application schematics on pages 6 and 7. v in = 5.0v to 28v, or vcc_5v = 5v 10%, c_vcc_5v = 4.7f, t a = -40c to +85c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 9) typ max (note 9) units
ISL9444 11 fn7665.0 may 23, 2011 switching frequency (note 9) f sw switching frequency r t = 20.5k 1080 1200 1320 khz switching frequency r t = 169k 168 198 228 khz switching frequency r t = 49.9k 540 600 660 khz v rt rt voltage r t = 49.9k 485 500 515 mv clock output and synchronization v clkh clkout output high isource = 1ma vcc_5v - 0.3 v v clkl clkout output low isink = 1ma 0.3 v f clk clkout frequency r t = vcc_5v 1080 1200 1320 khz f sync sync synchronization range r t = 49.9k 1020 1380 khz light load efficiency mode v modethh mode/sync threshold high 1.3 1.6 1.9 v v modethl mode/sync threshold low 1.1 1.4 1.7 v v cross diode emulaton phase threshold (note 11) v in = 12v -3 mv pwm gate driver (note 9) i gsrc source current 800 ma i gsnk sink current 2000 ma r ug_up upper drive pull-up vcc_5v = 5.0v 1.5 3 ? r ug_dn upper drive pull-down vcc_5v = 5.0v 1.1 2.5 ? r lg_up lower drive pull-up vcc_5v = 5.0v 1.5 3 ? r lg_dn lower drive pull-down vcc_5v = 5.0v 0.6 1.5 ? t gr rise time c out = 1000pf 8 ns t gf fall time c out = 1000pf 10 ns overvoltage protection v ovth ov trip point 114.5 118.5 123.5 % overcurrent protection i ocset overcurrent threshold (ocset_) (note 10) rocset = 55k 32 a full scale input current (isen_) (note 10) 15 a v ocset overcurrent set voltage (ocset_) 1.67 1.74 1.81 v over-temperature (note 9) t ot-th over-temperature shutdown 150 c t ot-hys over-temperature hysteresis 15 c notes: 6. in normal operation, where the device is supplied with voltage on the vin pin, the vcc_5v pin provides a 5v output capable of 75ma (min). when the vcc_5v pin is connected to external 5v supply, the internal ldo regulator is disabled. the voltage at vcc_5v should not exceed the voltage at vin at any time. (refer to the?pin descriptions? on page 2 for more details.) 7. this is the total sh utdown current with v in = 5.6v and 26v. 8. operating current is the supply current consumed when the device is active but not switching. it does not include gate drive current. 9. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. 10. check note 6 for vcc_5v and vin configurations. 11. threshold voltage at phase1, phase2 and phase3 pi ns for turning off the bottom mosfet during dem. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram on page 5 and typical application schematics on pages 6 and 7. v in = 5.0v to 28v, or vcc_5v = 5v 10%, c_vcc_5v = 4.7f, t a = -40c to +85c, typical values are at t a = +25c, unless otherwise specified. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 9) typ max (note 9) units
ISL9444 12 fn7665.0 may 23, 2011 typical performance curves of ISL9444 oscilloscope plot s are taken using the ISL9444eval1z evaluation board, v in = 12v, vout1 = 1.05v, vout2 = 3.3v, vout3 = 1.8v unless otherwise noted. figure 2. shutdown current vs temperature f igure 3. quiescent current vs temperature figure 4. vcc_5v vs load regulation figure 5. so ft-start pin charging current vs voltage on soft-start pin figure 6. normalized output voltage vs voltage on soft-start pin figure 7. phase node waveforms. all output voltages set at 1.05v 30.0 30.5 31.0 31.5 32.0 32.5 33.0 -40 -20 0 20 40 60 80 100 temperature (c) shutdown current (a) 4.3 4.5 4.7 4.9 5.1 5.3 -40-200 20406080100 o operating current (ma) temperature (c) v in = 28v v in = 4.5v 0 1 2 3 4 5 6 0 50 100 150 200 250 vcc_5v load current (ma) vcc_5v voltage (v) 0 0.4 0.8 1.2 1.6 2.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 soft-start pin voltage (v) channel 3 channel 1/2 soft-start pin charging current (a) 0 20 40 60 80 100 120 0 0.51.01.52.02.53.03.54.04.5 soft-start pin voltage (v) channel 2/3 channel 1 normalized output voltage (%) pwm1 pwm2 pwm3 time @ 1s/div
ISL9444 13 fn7665.0 may 23, 2011 figure 8. switching frequency vs temperature (r t = 49.9k ? ) figure 9. reference voltage vs temperature figure 10. pwm1 efficiency and load regulation figure 11. pwm1 input current comparison with mode = ccm/dem figure 12. pwm2 efficiency and load regulation figure 13. pwm2 input current comparison with mode = ccm/dem typical performance curves of ISL9444 oscilloscope plot s are taken using the ISL9444eval1z evaluation board, v in = 12v, vout1 = 1.05v, vout2 = 3.3v, vout3 = 1.8v unless otherwise noted. (continued) 550 570 590 610 630 650 -40 -20 0 20 40 60 80 100 temperature (c) switching frequency (khz) 680 690 700 710 720 -40 -20 0 20 40 60 80 100 temperature (c) reference voltage (mv) 1.035 1.039 1.043 1.047 1.051 1.055 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 load current (a) efficiency (%) pwm1 output voltage (v) efficiency ccm (%) efficiency dem (%) vout1 (v) 0.001 0.010 0.100 1.000 0.01 0.1 1 10 load current (a) input current (a) dem ccm 3.280 3.284 3.288 3.292 3.296 3.300 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 load current (a) efficiency (%) efficiency ccm (%) efficiency dem (%) vout2 (v) pwm2 output voltage (v) 0.001 0.010 0.100 1.000 10.000 0.01 0.1 1 10 load current (a) input current (a) dem ccm
ISL9444 14 fn7665.0 may 23, 2011 figure 14. pwm3 efficiency and load regulation figure 15. pwm3 input current comparison with mode = ccm/dem figure 16. pwm1 start-up. mode = ccm, load = 0a figure 17. pwm1 start-up. mode = dem, load = 0a figure 18. pwm2 start-up. mode = ccm, load = 0a figure 19. pwm2 start-up. mode = dem, load = 0a typical performance curves of ISL9444 oscilloscope plot s are taken using the ISL9444eval1z evaluation board, v in = 12v, vout1 = 1.05v, vout2 = 3.3v, vout3 = 1.8v unless otherwise noted. (continued) 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 load current (a) efficiency (%) pwm3 output voltage (v) 1.790 1.794 1.798 1.800 1.792 1.796 efficiency dem (%) efficiency ccm (%) vout3 (v) 0.001 0.010 0.100 1.000 10.000 0.01 0.1 1 10 load current (a) dem ccm input current (a) enss1 @ 2v/div vout1 @ 1v/div pgood1 @ 5v/div time @ 5ms/div inductor current @ 1a/div enss1 @ 2v/div vout1 @ 1v/div pgood1 @ 5v/div inductor current @ 1a/div time @ 5ms/div tkss2 @ 2v/div vout2 @ 2v/div pgood2 @ 5v/div inductor current @ 2a/div time @ 5ms/div time @ 5ms/div tkss2 @ 2v/div vout2 @ 2v/div pgood2 @ 5v/div inductor current @ 1a/div
ISL9444 15 fn7665.0 may 23, 2011 figure 20. pwm3 start-up. mode = ccm, load = 0a figure 21. pwm3 start-up. mode = dem, load = 0a figure 22. pwm1 output ripple, mode = 0v (dem) f igure 23. pwm1 output ripple, mode = 5v (ccm) figure 24. pwm load transient response figure 25. pwm1 ocp response. output short-circuited to ground and released. typical performance curves of ISL9444 oscilloscope plot s are taken using the ISL9444eval1z evaluation board, v in = 12v, vout1 = 1.05v, vout2 = 3.3v, vout3 = 1.8v unless otherwise noted. (continued) tkss3 @ 2v/div vout3 @ 1v/div pgood3 @ 5v/div time @ 5ms/div inductor current @ 2a/div tkss3 @ 2v/div vout3 @ 1v/div pgood3 @ 5v/div inductor current @ 2a/div time @ 5ms/div vout1 @ 20mv/div. load = 0ma vout1 @ 20mv/div. load = 100ma vout1 @ 20mv/div. load = 1000ma time @ 2ms/div time @ 2s/div time @ 2s/div vout1 @ 20mv/div. load = 0ma vout1 @ 20mv/div. load = 100ma vout1 @ 20mv/div. load = 1000ma time @ 2s/div time @ 2s/div time @ 2s/div 2a vout3 @ 100mv/div vout2 @ 100mv/div 4a 2a time @ 20s/div vout1 @ 100mv/div enss1 @ 5v/div vout1 @ 1v/div output current @ 10a/div pgood1 @ 5v/div time @ 50ms/div
ISL9444 16 fn7665.0 may 23, 2011 functional description general description the ISL9444 integrates control circuits for three synchronous buck converters. the three synchronous bucks operate out- of-phase to substantially reduce the input ripple and thus reduce the input filter requirements. each part has 3 independent enable/disable control lines (en/ss1, en2 and en3), which provide flexible power-up sequencing. the soft-start time is programmable individually by adjusting the soft-start capacitors connected from en/ss1, tk/ss2 and tk/ss3, respectively. the valley current mode control scheme with input voltage feed-forward ramp simplifies loop compensation and provides excellent rejection to input voltage variation. input voltage range the ISL9444 is designed to operat e from input supplies ranging from 4.5v to 28v. the input voltage range can be effectively limited by the available minimum pwm off time. where, v d1 = sum of the parasitic voltage drops in the inductor discharge path, including the lower fet, inductor and pc board. v d2 = sum of the voltage drops in the charging path, including the upper fet, inductor and pc board resistances. the maximum input voltage and minimum output voltage is limited by the minimum on-time (t on(min) ). where t on(min) = 100ns. internal 5v linear regulator (vcc_5v) and external vcc bias supply (extbias) all ISL9444 functions can be intern ally powered from an on-chip, low dropout 5v regulator or an ex ternal 5v bias voltage via the extbias pin. bypass the linear regulator?s output (vcc_5v) with a 4.7f capacitor to the power gr ound. the ISL9444 also employs an undervoltage lockout circuit which disables all regulators when vcc_5v falls below 3.6v. the internal ldo can source over 75ma to supply the ic, power the low side gate drivers and charge the boot capacitors. when driving large fets at high switching frequency, little or no regulator current may be available for external loads. for example, a single large fet with 15nc total gate charge requires 15nc x 300khz = 4.5ma (15nc x 600khz = 9ma). also, at higher input voltages with larger fets, the power dissipation across the internal 5v will incr ease. excessive dissipation across this regulator must be avoided to prevent junction temperature rise. thermal protection may be triggered if die temperature increases above +150c due to excessive power dissipation. when large mosfets are used, an external 5v bias voltage can be applied to extbias pin to alleviate excessive power dissipation. voltage at the extb ias pin must always be lower than the voltage at the vin pin to prevent biasing of the power stage through extbias and vcc_5v. an external uvlo circuit might be necessary to guarantee smooth soft-starting. the internal ldo has an overcurren t limit of typically 150ma. for better efficiency, connect vcc_5v to vin for 5v 10% input applications. enable signals and soft-start operation typical applications for the is l9444 use programmable analog soft-start or the tk/ssx pins for tracking. the soft-start time can be set by the value of the soft-start capacitors connected from the en/ss1 for pwm1 to ground and from tk/ssx pins to ground for pwm2 and pwm3. inrush current during start-up can be alleviated by adjusting the soft-starting time. after the vcc_5v pin reaches th e uvlo threshold, the ISL9444 pwm1 soft-start circuitry become s active. the internal 1.55a charge current begins charging up the soft-start capacitor connected from the en/ss1 pi n to gnd. the pwm1 output remains inactive until voltage on the en/ss1 pin reaches 1.3v. as the voltage on the en/ss1 pi n rises from 1.3v to 2v, the pwm1 reference voltage is cl amped to the voltage on the en/ss1 pin minus 1.3v. pwm1 output voltage thus rises from 0v to regulation as en/ss1 rises from 1.3v to 2v. charging of the soft-start capacitor continues unti l the voltage on the en/ss1 pin reaches 3.5v. power sequencing can be achieved by using the pgoodx and enx pins. when the enx pin is pu lled high, the internal 1.55a charge current begins charging up the soft-start capacitor connected from the tk/ssx pin to gnd. the respective reference voltage is clamped to the voltage on the tk/ssx pin. thus, pwm2 and pwm3 output voltages ramp from 0v to regulation as voltage on tk/ss2 and tk/ss3 goes up from 0v to 0.7v. charging of the soft-start capaci tors continues until the voltage on the tk/ssx reaches 3.5v. the typical soft-start time is set according to equation 4: for pwm2 and pwm3, when the soft-starting time set by external c ss or tracking is less than 2ms, an internal soft-start circuit of 2ms takes over the soft-start. there is no internal soft-start for pwm1. pgoodx will toggle to high when the corresponding output is up and in regulation. pulling the enx low disables th e corresponding pwm channel. the tk/ssx pin will also be discharged to gnd by internal mosfets. output voltage programming the ISL9444 provides a precision internal reference voltage to set the output voltage. based on this internal reference, the output voltage can thus be set from 0.7v up to a level determined by the input voltage, the maximum duty cycle, and the conversion efficiency of the circuit. v in min () v out v d1 + 1t ? off min () frequency ----------------------------------------------------------------------- ?? ?? ?? v d2 v d1 ? + = (eq. 2) v in max () v out x v out t on min () frequency ----------------------------------------------------------- - ?? ?? ?? (eq. 3) t ssx 0.7v c ssx 1.55 a ------------------- - ?? ?? = (eq. 4)
ISL9444 17 fn7665.0 may 23, 2011 a resistive divider from the outp ut to ground sets the output voltage of any pwm channel. the center point of the divider shall be connected to the fbx pin. the output voltage value is determined by equation 5. where r1 is the top resistor of the feedback divider network and r2 is the bottom resistor connected from fbx to ground. tracking operation the pwm2 and pwm3 of the isl9 444 can be independently set up to track the output of another pwm or an external supply. in the following discussion, we refer to the voltage rail to be tracked as the master rail while we refer to the voltage rail that follows the master as the slave rail. to implement tracking, an additional resistive divider is connected between the master rail and ground. the center point of the divider shall be connected to the tk/ssx pin of the slave pwm. the resistive divider ratio sets the ramping ratio between the two voltage rails. to implement coincident tracking, set the tracki ng resistive divi der ratio exactly the same as the slave rail output resistive divider given by equation 5. make sure that the vo ltage at tk/ssx is greater than 0.7v when the master rail reaches regulation. to minimize the impact of the 1.55a soft-start current on the tracking function, it is recommen ded to use resistors of less than 10k for the tracking resistive dividers. when overcurrent protection (ocp) is triggered for the slave pwm channel, the internal minimum soft-start circuit determines the ocp soft-start hiccup. light load efficiency enhancement when mode/sync is tied to gnd, the ISL9444 operates in high efficiency diode emulation mode and pulse skipping mode in light load condition. the inductor current is not allowed to reverse (discontinuous operation). at very light loads, the converter goes into diode emulation and triggers the pulse skipping function. here, the upper mosfet remains off until the output voltage drops to the point the error amplif ier output goes above the pulse skipping mode threshold. the minimum t on in the pulse skipping mode is 80ns; please select frequency so that the pwm t on is greater than 80ns at maximum vin at no load. pre-biased power-up the ISL9444 has the ability to soft -start with a pre-biased output. the output voltage would not be yanked down during pre-biased start-up. the pwm is not active until the soft-start ramp reaches the output voltage times the resistive divider ratio. overvoltage protection is alive during soft-starting. frequency selection switching frequency selection is a trade-off between efficiency and component size. low switching frequency improves efficiency by reducing mosfet switching loss. to meet output ripple and load transient requ irements, operat ion at a low switching frequency would require larger inductance and output capacitance. the switching frequency of the ISL9444 is set by a resistor connected from the rt pin to gnd according to equation 1. frequency setting curve shown in figure 26 assists in selecting the correct value for r t . frequency synchronization the mode/sync pin may be used to synchronize two or more ISL9444 or isl9443 controllers. when the mode/sync pin is connected to the clkout pin of another ISL9444, the two controllers operate in synchronization. when the mode/sync pin is connected to an external clock, the ISL9444 will synchronize to this external clock at half of the clock frequency. for proper operation, frequency setting resistor, r t , should be set according to equation 1. when frequency synchronization is in action, the controllers will enter forced continuous cu rrent mode at light load. out-of-phase operation to reduce input ripple current, the three pwm channels operate 180 out-of-phase. this reduces the input capacitor ripple current requirements, reduces power supply-induced noise, and improves emi. this effectively helps to lower component cost, save board space and reduce emi. triple pwms traditionally operate in-phase and turn on all three upper fets at the same time. the input capacitor must then support the instantaneous current requir ements of the three switching regulators simultaneously, resultin g in increased ripple voltage and current. the higher rms ripple current lowers the efficiency due to the power loss associated with the esr of the input capacitor. this typically requires more low-esr capacitors in parallel to minimize the input voltage ripple and esr-related losses, or to meet the required ripple current specification. with synchronized out-of-phase operation, the high-side mosfets turn off 180 out-of-phase. the instantaneous input current peaks of both regulators no longer overlap, resulting in reduced rms ripple current and input voltage ripple. this reduces the required input capacitor ripple current rating, v outx 0.7v r1 r2 + r2 --------------------- - ?? ?? = (eq. 5) figure 26. r t vs switching frequency r t (k ? ) frequency (khz) 0 250 500 750 1000 1250 0 20 40 60 80 100 120 140 160 180
ISL9444 18 fn7665.0 may 23, 2011 allowing fewer or less expensive capacitors, and reducing the shielding requirements for emi. the typical operating curves show the synchronized 180 out-of-phase operation. power failure monitor the ISL9444 has a power-failure monitor that helps to monitor an additional critical voltage on the power-fail input (pfi) pin. for example, the pfi pin could be used to provide an early power-fail warning, detect a low-battery condition, or simply monitor a power supply. an external resistor divider network is needed to provide monitoring of voltages greater than 1.22v. the threshold voltage is set according to equati on 6 (see typical application on page 7). pfo goes low whenever the pfi pin voltage is less than the 1.22v threshold voltage. gate control logic the gate control logic translates generated pwm signals into gate drive signals providing amplification, level shifting and shoot-through protection. the gate drivers have circuitry that helps optimize the ic performance over a wide range of operational conditions. as mosfet switching times can vary dramatically from type to type and with input voltag e, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower mosfets. shoot -through control logic provides a 16ns dead-time to ensure that both the upper and lower mosfets will not turn on simultaneously causing a shoot-through condition. gate drivers the low-side gate drivers are supplied from vcc_5v and provide a peak sink current of 2a and source current of 800ma for each pwm channel. the high-side gate drivers are also capable of delivering the same currents as the low-side gate drivers. gate-drive voltage for the upper n-channel mosfets are generated by flying capacitor boot circuits. a boot capacitor connected from the boot pin to the phase node provides power to the high-side mosfet driver. to limit the peak current in the ic, an external resistor may be placed between the boot pin and the boot capacitor. this small series resistor also damps any oscillations caused by the reso nant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. at start-up, the low-side mosfet turns on first and forces phase to ground in order to charge the boot capacitor to 5v. after the low-side mosfet turns off, the hi gh-side mosfet is turned on by closing an internal switch between boot and ugate. this provides the necessary gate-to-source voltage to turn on the upper mosfet, an action that boosts the 5v gate drive signal above vin. the current required to drive the upper mosfet is drawn from the internal 5v regulator. for optimal emi performance or re ducing phase node ringing, a small resistor might be placed between these pins to the positive terminal of the bootstrap capacitors. adaptive dead time the ISL9444 incorporates an adap tive dead time algorithm on the synchronous buck pwm contro llers that optimizes operation with varying mosfet conditions. this algorithm provides approximately 16ns of dead ti me between switching the upper and lower mosfet?s. this dead time is adaptive and allows operation with different mosfet?s without having to externally adjust the dead time using a resist or or capacitor. during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches a threshold of 1v, at whic h time the ugate is released to rise. adaptive dead time circuitry monito rs the upper mosfet gate voltage during ugate turn-off. once the upper mosfet gate-to-source voltage has dropped below a threshold of 1v, the lgate is allowed to rise. it is recommended to not use a resistor between ugate and lgate and the respective mosfet gates as it may interfere with the dead time circuitry. internal bootstrap diode the ISL9444 has integrated bootstrap diodes to help reduce total cost and reduce layout complexity. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap capacitor must have a maximum voltage rating above the maximu m input voltage plus 5v. the bootstrap capacitor can be chosen from equation 7. where q gate is the amount of gate charge required to fully charge the gate of the upper mosfet. the v boot term is defined as the allowable droop in the rail of the upper drive. as an example, suppose an upper mosfet has a gate charge (qgate) of 25nc at 5v and also assume the droop in the drive voltage over a pwm cycle is 200mv. one will find that a bootstrap capacitance of at least 0.125f is required. the next larger standard value capacitance of 0.22f should be used. a good quality ceramic capacitor is recommended. the internal bootstrap schottky di odes have a resistance of 1.5 ? (typ) at 800ma. combined with th e resistance rboot, this could lead to the boot capacitor charging insufficiently in cases where the bottom mosfet is turned on for a very short time. if such vpfith 1.22v r14 r15 + r15 ---------------------------- - = (eq. 6) boot ugate phase vcc_5v vin ISL9444 figure 27. upper gate driver circuit c b r boot optional external schottky c boot q gate v boot -------------------- - (eq. 7)
ISL9444 19 fn7665.0 may 23, 2011 circumstances are expected, an additional external schottky diode may be added from vcc_5v to the positive of the boot capacitor. rboot may still be necessary to lower emi due to fast turn-on of the upper mosfet. power-good indicators the three independent power-good pins can be used to monitor the status of the output voltages. pgoodx will be true (open drain) when the corresponding fbx pin is within 11% of the reference voltage. additionally, a capacitor from the pg3_dly pin to the ground sets a delay time for the pgood3 signal. after fb3 pin enters 11% of the reference range, a 1.9a cu rrent begins charging the cdly capacitor. when the pg3_dly voltage reaches 1.2v pgood3 goes high. the typical delay time is set according to equation 8: there is no extra delay when the pgood3 pin is pulled low. protection circuits the converter outputs are monitored and protected against overload, short circuit and undervoltage conditions. undervoltage lockout the ISL9444 includes uvlo protection which keeps the device in a reset condition until a proper operating voltage is applied. it also shuts down the ISL9444 if the operating voltage drops below a pre-defined value. all controllers are disabled when uvlo is asserted. when uvlo is asserted, pgood1, pgood2 and pgood3 are valid and will be de-asserted. overcurrent protection all the pwm controllers use the lower mosfet's on-resistance, r ds(on) , to monitor the current in the converter. the sensed voltage drop is compared with a threshold set by a resistor connected from the ocsetx pin to ground. where i oc is the desired overcurrent protection threshold, and r cs is a value of the current sense resistor connected to the isenx pin. if an overcurrent is detected, the upper mosfet remains off and the lower mosfet remains on until the next cycle. as a result, the converter will skip a pulse. when the overload condition is removed, the converter will resume normal operation. if an overcurrent is detected for 2 consecutive clock cycles, the ic enters a hiccup mode by turning off the gate drivers and entering soft-start. the ic will cycle 5 times through soft-start before trying to restart. the ic will continue to cycle through soft-start until the overcurrent condition is removed. hiccup mode is active during soft-start so care must be taken to ensure that the peak inductor current does not exceed the overcu rrent threshold during soft-start. because of the nature of this current sensing technique, and to accommodate a wide range of r ds(on) variations, the value of the overcurrent threshold should repr esent an overload current about 150% to 180% of the maximum operating current. if more accurate current protection is desired, place a current sense resistor in series with the lower mosfet source. when ocp is triggered, the en/ss1 or tk/ssx pins are pulled to ground by an internal mosfet. for pwm rails configured to track another voltage rail, the tk/ssx pin rises up much faster than the internal minimum soft-start ramp. the voltage reference will then be clamped to the internal minimum soft-start ramp. thus smooth soft-start hiccup is achiev ed even with tracking function. overvoltage protection all switching controllers within the ISL9444 have fixed overvoltage set points. the overvoltage set point is set at 118% of the nominal output voltage, the output voltage set by the feedback resistors. in the case of an overvoltage event, the ic will attempt to bring the output voltage back into regulation by keeping the upper mosfet turned off and modulating the lower mosfet for 2 consecutive pwm cycles. if the overvoltage condition has not been corrected in 2 cycles and the output voltage is above 118% of the nominal output voltage, the ISL9444 will turn off both th e upper mosfet and the lower mosfet. the ISL9444 will enter hiccup mode until the output voltage returns to 110% of the nominal output voltage. over-temperature protection the ic incorporates an over-tempe rature protection circuit that shuts the ic down when a die temperature of +150c is reached. normal operation resu mes when the die temperatures drops below +130c through the in itiation of a full soft-start cycle. when all three channels are disabled, thermal protection is inactive. this helps achieve a very low shutdown current of 33a. feedback loop compensation to reduce the number of external components and to simplify the process of determining compensation components, all pwm controllers have internally compensated error amplifiers. to make internal compensation possible, several design measures were taken. firstly, the ramp signal app lied to the pwm comparator is proportional to the input voltage provided at the vin pin. this keeps the modulator gain constant with varying input voltages. secondly, the load current proporti onal signal is derived from the voltage drop across the lowe r mosfet during the pwm time interval and is subtracted from the amplified error signal on the comparator input. this creates an internal current control loop. the resistor connected to the isen pin sets the gain in the current feedback loop. the following expression estimates the required value of the current sense resistor depending on the maximum operating load current and the value of the mosfet?s r ds(on) . choosing r cs to provide 30a of current to the current sample and hold circuitry is recommended but values down to 2a and t dly 1.2v c dly 1.9 a --------------- - ?? ?? = (eq. 8) r ocset 7 () r cs () i oc () r ds on () () --------------------------------------- = (eq. 9) r cs i max () r ds on () () 30 a ------------------------------------------- - (eq. 10)
ISL9444 20 fn7665.0 may 23, 2011 up to 100a can be used. a higher sampling current will help to stabilize the loop. due to the current loop feedback, the modulator has a single pole response with -20db slope at a fr equency determined by the load. where r o is load resistance and c o is load capacitance. for this type of modulator, a type 2 compensation circuit is usually sufficient. figure 28 shows a type 2 amplif ier and its response, along with the responses of the current mode modulator and the converter. the type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a fl at gain region at frequencies between the zero and the pole. zero frequency, amplifier high-frequency gain and modulator gain are chosen to satisfy most typical applications. the crossover frequency will appear at the point where the modulator attenuation equals the amplifier high frequency gain. the only task that the system designer has to complete is to specify the output filter capacitors to position the load main pole somewhere within one decade lower than the amplifier zero frequency. with this type of compensation, plenty of phase margin is easily achieved due to zero-pole pair phase ?boost?. conditional stability may occur only when the main load pole is positioned too much to the left side on the frequency axis due to excessive output filter capacitance. in this case, the esr zero placed within the 1.2khz to 30k hz range gives some additional phase ?boost?. some phase boos t can also be achieved by connecting capacitor c z in parallel with the upper resistor r 1 of the divider that sets the output voltage value. please refer to ?input capacitor selection? on page 22. layout guidelines careful attention to layout requirements is necessary for successful implementation of an ISL9444 based dc/dc converter. the ISL9444 switches at a very high frequency and therefore the switching times are very short. at these switching frequencies, even the shortest trace has significant impedance. also, the peak gate drive curre nt rises significantly in an extremely short time. transition speed of the current from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, generate emi, increase device overvoltage stress and ringing. careful component selection and proper pc board layout minimizes the magnitude of these voltage spikes. there are three sets of critical components in a dc/dc converter using the ISL9444: the controller, the switching power components and the small signal components. the switching power components are the most cr itical from a layout point of view because they switch a large amount of energy so they tend to generate a large amount of no ise. the critical small signal components are those connected to sensitive nodes or those supplying critical bias currents. a multi-layer printed circuit board is recommended. layout considerations 1. the input capacitors, upper fet, lower fet, inductor and output capacitor should be plac ed first. isolate these power components on the topside of the board with their ground terminals adjacent to one an other. place the input high frequency decoupling ceramic capacitors very close to the mosfets. 2. use separate ground planes for power ground and small signal ground. connect the sgnd and pgnd together close to the ic. do not connect them together anywhere else. 3. the loop formed by the input capacitor, the top fet and the bottom fet must be kept as small as possible. 4. ensure the current paths from the input capacitor to the mosfet, to the output inductor and output capacitor are as short as possible with maximum allowable trace widths. 5. place the pwm controller ic close to the lower fet. the lgate connection should be short and wide. the ic can be best placed over a quiet ground area. avoid switching ground loop currents in this area. 6. place vcc_5v bypass capacitor very close to vcc_5v pin of the ic and connect its ground to the pgnd plane. 7. place the gate drive componen ts - optional boot diode and boot capacitors - together near controller ic. 8. the output capacitors should be placed as close to the load as possible. use short wide copper regions to connect output capacitors to load to avoid inductance and resistances. 9. use copper filled polygons or wide but short trace to connect the junction of upper fet, lower fet and output inductor. also keep the phase node connection to the ic short. do not unnecessarily oversize the co pper islands for phase node. since the phase nodes are subjected to very high dv/dt f po 1 2 r o c o ?? ------------------------------ = (eq. 11) f z 1 2 r 2 c 1 ?? ----------------------------- - 10khz == (eq. 12) f p 1 2 r 1 c 2 ?? ----------------------------- - 600khz == (eq. 13) figure 28. feedback loop compensation r1 r2 c1 c2 f po f z f p f c modulator ea converter type 2 ea g ea = 18db g m = 17.5db
ISL9444 21 fn7665.0 may 23, 2011 voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. 10. route all high speed switchin g nodes away from the control circuitry. 11. create a separate small anal og ground plane near the ic. connect the sgnd pin to this pl ane. all small signal grounding paths including feedback resi stors, current limit setting resistors, soft-starting capacitors and enx pull-down resistors should be connected to this sgnd plane. 12. separate current sensing traces from phase node connections. 13. ensure the feedback connection to the output capacitor is short and direct. general powerpad design considerations the following is an example of how to use vias to remove heat from the ic. it is recommended to fill the thermal pad area with vias. a typical via array fills the thermal pad footprint such that their centers are 3x the radius apart from each other. keep the vias small but not so small that their inside diam eter prevents solder wicking through during reflow. connect all vias to the ground plan e. it is important the vias have a low thermal resistance for ef ficient heat transfer. it is important to have a complete connection of the plated-through hole to each plane. component selection guideline mosfet considerations the logic level mosfets are chosen for optimum efficiency given the potentially wide input voltage range and output power requirements. two n-channel mosfets are used in each of the synchronous-rectified buck converters for the 3 pwm outputs. these mosfets should be selected based upon r ds(on) , gate supply requirements, and thermal management considerations. power dissipation includes two loss components: conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycle (see equations 14 and 15). the conduction losses are the main component of power dissipation for the lower mosfets. only the upper mosfet has significant switching losses, since the lower device turns on and off into near zero voltage. the equations assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower mosfet?s body diode. a large gate-charge increases the switching time, t sw , which increases the upper mosfets? swit ching losses. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal- resistance specifications. output inductor selection the pwm converters require output inductors. the output inductor is selected to meet the output voltage ripple requirements. the inductor value determines the converter?s ripple current and the ripple voltage is a function of the ripple current and the output capacitor(s) esr. the ripple voltage expression is given in the capa citor selection section and the ripple current is approximated by equation 16: output capacitor selection the output capacitors for each output have unique requirements. in general, the output capacitors should be selected to meet the dynamic regulation requirements including ripple voltage and load transients. selection of output capacitors is also dependent on the output inductor, so some in ductor analysis is required to select the output capacitors. one of the parameters limiting the converter?s response to a load transient is the time required for the inductor current to slew to its new level. the ISL9444 will provide either 0% or maximum duty cycle in response to a load transient. the response time is the time interval required to slew the inductor current from an initial current value to the load current level. during this interval, the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). minimizing the response time can minimize the output capacitance required. al so, if the load transient rise time is slower than the inductor response time, as in a hard drive or cd drive, it reduces the requirement on the output capacitor. the maximum capacitor value required to provide the full, rising step, transient load current duri ng the response time of the inductor is: where c out is the output capacitor(s) required, l o is the output inductor, i tran is the transient load current step, v in is the input figure 29. pcb via pattern p upper i o 2 () r ds on () () v out () v in --------------------------------------------------------- - i o () v in () t sw () f sw () 2 ------------------------------------------------------- - + = (eq. 14) p lower i o 2 () r ds on () () v in v out ? () v in ------------------------------------------------------------------------ = (eq. 15) i l v in v out ? () v out () f s () l () v in () -------------------------------------------------- - = (eq. 16) c out l o () i tran () 2 2v in v o ? () dv out () ---------------------------------------------------- - = (eq. 17)
ISL9444 22 fn7665.0 may 23, 2011 voltage, v o is output voltage, and dv out is the drop in output voltage allowed during the load transient. high frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (equivalent series resistance) an d voltage rating requirements as well as actual capacitance requirements. the output voltage ripple is due to the inductor ripple current and the esr of the output capacitors as defined by: where i l is calculated in the ?input capacitor selection? on page 22. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load circuitry for specific decoupling requirements. use only specialized low-esr capacitors intended for switching-regulator applications fo r the bulk capacitors. in most cases, multiple small-case electrolytic capacitors perform better than a single large-case capacitor. the stability requirement on the se lection of the output capacitor is that the ?esr zero? (f z ) be between 2khz and 60khz. this range is set by an internal, single compensation zero at 8.8khz. the esr zero can be a factor of five on either side of the internal zero and still contribute to increased phase margin of the control loop. therefore: in conclusion, the output capaci tors must meet three criteria: 1. they must have sufficient bulk capacitance to sustain the output voltage during a load transient while the output inductor current is slewing to the value of the load transient. 2. the esr must be sufficiently low to meet the desired output voltage ripple due to the output inductor current. 3. the esr zero should be placed, in a rather large range, to provide additional phase margin. the recommended outp ut capacitor value for the ISL9444 is between 100f to 680f, to meet stability criteria with external compensation. use of aluminum electrolytic (poscap) or tantalum type capacitors is recommended. use of low esr ceramic capacitors is possible with loop analysis to ensure stability. input capacitor selection the important parameters for the bulk input capacitor(s) are the voltage rating and the rms current rating. for reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a conservative guideline. the ac rms input current varies with the load. the total rms current supplied by the input capacitance is: where dc is duty cycle of the respective pwm. depending on the specifics of the input power and its impedance, most (or all) of this current is supplied by the input capacitor(s). figure 30 shows the advantage of having the pwm converters operating out-of-phase. if the converters were operating in phase, the combin ed rms current would be the algebraic sum, which is a much larger value as shown. the combined out-of-phase current is the square root of the sum of the square of the individual reflected currents and is significantly less than the combined in-phase current. use a mix of input bypass capacitors to control the voltage ripple across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small ceramic capacitors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. for board designs that allow through-hole components, the sanyo os-con? series offer low esr and good temperature performance. for surface moun t designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. the tps series available from avx is surge current tested. v ripple i l esr () = (eq. 18) c out 1 2 esr () f z () --------------------------------- - = (eq. 19) i rms i rms1 2 i rms2 2 + = (eq. 20) i rmsx dc dc 2 ? i o ? = (eq. 21) figure 30. input rms current vs load 12345 3.3v and 5v load current input rms current 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 in phase out-of-phase 5v 3.3v
ISL9444 23 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7665.0 may 23, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: ISL9444 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change may 23, 2011 fn7665.0 initial release
ISL9444 24 fn7665.0 may 23, 2011 package outline drawing l40.5x5b 40 lead quad flat no-lead plastic package rev 0, 5/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.10 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view jedec reference drawing: mo220vhhe-1 7. 5.00 a b index area pin 1 6 5.00 (4x) 0.15 40 1 10 11 20 21 30 31 36x 0.40 4x 3.6 pin #1 6 exp. dap 3 .50 b c 0.10 m a 40x 0.20 4 40x 0.40 0.10 see detail "x" max 1.00 c seating plane 0.08 c c 0.10 0 . 00 min. 0 . 05 max. 5 0 . 2 ref c ( 3.50 ) ( 4. 80 typ ) (40x 0.60) (40x 0.20) ( 36x 0.4) index area

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