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w83194r - 630 166mhz clock for si s chipset publication release date: nov. 1999 - 1 - revision 0.65 1. general description the w83194r - 630 is a clock synthesizer for sis 540/630 chipset. w83194r - 630 provides all clocks required for high - speed risc or cisc microprocessor such as amd,cyrix,intel pentium, pentium ii and also provides 16 different frequencies of cpu clocks frequency setting. all clocks are externally selectable with smooth transitions. the w83194r - 630 makes sdram in synchronous or asynchronous frequency with cpu clocks. the w83194r - 630 provides i 2 c serial bus interface to program the registers to enable or disable each clock outputs and w83194r - 630 provides the 0.5%, 0.75% center type and 0~0.5% down type spread spectrum to reduce emi. the w83194r - 630 accepts a 14.318 mhz reference crystal as its input and runs on a 3.3v supply. high d rive pci and sdram clock outputs typically provide greater than 1 v /ns slew rate into 30 pf loads. cpu clock outputs typically provide better than 1 v /ns slew rate into 20 pf loads as maintaining 50 5% duty cycle. the fixed frequency outputs as ref, 24mhz, and 48 mhz provide better than 0.5v /ns slew rate. 2. product features supports pentium ? , pentium ? ii, amd and cyrix cpus with i 2 c. 3 cpu clocks 14 sdram clocks for 3 dimms 7 pci synchronous clocks. optional single or mixed supply: (all vd d = 3.3v) or (other s vdd = 3.3v, vddlcpu=2.5v) skew form cpu to pci clock 1 to 4 ns, center 2.6 ns sdram frequency synchronous or asynchronous to cpu clocks smooth frequency switch with selections from 66 to 166mhz i 2 c 2 - wire serial interface and i 2 c read back 0.5%, 0.75%center type, 0~0.5% down type spread spectrum to reduce emi programmable registers to enable/stop each output and select modes (mode as tri - state or normal ) 48 mhz for usb 24 mhz for super i/o packaged in 48 - pin ssop
w83194r - 630 preliminary publication release date: nov. 1999 - 2 - revision 0.65 3. block diagram pll2 xtal osc spread spectrum pll1 latch por stop ? 2 control logic config. reg. stop pci clock divder 5 14 7 48mhz 24_48mhz ref(0:1) cpuclk(0:2) sdram(0:13) pciclk(0:6) xin xout *fs(0:3) 4 *mode cpu_stop# pci_stop# *sdata *sclk 2 3 sel3.3_2.5# cpu_stop# pci_stop# pd# 4. pin configurati on 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vdd ref0x2/ *fs3 vss xin xout vddp pciclk_f/ *fs1 pciclk1/ *fs2 vss pciclk2/*mode pciclk3 pciclk4 pciclk5 sdram12 vddsd sdram_f sdram11 vddp sdram 10 sdram 8 *sdata *sdclk vddlcpu cpuclk_f vss cpuclk0 cpuclk1 vddsd sdram 0/cpu_stop# sdram 1/pci_stop# sdram 2/pd# vddsd sdram 3 vss sdram 4 sdram 5 sdram 6 sdram 7 vddsd vddsd 24_48mhz/sel2.5_3.3# ref1 vss sdram 9 48mhz/*fs0 pciclk6 vss vss
w83194r - 630 preliminary publication release date: nov. 1999 - 3 - revision 0.65 5. pin description in - input out - output i/o - bi - directional pin # - active low * - internal 250k w pull - up 5.1 crystal i/o symbol pin i/o function xin 4 in crystal input with internal loading capacitors and feedback resistors. xout 5 out crystal output at 14.318mhz nominally. 5.2 cpu, sdram, pci clock outputs symbol pin i/o function cpuclk_f 46 out low skew (< 250ps) clock outputs for host frequencies such as cpu, ch ipset and cache. vddlcpu is the supply voltage for these outputs. this pin will not be stopped by cpu_stop# cpuclk [ 0:1 ] 45,43 out low skew (< 250ps) clock outputs for host frequencies such as cpu, chipset and cache. vddlcpu is the supply voltage for these outputs. sdram_f 40 out sdram clock outputs which have syn. or asyn. frequencies as cpu clocks. this pin will not be stopped by cpu_stop# sdram0/cpu_stop# 17 i/o sdram clock outputs which have syn. or asyn. frequencies as cpu clocks. cpu_stop# input pin when mode=0. sdram1/pci_stop# 18 i/o sdram clock outputs which have syn. or asyn. frequencies as cpu clocks. pci_stop# input pin when mode=0. sdram2/pd# 20 i/o sdram clock outputs which have syn. or asyn. frequencies as cpu clocks. pd# input pin when mode=0. sdram[3:12] 21,28,29,31,32 ,34,35,37,38, 41 out sdram clock outputs which have syn. or asyn. frequencies as cpu clocks. pciclk_f/ *fs1 7 i/o latched input for fs1 at initial power up for h/w selecting the output frequency of cpu, sdra m and pci clocks.
w83194r - 630 preliminary publication release date: nov. 1999 - 4 - revision 0.65 pci free - running clock during normal operation. pciclk 1/ *fs2 8 i/o latched input for fs2 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. pci clock during normal operation. pciclk 2/ *mode 9 i/o latched input for mode at initial power up for input selection of cpu_stop#, pci_stop# and pd#. when mode=1, the above pins are sdram clock outputs. when mode=0, the pins are inputs acpi pins. pci clock during normal operation. pciclk [ 3:6 ] 11,12,13 ,14 out low skew (< 250ps) pci clock outputs. 5.3 i 2 c control interface symbol pin i/o function *sdata 23 i/o serial data of i 2 c 2 - wire control interface *sdclk 24 in serial clock of i 2 c 2 - wire control interface 5.4 fixed frequency outputs symbol pin i/o function ref0x2 / *fs3 2 i/o 3.3v, 14.318mhz reference clock output . internal 250k w pull - up. latched input for fs3 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. ref1 48 i/o 3.3v or 2.5v by vddlcpu, 14 .318mhz reference clock output. 24_48mhz/ sel2.5_3.3# 25 i/o sel2.5_3.3# controls the vdd of cpu. if logic 0 at power on, vddlcpu=3.3v. if logic 1, vddlcpu=2.5 24mhz or 48mhz selected by i2c for super i/o. 48mhz / *fs0 26 i/o internal 250k w pull - up. latched input for fs0 at initial power up for h/w selecting the output frequency of cpu, sdram and pci clocks. 48mhz output for usb during normal operation.
w83194r - 630 preliminary publication release date: nov. 1999 - 5 - revision 0.65 5.5 power pins symbol pin function vdd 1 power supply for ref0 crystal and core logic. vddlcpu 47 power supply for ref1, cpuclk_f and cpuclk[0:1], either 2.5v or 3.3v. vddp 6,15 power supply for pci outputs. vddsd 19,27,30,36,42 power supply for sdram and 48/24nhz outputs. vss 3,10,16,22,33,39,44 circuit ground. 6. frequency selecti on by hardware fs3 fs2 fs1 fs0 cpu (mhz) sdram (mhz) pci (mhz) ref (mhz) ioapic 0 0 0 0 66.8 100.2 33.4 14.318 0 0 0 1 100.2 100.2 33.4 14.318 0 0 1 0 122 122 30.5 14.318 0 0 1 1 133.6 100.2 33.4 14.318 0 1 0 0 66.8 116.9 33.4 14.318 0 1 0 1 100.2 133.6 33.4 14.318 0 1 1 0 100.2 150.3 33.4 14.318 0 1 1 1 133.6 133.6 33.4 14.318 1 0 0 0 66.8 66.8 33.4 14.318 1 0 0 1 97 97 32.3 14.318 1 0 1 0 97 129.3 32.3 14.318 1 0 1 1 95.2 95.2 31.7 14.318 1 1 0 0 95.2 126.6 31.7 14.318 1 1 0 1 112 112 37.3 14.318 1 1 1 0 96.2 96.2 32.1 14.318 1 1 1 1 166 166 33.3 14.318 7. sel3.3_2.5# buf fer selection sel3.3_2.5# ( pin 25 ) input l evel cpu operate at 1 vddlcpu = 2.5v 0 vddlcpu = 3.3v
w83194r - 630 preliminary publication release date: nov. 1999 - 6 - revision 0.65 8. function descrip tion 8.1 2 - wire i 2 c control interface the clock generator is a slave i2c component which can be read back the data stored in the latches for verification. all proceeding bytes must be sent to change one of the control bytes. the 2 - wire control interface allows each clock output individually enabled or disabled. on power up, the w83194r - 630 initializes with default register settings, and then it ptional to use the 2 - wire co ntrol interface. the sdata signal only changes when the sdclk signal is low, and is stable when sdclk is high during normal data transfer. there are only two exceptions. one is a high - to - low transition on sdata while sdclk is high used to indicate the beginning of a data transfer cycle. the other is a low - to - high transition on sdata while sdclk is high used to indicate the end of a data transfer cycle. data is always sent as complete 8 - bit bytes followed by an acknowledge generated. byte writing start s with a start condition followed by 7 - bit slave address [1101 0010], command code checking [0000 0000], and byte count checking. after successful reception of each byte, an acknowledge (low) on the sdata wire will be generated by the clock chip. controller can start to write to internal i 2 c registers after the string of data. the sequence order is as follows: bytes sequence order for i 2 c controller : clock address a(6:0) & r/w ack 8 bits dummy command code ack 8 bits dummy byte count ack byte0,1,2... until stop set r/w to 1 when read back the data sequence is as follows, [1101 0 011] : clock address a(6:0) & r/w ack byte 0 ack ack byte2, 3, 4... until stop byte 1 8.2 serial control registers the pin column lists the affected pin number and the @powerup column gives the state at true power up. registers are set to the values shown only on true power up. "command code" byte and "byte count" byte must be sent following the acknowledge of the address byte. although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. after that, the below described sequence (register 0, register 1, register 2, ....) will be valid and acknowledged.
w83194r - 630 preliminary publication release date: nov. 1999 - 7 - revision 0.65 frequency table by i2c ssel3 ssel2 ssel1 ssel0 cpu (mhz) sdram (mhz) pci (mhz) ref (mhz) ioapic 0 0 0 0 66.8 100.2 33.4 14.318 0 0 0 1 100.2 100.2 33.4 14.318 0 0 1 0 122 122 30.5 14.318 0 0 1 1 133.6 100.2 33.4 14.318 0 1 0 0 66.8 116.9 33.4 14.318 0 1 0 1 100.2 133.6 33.4 14.318 0 1 1 0 100.2 150.3 33.4 14 .318 0 1 1 1 133.6 133.6 33.4 14.318 1 0 0 0 66.8 66.8 33.4 14.318 1 0 0 1 97 97 32.3 14.318 1 0 1 0 97 129.3 32.3 14.318 1 0 1 1 95.2 95.2 31.7 14.318 1 1 0 0 95.2 126.6 31.7 14.318 1 1 0 1 112 112 37.3 14.318 1 1 1 0 96.2 96.2 32.1 14.318 1 1 1 1 166 166 33.3 14.318 8.2.1 register 0: cpu frequency select register (default = 0) bit @powerup pin description 7 0 - 0 = 0.5% center type spread spectrum modulation 1 = 0.75% center type spread spectrum modulation 6 0 - ssel2 (for frequency table s election by software via i 2 c) 5 0 - ssel1 (for frequency table selection by software via i 2 c) 4 0 - ssel0 (for frequency table selection by software via i 2 c) 3 0 - 0 = selection by hardware 1 = selection by software i 2 c - bit 2, 6:4 2 0 - ssel3 (for frequency table selection by software via i 2 c) 1 0 - 0 = normal 1 = spread spectrum enabled 0 0 - 0 = running 1 = tristate all outputs
w83194r - 630 preliminary publication release date: nov. 1999 - 8 - revision 0.65 8.2.2 register 1 : cpu clock register (1 = active, 0 = inactive) bit @powerup pin description 7 x - latched fs2# 6 1 - reserved 5 1 - 0 = 0.5% down type spread, overrides byte0 - bit7. 1= center type spread. 4 1 - reserved 3 1 43 cpuclk2 (active / inactive) 2 1 45 cpuclk1 (active / inactive) 1 1 46 cpuclk0 (active / inactive) 0 1 - reserved 8.2.3 register 2: pci clock register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - reserved 6 1 14 pciclk6 (active / inactive) 5 1 13 pciclk5 (active / inactive) 4 1 12 pciclk4 (active / inactive) 3 1 11 pciclk3 (active / inactive) 2 1 9 pciclk2 (active / inactive) 1 1 8 pciclk1 (active / inactive) 0 1 7 pciclk0 (active / inactive) 8.2.4 register 3: control register (1 = active, 0 = inactive) bit @powerup pin description 7 1 - 1 pin25 24_48mhz = 24mhz 0 pin25 24_48mhz = 48mhz 6 x - latched fs0# 5 1 26 48mhz (active / inactive) 4 1 25 24 - 48mhz (active / inactive) 3 1 - reserved 2 1 - reserved 1 1 48 ref1 (active / inactive) 0 1 2 ref0x2 (active / inactive)
w83194r - 630 preliminary publication release date: nov. 1999 - 9 - revision 0.65 8.2.5 register 4: sdram register (1 = active, 0 = inactive) bit @powerup pin description 7 1 41 sdram13 (active / inactive) 6 1 40 sdram12 (active / inactive) 5 1 38 sdram11 (active / inactive) 4 1 37 sdram10 (active / inactive) 3 x x latched fs1# 2 1 35 sdram9 (active / inactive) 1 x x latched fs3# 0 1 34 sdram8 (active / inactive) 8.2.6 register 5: sdram register(1 = active, 0 = inactive) bit @powerup pin description 7 1 32 sdram7 (active / inactive) 6 1 31 sdram6 (active / inactive) 5 1 29 sdram5 (active / inactive) 4 1 28 sdram4 (active / inactive) 3 1 21 sdram3 (active / ina ctive) 2 1 20 sdram2 (active / inactive) 1 1 18 sdram1 (active / inactive) 0 1 17 sdram0 (active / inactive) 8.2.7 register 6: winbond chip id register (read only) bit @powerup pin description 7 0 - winbond chip id 6 1 - winbond chip id 5 0 - winbond chip id 4 1 - winbond chip id 3 1 - winbond chip id 2 0 - winbond chip id 1 0 - winbond chip id 0 1 - winbond chip id
w83194r - 630 preliminary publication release date: nov. 1999 - 10 - revision 0.65 9.0 specifications 9.1 absolute maximum ratings stresses greater than those listed in this table may cause permanent damag e to the device. precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. maximum conditions for extended periods may affect reliability. unused inputs must always be tied to an appropriate logic voltage level (ground or vdd). symbol parameter rating vdd , v in voltage on any pin with respect to gnd - 0.5 v to + 7.0 v t stg storage temperature - 65 c to + 150 c t b ambient temperature - 55 c to + 125 c t a operating temperature 0 c to + 70 c 9.2 electronical characteristics --- input/output vddq1=vddq2 = vddq3 = vddq4 =3.3v, vddl1 =vddl2= 2.5v , t a = 0 c to +70 c parameter symbol min typ max units test conditions input low voltage v il vss - 0.3 0.8 v dc input high voltage v ih 2.0 vdd+0.3 v dc input low current i il - 5 m a no pull - up resistors input low current i il - 200 m a pull - up resistros input high current i ih - 5 5 m a input capacitance c in 5 pf logic inputs c out 6 pf output capacitance c inx 27 45 pf xin and xout operating supply current i dd3 100 ma cpu = 66.6 mhz pci = 33.3 mhz with load power down supply current i dd2 600 m a settling time ts 3 ms from first crossing to 1% target freq.
w83194r - 630 preliminary publication release date: nov. 1999 - 11 - revision 0.65 skew t cpu - pci 1 4 ns v t =1.5v 9.3 electronical characteristics of cpu clock vdd=2.5v +/ - 5%; c l =10 - 20pf parameter symbol min typ max units test conditions ouput impedance r dsp 13.5 30 ohm ouput impedance r dsn 13.5 30 ohm output low voltage v ol 0.4 v i ol =1ma output high voltage v oh 2.0 v i oh = - 1ma output low current i ol 19 ma output high current i oh - 27 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.4 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 2.0 ns 20pf load duty cycle dt 45 55 % v t =1.25v skew t sk 175 ps v t =1.25v jitter tsc - c 250 ps v t =1.25v 9.4 electronical characteristics of sdram clock vdd=3.3v +/ - 5%; c l =20 - 30pf parameter symbol min typ max units test conditions ouput impedance r dsp 11 30 ohm ouput impedance r dsn 11 30 ohm output low voltag e v ol 0.45 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 35 ma output high current i oh - 45 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.5 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 2.0 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 250 ps v t =1.5v jitter tsc - c 250 ps v t =1.5v
w83194r - 630 preliminary publication release date: nov. 1999 - 12 - revision 0.65 9.5 electronical characteristics of pci clock vdd=3.3v +/ - 5%; c l =10 - 30pf parameter symbol min typ max units test conditions ouput impedance r dsp 15 55 ohm ouput impedance r dsn 15 55 ohm output low voltage v ol 0.5 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 30 ma output high current i oh - 33 ma rise/fall time min between 0.4 v and 2.0 v t rf(min) 0.5 ns 10pf load rise/fall time max between 0.4 v and 2.0 v t rf(max) 2.0 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 500 ps v t =1.5v jitter tsc - c 500 ps v t =1.5v 9.6 electronical characteristics of 24/48mhz, ref clock vdd=3.3v +/ - 5%; c l = 20pf parameter symbol min typ max units test conditions ouput impedance r dsp 20 55 ohm ouput impedance r dsn 20 55 ohm output low voltage v ol 0.4 v i ol =1ma output high voltage v oh 2.4 v i oh = - 1ma output low current i ol 10 ma output high current i oh - 23 ma risetime t r 1.8 4 ns 10pf load fall time t f 1.7 4 ns 20pf load duty cycle dt 45 55 % v t =1.5v skew t sk 500 ps v t =1.5v jitter tsc - c 1000 ps v t =1.5v
w83194r - 630 preliminary publication release date: nov. 1999 - 13 - revision 0.65 10. ordering inform ation part number package type production flow w83194r - 630 48 pin ssop commercial, 0 c to +70 c 11. how to read the top marking 1st line: winbond logo and the type number: w83194r - 630 2nd line: tracking code 2 8051234 2 : wafers manufactured in winbond fab 2 8051234 : wafer production series lot number 3rd line: tracking code 942 g e d 942 : packages made in ' 99 , week 42 g : assembly house id; o means ose, g means gr e : internal use code d : ic revision all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . w83194r - 630 28051234 942ged
w83194r - 630 preliminary publication release date: nov. 1999 - 14 - revision 0.65 12. package drawing and dimensions headquarters no. 4, creation rd. iii science-based industrial park hsinchu, taiwan tel: 886-35-770066 fax: 886-35-789467 www: http://www.winbond.com.tw/ taipei office 11f, no. 115, sec. 3, min-sheng east rd. taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 tlx: 16485 wintpe winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii 123 hoi bun rd., kwun tong kowloon, hong kong tel: 852-27516023-7 fax: 852-27552064 winbond electronics (north america) corp. 2730 orchard parkway san jose, ca 95134 u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners . these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sale.

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