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12-bit, 4-channel parallel output sampling analog-to-digital converter features single supply: 2.7v to 5v 4-channel input multiplexer up to 200khz sampling rate full 12-bit parallel interface 1lsb inl and dnl no missing codes 72db sinad low power: 2mw ssop-28 package description the ads7842 is a complete, 4-channel, 12-bit analog-to- digital converter (adc). it contains a 12-bit, capacitor- based, successive approximation register (sar) adc with a sample-and-hold amplifier, interface for microprocessor use, and parallel, 3-state output drivers. the ads7842 is specified at a 200khz sampling rate while dissipating only 2mw of power. the reference voltage can be varied from 100mv to v cc with a corresponding lsb resolution from 24 v to 1.22mv. the ads7842 is tested down to 2.7v operation. low power, high speed, and an onboard multiplexer make the ads7842 ideal for battery-operated systems such as portable, multi-channel dataloggers and measurement equip- ment. the ads7842 is available in an ssop-28 package and is tested over the ?0 c to +85 c temperature range. applications data acquisition test and measurement industrial process control medical instruments laboratory equipment a d s 7 8 4 2 sar output latches and 3-state drivers 3-state parallel data bus comparator ads7842 cs wr busy clk rd cdac v ref 4-channel mux ain2 ain1 ain0 a0 a1 ain3 ads7842 sbas103b september 2000 revised may 2002 www.ti.com production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 2000, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ads7842 sbas103b 2 www.ti.com pin name description 1 ain0 analog input channel 0 2 ain1 analog input channel 1 3 ain2 analog input channel 2 4 ain3 analog input channel 3 5v ref voltage reference input. see electrical characteris- tics tables for ranges. 6 agnd analog ground 7 db11 data bit 11 (msb) 8 db10 data bit 10 9 db9 data bit 9 10 db8 data bit 8 11 db7 data bit 7 12 db6 data bit 6 13 db5 data bit 5 14 dgnd digital ground 15 db4 data bit 4 16 db3 data bit 3 17 db2 data bit 2 18 db1 data bit 1 19 db0 data bit 0 (lsb) 20 rd read input. active low. reads the data outputs in combination with cs. 21 cs chip select input. active low. the combination of cs taken low and wr taken low initiates a new conversion and places the outputs in the tri-state mode. 22 wr write input. active low. starts a new conversion and selects an analog channel via address inputs a0 and a1, in combination with cs. 23 busy busy goes low and stays low during a conversion. busy rises when a conversion is complete and enables the parallel outputs. 24 clk external clock input. the clock speed determines the conversion rate by the equation f clk = 16 f sample . 25, 26 a0, a1 address inputs. selects one of four analog input channels in combination with cs and wr. the address inputs are latched on the rising edge of either rd or wr. a1 a0 channel selected 0 0 ain0 0 1 ain1 1 0 ain2 1 1 ain3 27 v dig digital supply input. nominally +5v. 28 v ana analog supply input. nominally +5v. minimum relative specified accuracy sinad package temperature package ordering transport product (lsb) (db) package-lead designator (1) range marking number media, quantity ads7842e 2 68 ssop-28 db 40 c to +85 c ads7842e ads7842e rails, 48 """"""" ads7842e/1k tape and reel, 1000 ads7842eb 1 70 ssop-28 db 40 c to +85 c ads7842eb ads7842eb rails, 48 """"""" ads7842eb/1k tape and reel, 1000 absolute maximum ratings (1) +v cc to gnd ........................................................................ 0.3v to +6v analog inputs to gnd ............................................ 0.3v to +v cc + 0.3v digital inputs to gnd ........................................................... 0.3v to +6v power dissipation .......................................................................... 250mw maximum junction temperature ................................................... +150 c operating temperature range ........................................ 40 c to +85 c storage temperature range ......................................... 65 c to +150 c lead temperature (soldering, 10s) ............................................... +300 c electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degrada- tion to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. package/ordering information pin configuration top view ssop pin descriptions 1 2 3 4 5 6 7 8 8 10 11 12 13 14 ain0 ain1 ain2 ain3 v ref agnd db11 db10 db9 db8 db7 db6 db5 dgnd v ana v dig a1 a0 clk busy wr cs rd db0 db1 db2 db3 db4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ads7842e note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability.
ads7842 sbas103b 3 www.ti.com electrical characteristics: +5v at t a = 40 c to +85 c, +v cc = +5v, v ref = +5v, f sample = 200khz, and f clk = 16 f sample = 3.2mhz, unless otherwise noted. ads7842e ads7842eb parameter conditions min typ max min typ max units resolution 12 ? bits analog input full-scale input span 0 v ref ?? v capacitance 25 ? pf leakage current 1 ? a system performance no missing codes 12 ? bits integral linearity error 2 1 lsb (1) differential linearity error 0.8 0.5 1lsb offset error 3 ? lsb offset error match 0.15 1.0 ?? lsb gain error 4 3lsb gain error match 0.1 1.0 ?? lsb noise 30 ? vrms power-supply rejection 70 ? db sampling dynamics conversion time 12 ? clk cycles acquisition time 3 ? clk cycles throughput rate 200 ? khz multiplexer settling time 500 ? ns aperture delay 30 ? ns aperture jitter 100 ? ps dynamic characteristics total harmonic distortion (2) v in = 5vp-p at 10khz 78 72 80 76 db signal-to-(noise + distortion) v in = 5vp-p at 10khz 68 71 70 72 db spurious-free dynamic range v in = 5vp-p at 10khz 72 79 76 81 db channel-to-channel isolation v in = 5vp-p at 50khz 120 ? db reference input range 0.1 +v cc ?? v resistance dclk static 5 ? g ? input current 40 100 ?? a f sample = 12.5khz 2.5 ? a dclk static 0.001 3 ?? a digital input/output logic family cmos ? logic levels v ih | i ih | +5 a 3.0 5.5 ?? v v il | i il | +5 a 0.3 +0.8 ?? v v oh i oh = 250 a 3.5 ? v v ol i ol = 250 a 0.4 ? v data format straight binary ? external clock 0.2 3.2 ?? mhz power-supply requirements +v cc specified performance 4.75 5.25 ?? v quiescent current 550 900 ?? a f sample = 12.5khz 300 ? a power-down mode (3) , cs = +v cc 3 ? a power dissipation 4.5 ? mw temperature range specified performance 40 +85 ?? c ? same specifications as ads7842e. notes: (1) lsb means least significant bit. with v ref equal to +5.0v, one lsb is 1.22mv. (2) first five harmonics of the test frequency. (3) power-down mode at end of conversion when wr, cs, and busy conditions have all been met. refer to table iii of this data sheet.
ads7842 sbas103b 4 www.ti.com electrical characteristics: +2.7v at t a = 40 c to +85 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted. ads7842e ads7842eb ? same specifications as ads7842e. notes: (1) lsb means least significant bit. with v ref equal to +2.5v, one lsb is 610mv. (2) first five harmonics of the test frequency. (3) power-down mode at end of conversion when wr, cs, and busy conditions have all been met. refer to table iii of this data sheet. parameter conditions min typ max min typ max units resolution 12 ? bits analog input full-scale input span 0 v ref ?? v capacitance 25 ? pf leakage current 1 ? a system performance no missing codes 12 ? bits integral linearity error 2 1 lsb (1) differential linearity error 0.8 0.5 1lsb offset error 5 ? lsb offset error match 0.15 1.0 ?? lsb gain error 4 3lsb gain error match 0.1 1.0 ?? lsb noise 30 ? vrms power-supply rejection 70 ? db sampling dynamics conversion time 12 ? clk cycles acquisition time 3 ? clk cycles throughput rate 125 ? khz multiplexer settling time 500 ? ns aperture delay 30 ? ns aperture jitter 100 ? ps dynamic characteristics total harmonic distortion (2) v in = 2.5vp-p at 10khz 77 70 79 74 db signal-to-(noise + distortion) v in = 2.5vp-p at 10khz 68 71 70 72 db spurious-free dynamic range v in = 2.5vp-p at 10khz 72 78 76 80 db channel-to-channel isolation v in = 2.5vp-p at 50khz 100 ? db reference input range 0.1 +v cc ?? v resistance dclk static 5 ? g ? input current 13 40 ?? a f sample = 12.5khz 2.5 ? a dclk static 0.001 3 ?? a digital input/output logic family cmos ? logic levels v ih | i ih | +5 a+v cc 0.7 5.5 ?? v v il | i il | +5 a 0.3 +0.8 ?? v v oh i oh = 250 a+v cc 0.8 ? v v ol i ol = 250 a 0.4 ? v data format straight binary ? external clock 0.2 2 ?? mhz power-supply requirements +v cc specified performance 2.7 3.6 ?? v quiescent current 280 650 ?? a f sample = 12.5khz 220 ? a power-down mode (3) , cs = +v cc 3 ? a power dissipation 1.8 ? mw temperature range specified performance 40 +85 ?? c
ads7842 sbas103b 5 www.ti.com typical characteristics: +5v at t a = +25 c, +v cc = +5v, v ref = +5v, f sample = 200khz, and f clk = 16 f sample = 3.2mhz, unless otherwise noted. 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 1,123hz, 0.2db) 0 100 25 75 50 frequency (khz) amplitude (db) 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 10.3khz, 0.2db) 0 100 25 75 50 frequency (khz) amplitude (db) signal-to-noise ratio and signal-to- (noise + distortion) vs input frequency 10 1 100 input frequency (khz) snr and sinad (db) 74 73 72 71 70 69 68 sinad snr spurious-free dynamic range and total harmonic distortion vs input frequency 10 1100 input frequency (khz) sfdr (db) thd (db) 85 80 75 70 65 85 80 75 70 65 thd sfdr 12.0 11.8 11.6 11.4 11.2 11.0 effective number of bits vs input frequency 10 1 100 input frequency (khz) effective number of bits change in signal-to-(noise + distortion) vs temperature 20 40 100 temperature ( c) delta from +25 c (db) 0.4 0.2 0.0 0.2 0.4 0.6 0.6 0 20 40 60 80 f in = 10khz, 0.2db
ads7842 sbas103b 6 www.ti.com typical characteristics: +2.7v at t a = +25 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted. 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 1,129hz, 0.2db) 0 62.5 15.6 46.9 31.3 frequency (khz) amplitude (db) 0 20 40 60 80 100 120 frequency spectrum (4096 point fft; f in = 10.6khz, 0.2db) 0 62.5 15.6 46.9 31.3 frequency (khz) amplitude (db) signal-to-noise ratio and signal-to- (noise + distortion) vs input frequency 10 1 100 input frequency (khz) snr and sinad (db) 78 74 70 66 62 58 54 sinad snr thd sfdr spurious-free dynamic range and total harmonic distortion vs input frequency 10 1 100 input frequency (khz) sfdr (db) thd (db) 90 85 80 75 70 65 60 55 50 90 85 80 75 70 65 60 55 50 effective number of bits vs input frequency 10 1 100 input frequency (khz) effective number of bits 12.0 11.5 11.0 10.5 10.0 9.5 9.0 change in signal-to-(noise + distortion) vs temperature 20 40 100 temperature ( c) delta from +25 c (db) 0.2 0.0 0.2 0.4 0.6 0.8 0.4 0 20 40 60 80 f in = 10khz, 0.2db
ads7842 sbas103b 7 www.ti.com typical characteristics: +2.7v (cont.) at t a = +25 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted. output code 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 integral linearity error vs code 800 h fff h 000 h ile (lsb) output code 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 differential linearity error vs code 800 h fff h 000 h dle (lsb) supply current vs temperature 20 40 100 20 0 40 temperature ( c) supply current ( a) 400 350 300 250 200 150 100 60 80 power-down supply current vs temperature 20 40 100 20 0 40 temperature ( c) supply current (na) 140 120 100 80 60 40 20 60 80 change in gain vs temperature 20 40 100 20 0 40 temperature ( c) delta from +25 c (lsb) 0.15 0.10 0.05 0.00 0.05 0.10 0.15 60 80 change in offset vs temperature 20 40 100 20 0 40 temperature ( c) delta from +25 c (lsb) 0.6 0.4 0.2 0.0 0.2 0.4 0.6 60 80
ads7842 sbas103b 8 www.ti.com typical characteristics: +2.7v (cont.) at t a = +25 c, +v cc = +2.7v, v ref = +2.5v, f sample = 125khz, and f clk = 16 f sample = 2mhz, unless otherwise noted. supply current vs +v cc 3.5 25 2.5 4 +v cc (v) supply current ( a) 320 300 280 260 240 220 200 180 4.5 3 f sample = 12.5khz v ref = +v cc maximum sample rate vs +v cc 3.5 25 2.5 4 +v cc (v) sample rate (hz) 1m 100k 10k 1k 4.5 3 v ref = +v cc reference current vs sample rate 75 0125 25 50 100 sample rate (khz) reference current ( a) 14 12 10 8 6 4 2 0 reference current vs temperature 20 40 100 20 0 40 temperature ( c) reference current ( a) 18 16 14 12 10 8 6 60 80
ads7842 sbas103b 9 www.ti.com theory of operation the ads7842 is a classic sar adc. the architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. the converter is fabricated on a 0.6 m cmos process. the basic operation of the ads7842 is shown in figure 1. the device requires an external reference and an external clock. it operates from a single supply of 2.7v to 5.25v. the external reference can be any voltage between 100mv and +v cc . the value of the reference voltage directly sets the input range of the converter. the average reference input current depends on the conversion rate of the ads7842. analog inputs the ads7842 features four, single-ended inputs. the input current into each analog input depends on input voltage and sampling rate. essentially, the current into the device must charge the internal hold capacitor during the sample period. after this capacitance has fully charged, there is no further input current. the source of the analog input voltage must be able to charge the input capacitance to a 12-bit settling level within the same period, which can be as little as 350ns in some operating modes. while the converter is in the hold mode, or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1g ? . external clock the ads7842 requires an external clock to run the conver- sion process. this clock can vary between 200khz (12.5khz throughput) and 3.2mhz (200khz throughput). the duty cycle of the clock is unimportant as long as the minimum high and low times are at least 150ns and the clock period is at least 300ns. the minimum clock frequency is set by the leakage on the capacitors internal to the ads7842. basic operation figure 1 shows the simple circuit required to operate the ads7842 with channel 0 selected. a conversion can be initiated by bringing the wr pin (pin 22) low for a minimum of 25ns. busy (pin 23) will output a low during the conversion process and rises only after the conversion is complete. the 12 bits of output data will be valid on pins 7-13 and 15-19 following the rising edge of busy . figure 1. basic operation of the ads7842. ain0 ain1 ain2 ain3 v ref agnd db11 db10 db9 db8 db7 db6 db5 dgnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v ana v dig a1 a0 clk busy wr cs rd db0 db1 db2 db3 db4 3.2mhz clock busy output write input read input 2.2 f +5v 0v to v ref ads7842 + 0.1 f + 10 f +5v analog supply +
ads7842 sbas103b 10 www.ti.com starting a conversion a conversion is initiated on the falling edge of the wr input, with valid signals on a0, a1, and cs . the ads7842 will enter the conversion mode on the first rising edge of the external clock following the wr pin going low. the ads7842 will start the conversion on the 1st clock cycle. the msb will be approximated by the capacitive digital-to-analog con- verter (cdac) on the 1st clock cycle, the 2nd-msb on the 2nd cycle, and so on until the lsb has been decided on the 12th clock cycle. the busy output will go low 20ns after the falling edge of the wr pin. the busy output will return high just after the ads7842 has finished a conversion and the data will be valid on pins 7-13, 15-19. the rising edge of busy can be used to latch the data. it is recommended that the data be read immediately after each conversion. the switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter s performance. see figure 2. reading data data from the ads7842 will appear at pins 7-13 and 15-19. the msb will output on pin 7 while the lsb will output on pin 19. the outputs are coded in straight binary (with 0v = 000 h and v ref = fff h , see table iv). following a conversion, the busy pin will go high. after busy goes high, the cs and rd pins may be brought low to enable the 12-bit output bus. cs and rd must be held low for at least 25ns seconds following busy high. data will be valid 25ns seconds after the falling edge of both cs and rd . the output data will remain valid for 25ns seconds following the rising edge of both cs and rd . see figure 4 for the read cycle timing diagram. power-down mode the ads7842 incorporates a unique method of placing the adc in the power-down mode. rather than adding an extra pin to the package, the a0 address pin is used in conjunction with the rd pin to place the device in power-down mode and also to wake-up the adc following power-down. in this shutdown mode, all analog and digital circuitry is turned off. the simplest way to place the ads7842 in power-down mode is immediately following a conversion. after a conver- sion has been completed and the busy output has returned high, cs and rd must be brought low for a minimum of 25ns. while keeping cs low, rd is brought high and the ads7842 enters the power-down mode, provided the a0 pin is high (see figure 5 and table iii). in order to wake-up the device following power-down, a0 must be low when rd switches from low to high a second time (see figure 6). the typical supply current of the ads7842 with a 5v supply and 200khz sampling rate is 550 a. in the power-down mode the current is typically reduced to 3 a. symbol description min typ max units t conv conversion time 6.5 s t acq acquisition time 1.5 s t ckp clock period 500 ns t ckl clock low 150 ns t ckh clock high 150 ns t 1 cs to wr/rd setup time 0 ns t 2 address to cs hold time 0 ns t 3 cs low 25 ns t 4 clk to wr setup time 25 ns t 5 cs to busy low 20 ns t 6 clk to wr low 5 ns t 7 clk to wr high 25 ns t 8 wr to clk high 25 ns t 9 address hold time 5 ns t 10 address setup time 5 ns t 11 busy to rd delay 0 ns t 12 clk low to busy high 10 ns t 13 bus access 25 ns t 14 bus relinquish 25 ns t 15 address to rd high 2 ns t 16 address hold time 2 ns t 17 rd high to clk low 50 ns table ii. timing specifications (+v cc = +4.75v to +5.25v, t a = 40 c to +85 c, c load = 50pf). table i. timing specifications (+v cc = +2.7v to 3.6v, t a = 40 c to +85 c, c load = 50pf). symbol description min typ max units t conv conversion time 3.5 s t acq acquisition time 1.5 s t ckp clock period 300 ns t ckl clock low 150 ns t ckh clock high 150 ns t 1 cs to wr/rd setup time 0 ns t 2 address to cs hold time 0 ns t 3 cs low 25 ns t 4 clk to wr setup time 25 ns t 5 cs to busy low 20 ns t 6 clk to wr low 5 ns t 7 clk to wr high 25 ns t 8 wr to clk high 25 ns t 9 address hold time 5 ns t 10 address setup time 5 ns t 11 busy to rd delay 0 ns t 12 clk low to busy high 10 ns t 13 bus access 25 ns t 14 bus relinquish 25 ns t 15 address to rd high 2 ns t 16 address hold time 2 ns t 17 rd high to clk low 50 ns
ads7842 sbas103b 11 www.ti.com figure 2. normal operation, 16 clocks per conversion. cs rd wr busy a0 a1 comments 0x11x power-down mode 0x10x wake-up mode means rising edge triggered. x = don't care. table iii. truth table for power-down and wake-up modes. figure 3. initiating a conversion. 123 cs wr busy rd a0 a1 clk latching in address for next channel conversion 45 678 910111213141516 sample data valid db0-db11 digital output straight binary description analog input binary code hex code least significant bit (lsb) 1.2207mv full-scale 4.99878v 1111 1111 1111 fff midscale 2.5v 1000 0000 0000 800 midscale 1lsb 2.49878v 0111 1111 1111 7ff zero full-scale 0v 0000 0000 0000 000 table iv. ideal input voltages and output codes (v ref = 5v). t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 t ckl n + 1 (1) note: (1) addresses for next conversion (n + 1) latched in with rising edge of current wr (n). cs wr clk busy a0, a1
ads7842 sbas103b 12 www.ti.com figure 4. read timing following a conversion. figure 5. entering power-down using rd and a0. figure 6. initiating wake-up using rd and a0. t 1 t 12 t 11 t 14 t 13 t 3 note: internal register of current conversion updated 1/2 clock cycle prior to busy going high. cs rd clk busy n 1 conversion n to prevent pwd a0 must be 0 n-1 data valid a0 db0-db11 t 3 t 16 t 15 t 1 t 12 t 11 t 2 cs rd clk busy a0 note: rising edge of rd while a0 = 1 initiates power down immediately. cs rd a0 t 1 t 2 t 15 t 16 t 3 note: rising edge of 2nd rd while a0 = 0 places the ads7842 in sample mode.
ads7842 sbas103b 13 www.ti.com reference input the external reference sets the analog input range. the ads7842 will operate with a reference in the range of 100mv to +v cc . there are several critical items concerning the reference input and its wide voltage range. as the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. this is often referred to as the lsb size and is equal to the reference voltage divided by 4096. any offset or gain error inherent in the adc will appear to increase, in terms of lsb size, as the reference voltage is reduced. for example, if the offset of a given converter is 2lsbs with a 2.5v reference, then it will typically be 10lsbs with a 0.5v reference. in each case, the actual offset of the device is the same, 1.22mv. likewise, the noise or uncertainty of the digitized output will increase with lower lsb size. with a reference voltage of 100mv, the lsb size is 24 v. this level is below the internal noise of the device. as a result, the digital output code will not be stable and vary around a mean value by a number of lsbs. the distribution of output codes will be gaussian and the noise can be reduced by simply averaging consecutive conversion results or applying a digital filter. with a lower reference voltage, care should be taken to provide a clean layout including adequate bypassing, a clean (low-noise, low-ripple) power supply, a low-noise reference, and a low-noise input signal. because the lsb size is lower, the converter will also be more sensitive to nearby digital signals and electromagnetic interference. the voltage into the v ref input is not buffered and directly drives the cdac portion of the ads7842. typically, the input current is 13 a with a 2.5v reference. this value will vary by microamps depending on the result of the conversion. the reference current diminishes directly with both conversion rate and reference voltage. as the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference. data format the ads7842 output data is in straight offset binary format, see table iv. this table shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise. layout for optimum performance, care should be taken with the physical layout of the ads7842 circuitry. this is particularly true if the reference voltage is low and/or the conversion rate is high. the basic sar architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connec- tions, and digital inputs that occur just prior to latching the output of the analog comparator. thus, during any single conversion for an n-bit sar converter, there are n windows in which large external transient voltages can easily affect the conversion result. such glitches might originate from switch- ing power supplies, nearby digital logic, and high-power devices. the degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. the error can change if the external event changes in time with respect to the dclk input. with this in mind, power to the ads7842 should be clean and well bypassed. a 0.1 f ceramic bypass capacitor should be placed as close to the device as possible. in addition, a 1 f to 10 f capacitor and a 5 ? or 10 ? series resistor may be used to low-pass filter a noisy supply. the reference should be similarly bypassed with a 0.1 f capacitor. again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. if the reference voltage originates from an op amp, make sure that it can drive the bypass capacitor without oscillation (the series resistor can help in this case). the ads7842 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of clk during a conversion). the ads7842 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input. this is of particular concern when the reference input is tied to the power supply. any noise and ripple from the supply will appear directly in the digital results. while high frequency noise can be filtered out as discussed in the previous paragraph, voltage variation due to line frequency (50hz or 60hz) can be difficult to remove. the gnd pin should be connected to a clean ground point. in many cases, this will be the analog ground. avoid connec- tions which are too near the grounding point of a microcontroller or digital signal processor. if needed, run a ground trace directly from the converter to the power-supply entry point. the ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.
ads7842 sbas103b 14 www.ti.com package drawing msso002d january 1995 revised september 2000 db (r-pdso-g**) plastic small-outline 4040065 /d 09/00 28 pins shown gage plane 8,20 7,40 0,15 nom 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 C 8 0,10 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
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