EDI8F81024C 1megx8 sram module 1 EDI8F81024C rev. 7.0 4/96 eco#7470 1megx8 static ram cmos, module the EDI8F81024C is a 8 megabit cmos static ram based on eight 128kx8 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. a version featuring low power with data retention (edi8f81024lp) is also available. the EDI8F81024C is offered in a double sided, 36 pin single- in-line package (sip). surface mount sip technology is a cost effective solution to very high packing density requirements. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the EDI8F81024C requires no clocks or refreshing for operation. pin configurations and block diagram pin names a?-a19 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v10%) vss ground nc no connection pin names a?-a16 w g decoder a19 a18 a17 e dq?-dq7 decoder nc vcc w dq2 dq3 dq? a1 a2 a3 a4 vss dq5 a10 a11 a5 a13 a14 a19 e a15 a16 a12 a18 a6 dq1 vss a? a7 a8 a9 dq7 dq4 dq6 a17 vcc g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 features 1024kx8 bit cmos static random access memory ? access times 70 thru 100ns ? data retention function (edi8f81024lp) ? ttl compatible inputs and outputs ? fully static, no clocks high density packaging ? 36 pin sip, no. 62 ? 36 pin, flat sip, no. 336 single +5v (10%) supply operation electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748
2 EDI8F81024C rev. 7.0 4/96 eco#7470 EDI8F81024C 1megx8 sram module absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 80 130 ma supply current min cycle standby (ttl) power icc2 e ? vih, vin - vil -- 40 90 ma supply current vin ? vih full standby power icc3 e ? vcc-0.2v c -- 10 20 ma supply current (cmos) vin ? vcc-0.2v or lp -- 400 950 a vin - 0.2v input leakage current ili vin = 0v to vcc -- -- 10 a output leakage current ilo v i/o = 0v to vcc -- -- 10 a output high voltage voh ioh =-1.0ma 2.4 -- -- v output low voltage vol iol = 2.1ma -- -- 0.4 v *typical: ta = 25c, vcc = 5.0v capacitance truth table (f=1.0mhz, vin=vcc or vss) parameter sym max unit input capacitance (except dq pins) ci 58 pf capacitance (dq pins) cd/q 43 pf input (e) control lines cc 10 pf input (w) line (g) cw 60 pf these parameters are sampled, not 100% tested. ac test conditions voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature plastic -55c to +125c power dissipation 1 watt output current. 20 ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl =100pf (note: for tehqz,tghqz and twlqz, cl = 5pf) g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1
EDI8F81024C 1megx8 sram module 3 EDI8F81024C rev. 7.0 4/96 eco#7470 ac characteristics read cycle symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time tavav trc 70 85 100 ns address access time tavqv taa 70 85 100 ns chip enable access time telqv tacs 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 35 40 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 40 45 50 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z(1) tghqz tohz 30 35 40 ns tavav tavqv tavqx data 2 a q address 1 address 2 data 1 telqv telqx e q tehqz a tavav tavqv read cycle 2 - w high read cycle 1 - w high, g, e low note: parameter guaranteed, but not tested.
4 EDI8F81024C rev. 7.0 4/96 eco#7470 EDI8F81024C 1megx8 sram module ac characteristics write cycle note 1: parameter guaranteed, but not tested. write cycle symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time tavav twc 70 85 100 ns chip enable to end of write telwh tcw 65 70 80 ns teleh tcw 65 70 80 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 65 70 80 ns taveh taw 65 70 80 ns write pulse width twlwh twp 65 70 80 ns twleh twp 65 70 80 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 35 40 ns tdveh tdw 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 ns write cycle 1 - w controlled a e w d q tavav telwh tavwh twlwh tavwl tdvwh twhdx twhqx high z twlqz data valid twhax
EDI8F81024C 1megx8 sram module 5 EDI8F81024C rev. 7.0 4/96 eco#7470 write cycle 2 - e controlled a w e d q tavav tavel tehax tdveh tehdx teleh taveh data valid high z twleh data retention e controlled characteristic sym test conditions vdd min typ max unit 70c 85c data retention voltage vdd vdd = 0.2v 2 -- -- -- v data retention quiescent current iccdr e ? vdd -0.2v 2v -- 25 300 400 a vin ? vdd -0.2v 3v -- 50 450 550 a chip disable to data retention time (1) tcdr or vin - 0.2v 0 -- -- -- ns operation recovery time (1) tr tavav* -- -- -- ns note 1: parameter guaranteed, but not tested. * read cycle time data retention characteristics
6 EDI8F81024C rev. 7.0 4/96 eco#7470 EDI8F81024C 1megx8 sram module standard power low power with speed package data retention (ns) no. EDI8F81024C70bsc edi8f81024lp70bsc 70 62 EDI8F81024C85bsc edi8f81024lp85bsc 85 62 EDI8F81024C100bsc edi8f81024lp100bsc 100 62 EDI8F81024C70bfc edi8f81024lp70bfc 70 336 EDI8F81024C85bfc edi8f81024lp85bfc 85 336 EDI8F81024C100bfc edi8f81024lp85bfc 100 336 electronic designs incorporated ? one research drive ? westborough, ma 01581usa ? 508-366-5151 ? fax 508-836-4850 ? electronic designs europe ltd. ? shelley house, the avenue ? lightwater, surrey gu18 5rf united kingdom ? 01276 472637 ? fax: 01276 473748 electronic designs inc. reserves the right to change specifications without notice. cage no. 66301 package no. 336 36 pin flat sip package description package no. 62 36 pin single-in-line package note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. EDI8F81024C70bsc becomes EDI8F81024C70bsi. ordering information 0.125 min 35 x 0.100 =3.500 4.040 max 0.020 0.016 0.575 0.565 0.200 max 0.100 p1 max. .575 4.040 max. .200 max. 3.500 ref. 35 x .100 .100 typ. .050 .050
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