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1997 microchip technology inc. ds00541e-page 1 introduction pic16c5x microcontrollers from microchip are ideally suited for use as smart peripheral devices under the con- trol of the main processors in systems, due to their low cost and high speed. they are capable of performing tasks which would simply overload a conventional micro- processor, or require considerable logic circuitry, at a cost competitive with lower mid-range plds. to minimize the engineering overhead of adding multiple controllers to a product, it is convenient for the auxiliary controllers to emulate standard i/o peripherals. a common interface found in existing products is the i 2 c bus. this ef?ient, two-wire, bi-directional interface allows the designer to connect multiple devices together, with the microprocessor able to send data to and receive data from any device on the bus. this interface is found on a variety of components, such as plls, dacs, video controllers, and eeproms. if a product already contains one or more i 2 c devices, it is simple to add a pic16c5x emulating a compatible component. this application note describes the implementation of a standard slave device with multiple, bi-directional registers. a subset of the full i 2 c speci?ation is supported, which can be controlled by the same software which would talk to a microchip 24lcxx series eeprom. the i 2 c bus the i 2 c bus is a master-slave two-wire interface, consisting of a clock line (scl) and a data line (sda). bi-directional communication (and in a full, multi-master system, collision detection, and clock synchronization) is facilitated through the use of a ?ire-and (i.e., active-low, passive-high) connection. the standard mode i 2 c bus supports scl clock frequencies up to 100 khz. the fast-mode i 2 c bus sup- ports clock rates up to 400 khz. this application note will support the 100 khz (standard-mode) clock rate. each device has a unique seven bit address, which the master uses to access each individual slave device. during normal communication, the sda line is only per- mitted to change while the scl line is low, thus providing two violation conditions (figure 1) which are used to sig- nal a start condition (sda drops while scl is high) and a stop condition (sda rises while scl is high), which frame a message. author: don lekei nii norsat international inc. figure 1: i 2 c timing each byte of a transfer is 9-bits long (see timing chart in the program listing). the talker sends 8 data bits followed by a '1' bit. the listener acknowledges the receipt of the byte and gives permission to send the next byte by inserting a '0' bit over the trailing '1'. the lis- tener may indicate "not ready for data" by leaving the acknowledge bit as a '1'. the clock is generated by the master only. the slave device must respond to the master within the timing speci?ations of the i 2 c de?ition otherwise the master would be required to operate in slow mode, which most software implementations of i 2 c masters do not actually support. the speci?d (standard-mode) t cl is 4.7 m s, and t ch is only 4 m s, so it would be extremely dif- ?ult to achieve the timing of a hardware slave device with a conventional microcontroller. message format a message is always initiated by the master, and begins with a start condition, followed by a slave address (7 msbs) and direction bit (lsb = '1' for read, '0' for write). the addressed slave must acknowledge this byte if it is ready to communicate any data. if the slave fails to respond, the master should initiate a stop condi- tion and retry. if the direction bit is '0' the next byte is considered the sub-address (this is an extension to i 2 c used by most multi-register devices). the sub-address selects which "register" or ?unction subsequent read or write operations will affect. any additional bytes will be received and stored in consecutive locations until a stop is sent. if the slave is unable to process more data, it could termi- nate transfer by not acknowledging the last byte. scl sda start data bit more bits stop t sh t cl t ch 1 1 0 1 1 1 1 r/w a scl sda AN541 using a pic16c5x as a smart i 2 c ? peripheral
AN541 ds00541e -page 2 1997 microchip technology inc. if the direction bit is '1', the sla v e will tr ansf er successiv e b ytes to the master (the master holds the line at '1'), while the master ac kno wledges each b yte with a '0' in the ninth bit. the master can ter minate the tr ansf er b y not ac kno wledging the last b yte , while the sla v e can stop the tr ansf er b y gener ating a stop condition. the star t address of a read oper ation is set b y sending a wr ite request with a sub-address only (no data b ytes). f or a detailed set of timing diag r ams and diff erent comm unication modes , consult an y of the microchip 24lcxx eepr om speci cations . this prog r am comm unicates using the same f or mats . implement a tion the chip will respond to sla v e address "device_address", which b y def ault is d6 16 (d7 16 f or read). this address w as chosen because it is the f our th optional address of a philips pcf8573 cloc k /calender or a td a8443 tipple video s witch (unlik ely that a product w ould contain f our of those). figure 2: schema tic of i 2 c connections the connections to the de vice are sho wn in figure 2 . the use of ra0 f or data input is required. data is shifted directly out of the por t. the code could be mod- i ed to mak e it por t independent, b ut the loss of ef - ciency ma y hinder some real-time applications . this application em ulates an i 2 c de vice with 8 registers , accessed as sub-addresses 1 through 8 (module 7), plus a data channel (0). the e xample code retur ns an id str ing when the data channel is accessed. when b ytes are wr itten to sub-addresses other than 0, the y are stored in i2cr0-i2cr7 (i2cr0 gets data wr itten to sub-address 8). sd a scl u1 ra2 ra3 t0cki mclr v ss rb0 rb1 rb2 rb3 ra1 ra0 osc1 osc2 v dd rb7 rb6 rb5 rb4 +5v r2* +5v pic16c5x 100 w x1 20 mhz 15 pf 15 pf *r2 ma y be needed if not pro vided at the master . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 figure 3: i 2 c device flo wchar t reset initializ e i 2 c p or ts reset i 2 c places do main user t ask do main user t ask sd a and scl both high? t est scl, sd a cloc k in 8-bits sla v e address correct? send a ck bit = 0? cloc k in 8-bits send a ck get sub-address stop? cloc k in 8-bits send a ck get sub-address process message cloc k out 8-bits send a ck process byte stop? user message clean up code y es no x, 0 1, 1 1, 0 stop no y es no y es stop no no y es y es
1997 microchip technology inc. ds00541e -page 3 AN541 when the initial subaddress is 0, the ag b_id is set. this is used to indicate access to a special channel. in this case , the data channel is used to retur n an id message , or output data to por tb , ho w e v er the natur al e xtension w ould be to use this as a data i/o channel. t o mak e the basic de vice routines easily adaptab le to a v ar iety of uses , macros are used to implement the application speci c code . this allo ws the de v eloper the option of using subroutine calls , or in-line code to a v oid the 4 cloc k cycle o v erhead and use of the precious stac k. macr o user code function user_main code to e x ecute in the main loop while not in a message . if this code tak es too long, t sh of 4 m s will be violated ( figure 1 ). the sla v e will simply miss the address , not ac kno wledge , and the master will retr y . user_q this w ould be quic k user code to implement real-time processes . in most applications , this macro w ould be empty . if used, this rou- tine should be k ept under 4 m s if possib le . user_msg this w ould be user code to pro- cess a message . it is inser ted after a message is successfully receiv ed. user_recv this w ould be user code to pro- cess a receiv ed b yte . it allo ws the user to add e xtr a code to imple- ment special pur pose sub-addresses such as fifos . user_xmit this w ould be user code to pre- pare an output b yte . in the def ault routine , it tr aps sub-address 0 and calls the id str ing function. ref erences: i 2 c bus speci cation , philips cor por ation, december 1988. the i 2 c b us and ho w to use it (including speci cation), signetics/philips semiconductors , j an uar y 1992. f enger , car l, "the inter-integ r ated circuit (i 2 c) ser ial bus: theor y and pr actical consider ation", application note 168, philips components , december 1988. "24c16 16k cmos ser ial electr ically er asab le pr om", microchip data book (1992). about the a uthor: don lek ei has been designing microprocessor based products o v er 14 y ears . he has de v eloped man y softw are and hardw are products f or a wide v ar iety of applications . mr . lek ei is manager of adv anced t echnologies at nii norsat inter national inc. at their canadian headquar ters in surre y , br itish columbia. norsat designs and man uf actures products to receiv e broadcast comm unications from satellites , terrestr ial broadcasting systems and optical bre . norsat de v elops technologies and products f or satellite enter tainment tele vision, broadcast m usic and data netw or ks .
AN541 ds00541e -pag e 4 1997 microchip technology inc. appendix a: i2c.asm mpasm 01.40 released i2c.asm 1-16-1997 14:51:28 page 1 loc object code line source text value 00001 list p=16c54, c=80, n=0, r=dec 00002 ; 00003 ;***************************************************************** 00004 ; 00005 ; program: i2c.asm 00006 ; revision date: 00007 ; 1-13-97 compatibility with mpasmwin 1.40 00008 ; 00009 ;*************************************************************** 00010 ; 00000676 00011 cpu equ 1654 00000000 00012 sim equ 0 ;change timing constants for simulator 00013 00014 if (cpu==1654) || (cpu==1655) 000001ff 00015 _resvec equ 01ffh ;16c54 start address 00016 endif 00017 00018 if cpu==1656 00019 _resvec equ 03ffh ;16c56 start address 00020 endif 00021 00022 if cpu==1657 00023 _resvec equ 07ffh ;16c57 start address 00024 endif 00025 00026 ;*** reset vector ******************************************* 00027 01ff 00028 org _resvec ; 01ff 00029 resvec ; 01ff 0a0b 00030 goto init ; 00031 00032 ;*********************************************************** 00033 00034 ;*********************************************************** 00035 ;* macros to set/clear/branch/skip on bits 00036 ;* these macros define and use synthetic bit labels 00037 ;* bit labels contain the address and bit of a location 00038 ;* 00039 ;********************************************************************** 00040 ;* usage description 00041 ;* ----------------------- --------------------- 00042 ;* bit label,bit,file ;define a bit label 00043 ;* seb label ;set bit using bit label 00044 ;* clb label ;clear bit using bit label 00045 ;* skbs label ;skip on bit set 00046 ;* skbc label ;skip on bit clear 00047 ;* bbs label,address ;branch on bit set 00048 ;* bbc label,address ;branch on bit clear 00049 ;* cbs label,address ;call on bit set 00050 ;* cbc label,address ;call on bit clear 00051 ;* 00052 ;********************************************************************** 00053 00054 bit macro label,bit,file ;define a bit label please che c k the microchip bbs f or the latest v ersion of the source cod e . microchip s w o r ldwid e w eb address : ww w .microchi p .com ; bulletin board suppo r t : mchipbbs using compuse r v e (compuse r v e membership not required).
1997 microchip technology inc. ds00541e -page 5 AN541 00055 label equ file<<8|bit ;(macro) 00056 endm ; 00057 00058 seb macro label ;set bit 00059 bsf label>>8,label &7 ;(macro) 00060 endm ; 00061 00062 clb macro label ;clear bit 00063 bcf label>>8,label &7 ;(macro) 00064 endm ; 00065 00066 skbs macro label ;skip on bit set 00067 btfss label>>8,label &7 ;(macro) 00068 endm 00069 00070 skbc macro label ;skip on bit clear 00071 btfsc label>>8,label &7 ;(macro) 00072 endm 00073 00074 bbs macro label,address ;branch on bit set 00075 btfsc label>>8,label &7 ;(macro) 00076 goto address ;(macro) 00077 endm ; 00078 00079 bbc macro label,address ;branch on bit clear 00080 btfss label>>8,label &7 ;(macro) 00081 goto address ;(macro) 00082 endm 00083 00084 cbs macro label,address ;call on bit set 00085 call label>>8,label &7 ;(macro) 00086 endm ; 00087 00088 cbc macro label,address ;call on bit clear 00089 call label>>8,label &7 ;(macro) 00090 endm 00091 00092 00093 ;for assembler portability 00094 00000000 00095 w equ 0 ;for file,w 00000000 00096 w equ 0 ;for file,w 00000001 00097 f equ 1 ;for file,f 00000001 00098 f equ 1 ;for file,f 00099 00100 ;******************************************************************* 00101 ;* register declarations 00102 ;******************************************************************* 00103 00104 0000 00105 org 0 ;org for register declarations 00106 0000 00107 ind res 1 ;0=pseudo-reg 0 for in direct (fsr) 0001 00108 tmr0 res 1 ;1=real time counter 0002 00109 pc res 1 ;2=pc 0003 00110 status res 1 ;3=status reg 00111 00112 ;* status reg bits 00113 00114 bit b_c,0,status ;carry 00000300 m b_c equ status<<8|0 ;(macro) 00115 bit b_dc,1,status ;half carry 00000301 m b_dc equ status<<8|1 ;(macro) 00116 bit b_z,2,status ;zero 00000302 m b_z equ status<<8|2 ;(macro) 00117 bit b_pd,3,status ;power down
AN541 ds00541e -page 6 1997 microchip technology inc. 00000303 m b_pd equ status<<8|3 ;(macro) 00118 bit b_to,4,status ;timeout 00000304 m b_to equ status<<8|4 ;(macro) 00119 bit b_pa0,5,status ;page select (56/57 only) 00000305 m b_pa0 equ status<<8|5 ;(macro) 00120 bit b_pa1,6,status ;page select (56/57 only) 00000306 m b_pa1 equ status< ;(macro) 00121 bit b_pa2,7,status ;gp flag 00000307 m b_pa2 equ status<<8|7 ;(macro) 00122 0004 00123 fsr res 1 ;4=file select reg 0-4 =indirect address 0005 00124 porta res 1 ;5=port a i/o register (4 bits) 0006 00125 portb res 1 ;6=port b i/o register 00126 00127 if (cpu==1655)||(cpu==1657) 00128 portc res 1 ;7=i/o port c on 16c54/56 only 00129 endif 00130 00131 ;registers used by this code 00132 0007 00133 i2cflg res 1 ;i2c flag reg 00134 ;--i2c flags------------------------------------------------- 00135 bit b_rd,0,i2cflg ;flag: 1=read 00000700 m b_rd equ i2cflg<<8|0 ;(macro) 00136 bit b_ua,1,i2cflg ;flag: 0=reading unit address 00000701 m b_ua equ i2cflg<<8|1 ;(macro) 00137 bit b_sa,2,i2cflg ;flag: 1=reading subabbress 00000702 m b_sa equ i2cflg<<8|2 ;(macro) 00138 bit b_id,3,i2cflg ;flag: 1=reading id 00000703 m b_id equ i2cflg<<8|3 ;(macro) 00139 ;------------------------------------------------------------ 0008 00140 i2creg res 1 ;i2c i/o register 0009 00141 i2csuba res 1 ;subaddress 000a 00142 i2cbits res 1 ;i2c xmit bit counter 00143 00144 00145 ;********************************************************************** 00146 ;* 8 pseudo registers accessed by sub-addresses 1-8 00147 ;* (address 0 accesses the id string) 00148 ;* these are read-write registers 00149 ;********************************************************************** 00150 00151 0000000b 00152 i2cr0 equ $ ;sub-address 8 000b 00153 res 1 ;8 pseudo registers 00154 0000000c 00155 i2cr1 equ $ ;sub-address 1 000c 00156 res 1 00157 0000000d 00158 i2cr2 equ $ ;sub-address 2 000d 00159 res 1 00160 0000000e 00161 i2cr3 equ $ ;sub-address 3 000e 00162 res 1 00163 0000000f 00164 i2cr4 equ $ ;sub-address 4 000f 00165 res 1 00166 00000010 00167 i2cr5 equ $ ;sub-address 5 0010 00168 res 1 00169 00000011 00170 i2cr6 equ $ ;sub-address 6 0011 00171 res 1 00172 00000012 00173 i2cr7 equ $ ;sub-address 7 0012 00174 res 1
1997 microchip technology inc. ds00541e -page 7 AN541 00175 00176 ;constants used by program 00177 000000d6 00178 device_address equ 0d6h ;i2c device address (device_address+1 = read) 00179 00180 ;************************************************************** 00181 ;** porta definitions 00182 ;** i2c interface uses porta 00183 ;** note sda goes to a0 for code efficiency 00184 ;** 00185 ;*************************************************************** 00186 00187 000000f7 00188 taread equ b11110111 ;trisa register for sda read 000000f6 00189 tawrite equ b11110110 ;trisa register for sda write 000000f7 00190 tainit equ taread ;initial trisa value 00191 00192 bit b_sda,0,porta ;i2c sda (data) this must be bit 0! 00000500 m b_sda equ porta<<8|0 ;(macro) 00193 bit b_scl,1,porta ;i2c scl (clock) 00000501 m b_scl equ porta<<8|1 ;(macro) 00194 ;spare b_???,2,porta ;not used 00195 ;spare b_???,3,porta ;not used 00196 00197 ;************************************************************** 00198 ;** 00199 ;** port b definition (parallel out) 00200 ;** 00201 ;**************************************************************** 00000000 00202 tbinit equ b00000000 ;port b tris (all output) 000000ff 00203 pbinit equ b11111111 ;port b init 00204 00205 00206 ;********************************************************************** 00207 ;* macros to contain user poll loop code. 00208 ;* these are implemented as macros to allow ease of modification, 00209 ;* especially in real-time applications. the functions could be coded 00210 ;* as in-line code or as subroutines depending on rom/time tradeoffs. 00211 ;* 00212 ;* user_main: decision or code to perform at idle time 00213 ;* 00214 ;* user_q: quick code for use during transfer - max 8 s for 00215 ;* full i2c spec. more than 4s may result in i2c 00216 ;* retries (at full spec speed. 00217 ;* 00218 ;* user_msg: code to execute at receipt of i2c command. 00219 ;* 00220 ;********************************************************************** 00221 00222 user_main macro 00223 ;*** this would be user code for idle loop 00224 endm 00225 00226 user_q macro 00227 ;*** this would be quick user code 00228 endm 00229 00230 user_msg macro 00231 ;*** this would be user code to process a message 00232 endm 00233 00234 user_recv macro 00235 ;*** this would be user code to process a received byte 00236 ;*** example code sends sub-address 0 to port b 00237 bbc b_id,_nxi_notid ;channel 0! bit set if initial address was 0 00238 movfw i2creg ;get received byte
AN541 ds00541e -page 8 1997 microchip technology inc. 00239 movwf portb ;and write it on portb 00240 goto in_cont 00241 _nxi_notid 00242 endm 00243 00244 user_xmit macro 00245 ;*** this would be user code to prepare an output byte 00246 ;*** example code sends id string to output 00247 bbc b_id,_nxo_notid ;channel 0! bit set if initial address was 0 00248 call getid ;get next byte from id channel 00249 goto out_cont ;and send it 00250 _nxo_notid 00251 endm 00252 00253 ;******************************************************************* 00254 ; start of code 00255 ;******************************************************************* 0000 00256 org 0 00257 ;******************************************************************* 00258 ;* device id table (must be at start) 00259 ;* table for unit id returns next char in w 00260 ;******************************************************************* 0000 00261 getid 0000 0209 00262 movfw i2csuba ;w=i2csuba 0001 0e07 00263 andlw 07h ;limit to 8 locations 0002 01e2 00264 addwf pc,f 00265 00266 ;********************************************************************** 00267 ;* device id text: read starting at sub-address 0 00268 ;********************************************************************** 00269 0003 0850 00270 retlw p 0004 0849 00271 retlw i 0005 0843 00272 retlw c 0006 0849 00273 retlw i 0007 0832 00274 retlw 2 0008 0843 00275 retlw c 0009 0800 00276 retlw 0 000a 0800 00277 retlw 0 00278 00279 00280 ;********************************************************************** 00281 ;* i2c device routines 00282 ;* 00283 ;* enable must be high, else state goes to 0 00284 ;* write is to me, read is from me. 00285 ;* 00286 ;* <============== first byte / subsequent writes =====> 00287 ;* 00288 ;* sda --|x-----x-----x-----x-----x-----x-----x-----x---x------| |-- 00289 ;* |---x-----x-----x-----x-----x-----x-----x-----x---x******|--| 00290 ;* (bit) s 7 6 5 4 3 2 1 0 ackout 00291 ;* scl -----| |--| |--| |--| |--| |--| |--| |--| |--| 00292 ;* |--| |--| |--| |--| |--| |--|--| |--| |--| 00293 ;* 00294 ;* state: 0 1 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 4 5 6 2 3 0 00295 ;* 00296 ;* <============== subsequant reads ===================> 00297 ;* 00298 ;* sda x-----x-----x-----x-----x-----x-----x-----x----x------x----- 00299 ;* --x-----x-----x-----x-----x-----x-----x-----x----x******x----- 00300 ;* (bit)ack 7 6 5 4 3 2 1 0 ackin 00301 ;* scl --| |--| |--| |--| |--| |--| |--| |--| |--| |--| |-- 00302 ;* |--| |--| |--| |--| |--| |--| |--| |--| |--| |--| 00303 ;* 00304 ;* state: 7 8 7 8 7 8 7 8 7 8 7 8 7 8 7 8 9 a 7 8
1997 microchip technology inc. ds00541e -page 9 AN541 00305 ;* 00306 ;* <============== final read =========================> 00307 ;* 00308 ;* sda x-----x-----x-----x-----x-----x-----x-----x----x-|**|------- 00309 ;* --x-----x-----x-----x-----x-----x-----x-----x----x*|--| 00310 ;* (bit)ack 7 6 5 4 3 2 1 0 ackin 00311 ;* scl --| |--| |--| |--| |--| |--| |--| |--| |--| |--------- 00312 ;* |--| |--| |--| |--| |--| |--| |--| |--| |--| 00313 ;* 00314 ;* state: 7 8 7 8 7 8 7 8 7 8 7 8 7 8 7 8 9 a 0 0 00315 ;* 00316 ;* state b is an ignore bit state for non-addressed bits 00317 ;* state c indicates last sample had ena low on rising 00318 ;* edge of ena, data low = low voltage, data&clock low = reset 00319 ;***************************************************************** 00320 00321 ;i2c interface uses porta 00322 ;note sda must be on porta,0 for code efficiency 00323 00324 ;***************************************************************** 00325 ;** init 00326 ;** hardware reset entry point 00327 ;** 00328 ;***************************************************************** 000b 00329 init ;power-on entry 00330 00331 ;***************************************************************** 00332 ;** reset 00333 ;** software reset entry point 00334 ;** 00335 ;***************************************************************** 000b 00336 reset ;soft reset 00337 000b 0cf7 00338 movlw tainit ;init ports 000c 0005 00339 tris porta 000d 0c00 00340 movlw tbinit 000e 0006 00341 tris portb 000f 0cff 00342 movlw pbinit 0010 0026 00343 movwf portb 00344 00345 ;***************************************************************** 00346 ; main wait loop while idle. poll loop should be called here 00347 ; 00348 ;***************************************************************** 00349 0011 00350 i2cwait 0011 0004 00351 clrwdt ;clear watchdog timer 00352 clb b_ua ;init state flags 0012 0427 m bcf b_ua>>8,b_ua&7 ;(macro) 00353 clb b_sa ;init state flags 0013 0447 m bcf b_sa>>8,b_sa&7 ;(macro) 00354 clb b_rd ;init state flags 0014 0407 m bcf b_rd>>8,b_rd&7 ;(macro) 00355 0015 00356 loop1 0015 0004 00357 clrwdt ;clear watchdog timer 00358 00359 user_main ;call user code while in idle state m ;*** this would be user code for idle loop 00360 00361 skbc b_sda ;wait for sda&scl=h 0016 0605 m btfsc b_sda>>8,b_sda&7 ;(macro) 0017 00362 loop2 00363 skbs b_scl ; 0017 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 0018 0a15 00364 goto loop1 ; no longer valid to wait for start!
AN541 ds00541e -page 10 1997 microchip technology inc. 00365 0019 0004 00366 clrwdt ;clear watchdog timer 00367 00368 user_main ;call user code while in idle state m ;*** this would be user code for idle loop 00369 00370 ;** wait for start ** 00371 skbc b_scl ;clock has dropped 001a 0625 m btfsc b_scl>>8,b_scl&7 ;(macro) 00372 skbc b_sda ;data dropped... start! 001b 0605 m btfsc b_sda>>8,b_sda&7 ;(macro) 001c 0a17 00373 goto loop2 00374 00375 ;** start received! --- wait for first bit! 001d 00376 loop3 00377 bbs b_sda,i2cwait ;data raised before clock dropped -- abort 001d 0605 m btfsc b_sda>>8,b_sda&7 ;(macro) 001e 0a11 m goto i2cwait ;(macro) 00378 bbs b_scl,loop3 ;wait for clock low 001f 0625 m btfsc b_scl>>8,b_scl&7 ;(macro) 0020 0a1d m goto loop3 ;(macro) 00379 00380 0021 00381 nextbyte 0021 0004 00382 clrwdt ;clear watchdog timer 0022 0c01 00383 movlw 1 ;init receive byte so bit falls off at end! 0023 0028 00384 movwf i2creg 00385 00386 ;*shift bits! external poll may be executed during low clock cycle only! 00387 ;*enable line is checked for loss of enable only during high clock 00388 00389 ;*** clock is low -- data may change here 00390 ;*** we have at least 4 s before any change can occur 00391 0024 00392 loop4 00393 user_q m ;*** this would be quick user code 0024 00394 loop4a 00395 bbc b_scl,loop4a ;wait for clock high 0024 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 0025 0a24 m goto loop4a ;(macro) 00396 00397 ;*** clock is high -- shift bit - then watch for chang e 0026 0305 00398 rrf porta,w ;move ra0 into c 0027 0368 00399 rlf i2creg,f ;shift in bit 0028 0603 00400 skpnc ;skip if not done 0029 0a36 00401 goto ack_i2c ;acknowledge byte 00402 002a 0608 00403 btfsc i2creg,0 ;skip if data bit was 0 002b 0a31 00404 goto ii_1 ;this bit was set 002c 00405 ii_0 00406 bbc b_scl,loop4 ;wait for clock low 002c 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 002d 0a24 m goto loop4 ;(macro) 00407 skbs b_sda ;data low-high == stop 002e 0705 m btfss b_sda>>8,b_sda&7 ;(macro) 002f 0a2c 00408 goto ii_0 0030 00409 i2cstop 00410 user_msg ;process completed message! m ;*** this would be user code to process a message 0030 0a11 00411 goto i2cwait ;back to main loop 00412 00413 ii_1 bbc b_sda,i2cwait ;data high-low == start 0031 0705 m btfss b_sda>>8,b_sda&7 ;(macro) 0032 0a11 m goto i2cwait ;(macro)
1997 microchip technology inc. ds00541e -page 11 AN541 00414 bbc b_scl,loop4 ;wait for clock low 0033 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 0034 0a24 m goto loop4 ;(macro) 0035 0a31 00415 goto ii_1 00416 0036 00417 ack_i2c 00418 bbc b_ua,ack_ua ;not addressed - check unit address 0036 0727 m btfss b_ua>>8,b_ua&7 ;(macro) 0037 0a8b m goto ack_ua ;(macro) 00419 bbs b_sa,ack_sa ;reading secondary address 0038 0647 m btfsc b_sa>>8,b_sa&7 ;(macro) 0039 0a97 m goto ack_sa ;(macro) 00420 00421 ;**** 00422 ;** do what must be done with new data bytes here (before ackloop) 00423 ;** dont ack if byte cant be processed! 00424 ;**** 00425 ;-------- 00426 00427 user_recv m ;*** this would be user code to process a received byte m ;*** example code sends sub-address 0 to port b m bbc b_id,_nxi_notid ;channel 0! bit set if initial address was 0 003a 0767 m btfss b_id>>8,b_id&7 ;(macro) 003b 0a3f m goto _nxi_notid ;(macro) 003c 0208 m movfw i2creg ;get received byte 003d 0026 m movwf portb ;and write it on portb 003e 0a47 m goto in_cont 003f m _nxi_notid 00428 003f 0c07 00429 movlw 07h ;register count 0040 0169 00430 andwf i2csuba,f ;limit register count 0041 0c0b 00431 movlw i2cr0 ;pseudo-registers 0042 01c9 00432 addwf i2csuba,w ;offset from buffer start 0043 02a9 00433 incf i2csuba, f ;next sub-address 0044 0024 00434 movwf fsr ;indirect address 0045 0208 00435 movfw i2creg 0046 0020 00436 movwf ind ;put data into register 00437 0047 00438 in_cont ;continue point for intercepted bytes 00439 0047 00440 ackloop 00441 bbs b_scl,ackloop ;wait for clock low 0047 0625 m btfsc b_scl>>8,b_scl&7 ;(macro) 0048 0a47 m goto ackloop ;(macro) 00442 00443 clb b_sda ;set ack 0049 0405 m bcf b_sda>>8,b_sda&7 ;(macro) 004a 0cf6 00444 movlw tawrite 004b 0005 00445 tris porta 00446 clb b_sda ;set ack (just in case docs are wrong) 004c 0405 m bcf b_sda>>8,b_sda &7 ;(macro) 00447 00448 004d 00449 ackloop2 00450 user_q m ;*** this would be quick user code 00451 bbc b_scl,ackloop2 ;wait for clock high 004d 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 004e 0a4d m goto ackloop2 ;(macro) 00452 004f 00453 ackloop3 00454 user_q m ;*** this would be quick user code 00455 bbs b_scl,ackloop3 ;wait for clock low 004f 0625 m btfsc b_scl>>8,b_scl&7 ;(macro)
AN541 ds00541e -page 12 1997 microchip technology inc. 0050 0a4f m goto ackloop3 ;(macro) 00456 0051 0cf7 00457 movlw taread ;end ack 0052 0005 00458 tris porta 00459 00460 bbc b_rd,nextbyte ;skip if read (we were acking address only) 0053 0707 m btfss b_rd>>8,b_rd&7 ;(macro) 0054 0a21 m goto nextbyte ;(macro) 00461 00462 00463 ;********************************************************************* 00464 ; i2c readback (i2c read request) 00465 ; application specific code to get bytes to send may be added here. 00466 ; this routine gets data from location pointed to by i2csuba and 00467 ; sends it to i2c. subsequent reads get sequential addresses. this 00468 ; version ands the register # with 7 to limit to 8 registers (for 00469 ; speed). thiscould be modified to do a comparison to an absolute 00470 ; number. 00471 ;********************************************************************* 00472 0055 00473 nextout 00474 00475 ;*** <<< put next byte into i2creg here now! >>> *** 00476 00477 user_xmit m ;*** this would be user code to prepare an output byte m ;*** example code sends id string to output m bbc b_id,_nxo_notid ;channel 0! bit set if initial address was 0 0055 0767 m btfss b_id>>8,b_id&7 ;(macro) 0056 0a59 m goto _nxo_notid ;(macro) 0057 0900 m call getid ;get next byte from id channel 0058 0a60 m goto out_cont ;and send it 0059 m _nxo_notid 00478 0059 0c07 00479 movlw 07h ;register count 005a 0169 00480 andwf i2csuba,f ;limit register count 005b 0c0b 00481 movlw i2cr0 ;pseudo-registers 005c 01c9 00482 addwf i2csuba,w ;offset from buffer start 005d 02a9 00483 incf i2csuba, f ;next sub-address 005e 0024 00484 movwf fsr ;indirect address 005f 0200 00485 movfw ind ;get data from register 00486 0060 00487 out_cont 0060 0028 00488 movwf i2creg 00489 ;-- add code here to init i2creg! when b_id is clear! 0061 0c08 00490 movlw 8 ;bit counter 0062 002a 00491 movwf i2cbits 00492 00493 ;** out bits! -- external poll may be executed during low clock cycle, 00494 ; but may also be executed during high cycle if necessary. 00495 00496 ;* enable line is checked for loss of enable only during high clock 00497 00498 ;*** clock is low -- change data here first! 00499 00500 ;*** loop 1: data was 1 0063 00501 iiout_loop_1 0063 0368 00502 rlf i2creg,f ;shift data out, msb first 0064 0603 00503 skpnc ;1->0: change 0065 0a79 00504 goto iiout_1 ;output another 1! 00505 clb b_sda ;output 0 0066 0405 m bcf b_sda>>8,b_sda&7 ;(macro) 0067 0cf6 00506 movlw tawrite 0068 0005 00507 tris porta 00508 clb b_sda ;set data (just in case docs are wrong) 0069 0405 m bcf b_sda>>8,b_sda&7 ;(macro)
1997 microchip technology inc. ds00541e -page 13 AN541 00509 006a 00510 iiout_0 006a 0004 00511 clrwdt ;clear watchdog timer 00512 00513 user_q m ;*** this would be quick user code 00514 006b 00515 iiout_loop_02 00516 bbc b_scl,iiout_loop_02 ;wait for clock high 006b 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 006c 0a6b m goto iiout_loop_02 ;(macro) 00517 00518 user_q m ;*** this would be quick user code 00519 006d 00520 iiout_loop_03 00521 bbs b_scl,iiout_loop_03 ;wait for clock low 006d 0625 m btfsc b_scl>>8,b_scl&7 ;(macro) 006e 0a6d m goto iiout_loop_03 ;(macro) 00522 006f 02ea 00523 decfsz i2cbits, f ;count bits 0070 0a74 00524 goto iiout_loop_0 ;loop for last bit 0 0071 0cf7 00525 movlw taread ;done with last bit 0... set to 1 for ack 0072 0005 00526 tris porta 0073 0a80 00527 goto iiout_ack ;get ack 00528 0074 00529 iiout_loop_0 0074 0368 00530 rlf i2creg,f ;shift data out, msb first 0075 0703 00531 skpc ;0->1: change 0076 0a6a 00532 goto iiout_0 ;output another 0! 00533 0077 0cf7 00534 movlw taread ;set to 1 0078 0005 00535 tris porta 00536 0079 00537 iiout_1 0079 0004 00538 clrwdt ;clear watchdog timer 00539 00540 00541 user_q m ;*** this would be quick user code 00542 007a 00543 iiout_loop_12 00544 bbc b_scl,iiout_loop_12 ;wait for clock high 007a 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 007b 0a7a m goto iiout_loop_12 ;(macro) 00545 00546 00547 user_q m ;*** this would be quick user code 00548 007c 00549 iiout_loop_13 00550 bbs b_scl,iiout_loop_13 ;wait for clock low 007c 0625 m btfsc b_scl>>8,b_scl&7 ;(macro) 007d 0a7c m goto iiout_loop_13 ;(macro) 00551 007e 02ea 00552 decfsz i2cbits, f ;count bits 007f 0a63 00553 goto iiout_loop_1 ;loop for last bit 1 00554 00555 0080 00556 iiout_ack ;get acknowledge 0080 02a9 00557 incf i2csuba, f ;next sub-address 00558 0081 00559 iiout_loop_a2 00560 bbc b_scl,iiout_loop_a2 ;wait for clock high 0081 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 0082 0a81 m goto iiout_loop_a2 ;(macro)
AN541 ds00541e -page 14 1997 microchip technology inc. 00561 00562 bbs b_sda,i2cwait ;no ack --- wait for restart! 0083 0605 m btfsc b_sda>>8,b_sda&7 ;(macro) 0084 0a11 m goto i2cwait ;(macro) 00563 00564 ;-- prepare next character here! 00565 0085 00566 iiout_loop_a3 00567 bbc b_scl,nextout ;wait for clock low - output next char! 0085 0725 m btfss b_scl>>8,b_scl&7 ;(macro) 0086 0a55 m goto nextout ;(macro) 00568 00569 bbs b_sda,iiout_loop_a3 ;watch out for new start condition! 0087 0605 m btfsc b_sda>>8,b_sda&7 ;(macro) 0088 0a85 m goto iiout_loop_a3 ;(macro) 0089 0a11 00570 goto i2cwait ;stop received! 008a 00571 user_read ;user code to process data sent 00572 008a 0a11 00573 goto i2cwait 00574 00575 00576 ;********************************************************************** 00577 ;* unit address received - check for valid address 00578 ;* 00579 ;********************************************************************** 008b 00580 ack_ua 00581 seb b_ua ;flag unit address received 008b 0527 m bsf b_ua>>8,b_ua&7 ;(macro) 008c 0608 00582 btfsc i2creg,0 ;skip if data coming in 00583 seb b_rd ;flag - reading from slave 008d 0507 m bsf b_rd>>8,b_rd&7 ;(macro) 008e 0208 00584 movf i2creg,w ;get address 008f 0efe 00585 andlw 0feh ;mask direction flage before compare 0090 0fd6 00586 xorlw device_address ;device address 0091 0743 0a11 00587 bnz i2cwait ;not for me! (skip rest of message) 00588 bbs b_rd,ackloop ;read - no secondary address 0093 0607 m btfsc b_rd>>8,b_rd&7 ;(macro) 0094 0a47 m goto ackloop ;(macro) 00589 seb b_sa ;next is secondary address 0095 0547 m bsf b_sa>>8,b_sa&7 ;(macro) 0096 0a47 00590 goto ackloop ;yes! ack address and continue! 00591 00592 ;********************************************************************** 00593 ;* secondary address received - stow it! 00594 ;* sa = 0 is converted to 128 to facilitate id read 00595 ;********************************************************************** 0097 00596 ack_sa 00597 clb b_sa ;flag second address received 0097 0447 m bcf b_sa>>8,b_sa&7 ;(macro) 00598 clb b_id 0098 0467 m bcf b_id>>8,b_id&7 ;(macro) 0099 0208 00599 movfw i2creg ;get subaddress 009a 0643 00600 skpnz ;not 0 00601 seb b_id ;flag - id area selected 009b 0567 m bsf b_id>>8,b_id&7 ;(macro) 009c 0029 00602 movwf i2csuba ;set subaddress 009d 0a47 00603 goto ackloop 00604 00605 00606 end
1997 microchip technology inc. ds00541e -page 15 AN541 memory usage map (x = used, - = unused) 0000 : xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0040 : xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 0080 : xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx-- ---------------- ---------------- 01c0 : ---------------- ---------------- ---------------- ---------------x all other memory blocks unused. program memory words used: 159 program memory words free: 353 errors : 0 warnings : 0 reported, 0 suppressed messages : 0 reported, 0 suppressed
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