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? application note using the i 2 c-bus protocol with the st9 AN415 / 1092 introduction the serial peripheral interface (spi) in the st9 has been designed to handle a wide variety of serial bus protocols, including sbus, imbus, and i 2 c-bus. certain standard i 2 c-bus features have not been directly implemented in hardware, but may be realized with simple software routines, based on the spi,contained in the standard st9 core. this application note gives an example of such routines, suitable for interfacing the st9 with a serial memory device. characteristics of the i 2 c-bus the i 2 c-bus comprises two bidirectional lines, one for data signals (sda) and one for clock signals (sck). both the sda and the sck lines must be connected to the positive supply via pull-up resistors (figure 1). myriam chabaud and alan dunworth figure 1. connection of st24c02 and st9 in i 2 c-bus note : although the st24c02 2k bit eprom is shown, this circuit will work with serial eeproms up to 16 k bit capacity (st24c16) and all others in the st24cxx and st25cxx families. 1/34
the following basic definitions are applied: * master: the device which initiates the transfer, generates the clock signals, and terminates the transfer is referred to as the master. in our present application the st9 always acts as the master. * slave: this is the device addressed by the master (always the serial memory). * transmitter: this is the device which sends data to the bus. in our application the st9 acts as transmitter when it is writing data in the serial memory. conversely, the serial memory serves as transmitter when the st9 is reading data from memory. * receiver: this is the device which receives data from the bus. in our application this will be the st9 when reading data, or the serial memory when the st9 commands a write operation. the following protocol has been defined: * data transfer a data transfer may be initiated only when the bus is not busy. * data line stable: during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: figure 2. data transfer sequence of the serial bus * start data transfer: a change in the state of the data line from high to low, while the clock is high, defines the start condition. * stop data transfer: a change in the state of the data line from low to high, while the clock is high, defines the stop condition. ? using the i 2 c-bus protocol with the st9 2/34
* data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on sda may be changed during the low period of the clock signal. there is one clock pulse for each bit of data. * data transfer: each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes,transferred between the start and stop conditions, is limited to eight bytes in the st24c02 memory device erase + write mode, and is not limited in the read mode. * acknowledge: each byte of eight bits is followed by an acknowledge bit. this acknowledge bit is a low level put on the sda line by the receiver. at the same time the transmitter releases the sda line to the high impedance state, and the master device generates an additional 9th acknowledge-related clock pulse. the receiving device acknowledges the receipt of the 8-bit byte by pulling the sda down so that is stable low during the 9th clock pulse. of course, set-up and hold-times must be respected. the st9 when acting as a master receive device, i.e. during serial memory read operations, must signal an end of data by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the serial memory must leave the sda line high to enable the master to generate a stop condition. figure 3. acknowledgement and the 9th clock pulse ? using the i 2 c-bus protocol with the st9 3/34
basic software operations the following aspects of the i 2 c-bus protocol have not been directly implemented but must be simulated in software. * generation of start conditions, * generation of stop conditions, * generation of the acknowledge pulse (9th clock signal), * generation of the acknowledge , when the st9 acts as a receiver, i.e. in read mode. * test of the acknowledge from the receiver, when the st9 acts as a transmitter, i.e. in write mode. in order to implement these features it is necessary to drive sda and/or sck high or low in the correct timing sequence. the sdo and sck signals are defined as alternate functions. these pins are configured with open-drain outputs and ttl inputs. the sdi signal is defined as an input. the spi unit is enabled or disabled using the flag spen, bit 7 in spicr, the spi control register. when the spi is disabled, both sck and sdo are released to the highimpedance state. the presence of pull-up resistors, as shown in figure 1, effectively defines both sck and sda as high, whenever the spi is disabled. note however that sda may be driven low either by the actions of peripherals connected to the sda line, or by appropriate action of the st9 on the sdo line when it is defined as a normal output. when the spi is enabled (spen = a1o), it may be in either an active or passive state. the active state is entered by loading a byte of data into the spi data register. this automatically causes the spi to generate a sequence of 8 clock pulses, during which data is shifted out on the sdo line, and input data on the sdi input is clocked into the serial input register. on completing this sequence the spi will revert to its passive (rest) mode. when the spi is in its rest mode, the sck clock output is in a state selected by cpol, bit 3 of spicr. thus with cpol set to a value of a1o the sck output will be low. the value of sdo will be low (non-programmable) when the spi is enabled but inactive. if the spi is enabled and in the rest (passive) state sdo and hence sda will be low. if the spi is disabled sdo will be released to high impedance, and hence to the high level by the presence of the pull-up resistor. it may be pulled low by loading a zero into the port 2 pin 1 output buffer and then specifying this pin as a normal port output pin. having established these basic preliminaries we can proceed to discuss the provision, by software, of basic i 2 c-bus operations. ? using the i 2 c-bus protocol with the st9 4/34
simulation of basic i 2 c-bus operations using the basic operations described in the above sections the various i 2 c-bus protocol features may be implemented as follows. generation of start conditions the generation of a start condition is implemented in procedure init_start_i2c (appendix a). a) disable the spi unit putting sda and sck in the high-impedance state. b with the spi disabled and sck high, pull the sdo line low by respecifying sdi as a normal output. c) hold the above condition for a period of ~5 m s by calling the delai macro (see appendix a). d) enable the spi, specifying sck to the rest clock state (low). e) respecify the sdo output as an alternate function. generation of stop conditions the generation of a stop condition is implemented in procedure gen_stop (see appendix a). a) pull the sda line low by respecifying sdo as a normal port output. b) release sck to high by disabling the spi. note that sda will remain low. c) hold this condition for ~5 m s using delai macro (see appendix a) so as to meet the set-up time specification d) respecify sdo as an alternate function and hence allow sda to be pulled high by the pull-up resistor. generation of 9th clock pulse with acknowledge test after the transmission of 8 data bits a 9th clock pulse may be generated and the acknowledge tested as implemented in procedure test_ack (see appendix a). a) release sck and sda to the high impedance state by disabling the spi. b) wait until the sck line goes high. c) test for low on the sda line placed by the receiver (slave). d) hold the sck line high for 5 m s using delai macro. e) force sck and sda to low by enabling the spi. generation of 9th clock and acknowledge after the reception of 8 data bits a 9th clock pulse may be generated and an acknowledge asserted as implemented in procedure gen_ack (see appendix a). a) pull the sda line low by respecifying sdo as a normal port output. b) release sck to high by disabling the spi. note that sda will remain low. c) hold the sck line high for 5 m s using delai macro. d) force sck to low by enabling the spi. e) finally respecify the sdo port pin as an alternate function. ? using the i 2 c-bus protocol with the st9 5/34
types of transfer operation supported the st9 supports the following three types of transfer with an electrically erasable serial memory (eeprom) which features an i 2 c-bus protocol, e.g. st24c02. * random write (1 to 8 bytes), * random read (1 to n bytes), * current address read (or verify), (1 to n bytes.) random write mode the serial i 2 c-bus protocol for random write operations is shown in figure 4 (single byte) or figure 5 (for up to 8 bytes). figure 4. i 2 c-bus protocol for random write mode (1 byte) figure 5. i 2 c-bus protocol for random write mode (n bytes) to write a single byte the master st9 has to transmit a sequence of 3 bytes representing successively: a) slave address: 7 bits + 8th bit = a0o signifying transmit operation. b) word address: 8 bits. c) data value: 8 bits. the st9master generates the start condition and then transmits the sequence of 3 bytes by successively loading them into the spi data register. each such data load generates a sequence of 8 clocks and 8 ? using the i 2 c-bus protocol with the st9 6/34
data bits, after which the st9 generates a 9th clock pulse and tests for an acknowledge from the slave. after the data pulse has been received and acknowledged by the slave the master terminates the transfer by generating a stop condition. to write a page of n bytes (1< n> 8) the master st9 has to transmit the above sequence of 3 bytesfollowed by the remaining n - 1 data bytes. the slave device contains an 8-bit address pointer, the 3 low order bits of which are incremented by 1 after each read/write operation with the 5 high order bits remaining constant. thus a page of up to n = 8 bytes may be written in this way. the transfer sequence proceeds as described above except that the slave continues to accept data words for writing to sequential locations until such time as the master signals end of transmission by sending a stop condition. random read mode the serial i 2 c-bus protocol for random read operations is shown in figure 6. to read a single byte the master st9 has to transmit a sequence of 3 bytes representing successively: a) slave address: 7 bits + 8th bit = a0o signifying transmit operation. b) word address: 8 bits. c) slave address: 7 bits + 8th bit = a1o signifying receive operation. figure 6. i 2 c-bus protocol for random read mode (n bytes) ? using the i 2 c-bus protocol with the st9 7/34
the st9 master generates the start condition and then transmits a dummy write operation comprising the slave address byte, followed by the word address. both these byte operations are followed by a 9th clock pulse and a concurrent test for slave acknowledge. at this point the master transmitter must become the master receiver. this is achieved by sending another start condition, followed by the retransmission of the slave address with the 8th bit set now to a1o to indicate that the subsequent data transfers are from the slave to the st9 master. from this point on the slave will provide words addressed in sequence as long as the master continues to acknowledge receipt of data. note that the address counter for read operations increments over all 8 address bits, thus enabling the entire memory to be read in one operation. the master can terminate the transfer at any time by generating a stop condition instead of an acknowledgement. current address read mode in this alternative read mode the master reads from memory at the last location referenced in either read or write mode. the serial i 2 c-bus protocol for current address read operations is shown in figure 7. to read any number of bytes the master st9 has to transmit a single byte. device address: 7 bits + 8th bit = a1o signifying receive operation. the st9 master generates the start condition and then transmits the slave address byte. at this point the master now issues an acknowledge indicating that it requires additional data. from this point on the slave will provide words addressed in sequence as long as the master continues to acknowledge receipt of data. the master can terminate the transfer at any time by issuing a stopcondition instead of an acknowledgement. figure 7. i 2 c-bus protocol for current address read mode (n bytes) ? using the i 2 c-bus protocol with the st9 8/34
eep_man: an i 2 c-bus protocol eeprom manager appendix a contains a detailed assembler listing of a representative example of an eeprom manager for a device respecting the i 2 c-bus serial protocol. this example is not intended to be definitive but should be taken as illustrative example of the use of the st9 in such applications. modifications and extensions, depending on the particular application, will readily occur to the application engineer, e.g. the use of the st9 stacks as an alternative mechanism for transferring data and parameters between the manager and the calling program. note that appendix a makes use of a number of macros which are separately listed and defined in appendix c. the eep_man / calling program interface a calling program interfaces to eep_man using four registers for calling parameters and a register-file for data. parameter/ transfer-status registers a call to eep_man is initialized byloading parameter values intothree registers, viz. eep_funct , eep_add , and nb_bytes. the status of a current transfer can be monitored by reading a fourth register, stat_eep, in which eep_man records a value giving the status of the eeprom device. eep_funct register, r3. this register is loaded with one of the following values to specify the mode of data transfer required: 1: read_funct : random read mode. 2: write_funct : random write mode. 3: verify_funct : current address (verify) mode. eep_add register, r0. this register should be loaded with the value of the eeprom byte starting address for random read/write operations. for a current address (verify) operation the contents of this register is a don't-care value. nb_bytes register, r6. this register should be loaded with the number of bytes, #n, which should be transferred in the operation. this value may have a value from 1 to 8 for write operations, or 1 to 256 for read operations. stat_eep register, r4. eep_man loads this register with one of the following values to specify the current eeprom status. 0: eep_ok : the eeprom is ok. 1: lect_on : the eeprom is reading a byte (random address mode). 2: verif_on : the eeprom is reading the current byte. 3: ecr_on : the eeprom is programming a byte (random address mode). 4: no_ack : the eeprom has not acknowledged a byte transferred from the st9 80h: eep_free_mask : the eeprom is available for a new operation. ? using the i 2 c-bus protocol with the st9 9/34
transfer of data values data_table register file a register-file, starting at r32 and of size #n should be reserved for read/verify operations, or loaded with data to be transferred to the eeprom for a write operation. the first byte to be transferred should be loaded into register r31+#n, and the last byte should be loaded into register r32. eep_man data transfer initialization routines after loading the parameter registers and setting up and, if appropriate,loading the data table, the calling routine tests stat_eep to check that the eeprom is free, and then calls procedure eep_man . this procedure first saves the byte address counter value, nb_byte , specifies the port 2 pins sdo and sck as alternate functions, and sdi as an input, and then calls one of the three maininitializing routines read_eep, verif_eep, or write_eep , depending on the value transferred in register eep_funct . these three procedures essentially carry out identical functions. after verifying that the eeprom is not busy, they enable the spi interrupt, generate a start condition, and transfer the eeprom device address by loading this value into the spi data register, spidr. note that the eeprom device address is 7 bits long together with an eight bit which is set to a0o for read or write operations, and set to o1o for verify operations. in addition, a value of a1o is loaded into the transaction status register, stat_trans_spi to indicate that the device address has been transferred. this register is loaded with an appropriate identifying value each time the spi data register is loaded. stat_trans_spi register, r 5 . this register serves as an internal status register, used by eep_man and its associated routines, to maintain a record of the nature of the current st9 to eeprom transfer. 1: t_add_slave : the eeprom device address has been transferred. 2: t_add_eep : the eeprom byte address has been transferred. 3: trans_wr_data : a write byte has been transferred. 4: trans_rd_data : a read byte has been transferred. after initiating a byte transfer by loading the spi data register, spidr, a return is made to the calling routine. at the completion of the byte transfer (8 sck clock pulses) the spi raises an interrupt on channel b0 (associated to external interrupt int2). ? using the i 2 c-bus protocol with the st9 10/34
the spi interrupt service routine this routine is called at the termination of the transmission of each byte representing a device address, word address, read data, or write data. the action effected by this routine (procedure it_end_trans, see appendix a) depends upon the values contained in the following registers: 1: stat_trans_spi register, r5. 2: stat_eep register, r4. 3: nb_bytes register, r6. 4: eep_funct register, r3. the required action depends on the nature of the previously transferred byte, indicated by the value contained in stat_trans_spi. in the case of data byte transfers the next action also depends on whether the required number of bytes has been transferred, as indicated by the value of nb_bytes. the organization of it_end_trans is illustrated by the flow diagram of figure 8. this will be described by considering in detail the logical flow of events associated with each of the three modes of data transfer. random write mode figure 5 illustrates the sequence of byte transfers involved in writing n bytes in random write mode, observing the i 2 c-bus protocol. (i) transmission of slave device address. this operation is initiated by procedure write_eep which generates a start condition, loads the device address (with the 8th bit set to 0) in spidr, thus initiating the transfer, and then returns to the calling program. in addition, this routine loads the following values into the status registers: stat_trans_spi <-1 (#t_add_slave) stat_eep <-3 (#ecr_on) (ii) transmission of word address. after transmission of the 8 bits of the device address, an interrupt is raised and entry made to interrupt procedure it_end_trans . the logical flow then follows the path ai (refer to figure 8), as a result of which the required random word address is loaded into spidr, so effecting the required byte transfer. in addition, this routine loads (or retains) the following values in the status registers: stat_trans_spi <-2 (#t_add_eep) stat_eep <-3 (#ecr_on) (iii) transmission of 1st data byte . after transmission of the 8 bits of the word address, an interrupt is raised and entry made to interrupt procedure it_end_trans . the logical flow then follows the path acg (refer to figures 8, 8b), as a result of which the 1st data byte is loaded into spidr, so effecting the required byte transfer. in addition, this routine loads (or retains) the following values in the status registers: stat_trans_spi <-3 (#trans_wr_data). stat_eep <-3 (#ecr_on) ? using the i 2 c-bus protocol with the st9 11/34
figure 8. flow diagram of the it_end_trans interrupt routine ? using the i 2 c-bus protocol with the st9 12/34
figure 8a. flow diagram of the it_end_trans interrupt routine (continued) ? using the i 2 c-bus protocol with the st9 13/34
figure 8b. flow diagram of the it_end_trans interrupt routine (continued) figure 8c. flow diagram of the it_end_trans interrupt routine (continued) ? using the i 2 c-bus protocol with the st9 14/34
(iv) transmission of subsequent data bytes . after transmission of byte #m (1 < m < n), an interrupt is raised and entry made to interrupt procedure it_end_trans. the logical flow then follows the path acfo (refer to figures 8, 8c ) as a result of which data byte #m + 1 is loaded into spidr, so effecting the required byte transfer. the following values are retained in the status registers: stat_trans_spi <-3 (#trans_wr_data). stat_eep <-3 (#ecr_on) (v) transmission of the final data byte. after transmission of byte #n, an interrupt is raised and entry made to interrupt procedure it_end_trans. the logical flow then follows the path acfn (refer to figures 8, 8c). on this occasion the watch-dog timer routine, prog_delay ( see appendix a) is entered to generate a delay equal to n x 5 milliseconds to enable the eeprom to be programmed with the new data values. for this purpose the watch_dog timer isinitialized in single operation, count-down mode, and a constant value is loaded into the counter appropriate to the required delay. an interrupt is enabled on channel a0 for the timer eoc event, and a return is made to the calling program. when the timer times out, entry is made to interrupt routine temp0 (see appendix a). this routine clears the a0 interrupt pending bit, sets the eep_free_mask bit to 1, and returns to the calling program. at this point the eeprom is available again for further data transfers. random read mode figure 6 illustrates the sequence of byte transfers involved in reading n bytes in random read mode, observing the i 2 c-bus protocol. (i) transmission of slave device address. this operation is initiated by procedure read_eep which generates a start condition, loads the device address in spidr (with the 8th bit set to a0o), thus initiating the transfer, and then returns to the calling program. in addition, this routine loads the following values into the status registers: stat_trans_spi <-1 (#t_add_slave) stat_eep <-1 (#lect_on) (ii) transmission of word address. after transmission of the 8 bits of the device address, an interrupt is raised and entry made to interrupt procedure it_end_trans . the logical flow then follows the path ai (refer to figure 8), as a result of which the required random word address is loaded into spidr, so effecting the required byte transfer. in addition, this routine loads (or retains) the following values in the status registers: stat_trans_spi <-2 (#t_add_eep) stat_eep <-1 (#lect_on) ? using the i 2 c-bus protocol with the st9 15/34
(iii) retransmission of slave device address. after transmission of the 8 bits of the word address, an interrupt is raised and entry made to interrupt procedure it_end_trans . the logical flow then follows the path ach (refer to figure 8), as a result of which the device address (with the 8th bit set to a1o), loaded into spidr, so effecting the required byte transfer. in addition, this routine loads the following values in the status registers: stat_trans_spi <-1 (#t_add_slave) stat_eep <-2 (#verif_on) (iv) read of 1st data byte. after the retransmission of the 8 bits of the device address, an interrupt is raised and entry made to interrupt procedure it_end_trans. the logical flow then follows the path aj (refer to figure 8), as a result of which a value of 0ffh is loaded into spidr, so effecting the required byte transfer from the slave memory. in addition, this routine loads (or retains) the following values in the status registers: stat_trans_spi <-4 (#trans_rd_data). stat_eep <-2 (#verif_on) ( v) read of subsequent data bytes. after transmission of byte #m (1 < m < n), an interrupt is raised and entry made to interrupt procedure it_end_trans . the logical flow then follows the path bel (refer to figure 8), as a result of which data byte #m + 1 is loaded into spidr, so effecting the required byte transfer. the following values are retained in the status registers: stat_trans_spi <-4 (#trans_rd_data). stat_eep <-2 (#verif_on) (vi) read of the final data byte. after transmission of byte #n, an interrupt israised and entry made to interruptprocedure it_end_trans . the logical flow then follows the path bk (refer to figure 8), as a result of which the stop condition is generated and the eeprom free bit set in stat_eep . ? using the i 2 c-bus protocol with the st9 16/34
current address read (verify) mode figure 7 illustrates the sequence of byte transfers involved in reading n bytes in random write mode, observing the i 2 c-bus protocol. (i) transmission of slave device address. this operation is initiated by procedure verif_eep which generates a start condition, loads the device address (with the 8th bit set to a1o) in spidr, thus initiating the transfer, and then returns to the calling program. in addition, this routine loads the following values into the status registers: stat_trans_spi <-1 (#t_add_slave) stat_eep <-2 (#verif_on) (ii) read of 1st data byte. after the retransmission of the 8 bits of the device address, an interrupt is raised and entry made to interrupt procedure it_end_trans . the logical flow then follows the path aj (refer to figure 8), as a result of which a value of 0ffh is loaded into spidr, so effecting the required byte transfer from the slave memory. in addition, this routine loads (or retains) the following values in the status registers: stat_trans_spi <-4 (#trans_rd_data). stat_eep <-2 (#verif_on) (iii) read of subsequent data bytes. after transmission of byte #m (1 m n), an interrupt is raised and entry made to interrupt procedure it_end_trans. the logical flow then follows the path bel (refer to figure 8), as a result of which data byte #m + 1 is loaded into spidr, so effecting the required byte transfer. the following values are retained in the status registers: stat_trans_spi <-4 (#trans_rd_data). stat_eep <-2 (#verif_on) (iv) read of the final data byte. after transmission of byte #n, an interrupt is raised and en try mad e to interrupt procedure it_end_trans. the logical flow then follows the path bk (refer to figure 8), as a result of which the stop condition is generated and the eeprom free bit set in stat_eep . ? using the i 2 c-bus protocol with the st9 17/34
illustrative calling routines appendix b contains listing of suitable calling routines to write 4 bytes to the serial eeprom or to read 6 bytes. included also in appendix b are the appropriate st9 core system and peripheral initialization routines (see also reference 1). these programs make use of the file of st9 standard register and register bit definitions listed in application note an411, symbols.inc. it will be noted that the calling routines, after initiating the data transfers, wait in test and branch loops until the eeprom is free. in a practical real-time application this waiting time (>n.5 ms for an n byte write transfer) could be used for useful processing. references (1) application note 413, ainitialization of the st9o, pierre guillemin and alan dunworth, sgs-thomson microelectronics. (2) the ast9 technical manualo, sgs-thomson microelectronics. ? using the i 2 c-bus protocol with the st9 18/34
.titlea st9 spi use with i 2 c protocol. january 24 1990 o .sbttla eeprom manager version 2.0 o .list bex .global it_end_trans, tempo, eep_man .extern reset_start ;**************************** ;* module macro definitions * ;**************************** .library ac:\st9\inc\bitmacro.inco ; change as required .mcall ifbit, attbit ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee .macrodelai ?loop_var ld counter,#03h ; 10 tcy. loop_var: dec counter ; 6 tcy. jrnz loop_var ; 12 tcy: a loop = 1.5 fs ; with a 12 mhz system clock. .endm ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee .macrodis_spi_it ; disable spi interrupt. and eipr,#~ipb0m ; reset the b0 ( spi interrupt) pending bit. and eimr,#~ib0m ; disable spi channel (b0). .endm ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee .macroen_spi_it ; enable spi interrupt. and eipr,#~ipb0m ; clear request on spi channel (b0). nop or eimr,#ib0m ; enable spi channel (b0). .endm ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee .macroinit_trans_read ; initialize spi register and interrupt ; for read operation. ld stat_trans_spi,#trans_rd_data ; initialisation for read operation. spp #0 ld spi_tamp,#0ffh ; to read the data from the eeprom. .endm ;eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee appendix a. eeprom i 2 c-bus manager routine ? using the i 2 c-bus protocol with the st9 19/34
;*********************** ; register declarations. ;*********************** eep_add = r0 ; operation address in the eeprom. write_data = r1 ; data to be programmed in the eeprom. write_data = r1 read_data = r2 ; data which has been read from the eeprom. read_data = r2 eep_funct = r3 stat_eep = r4 stat_trans_spi = r5 nb_byte = r6 ; number of bytes to be written ; (maximum 8) or to read. nb_byte = r6 spi_tamp = r7 memo_nb_byte = r14 counter = r15 data_table = 31 ; the real beginning of the table ; (1fh) ; to store data is r20h. ;*********************** ; constant declarations. ;*********************** add_eep_w == 0a0h ; address the external eeprom slave ; for write operation. add_eep_r == 0a1h ; address the external eeprom slave ; for read operation. sdi_mask = 02h ; sdi = bit 1 of port 2. sck_mask = 04h ; sck = bit 2 of port 2. sdo_mask = 08h ; sdo = bit 3 of port 2. ;eee status of eep_funct register. ; this register is used to indicate the eeprom manager the ; function to be executed. read_funct == 1 ; read mode: read after transferring the ; address pointer. ; ie: read from the current address. write_funct == 2 ; write mode. verif_funct == 3 ; alternate read mode: ;read operation without programming ;the address pointer. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 20/34
;eee status of stat_trans_spi register. ; this register permits the eeprom manager (in the spi interrupt routine) ... ; ... to know the type of the byte which has just been transmitted. t_add_slave == 1 ; the eeprom address has been transferred. t_add_eep == 2 ; the operation address has been transferred. trans_wr_data == 3 ; the data to be written has been transferred. trans_rd_data == 4 ; the data to be read has been received. ;eee status of stat_eep register. ; this register permits the caller to know the status of the eeprom. eep_ok == 0 ; eeprom is ok. lect_on == 1 ; eeprom is reading a byte. verif_on == 2 ; eeprom is reading the current byte. ecr_on == 3 ; eeprom is programming a byte. no_ack == 4 ; eeprom has not acknowledged. eep_free_mask == 80h ; eeprom is ready for a new operation... ; ... if this bit is equal to 1. .text ;******************************************************************************** ; eep_manager: eeprom manager. ; ;******************************************************************************** proc eep_man [ppr] { ; save page pointer. spp #0 dis_spi_it ld memo_nb_byte,nb_byte ; save nb_byte before decrement for ; programmation tempo. switch [ eep_funct ] { case #read_funct: call read_eep case #verif_funct: call verif_eep case #write_funct: call write_eep } ;e- end of switch. } ;e end of proc. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 21/34
;******************************************************************************** ; read_eep: normal read mode. ; read of some bytes after setting the slave address. ; ;******************************************************************************** proc read_eep [ppr] { ifbit stat_eep,#eep_free_mask ; test if eeprom free. ;{ call init_start_i 2 c ; spi and related interrupt initialization.. ; ... to support i 2 c protocol... ; ... generate a start condition. ld stat_trans_spi,#t_add_slave; slave address will be transferred. ld stat_eep,#lect_on ; a read condition is started. ; eeprom is not free = eep_free_bit = 0. ld spidr,#add_eep_w ; eeprom address in write mode to transfer ; pointer. } ;e- end of if. } ;e- end of proc. ;******************************************************************************** ; verif_eep: alternate read mode. ; read of some bytes without setting the address pointer. ; ;******************************************************************************** proc verif_eep [ppr] { ifbit stat_eep,#eep_free_mask ; test if eeprom free. ;{ call init_start_i 2 c ; spi and related interrupt initialization.. ; ... to support i 2 c protocol... ; ... generate a start condition. ld stat_trans_spi,#t_add_slave; slave address will be transferred. ld stat_eep,#verif_on ; a verif condition is started. ; eeprom is not free = eep_free_bit = 0. ld spidr,#add_eep_r ; eeprom address in read mode. } ;e- end of if. } ;e- end of proc. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 22/34
;******************************************************************************** ; write_eep: write of some bytes. ; ;******************************************************************************** proc write_eep [ppr] { ifbit stat_eep,#eep_free_mask ; test if eeprom free. ;{ call init_start_i 2 c ; spi and related interrupt initialization.. ; ... to support i 2 c protocol... ; ... generate a start condition. ld stat_trans_spi,#t_add_slave; slave address will be transferred. ld stat_eep,#ecr_on ; a write condition is started. ; eeprom is not free = eep_free_bit = 0. ld spidr,#add_eep_w ; eeprom address in write mode. } ;e- end of if. } ;e- end of proc. ;******************************************************************************** ; init_start_i 2 c: ; initialize spi to support i 2 c protocol. ; generation of a start condition. ; ;******************************************************************************** proc init_start_i 2 c [ppr] { ;e- spi initialization. spp #0 ; spi and ext. interrupts registers in page 0. ld spicr,#042h ; spi is disabled = sda and sck in hz (1). ;i 2 c bus mode is selected. ; sck frequency # 100 khz. ;e- start condition generation. and p2dr,#~sdo_mask; prepare a0o on output buffer of sdo. spp #p2c_pg and p2c0r,#~sdo_mask ; sdo line in output - sda line = a0o. delai ; wait for start condition hold time. spp #0 or spicr,#spen ; enable spi. en_spi_it ; enable spi interrupt. spp #p2c_pg or p2c0r,#sdo_mask; sdo line in af. } ;e- end appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 23/34
;******************************************************************************** ; gen_stop: generation of a stop condition. ; ;******************************************************************************** proc gen_stop [ppr] { spp #0 dis_spi_it ; disable spi interrupt. and p2dr,#~sdo_mask; prepare a0o on output buffer of sdo. spp #p2c_pg and p2c0r,#~sdo_mask ; sdo line in output - sda line = a0o. spp #0 and spicr,#~spen ; disable spi - release sck line - sck = a1o. delai ; wait for stop condition setup. spp #p2c_pg or p2c0r,#sdo_mask; sdo in af - release sda line - sda = a1o. } ;e- end ;******************************************************************************** ; gen_ack: ack pulse generation, ; and force the sda line to 0 for acknowledgement. ; ;******************************************************************************** proc gen_ack [ ppr ] { and p2dr,#~sdo_mask; prepare a0o on output buffer of sdo. spp #p2c_pg and p2c0r,#~sdo_mask ; sdo line in output - sda line = a0o. spp #0 and spicr,#~spen ; disable spi - release sck line - sck = a1o. delai ; wait for ack hold time. or spicr,#spen ; enable spi - force sda and sck low. spp #p2c_pg or p2c0r,#sdo_mask; sdo line in af. } ;e- end of proc. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 24/34
********************************************************************************* ; test_ack: ack pulse generation, ; and check the slave acknowledgment. ;******************************************************************************** proc test_ack [ ppr ] { and spicr,#~spen ; release spi lines in disabling it. attbit p2dr,#sck_mask ; wait for sck going high. ifbit p2dr, #sdi_mask ; check if receiver has acknowledged. ;(sda = 0). ; { ; if no ack. ld stat_eep,#no_ack } else { ; if ack ok. delai ; wait for high period of the clock. } ;e- end of if. or spicr,#spen ; enable spi - force sda low. } ;e- end of proc. ;******************************************************************************** ; it_end_trans: spi end of transmission interrupt service routine. ; this interrupt is connected to channel b0 in the st9. ;******************************************************************************** it_end_trans:: pushu ppr pushuw rpp srp #0 spp #0 if [ stat_trans_spi == #trans_rd_data ] { ;e- a data to be read has been received from eeprom. ld read_data,spidr; for the next instruction addressing mode. ld data_table(nb_byte),read_data ; save the received data. dec nb_byte ; number of bytes to be read. if [ setz ] { ; if the last byte has been read. call gen_stop ; g n rate stop condition in i2c protocol. ld stat_eep,#eep_free_mask ; indicates to the caller than ;eeprom is ok and free. }else{ call gen_ack ; ack pulse generation and force sda line ;to0. init_trans_read } ;e- end of else. } else { call test_ack ; ack pulse generation and test eeprom ;response.. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 25/34
if [ stat_eep == #no_ack ] { ; if no acknowledge from eeprom. call gen_stop ; stop generation. or stat_eep,#eep_free_mask ; indicates to the caller than ; eeprom is free. switch [ stat_trans_spi ] { case #t_add_slave: ;e- the slave address has been transferred. if [ stat_eep == #verif_on ] { ;e- the slave address has been transmitted for a verif operation. } else { ;e- the slave address has been transmitted for a write or a random read operation. ld stat_trans_spi,#t_add_eep ; transfer of the address of ; the eeprom operation. spp #0 ld spi_tamp,eep_add ; to transfer the read ;or write address. case #t_add_eep: ;e- the write or random read address has been transmitted. ]{ ;e- the random read addresss has been transmitted. call init_start_i2c ; a start condition is ; necessary here. ld stat_trans_spi,#t_add_slave ; the slave address must ; be transmitted again. ld spi_tamp,#add_eep_r ; eeprom address in read ; mode. ld stat_eep,#verif_on ; the next sequence is ; the same than verif ; sequence. ;e- the write address has been transmitted. } else { spp #0 ld stat_trans_spi,#trans_wr_data ; initialisation for transfer ; of data to be written. ld write_data,data_table(nb_byte) ; the first data to programm. ld spi_tamp,write_data } ;e- end of else. case #trans_wr_data: ;e- the data to be written has been transmitted. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 26/34
spp #0 dec nb_byte ; number of bytes to write. if [ clz ] { ; if the last byte has not yet ; been written. ld write_data,data_table(nb_byte) ld spi_tamp,write_data } else { ; if all data have been programmed. ; write sequence is finished. call prog_delay ; initialise watch dog timer ;to generate a 5 ms delay. call gen_stop ; stop condition generation. } ;e- end of else. } ;e- end of switch. } ;e- end of else. } ;e- end of else. popuw rpp ld spidr,spi_tamp ; data to transmit via spi. popu ppr iret ;******************************************************************************** ; prog_delay initialize the watchdog-timer to generate the delay ; necessary for programmation. ; ;******************************************************************************** proc prog_delay [ ppr ] { pushuw rpp spp #wdt_pg srp # (15 * 2) ; to access in paged registers with r. ld wcr,#wden ; watch dog mode disabled, no wait states. clr wdtpr ; to have 333 ns (with system clock = 12 mhz) ; in minimum count, ; prescaler = 0. ldw wdtr,#15015 ; 15015 * 333 ns = 5 ms. while [ clz ] { addw wdtr,#15015 ; 5 ms delay is multiplied by ; the number of bytes to programm. dec memo_nb_byte } or wdtcr,#( stsp | sc ) ; timer starts down counting. ; single mode. ; watch dog disabled. appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 27/34
; input section disabled. ; output disabled. ; interrupt a0 on timer eoc. ; top level interrupt on sw trap. popuw rpp } ;******************************************************************************** ; tempo: interrupt service routine of the watchdog timer end of count. ; this interrupt is connected to the a0 channel in the st9. ; ;******************************************************************************** tempo: pushu ppr spp #0 and eipr,#~ipa0m ; reset of wd/timer eoc interrupt pending ;bit. or stat_eep,#eep_free_mask ; write sequence is finished. popu ppr iret appendix a. eeprom i 2 c-bus manager routine (continued) ? using the i 2 c-bus protocol with the st9 28/34
.titlea main example for eepprom manager call january 24 1990 o .extern it_end_trans, eep_man, tempo .global reset_start ;************************** ; module macro definitions. ;************************** .library ac:\st9\inc\bitmacro.inco ; change if required .mcall attbit ;*********************** ; register declarations. ;*********************** eep_add = r0 ; operation address in the eeprom. write_data = r1 ; data to be programmed in the eeprom. write_data = r1 read_data = r2 ; data which has been read in the eeprom. read_data = r2 eep funct = r3 stat_eep = r4 stat_trans_spi = r5 nb_byte = r6 nb_byte = r6 cpt_delay = rr8 data_table = 31 ; the real beginning of the table to store ; data is r20h. ; 01fh ;**************************** ; interrupt vector addresses. ;**************************** ore_it_vect := 00h ; core interrupt vectors ext_it_vect := 20h ; external interrupt vectors ;****************** ; start of program. ;****************** start_prog := 100h ; start address program ;******************* ; stack declaration. ;******************* sstack := ( 14 * 16 ) - 1; system stack address group d c ustack := ( 12 * 16 ) - 1; user stack address group b appendix b. examples of calling programs ? using the i 2 c-bus protocol with the st9 29/34
;******************************************** ; declaration of the interrupt vectors table. ;******************************************** .text ; start of program .org core_it_vect ; core interrupt vector ; ********************* .word reset_start ; power on interrupt vector .org ext_it_vect ; external interrupt vector ; ************************* .word tempo ; channel a0 for watchdog timer. .word 0000 ; channel a1 not used/ .word it_end_trans ; channel b0 for spi. ;********************** ; start of main module. ;********************** .org start_prog ; start of code reset_start: spp #0 ld moder,#( sspm | uspm| div2m ); clock mode register ; internal stack ; no precaling ; external clock divided by 2 ;e- spi and related i/o initialization. spp #p2c_pg ; p21 = sdi: in/tri/ttl. ld p2c0r,#00001110b ; p22 = sck: af/od/ttl. ld p2c1r,#11111101b ; p23 = sdo: af/od/ttl. ld p2c2r,#00001110b ; others = out/pp/ttl. spp #0 ld cicr,#( gcenm | iamm | cplm ); central interrupt control register ; priority level = 7 ; nested arbitration mode ; disable interrupt ; enable counters spp #0 srp #(15 * 2) ; to access page 0 registers clr eipr ; disable all the external interrupt ; pending bits. nop ; see warning (technical manual - chapter 8) ld eivr,#ext_it_vect ; external interrupt vector. ; iaos - tlis = 00 = ... ld eiplr,#0fbh ; priority level for group inta0 ; inta1 = 6, 7. appendix b. examples of calling programs (continued) ? using the i 2 c-bus protocol with the st9 30/34
ld eimr,#01 ; unmask interrupt a0 channel ; (wdt end of count). ; ( spi eot ). ; bit is active. clr flagr ; init flag ld ssplr,#sstack + 1 ; load system stack pointer ld usplr,#ustack + 1 ; load user stack pointer ld stat_eep,#eep_free_mask ; eeprom is free, no function in service. ei ;******************************************************************************** ;exemple of call to the eeprom manager to programm 4 bytes from the address 010h. ;******************************************************************************** begin_write:: ld eep_funct,#write_funct ; function to be executed by the ; eeprom manager. ld eep_add,#010h ; 1st address to be programmed. ld nb_byte,#4 ; number of bytes to program. ld r#(data_table+4),#78h ; 1st data to programm. ld r#(data_table+3),#49h ; 2nd data to programm. ld r#(data_table+2),#10h ; 3rd data to programm. ld r#(data_table+1),#94h ; 4th data to programm. call eep_man attbit stat_eep,#eep_free_mask ; wait for end of write procedure ; (programming delay also). ; by the st9. nop ; to replace by a jr instruction ; under sdbst9 for debug. nop ;******************************************************************************** ;example of call to the eeprom manager to read 6 bytes from the address 0fh. ;this can be a verification of the last programmation. ;******************************************************************************** begin_read:: ld eep_funct,#read_funct ; function to be executed by the ; eeprom manager. ld eep_add,#0fh ; read address in eeprom. ld nb_byte,#6 ; number of data to be read. call eep_man attbit stat_eep,#eep_free_mask ; wait for end of read procedure. ; here some instructions ; could be executed by the st9. end_read:: jr end_read appendix b. examples of calling programs (continued) ? using the i 2 c-bus protocol with the st9 31/34
titlea bitmacro.inc 05 december 1989 o ;******************************************************************************** ;******************************************************************************** ; bitmacro: macro file allowing bit test like pseudo_macros programmation, ; user must declare the macro used in his st9 source file like the following example ;.library ac:\st9\inc\bitmacro.inco ;.mcall ifbit, ifnobit, and so on ;******************************************************************************** ;******************************************************************************** ;******************************************************************************** ;e- macro-instruction ifbit: test if a bit is 1. ; parameters: - destination: all addressing mode allowed by ; theotm*instruction. ; - mask selecting the bit to be tested. ; ex: 00000010b for bit 1 test. ; ; !!! do not forget the a}o after instructions executed when the condition is ; true. ; application example ; ifbit dest,mask ; ... ; ... ;} .macroifbit dest,mask tm dest,mask if [ clz ] { ; the bit is set to 1. .endm ;******************************************************************************** ;******************************************************************************** ; macro-instruction whilebit: do while bit is 1. ; parameters: - destination: all addressing mode used for atmo instruction. ; - mask selecting the bit to be tested. ; ex: 00000010b to test bit 1. ; ; application example do { ; ... ; ... whilebit dest,mask .macrowhilebit dest,mask tm dest,mask } while [ clz ] ; the bit is set to 1. .endm appendix c. module macro definitions ? using the i 2 c-bus protocol with the st9 32/34
;******************************************************************************** ;******************************************************************************** ;e- macro-instruction ifnobit: test if a bit is 0. ; parameters: - destination: all the addressing mode used for the atmo ; instruction. ; - mask selecting the bit to be tested. ; ex: 00000010b to test bit 1. ; ; !!! do not forget the a}o after instructions executed when the condition is ; true. ; application example ; ifnobit dest,mak ; ... ... ;} .macroifnobit dest,mask tm dest,mask if [ setz ] { ; the bit is set to 1. .endm ;******************************************************************************** ;******************************************************************************** ;e- macro-instruction whilenobit: do while bit = 0. ; parameters: - destination: all the addressing mode used for the atmo ; instruction. ; - mask selecting the bit to be tested. ; ex: 00000010b to test bit 1. ; ; application example do { ; ... ; ... whilenobit dest,mak .macrowhilenobit dest,mask tm dest,mask } while [ setz ] ; the bit is set to 1. .endm ;******************************************************************************** ;******************************************************************************** ;e- waitbit: waiting for a bit to be 1. ; parameters: - destination: all the addressing mode used for atmo ; instruction. ; - mask selecting the bit to be tested. ; ex: 00000010b to test bit 1. ; .macrowaitbit dest,mask ******** do { tm dest,mask } while [ setz ] ; waiting for bit = 1. .endm appendix c. module macro definitions (continued) ? using the i 2 c-bus protocol with the st9 33/34
;******************************************************************************** ;******************************************************************************** waitnobit: waiting for a bit to be a 0. ; parameters: - destination: all the addressing mode used with the atmo ; instruction. ; - mask selecting the bit to be testesd. ; ex: 00000010b to test bit 1. ; .macrowaitnobit dest,mask do { tm dest,mask } while [ clz ] ; waiting for the bit = 0. .endm ;******************************************************************************** appendix c. module macro definitions (continued) information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved. purchase of i 2 c components by sgs-thomson microelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the nether- lands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. the software included in this note is for guidance only. sgs-thomson shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from use of the software. ? using the i 2 c-bus protocol with the st9 34/34

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