features n -69dbc 2nd and 3rd harmonics at 20mhz n -3db bandwidth of 270mhz n 0.05% settling in 15ns n 3000v/ s slew rate n 1mv input offset voltage, 10 v/ drift n ?0v, 100ma max output n direct replacement for clc232 applications n flash a/d drivers n dac current-to-voltage conversion n wide dynamic range if amps n vco drivers n dds postamps n radar/communication receivers n precision line drivers general description the KH232 is a wideband low distortion operational amplifier designed specifically for high speed, low gainapplications requiring wide dynamic range. utilizing a current feedback architecture, the KH232 offers high speed performance while maintaining dc precision. the KH232 offers precise gains from ? to ? with a true 0.1% linearity and provides stable, oscillation-free operation across the entire gain range without external compensation. the KH232, a pin compatible enhanced version of the kh231, reduces 2nd and 3rd harmonic distortion to an extremely low -69dbc at 20mhz (2v pp , r l = 100 ). additional features provided by the KH232 include a small signal bandwidth of270mhz, a large signal bandwidth of 95mhz and a 3000v/ s slew rate. the input offset voltage is typically 1mv with an input offset drift of 10 v/. the KH232 combines these high performance features with its 0.05% settling time of 15ns and its 100madrive capability to provide high speed, high resolution a/d and d/a converter systems with an attractive solution for driving and buffering. wide dynamic range systems such as radar and communication receivers requiring low harmonic distortion and low noise will find the KH232 to be an excellent choice. as a line driver, the KH232 set at a gain of 2 cancels matched line losses. the KH232 is constructed using thin film resistor/bipolar transistor technology, and is available in the following versions: KH232ai -25 to +85? 12-pin to-8 can KH232ak -55 to +125? 12-pin to-8 can, features burn-in & hermetic testing KH232am -55 to +125? 12-pin to-8 can, environmentallyscreened and electrically tested to mil-std-883 KH232hxc -55 to +125? smd#: 5962-9166501hxc KH232hxa -55 to +125? smd#: 5962-9166501hxa KH232 low distortion wideband op amp rev. 1a january 2004 typical performance gain setting parameter 1 2 5 -1 -2 -5 units -3db bandwidth 430 270 135 220 175 110 mhz rise time (2v) 1.8 2.0 2.5 2.0 2.2 2.9 ns slew rate 2.5 3.0 3.0 3.0 3.0 3.0 v/ns settling time (to 0.1%) 12 12 12 12 12 15 ns supply voltage 8 adjust 7 gnd 9 -v cc 2 adjust 3 gnd 1 +v cc 6 v+ 5 v- 4 nc 10 -v cc v o +v cc 11 12 4 4 collector supply output collector supply supply voltage i cc adjust i cc adjust case ground non-inverting input inverting input not connected case ground + - bottom view pins 2 and 8 are used to adjust the sup- ply current or to adjust the offset voltage (see text). these pins are normally left unconnected. www.cadeka.com
2 rev. 1a january 2004 data sheet KH232 parameters conditions typ min & max ratings units sym ambient temperature KH232ai +25 -25 +25 +85 ambient temperature KH232ak/am/hxc/hxa +25 -55 +25 +125c frequency domain response = -3db bandwidth (note 2) v o 0.63v pp 270 >200 >200 >200 mhz ssbw v o 2v pp 165 >145 >145 >120 mhz ssbw large-signal bandwidth v o 10v pp 95 >80 >80 >60 mhz fpbw gain flatness (note 2) v o 0.63v pp = peaking 0.1 to 50mhz 0.1 <0.6 <0.3 <0.6 db gfpl = peaking >50mhz 0.1 <1.5 <0.3 <0.8 db gfph = rolloff at 100mhz 0.4 <0.6 <0.6 <1.0 db gfr group delay to 100mhz 3.5 0.5 C C C ns gd linear phase deviation to 100mhz 0.5 <2.0 <2.0 <2.0 lpd reverse isolation non-inverting 53 >43 >43 >43 db rini inverting 36 >26 >26 >26 db riin time domain response rise and fall time 2v step 2.0 <2.4 <2.3 <2.7 ns trs 10v step 5.0 <7.0 <6.5 <6.5 ns trl settling time to 0.05% 5v step 15 C C C ns ts to 0.1% 2.5v step 12 <22 <17 <22 ns tsp overshoot 5v step 5 <15 <10 <15 % os slew rate (overdriven input) 3.0 >2.5 >2.5 >1.8 v/ns sr overload recovery <1% error <50ns pulse, 200% overdrive 120 C C C ns or noise and distortion response = 2nd harmonic distortion 2v pp , 20mhz -69 <-64 <-64 <-56 dbc hd2 = 3rd harmonic distortion 2v pp , 20mhz -69 <-64 <-64 <-64 dbc hd3 equivalent input noise voltage >100khz 2.8 <3.2 <3.2 <3.5 nv/ hz vn inverting current >100khz 20 <23 <23 <25 pa/ hz icn non-inverting current >100khz 2.3 <2.6 <2.6 <2.9 pa/ hz ncn noise floor >100khz -155 <-154 <-154 <-153 dbm(1hz) snf integrated noise 1khz to 200mhz 57 <64 <64 <72 vrms inv integrated noise 5mhz to 200mhz 57 <64 <64 <72 vrms inv static, dc performance * input offset voltage 1 <4.0 <2.0 <4.5 mv vio average temperature coefficient 10 <25 <25 <25 v/ dvio * input bias current non-inverting 5.0 <29 <21 <31 a ibn average temperature coefficient 50 <125 <125 <125 na/ dibn * input bias current inverting 10 <31 <15 < 35 a ibi average temperature coefficient 125 <200 <200 <200 na/ dibi * power supply rejection ratio 50 >45 >45 >45 db psrr common mode rejection ratio 46 >40 >40 >40 db cmrr * supply current no load 25 <27 <27 <29 ma icc miscellaneous performance non-inverting input resistance dc 400 >100 >200 >400 k rin non-inverting input capacitance 1.3 <2.5 <2.5 <2.5 pf cin output impedance @ 100mhz 5, 37 C C C , nh ro output voltage range no load 12 > 11 > 11 > 11 v vo min/max ratings are based on product characterization and simulation. individual parameters are tested as noted. outgoing quality levels are determined from tested parameters. absolute maximum ratings recommended operating conditions v cc 20v v cc 5v to 15v i o 100ma i o 75ma common mode input voltage, v o |v cc | >15v (30-|v cc |)v common mode input voltage (|v cc | -5)v |v cc | 15v |v cc |v gain range 1 to 5 differential input voltage 3v thermal resistance (see thermal model) junction temperature +175 operating temperature ai: -25c to +85 ak/am/hxc/hxa: -55 to +125? storage temperature -65c to +150c lead temperature (soldering 10s) +300 KH232 electrical characteristics ( t a = +25c, a v = +2v, v cc = ?5v, r l = 100 , r f = 250 ; unless specified) note 1: * ai/ak/am/hxc/hxa 100% tested at +25 = ak/am/hxc/hxa 100% tested at +25 and sample tested at -55 and +125? = ai sample tested at +25c note 2: the output amplitude used in testing is 0.63v pp . performance is guaranteed for conditions listed.
KH232 data sheet rev. 1a january 2004 3 KH232 typical performance characteristics (t a = +25c, a v = +2, v cc = 15v, r l = 100 , r f = 250 ; unless specified) non-inverting frequency response n o r m a l i z e d m a g n i t u d e ( 1 d b / d i v ) frequency (mhz) k 0 150 300 gain phase p h a s e ( 4 5 d e g / d i v ) a v = 5 a v = 1 a v = 2 a v = 5 a v = 2 a v = 1 inverting frequency response n o r m a l i z e d m a g n i t u d e ( 1 d b / d i v ) frequency (mhz) k 0 150 300 gain phase p h a s e ( 4 5 d e g / d i v ) a v = -5 a v = -1 a v = -2 a v = -5 a v = -2 a v = -1 settling time vs. c l s e t t l i n g t i m e ( n s ) c l (pf) 35 15 10 30 r s 1k 5 0 100 1000 20 25 r s ( ) 70 30 20 60 10 40 50 t s r s c l a v = +2 bandwidth vs. v cc r e l a t i v e b a n d w i d t h v cc (v) k 4 6 8 10 12 14 16 pins 1 and 2 shorted pins 8 and 9 shorted 0.4 0.6 0.8 1.0 1.2 frequency response vs. r l ( 1 d b / d i v ) frequency (mhz) k 0 150 300 r l = 50 a v = 2 r l = 200 r l = 100 r l = 500 large signal non-inverting gain & phase ( 1 d b / d i v ) p h a s e ( 4 5 d e g / d i v ) frequency (mhz) k 0 150 300 gain phase a v = 2 v o = 10v pp 2nd harmonic distortion d i s t o r t i o n ( d b c ) frequency (hz) k 1 10 100 -90 -60 -50 -40 -20 -30 4v pp -70 -80 8v pp 2v pp 1v pp 3rd harmonic distortion d i s t o r t i o n ( d b c ) frequency (hz) k 1 10 100 -90 -60 -50 -40 -20 -30 4v pp -70 -80 8v pp 2v pp 1v pp 2nd and 3rd harmonic distortion d i s t o r t i o n ( d b c ) frequency (mhz) -40 -75 -70 -65 -60 -55 -50 -45 -90 1 10 100 -80 -85 2nd 3rd v o = 2v pp 2-tone, 3rd order intermod. intercept i n t e r d e p t p o i n t ( d b m ) frequency (mhz) 50 35 25 20 45 50 50 p out 15 0 10 20 30 40 50 60 70 80 90 100 30 40 equivalent input noise n o i s e v o l t a g e ( n v / h z ) frequency (hz) k 100 10m 1k 10k 100k 1m inverting current 20pa/ hz non-inverting current 2.3pa/ hz voltage 2.8nv/ hz 1 10 100 n o i s e c u r r e n t ( p a / h z ) 1 10 100 100m cmrr and psrr k cmrr psrr p s r r / c m r r ( d b ) frequency (hz) 1 10 100 1k 10k 100k 100m 10 30 40 50 1m 10m 20 small signal pulse response o u t p u t v o l t a g e ( 4 0 0 m v / d i v ) time (5ns/div) k a v = -2 a v = 2 large signal pulse response o u t p u t v o l t a g e ( 2 v / d i v ) time (5ns/div) k a v = -2 a v = 2 settling time k 50ns/div 5ns/div s e t t l i n g e r r o r ( % ) time (ns) -0.20 -0.15 0.05 0.10 0.20 0.15 0 -0.05 -0.10
data sheet KH232 4 rev. 1a january 2004 operation the KH232 is based on the current feedback op amp topology, a design that uses current feedback instead of the usual voltage feedback. the use of the KH232 is basically the same as that of the conventional op amp (see figures 1 and 2). since thedevice is designed specifically for low gain applications, the best performance is obtained when the circuit is used at gains between 1 and 5. additionally, performance is optimum when a 250 feedback resistor is used. figure 1: recommended non-inverting gain circuit figure 2: recommended inverting gain circuit layout considerations to assure optimum performance the user should follow good layout practices which minimize the unwanted coupling of signals between nodes. during initial bread-boarding of the circuit use direct point to point wiring, keeping the lead lengths to less than 0.25 the use of solid, unbroken ground plane is helpful. avoid wire-wrap type pc boards and methods. sockets with small, short pin receptacles may be used with minimal performance degradation although their use is not recommended. during pc board layout keep all traces short and direct the resistive body of r g should be as close as possible to pin 5 to minimize capacitance at that point. for thesame reason, remove ground plane from the vicinity of pins 5 and 6. in other areas, use as much ground plane as possible on one side of the board. it is especially important to provide a ground return path for current from the load resistor to the power supply bypass capacitors. ceramic capacitors of 0.01 to 0.1 f (with short leads) should be less than 0.15 inches from pins 1 and 9.larger tantalum capacitors should be placed within one inch of these pins. v cc connections to pins 10 and 12 can be made directly from pins 9 and 1, but better supplyrejection and settling time are obtained if they are separately bypassed as in figures 1 and 2. to prevent signal distortion caused by reflections from impedance mismatches, use terminated microstrip or coaxial cable when the signal must traverse more than a few inches. since the pc board forms such an important part of the circuit, much time can be saved if prototype boards ofany high frequency sections are built and tested early in the design phase. evaluation boards designed for either inverting or non-inverting gains are available. offset voltage adjustment if trimming of the input offset voltage (v os = v ni -v in ) is desired, a resistor value of 10k to 1m placed between pins 8 and 9 will cause v os to become more negative by 8mv to 0.2mv respectively. similarly, a resistor placed between pins 1 and 2 will cause v os , to become more positive. thermal considerations at high ambient temperatures or large internal power dissipations, heat sinking is required to maintain acceptable junction temperatures. use the thermal model on the previous page to determine junction temperatures. many styles of heat sinks are available for to-8 packages; the thermalloy 2240 and 2268 are good examples. some heat sinks are the radial fin type which cover the pc board and may interfere with external components. an excellent solution to this problem is to use surface mounted resistors and capacitors. they have a very low profile and actually improve high frequency performance. for use of these heat sinks with conventional components, a 0.1high spacer can be inserted under the to-8 package to allow sufficient clearance. 33 +15v 0.1 3.9 .01 capactance in f 1 12 5 3,7 r l 100 10 11 33 .01 0.1 3.9 -15v 9 + - KH232 v o r f = 250 6 r g v in r i 49.9 a r r v f g = 1+ 250 33 +15v 0.1 3.9 .01 capactance in f 1 12 5 3,7 r l 100 10 11 33 .01 0.1 3.9 -15v 9 + - KH232 v o r f = 250 for z in = 50 , select r g || r i = 50 6 100 v in r i 250 r g a r r v f g = ? ? ? ? ? ? ?
KH232 data sheet rev. 1a january 2004 5 other methods of heat sinking may be used, but for best results, make contact with the base of the KH232package, use a large thermal capacity heat sink and use forced air convection. low v cc operation: supply current adjustment the KH232 is designed to operate on supplies as low as 5v. in order to improve full bandwidth at reduced supply voltages, the supply current (i cc ) must be increased. the plot of bandwidth vs. v cc , shows the effect of shorting pins 1 and 2 and pins 8 and 9; this will increase both bandwidth and supply current. care should be taken to not exceed the maximum junction temperatures; for this reason this technique should not be used with supplies exceeding 10v. for intermediate values of v cc , external resistors between pins 1 and 2 and pins 8 and 9 can be used. p (circuit) = (i cc )((+v cc ) C(v cc )) where i cc = 14ma at 15v p (xxx) = [( v cc ) Cv out C(i col ) (r col + 4)] (i col ) (%duty) for positive v o and v cc , this is the power in the npn device. for negative v o and v cc , this is the power in the pnp device. i col = v o /r l or 12ma, whichever is greater. (include feed- back r in r l .) r col is a resistor (33 recommended) between the xxx collector and v cc . the limiting factor for output current and voltage is junction temperature. of secondary importance is i (out) , which should not exceed 150ma. t j(pnp) = p (pnp) (100 + ca ) + (p (cir) + p (npn) )( ca ) + t a , similar for t j(npn) . t j(cir) = p (cir) (48 + ca ) + (p (pnp) + p (npn) )( ca ) + t a . ca = 65/w for the KH232 without heat sink in still air. 35/w for the KH232 with a thermalloy 2268a heat sink in still air. 15/w for the KH232 with a thermalloy 2268a heat sink at 300 ft/min air. (thermalloy 2240a works equally as well.) for example, with the KH232 operating at 15v while driving a 100 load at 15v pp output (50% duty cycle pulse waveform, dc = 0), p (npn) = p (pnp) = 190mw (r col = 33) and p (cir) = 0.42w. then with the thermalloy 2268 heat sink and air flow of 300 ft/min the output transistors t j is 31 above ambient and worst case t j in the rest of the circuit is 32 above ambient. in still air, however, the rise in t j is 47 and 48? respectively. with no heat sink, the rise in t j is 71 and 72? respectively! under most conditions, heat sinking is required . + - t ambient ca t case 48 c/w t j(circuit) p circuit 100c/w t j(npn) p npn 100c/w p pnp t j(pnp)
KH232 package dimensions data sheet KH232 symbol inches milimeters
minimun maximum minimum maximum
a 0.142 0 .181 3. 61 4 .60
b 0.016 0.019 0.41 0.48
d 0.595 0.605 15.11 15.37
d 1 0.543 0.555 13.79 14.10
e 0.400 bsc 10.16 bsc
e 1 0.200 bsc 5.08 bsc
e 2 0.100 bsc 2.54 bsc
f 0.016 0.030 0.41 0.76
k 0.026 0.036 0.66 0.91 k 1 0.026 0.036 0.66 0.91
l 0.310 0.340 7.87 8.64
45 bsc 45 bsc notes:
seal: cap weld
lead finish: gold per mil-m-38510
package composition:
package: metal
lid: type a per mil-m-38510 8 7 9 2 3 1 5 6 4 11 10 12 k 1 e dd 1 to-8
e 1 e 2 k l a f b life support policy cadekas products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of cadeka microcircuits, inc. as used herein: 1. life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. cadeka does not assume any responsibility for use of any circuitry described, and cadeka reserves the right at any time without notice to change said circuitry and specifications. www.cadeka.com ?2004 cadeka microcircuits, llc
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